[mirror_ubuntu-bionic-kernel.git] / drivers / spi / spi-fsl-dspi.c

/*
 * drivers/spi/spi-fsl-dspi.c
 *
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Freescale DSPI driver
 * This file contains a driver for the Freescale DSPI
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/sched.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>

#define DRIVER_NAME "fsl-dspi"

#define TRAN_STATE_RX_VOID		0x01
#define TRAN_STATE_TX_VOID		0x02
#define TRAN_STATE_WORD_ODD_NUM	0x04

#define DSPI_FIFO_SIZE			4

#define SPI_MCR		0x00
#define SPI_MCR_MASTER		(1 << 31)
#define SPI_MCR_PCSIS		(0x3F << 16)
#define SPI_MCR_CLR_TXF	(1 << 11)
#define SPI_MCR_CLR_RXF	(1 << 10)

#define SPI_TCR			0x08

#define SPI_CTAR(x)		(0x0c + (((x) & 0x3) * 4))
#define SPI_CTAR_FMSZ(x)	(((x) & 0x0000000f) << 27)
#define SPI_CTAR_CPOL(x)	((x) << 26)
#define SPI_CTAR_CPHA(x)	((x) << 25)
#define SPI_CTAR_LSBFE(x)	((x) << 24)
#define SPI_CTAR_PCSSCR(x)	(((x) & 0x00000003) << 22)
#define SPI_CTAR_PASC(x)	(((x) & 0x00000003) << 20)
#define SPI_CTAR_PDT(x)	(((x) & 0x00000003) << 18)
#define SPI_CTAR_PBR(x)	(((x) & 0x00000003) << 16)
#define SPI_CTAR_CSSCK(x)	(((x) & 0x0000000f) << 12)
#define SPI_CTAR_ASC(x)	(((x) & 0x0000000f) << 8)
#define SPI_CTAR_DT(x)		(((x) & 0x0000000f) << 4)
#define SPI_CTAR_BR(x)		((x) & 0x0000000f)

#define SPI_CTAR0_SLAVE	0x0c

#define SPI_SR			0x2c
#define SPI_SR_EOQF		0x10000000

#define SPI_RSER		0x30
#define SPI_RSER_EOQFE		0x10000000

#define SPI_PUSHR		0x34
#define SPI_PUSHR_CONT		(1 << 31)
#define SPI_PUSHR_CTAS(x)	(((x) & 0x00000003) << 28)
#define SPI_PUSHR_EOQ		(1 << 27)
#define SPI_PUSHR_CTCNT	(1 << 26)
#define SPI_PUSHR_PCS(x)	(((1 << x) & 0x0000003f) << 16)
#define SPI_PUSHR_TXDATA(x)	((x) & 0x0000ffff)

#define SPI_PUSHR_SLAVE	0x34

#define SPI_POPR		0x38
#define SPI_POPR_RXDATA(x)	((x) & 0x0000ffff)

#define SPI_TXFR0		0x3c
#define SPI_TXFR1		0x40
#define SPI_TXFR2		0x44
#define SPI_TXFR3		0x48
#define SPI_RXFR0		0x7c
#define SPI_RXFR1		0x80
#define SPI_RXFR2		0x84
#define SPI_RXFR3		0x88

#define SPI_FRAME_BITS(bits)	SPI_CTAR_FMSZ((bits) - 1)
#define SPI_FRAME_BITS_MASK	SPI_CTAR_FMSZ(0xf)
#define SPI_FRAME_BITS_16	SPI_CTAR_FMSZ(0xf)
#define SPI_FRAME_BITS_8	SPI_CTAR_FMSZ(0x7)

#define SPI_CS_INIT		0x01
#define SPI_CS_ASSERT		0x02
#define SPI_CS_DROP		0x04

struct chip_data {
	u32 mcr_val;
	u32 ctar_val;
	u16 void_write_data;
};

struct fsl_dspi {
	struct spi_master	*master;
	struct platform_device	*pdev;

	struct regmap		*regmap;
	int			irq;
	struct clk		*clk;

	struct spi_transfer	*cur_transfer;
	struct spi_message	*cur_msg;
	struct chip_data	*cur_chip;
	size_t			len;
	void			*tx;
	void			*tx_end;
	void			*rx;
	void			*rx_end;
	char			dataflags;
	u8			cs;
	u16			void_write_data;
	u32			cs_change;

	wait_queue_head_t	waitq;
	u32			waitflags;
};

static inline int is_double_byte_mode(struct fsl_dspi *dspi)
{
	unsigned int val;

	regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);

	return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
}

static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
		unsigned long clkrate)
{
	/* Valid baud rate pre-scaler values */
	int pbr_tbl[4] = {2, 3, 5, 7};
	int brs[16] = {	2,	4,	6,	8,
		16,	32,	64,	128,
		256,	512,	1024,	2048,
		4096,	8192,	16384,	32768 };
	int scale_needed, scale, minscale = INT_MAX;
	int i, j;

	scale_needed = clkrate / speed_hz;

	for (i = 0; i < ARRAY_SIZE(brs); i++)
		for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
			scale = brs[i] * pbr_tbl[j];
			if (scale >= scale_needed) {
				if (scale < minscale) {
					minscale = scale;
					*br = i;
					*pbr = j;
				}
				break;
			}
		}

	if (minscale == INT_MAX) {
		pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
			speed_hz, clkrate);
		*pbr = ARRAY_SIZE(pbr_tbl) - 1;
		*br =  ARRAY_SIZE(brs) - 1;
	}
}

static int dspi_transfer_write(struct fsl_dspi *dspi)
{
	int tx_count = 0;
	int tx_word;
	u16 d16;
	u8  d8;
	u32 dspi_pushr = 0;
	int first = 1;

	tx_word = is_double_byte_mode(dspi);

	/* If we are in word mode, but only have a single byte to transfer
	 * then switch to byte mode temporarily.  Will switch back at the
	 * end of the transfer.
	 */
	if (tx_word && (dspi->len == 1)) {
		dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
		regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
				SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
		tx_word = 0;
	}

	while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
		if (tx_word) {
			if (dspi->len == 1)
				break;

			if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
				d16 = *(u16 *)dspi->tx;
				dspi->tx += 2;
			} else {
				d16 = dspi->void_write_data;
			}

			dspi_pushr = SPI_PUSHR_TXDATA(d16) |
				SPI_PUSHR_PCS(dspi->cs) |
				SPI_PUSHR_CTAS(dspi->cs) |
				SPI_PUSHR_CONT;

			dspi->len -= 2;
		} else {
			if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {

				d8 = *(u8 *)dspi->tx;
				dspi->tx++;
			} else {
				d8 = (u8)dspi->void_write_data;
			}

			dspi_pushr = SPI_PUSHR_TXDATA(d8) |
				SPI_PUSHR_PCS(dspi->cs) |
				SPI_PUSHR_CTAS(dspi->cs) |
				SPI_PUSHR_CONT;

			dspi->len--;
		}

		if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
			/* last transfer in the transfer */
			dspi_pushr |= SPI_PUSHR_EOQ;
			if ((dspi->cs_change) && (!dspi->len))
				dspi_pushr &= ~SPI_PUSHR_CONT;
		} else if (tx_word && (dspi->len == 1))
			dspi_pushr |= SPI_PUSHR_EOQ;

		if (first) {
			first = 0;
			dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
		}

		regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);

		tx_count++;
	}

	return tx_count * (tx_word + 1);
}

static int dspi_transfer_read(struct fsl_dspi *dspi)
{
	int rx_count = 0;
	int rx_word = is_double_byte_mode(dspi);
	u16 d;

	while ((dspi->rx < dspi->rx_end)
			&& (rx_count < DSPI_FIFO_SIZE)) {
		if (rx_word) {
			unsigned int val;

			if ((dspi->rx_end - dspi->rx) == 1)
				break;

			regmap_read(dspi->regmap, SPI_POPR, &val);
			d = SPI_POPR_RXDATA(val);

			if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
				*(u16 *)dspi->rx = d;
			dspi->rx += 2;

		} else {
			unsigned int val;

			regmap_read(dspi->regmap, SPI_POPR, &val);
			d = SPI_POPR_RXDATA(val);
			if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
				*(u8 *)dspi->rx = d;
			dspi->rx++;
		}
		rx_count++;
	}

	return rx_count;
}

static int dspi_transfer_one_message(struct spi_master *master,
		struct spi_message *message)
{
	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	struct spi_device *spi = message->spi;
	struct spi_transfer *transfer;
	int status = 0;
	message->actual_length = 0;

	list_for_each_entry(transfer, &message->transfers, transfer_list) {
		dspi->cur_transfer = transfer;
		dspi->cur_msg = message;
		dspi->cur_chip = spi_get_ctldata(spi);
		dspi->cs = spi->chip_select;
		if (dspi->cur_transfer->transfer_list.next
				== &dspi->cur_msg->transfers)
			transfer->cs_change = 1;
		dspi->cs_change = transfer->cs_change;
		dspi->void_write_data = dspi->cur_chip->void_write_data;

		dspi->dataflags = 0;
		dspi->tx = (void *)transfer->tx_buf;
		dspi->tx_end = dspi->tx + transfer->len;
		dspi->rx = transfer->rx_buf;
		dspi->rx_end = dspi->rx + transfer->len;
		dspi->len = transfer->len;

		if (!dspi->rx)
			dspi->dataflags |= TRAN_STATE_RX_VOID;

		if (!dspi->tx)
			dspi->dataflags |= TRAN_STATE_TX_VOID;

		regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
		regmap_update_bits(dspi->regmap, SPI_MCR,
				SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
				SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
		regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
				dspi->cur_chip->ctar_val);
		if (transfer->speed_hz)
			regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
					dspi->cur_chip->ctar_val);

		regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
		message->actual_length += dspi_transfer_write(dspi);

		if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
			dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
		dspi->waitflags = 0;

		if (transfer->delay_usecs)
			udelay(transfer->delay_usecs);
	}

	message->status = status;
	spi_finalize_current_message(master);

	return status;
}

static int dspi_setup(struct spi_device *spi)
{
	struct chip_data *chip;
	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	unsigned char br = 0, pbr = 0, fmsz = 0;

	if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
		fmsz = spi->bits_per_word - 1;
	} else {
		pr_err("Invalid wordsize\n");
		return -ENODEV;
	}

	/* Only alloc on first setup */
	chip = spi_get_ctldata(spi);
	if (chip == NULL) {
		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
		if (!chip)
			return -ENOMEM;
	}

	chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
		SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;

	chip->void_write_data = 0;

	hz_to_spi_baud(&pbr, &br,
			spi->max_speed_hz, clk_get_rate(dspi->clk));

	chip->ctar_val =  SPI_CTAR_FMSZ(fmsz)
		| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
		| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
		| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
		| SPI_CTAR_PBR(pbr)
		| SPI_CTAR_BR(br);

	spi_set_ctldata(spi, chip);

	return 0;
}

static void dspi_cleanup(struct spi_device *spi)
{
	struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);

	dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
			spi->master->bus_num, spi->chip_select);

	kfree(chip);
}

static irqreturn_t dspi_interrupt(int irq, void *dev_id)
{
	struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;

	struct spi_message *msg = dspi->cur_msg;

	regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
	dspi_transfer_read(dspi);

	if (!dspi->len) {
		if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
			regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
			SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));

		dspi->waitflags = 1;
		wake_up_interruptible(&dspi->waitq);
	} else
		msg->actual_length += dspi_transfer_write(dspi);

	return IRQ_HANDLED;
}

static const struct of_device_id fsl_dspi_dt_ids[] = {
	{ .compatible = "fsl,vf610-dspi", .data = NULL, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);

#ifdef CONFIG_PM_SLEEP
static int dspi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct fsl_dspi *dspi = spi_master_get_devdata(master);

	spi_master_suspend(master);
	clk_disable_unprepare(dspi->clk);

	return 0;
}

static int dspi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct fsl_dspi *dspi = spi_master_get_devdata(master);

	clk_prepare_enable(dspi->clk);
	spi_master_resume(master);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);

static const struct regmap_config dspi_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
	.max_register = 0x88,
};

static int dspi_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct fsl_dspi *dspi;
	struct resource *res;
	void __iomem *base;
	int ret = 0, cs_num, bus_num;

	master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
	if (!master)
		return -ENOMEM;

	dspi = spi_master_get_devdata(master);
	dspi->pdev = pdev;
	dspi->master = master;

	master->transfer = NULL;
	master->setup = dspi_setup;
	master->transfer_one_message = dspi_transfer_one_message;
	master->dev.of_node = pdev->dev.of_node;

	master->cleanup = dspi_cleanup;
	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
					SPI_BPW_MASK(16);

	ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
	if (ret < 0) {
		dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
		goto out_master_put;
	}
	master->num_chipselect = cs_num;

	ret = of_property_read_u32(np, "bus-num", &bus_num);
	if (ret < 0) {
		dev_err(&pdev->dev, "can't get bus-num\n");
		goto out_master_put;
	}
	master->bus_num = bus_num;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base)) {
		ret = PTR_ERR(base);
		goto out_master_put;
	}

	dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
						&dspi_regmap_config);
	if (IS_ERR(dspi->regmap)) {
		dev_err(&pdev->dev, "failed to init regmap: %ld\n",
				PTR_ERR(dspi->regmap));
		return PTR_ERR(dspi->regmap);
	}

	dspi->irq = platform_get_irq(pdev, 0);
	if (dspi->irq < 0) {
		dev_err(&pdev->dev, "can't get platform irq\n");
		ret = dspi->irq;
		goto out_master_put;
	}

	ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
			pdev->name, dspi);
	if (ret < 0) {
		dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
		goto out_master_put;
	}

	dspi->clk = devm_clk_get(&pdev->dev, "dspi");
	if (IS_ERR(dspi->clk)) {
		ret = PTR_ERR(dspi->clk);
		dev_err(&pdev->dev, "unable to get clock\n");
		goto out_master_put;
	}
	clk_prepare_enable(dspi->clk);

	init_waitqueue_head(&dspi->waitq);
	platform_set_drvdata(pdev, master);

	ret = spi_register_master(master);
	if (ret != 0) {
		dev_err(&pdev->dev, "Problem registering DSPI master\n");
		goto out_clk_put;
	}

	return ret;

out_clk_put:
	clk_disable_unprepare(dspi->clk);
out_master_put:
	spi_master_put(master);

	return ret;
}

static int dspi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct fsl_dspi *dspi = spi_master_get_devdata(master);

	/* Disconnect from the SPI framework */
	clk_disable_unprepare(dspi->clk);
	spi_unregister_master(dspi->master);
	spi_master_put(dspi->master);

	return 0;
}

static struct platform_driver fsl_dspi_driver = {
	.driver.name    = DRIVER_NAME,
	.driver.of_match_table = fsl_dspi_dt_ids,
	.driver.owner   = THIS_MODULE,
	.driver.pm = &dspi_pm,
	.probe          = dspi_probe,
	.remove		= dspi_remove,
};
module_platform_driver(fsl_dspi_driver);

MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
349ad66c CF	1	/*
	2	* drivers/spi/spi-fsl-dspi.c
	3	*
	4	* Copyright 2013 Freescale Semiconductor, Inc.
	5	*
	6	* Freescale DSPI driver
	7	* This file contains a driver for the Freescale DSPI
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	*/
	15
a3108360 XL	16	#include <linux/clk.h>
	17	#include <linux/delay.h>
	18	#include <linux/err.h>
	19	#include <linux/errno.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/io.h>
349ad66c CF	22	#include <linux/kernel.h>
349ad66c CF	23	#include <linux/module.h>
a3108360 XL	24	#include <linux/of.h>
a3108360 XL	25	#include <linux/of_device.h>
349ad66c	26	#include <linux/platform_device.h>
a3108360	27	#include <linux/pm_runtime.h>
1acbdeb9	28	#include <linux/regmap.h>
349ad66c	29	#include <linux/sched.h>
349ad66c CF	30	#include <linux/spi/spi.h>
349ad66c CF	31	#include <linux/spi/spi_bitbang.h>
349ad66c CF	32
	33	#define DRIVER_NAME "fsl-dspi"
	34
	35	#define TRAN_STATE_RX_VOID 0x01
	36	#define TRAN_STATE_TX_VOID 0x02
	37	#define TRAN_STATE_WORD_ODD_NUM 0x04
	38
	39	#define DSPI_FIFO_SIZE 4
	40
	41	#define SPI_MCR 0x00
	42	#define SPI_MCR_MASTER (1 << 31)
	43	#define SPI_MCR_PCSIS (0x3F << 16)
	44	#define SPI_MCR_CLR_TXF (1 << 11)
	45	#define SPI_MCR_CLR_RXF (1 << 10)
	46
	47	#define SPI_TCR 0x08
	48
5cc7b047	49	#define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
349ad66c CF	50	#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
	51	#define SPI_CTAR_CPOL(x) ((x) << 26)
	52	#define SPI_CTAR_CPHA(x) ((x) << 25)
	53	#define SPI_CTAR_LSBFE(x) ((x) << 24)
	54	#define SPI_CTAR_PCSSCR(x) (((x) & 0x00000003) << 22)
	55	#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
	56	#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
	57	#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
	58	#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
	59	#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
	60	#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
	61	#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
	62
	63	#define SPI_CTAR0_SLAVE 0x0c
	64
	65	#define SPI_SR 0x2c
	66	#define SPI_SR_EOQF 0x10000000
	67
	68	#define SPI_RSER 0x30
	69	#define SPI_RSER_EOQFE 0x10000000
	70
	71	#define SPI_PUSHR 0x34
	72	#define SPI_PUSHR_CONT (1 << 31)
5cc7b047	73	#define SPI_PUSHR_CTAS(x) (((x) & 0x00000003) << 28)
349ad66c CF	74	#define SPI_PUSHR_EOQ (1 << 27)
	75	#define SPI_PUSHR_CTCNT (1 << 26)
	76	#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
	77	#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
	78
	79	#define SPI_PUSHR_SLAVE 0x34
	80
	81	#define SPI_POPR 0x38
	82	#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
	83
	84	#define SPI_TXFR0 0x3c
	85	#define SPI_TXFR1 0x40
	86	#define SPI_TXFR2 0x44
	87	#define SPI_TXFR3 0x48
	88	#define SPI_RXFR0 0x7c
	89	#define SPI_RXFR1 0x80
	90	#define SPI_RXFR2 0x84
	91	#define SPI_RXFR3 0x88
	92
	93	#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
	94	#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
	95	#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
	96	#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
	97
	98	#define SPI_CS_INIT 0x01
	99	#define SPI_CS_ASSERT 0x02
	100	#define SPI_CS_DROP 0x04
	101
	102	struct chip_data {
	103	u32 mcr_val;
	104	u32 ctar_val;
	105	u16 void_write_data;
	106	};
	107
	108	struct fsl_dspi {
9298bc72	109	struct spi_master *master;
349ad66c CF	110	struct platform_device *pdev;
349ad66c CF	111
1acbdeb9	112	struct regmap *regmap;
349ad66c	113	int irq;
88386e85	114	struct clk *clk;
349ad66c	115
88386e85	116	struct spi_transfer *cur_transfer;
9298bc72	117	struct spi_message *cur_msg;
349ad66c CF	118	struct chip_data *cur_chip;
	119	size_t len;
	120	void *tx;
	121	void *tx_end;
	122	void *rx;
	123	void *rx_end;
	124	char dataflags;
	125	u8 cs;
	126	u16 void_write_data;
9298bc72	127	u32 cs_change;
349ad66c	128
88386e85 CF	129	wait_queue_head_t waitq;
88386e85 CF	130	u32 waitflags;
349ad66c CF	131	};
	132
	133	static inline int is_double_byte_mode(struct fsl_dspi *dspi)
	134	{
1acbdeb9	135	unsigned int val;
349ad66c	136
1acbdeb9	137	regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
349ad66c	138
1acbdeb9	139	return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
349ad66c CF	140	}
	141
	142	static void hz_to_spi_baud(char pbr, char br, int speed_hz,
	143	unsigned long clkrate)
	144	{
	145	/* Valid baud rate pre-scaler values */
	146	int pbr_tbl[4] = {2, 3, 5, 7};
	147	int brs[16] = { 2, 4, 6, 8,
	148	16, 32, 64, 128,
	149	256, 512, 1024, 2048,
	150	4096, 8192, 16384, 32768 };
6fd63087 AB	151	int scale_needed, scale, minscale = INT_MAX;
	152	int i, j;
	153
	154	scale_needed = clkrate / speed_hz;
	155
	156	for (i = 0; i < ARRAY_SIZE(brs); i++)
	157	for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
	158	scale = brs[i] * pbr_tbl[j];
	159	if (scale >= scale_needed) {
	160	if (scale < minscale) {
	161	minscale = scale;
	162	*br = i;
	163	*pbr = j;
	164	}
	165	break;
349ad66c CF	166	}
	167	}
	168
6fd63087 AB	169	if (minscale == INT_MAX) {
	170	pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
	171	speed_hz, clkrate);
	172	*pbr = ARRAY_SIZE(pbr_tbl) - 1;
	173	*br = ARRAY_SIZE(brs) - 1;
	174	}
349ad66c CF	175	}
	176
	177	static int dspi_transfer_write(struct fsl_dspi *dspi)
	178	{
	179	int tx_count = 0;
	180	int tx_word;
	181	u16 d16;
	182	u8 d8;
	183	u32 dspi_pushr = 0;
	184	int first = 1;
	185
	186	tx_word = is_double_byte_mode(dspi);
	187
	188	/* If we are in word mode, but only have a single byte to transfer
	189	* then switch to byte mode temporarily. Will switch back at the
	190	* end of the transfer.
	191	*/
	192	if (tx_word && (dspi->len == 1)) {
	193	dspi->dataflags \|= TRAN_STATE_WORD_ODD_NUM;
1acbdeb9 CF	194	regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
1acbdeb9 CF	195	SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
349ad66c CF	196	tx_word = 0;
	197	}
	198
	199	while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
	200	if (tx_word) {
	201	if (dspi->len == 1)
	202	break;
	203
	204	if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
	205	d16 = (u16 )dspi->tx;
	206	dspi->tx += 2;
	207	} else {
	208	d16 = dspi->void_write_data;
	209	}
	210
	211	dspi_pushr = SPI_PUSHR_TXDATA(d16) \|
	212	SPI_PUSHR_PCS(dspi->cs) \|
	213	SPI_PUSHR_CTAS(dspi->cs) \|
	214	SPI_PUSHR_CONT;
	215
	216	dspi->len -= 2;
	217	} else {
	218	if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
	219
	220	d8 = (u8 )dspi->tx;
	221	dspi->tx++;
	222	} else {
	223	d8 = (u8)dspi->void_write_data;
	224	}
	225
	226	dspi_pushr = SPI_PUSHR_TXDATA(d8) \|
	227	SPI_PUSHR_PCS(dspi->cs) \|
	228	SPI_PUSHR_CTAS(dspi->cs) \|
	229	SPI_PUSHR_CONT;
	230
	231	dspi->len--;
	232	}
	233
	234	if (dspi->len == 0 \|\| tx_count == DSPI_FIFO_SIZE - 1) {
	235	/* last transfer in the transfer */
	236	dspi_pushr \|= SPI_PUSHR_EOQ;
9298bc72 CF	237	if ((dspi->cs_change) && (!dspi->len))
9298bc72 CF	238	dspi_pushr &= ~SPI_PUSHR_CONT;
349ad66c CF	239	} else if (tx_word && (dspi->len == 1))
	240	dspi_pushr \|= SPI_PUSHR_EOQ;
	241
	242	if (first) {
	243	first = 0;
	244	dspi_pushr \|= SPI_PUSHR_CTCNT; /* clear counter */
	245	}
	246
1acbdeb9 CF	247	regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
1acbdeb9 CF	248
349ad66c CF	249	tx_count++;
	250	}
	251
	252	return tx_count * (tx_word + 1);
	253	}
	254
	255	static int dspi_transfer_read(struct fsl_dspi *dspi)
	256	{
	257	int rx_count = 0;
	258	int rx_word = is_double_byte_mode(dspi);
	259	u16 d;
9298bc72	260
349ad66c CF	261	while ((dspi->rx < dspi->rx_end)
	262	&& (rx_count < DSPI_FIFO_SIZE)) {
	263	if (rx_word) {
1acbdeb9 CF	264	unsigned int val;
1acbdeb9 CF	265
349ad66c CF	266	if ((dspi->rx_end - dspi->rx) == 1)
	267	break;
	268
1acbdeb9 CF	269	regmap_read(dspi->regmap, SPI_POPR, &val);
1acbdeb9 CF	270	d = SPI_POPR_RXDATA(val);
349ad66c CF	271
	272	if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
	273	(u16 )dspi->rx = d;
	274	dspi->rx += 2;
	275
	276	} else {
1acbdeb9 CF	277	unsigned int val;
	278
	279	regmap_read(dspi->regmap, SPI_POPR, &val);
	280	d = SPI_POPR_RXDATA(val);
349ad66c CF	281	if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
	282	(u8 )dspi->rx = d;
	283	dspi->rx++;
	284	}
	285	rx_count++;
	286	}
	287
	288	return rx_count;
	289	}
	290
9298bc72 CF	291	static int dspi_transfer_one_message(struct spi_master *master,
9298bc72 CF	292	struct spi_message *message)
349ad66c	293	{
9298bc72 CF	294	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	295	struct spi_device *spi = message->spi;
	296	struct spi_transfer *transfer;
	297	int status = 0;
	298	message->actual_length = 0;
	299
	300	list_for_each_entry(transfer, &message->transfers, transfer_list) {
	301	dspi->cur_transfer = transfer;
	302	dspi->cur_msg = message;
	303	dspi->cur_chip = spi_get_ctldata(spi);
	304	dspi->cs = spi->chip_select;
	305	if (dspi->cur_transfer->transfer_list.next
	306	== &dspi->cur_msg->transfers)
	307	transfer->cs_change = 1;
	308	dspi->cs_change = transfer->cs_change;
	309	dspi->void_write_data = dspi->cur_chip->void_write_data;
	310
	311	dspi->dataflags = 0;
	312	dspi->tx = (void *)transfer->tx_buf;
	313	dspi->tx_end = dspi->tx + transfer->len;
	314	dspi->rx = transfer->rx_buf;
	315	dspi->rx_end = dspi->rx + transfer->len;
	316	dspi->len = transfer->len;
	317
	318	if (!dspi->rx)
	319	dspi->dataflags \|= TRAN_STATE_RX_VOID;
	320
	321	if (!dspi->tx)
	322	dspi->dataflags \|= TRAN_STATE_TX_VOID;
	323
	324	regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
	325	regmap_update_bits(dspi->regmap, SPI_MCR,
	326	SPI_MCR_CLR_TXF \| SPI_MCR_CLR_RXF,
	327	SPI_MCR_CLR_TXF \| SPI_MCR_CLR_RXF);
1acbdeb9 CF	328	regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
1acbdeb9 CF	329	dspi->cur_chip->ctar_val);
9298bc72 CF	330	if (transfer->speed_hz)
	331	regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
	332	dspi->cur_chip->ctar_val);
349ad66c	333
9298bc72 CF	334	regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
9298bc72 CF	335	message->actual_length += dspi_transfer_write(dspi);
1acbdeb9	336
9298bc72 CF	337	if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
	338	dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
	339	dspi->waitflags = 0;
349ad66c	340
9298bc72 CF	341	if (transfer->delay_usecs)
9298bc72 CF	342	udelay(transfer->delay_usecs);
349ad66c CF	343	}
349ad66c CF	344
9298bc72 CF	345	message->status = status;
	346	spi_finalize_current_message(master);
	347
	348	return status;
349ad66c CF	349	}
349ad66c CF	350
9298bc72	351	static int dspi_setup(struct spi_device *spi)
349ad66c CF	352	{
	353	struct chip_data *chip;
	354	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
	355	unsigned char br = 0, pbr = 0, fmsz = 0;
	356
ceadfd8d BD	357	if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
	358	fmsz = spi->bits_per_word - 1;
	359	} else {
	360	pr_err("Invalid wordsize\n");
	361	return -ENODEV;
	362	}
	363
349ad66c CF	364	/* Only alloc on first setup */
	365	chip = spi_get_ctldata(spi);
	366	if (chip == NULL) {
973fbce6	367	chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
349ad66c CF	368	if (!chip)
	369	return -ENOMEM;
	370	}
	371
	372	chip->mcr_val = SPI_MCR_MASTER \| SPI_MCR_PCSIS \|
	373	SPI_MCR_CLR_TXF \| SPI_MCR_CLR_RXF;
349ad66c CF	374
	375	chip->void_write_data = 0;
	376
	377	hz_to_spi_baud(&pbr, &br,
	378	spi->max_speed_hz, clk_get_rate(dspi->clk));
	379
	380	chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
	381	\| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
	382	\| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
	383	\| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
	384	\| SPI_CTAR_PBR(pbr)
	385	\| SPI_CTAR_BR(br);
	386
	387	spi_set_ctldata(spi, chip);
	388
	389	return 0;
	390	}
	391
973fbce6 BD	392	static void dspi_cleanup(struct spi_device *spi)
	393	{
	394	struct chip_data chip = spi_get_ctldata((struct spi_device )spi);
	395
	396	dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
	397	spi->master->bus_num, spi->chip_select);
	398
	399	kfree(chip);
	400	}
	401
349ad66c CF	402	static irqreturn_t dspi_interrupt(int irq, void *dev_id)
	403	{
	404	struct fsl_dspi dspi = (struct fsl_dspi )dev_id;
	405
9298bc72	406	struct spi_message *msg = dspi->cur_msg;
349ad66c	407
9298bc72	408	regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
349ad66c CF	409	dspi_transfer_read(dspi);
	410
	411	if (!dspi->len) {
	412	if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
1acbdeb9	413	regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
9298bc72	414	SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
1acbdeb9	415
349ad66c CF	416	dspi->waitflags = 1;
349ad66c CF	417	wake_up_interruptible(&dspi->waitq);
9298bc72 CF	418	} else
9298bc72 CF	419	msg->actual_length += dspi_transfer_write(dspi);
349ad66c CF	420
	421	return IRQ_HANDLED;
	422	}
	423
790d1902	424	static const struct of_device_id fsl_dspi_dt_ids[] = {
349ad66c CF	425	{ .compatible = "fsl,vf610-dspi", .data = NULL, },
	426	{ /* sentinel */ }
	427	};
	428	MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
	429
	430	#ifdef CONFIG_PM_SLEEP
	431	static int dspi_suspend(struct device *dev)
	432	{
	433	struct spi_master *master = dev_get_drvdata(dev);
	434	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	435
	436	spi_master_suspend(master);
	437	clk_disable_unprepare(dspi->clk);
	438
	439	return 0;
	440	}
	441
	442	static int dspi_resume(struct device *dev)
	443	{
349ad66c CF	444	struct spi_master *master = dev_get_drvdata(dev);
	445	struct fsl_dspi *dspi = spi_master_get_devdata(master);
	446
	447	clk_prepare_enable(dspi->clk);
	448	spi_master_resume(master);
	449
	450	return 0;
	451	}
	452	#endif /* CONFIG_PM_SLEEP */
	453
ba811add	454	static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
349ad66c	455
409851c3	456	static const struct regmap_config dspi_regmap_config = {
1acbdeb9 CF	457	.reg_bits = 32,
	458	.val_bits = 32,
	459	.reg_stride = 4,
	460	.max_register = 0x88,
349ad66c CF	461	};
	462
	463	static int dspi_probe(struct platform_device *pdev)
	464	{
	465	struct device_node *np = pdev->dev.of_node;
	466	struct spi_master *master;
	467	struct fsl_dspi *dspi;
	468	struct resource *res;
1acbdeb9	469	void __iomem *base;
349ad66c CF	470	int ret = 0, cs_num, bus_num;
	471
	472	master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
	473	if (!master)
	474	return -ENOMEM;
	475
	476	dspi = spi_master_get_devdata(master);
	477	dspi->pdev = pdev;
9298bc72 CF	478	dspi->master = master;
	479
	480	master->transfer = NULL;
	481	master->setup = dspi_setup;
	482	master->transfer_one_message = dspi_transfer_one_message;
	483	master->dev.of_node = pdev->dev.of_node;
349ad66c	484
973fbce6	485	master->cleanup = dspi_cleanup;
349ad66c CF	486	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	487	master->bits_per_word_mask = SPI_BPW_MASK(4) \| SPI_BPW_MASK(8) \|
	488	SPI_BPW_MASK(16);
	489
	490	ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
	491	if (ret < 0) {
	492	dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
	493	goto out_master_put;
	494	}
	495	master->num_chipselect = cs_num;
	496
	497	ret = of_property_read_u32(np, "bus-num", &bus_num);
	498	if (ret < 0) {
	499	dev_err(&pdev->dev, "can't get bus-num\n");
	500	goto out_master_put;
	501	}
	502	master->bus_num = bus_num;
	503
	504	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1acbdeb9 CF	505	base = devm_ioremap_resource(&pdev->dev, res);
	506	if (IS_ERR(base)) {
	507	ret = PTR_ERR(base);
349ad66c CF	508	goto out_master_put;
	509	}
	510
1acbdeb9 CF	511	dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
	512	&dspi_regmap_config);
	513	if (IS_ERR(dspi->regmap)) {
	514	dev_err(&pdev->dev, "failed to init regmap: %ld\n",
	515	PTR_ERR(dspi->regmap));
	516	return PTR_ERR(dspi->regmap);
	517	}
	518
349ad66c CF	519	dspi->irq = platform_get_irq(pdev, 0);
	520	if (dspi->irq < 0) {
	521	dev_err(&pdev->dev, "can't get platform irq\n");
	522	ret = dspi->irq;
	523	goto out_master_put;
	524	}
	525
	526	ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
	527	pdev->name, dspi);
	528	if (ret < 0) {
	529	dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
	530	goto out_master_put;
	531	}
	532
	533	dspi->clk = devm_clk_get(&pdev->dev, "dspi");
	534	if (IS_ERR(dspi->clk)) {
	535	ret = PTR_ERR(dspi->clk);
	536	dev_err(&pdev->dev, "unable to get clock\n");
	537	goto out_master_put;
	538	}
	539	clk_prepare_enable(dspi->clk);
	540
	541	init_waitqueue_head(&dspi->waitq);
017145fe	542	platform_set_drvdata(pdev, master);
349ad66c	543
9298bc72	544	ret = spi_register_master(master);
349ad66c CF	545	if (ret != 0) {
	546	dev_err(&pdev->dev, "Problem registering DSPI master\n");
	547	goto out_clk_put;
	548	}
	549
349ad66c CF	550	return ret;
	551
	552	out_clk_put:
	553	clk_disable_unprepare(dspi->clk);
	554	out_master_put:
	555	spi_master_put(master);
349ad66c CF	556
	557	return ret;
	558	}
	559
	560	static int dspi_remove(struct platform_device *pdev)
	561	{
017145fe AL	562	struct spi_master *master = platform_get_drvdata(pdev);
017145fe AL	563	struct fsl_dspi *dspi = spi_master_get_devdata(master);
349ad66c CF	564
349ad66c CF	565	/* Disconnect from the SPI framework */
05209f45	566	clk_disable_unprepare(dspi->clk);
9298bc72 CF	567	spi_unregister_master(dspi->master);
9298bc72 CF	568	spi_master_put(dspi->master);
349ad66c CF	569
	570	return 0;
	571	}
	572
	573	static struct platform_driver fsl_dspi_driver = {
	574	.driver.name = DRIVER_NAME,
	575	.driver.of_match_table = fsl_dspi_dt_ids,
	576	.driver.owner = THIS_MODULE,
	577	.driver.pm = &dspi_pm,
	578	.probe = dspi_probe,
	579	.remove = dspi_remove,
	580	};
	581	module_platform_driver(fsl_dspi_driver);
	582
	583	MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
b444d1df	584	MODULE_LICENSE("GPL");
349ad66c	585	MODULE_ALIAS("platform:" DRIVER_NAME);