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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
8b60d6c2 MH |
2 | /* |
3 | * Freescale eSPI controller driver. | |
4 | * | |
5 | * Copyright 2010 Freescale Semiconductor, Inc. | |
8b60d6c2 | 6 | */ |
8b60d6c2 | 7 | #include <linux/delay.h> |
a3108360 | 8 | #include <linux/err.h> |
8b60d6c2 | 9 | #include <linux/fsl_devices.h> |
a3108360 | 10 | #include <linux/interrupt.h> |
a3108360 | 11 | #include <linux/module.h> |
8b60d6c2 MH |
12 | #include <linux/mm.h> |
13 | #include <linux/of.h> | |
5af50730 RH |
14 | #include <linux/of_address.h> |
15 | #include <linux/of_irq.h> | |
8b60d6c2 | 16 | #include <linux/of_platform.h> |
a3108360 XL |
17 | #include <linux/platform_device.h> |
18 | #include <linux/spi/spi.h> | |
e9abb4db | 19 | #include <linux/pm_runtime.h> |
8b60d6c2 MH |
20 | #include <sysdev/fsl_soc.h> |
21 | ||
8b60d6c2 | 22 | /* eSPI Controller registers */ |
46afd38b HK |
23 | #define ESPI_SPMODE 0x00 /* eSPI mode register */ |
24 | #define ESPI_SPIE 0x04 /* eSPI event register */ | |
25 | #define ESPI_SPIM 0x08 /* eSPI mask register */ | |
26 | #define ESPI_SPCOM 0x0c /* eSPI command register */ | |
27 | #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/ | |
28 | #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/ | |
29 | #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */ | |
30 | ||
31 | #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4) | |
8b60d6c2 | 32 | |
8b60d6c2 | 33 | /* eSPI Controller mode register definitions */ |
81abc2ec HK |
34 | #define SPMODE_ENABLE BIT(31) |
35 | #define SPMODE_LOOP BIT(30) | |
8b60d6c2 MH |
36 | #define SPMODE_TXTHR(x) ((x) << 8) |
37 | #define SPMODE_RXTHR(x) ((x) << 0) | |
38 | ||
39 | /* eSPI Controller CS mode register definitions */ | |
81abc2ec HK |
40 | #define CSMODE_CI_INACTIVEHIGH BIT(31) |
41 | #define CSMODE_CP_BEGIN_EDGECLK BIT(30) | |
42 | #define CSMODE_REV BIT(29) | |
43 | #define CSMODE_DIV16 BIT(28) | |
8b60d6c2 | 44 | #define CSMODE_PM(x) ((x) << 24) |
81abc2ec | 45 | #define CSMODE_POL_1 BIT(20) |
8b60d6c2 MH |
46 | #define CSMODE_LEN(x) ((x) << 16) |
47 | #define CSMODE_BEF(x) ((x) << 12) | |
48 | #define CSMODE_AFT(x) ((x) << 8) | |
49 | #define CSMODE_CG(x) ((x) << 3) | |
50 | ||
54731265 | 51 | #define FSL_ESPI_FIFO_SIZE 32 |
e508cea4 | 52 | #define FSL_ESPI_RXTHR 15 |
54731265 | 53 | |
8b60d6c2 | 54 | /* Default mode/csmode for eSPI controller */ |
e508cea4 | 55 | #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR)) |
8b60d6c2 MH |
56 | #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ |
57 | | CSMODE_AFT(0) | CSMODE_CG(1)) | |
58 | ||
59 | /* SPIE register values */ | |
8b60d6c2 MH |
60 | #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) |
61 | #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) | |
81abc2ec HK |
62 | #define SPIE_TXE BIT(15) /* TX FIFO empty */ |
63 | #define SPIE_DON BIT(14) /* TX done */ | |
64 | #define SPIE_RXT BIT(13) /* RX FIFO threshold */ | |
65 | #define SPIE_RXF BIT(12) /* RX FIFO full */ | |
66 | #define SPIE_TXT BIT(11) /* TX FIFO threshold*/ | |
67 | #define SPIE_RNE BIT(9) /* RX FIFO not empty */ | |
68 | #define SPIE_TNF BIT(8) /* TX FIFO not full */ | |
69 | ||
70 | /* SPIM register values */ | |
71 | #define SPIM_TXE BIT(15) /* TX FIFO empty */ | |
72 | #define SPIM_DON BIT(14) /* TX done */ | |
73 | #define SPIM_RXT BIT(13) /* RX FIFO threshold */ | |
74 | #define SPIM_RXF BIT(12) /* RX FIFO full */ | |
75 | #define SPIM_TXT BIT(11) /* TX FIFO threshold*/ | |
76 | #define SPIM_RNE BIT(9) /* RX FIFO not empty */ | |
77 | #define SPIM_TNF BIT(8) /* TX FIFO not full */ | |
8b60d6c2 MH |
78 | |
79 | /* SPCOM register values */ | |
80 | #define SPCOM_CS(x) ((x) << 30) | |
81abc2ec HK |
81 | #define SPCOM_DO BIT(28) /* Dual output */ |
82 | #define SPCOM_TO BIT(27) /* TX only */ | |
83 | #define SPCOM_RXSKIP(x) ((x) << 16) | |
8b60d6c2 | 84 | #define SPCOM_TRANLEN(x) ((x) << 0) |
81abc2ec | 85 | |
5cfa1e4e | 86 | #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */ |
8b60d6c2 | 87 | |
e9abb4db HK |
88 | #define AUTOSUSPEND_TIMEOUT 2000 |
89 | ||
35ab046b HK |
90 | struct fsl_espi { |
91 | struct device *dev; | |
92 | void __iomem *reg_base; | |
93 | ||
05823432 HK |
94 | struct list_head *m_transfers; |
95 | struct spi_transfer *tx_t; | |
96 | unsigned int tx_pos; | |
97 | bool tx_done; | |
dcb425f3 HK |
98 | struct spi_transfer *rx_t; |
99 | unsigned int rx_pos; | |
100 | bool rx_done; | |
05823432 | 101 | |
e1cdee73 | 102 | bool swab; |
35ab046b HK |
103 | unsigned int rxskip; |
104 | ||
35ab046b HK |
105 | spinlock_t lock; |
106 | ||
107 | u32 spibrg; /* SPIBRG input clock */ | |
108 | ||
109 | struct completion done; | |
110 | }; | |
111 | ||
219b5e3b HK |
112 | struct fsl_espi_cs { |
113 | u32 hw_mode; | |
114 | }; | |
115 | ||
35ab046b | 116 | static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset) |
46afd38b | 117 | { |
35ab046b | 118 | return ioread32be(espi->reg_base + offset); |
46afd38b HK |
119 | } |
120 | ||
dcb425f3 HK |
121 | static inline u16 fsl_espi_read_reg16(struct fsl_espi *espi, int offset) |
122 | { | |
7e2ef003 | 123 | return ioread16be(espi->reg_base + offset); |
dcb425f3 HK |
124 | } |
125 | ||
35ab046b | 126 | static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset) |
46afd38b | 127 | { |
35ab046b | 128 | return ioread8(espi->reg_base + offset); |
46afd38b HK |
129 | } |
130 | ||
35ab046b | 131 | static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset, |
46afd38b HK |
132 | u32 val) |
133 | { | |
35ab046b | 134 | iowrite32be(val, espi->reg_base + offset); |
46afd38b HK |
135 | } |
136 | ||
05823432 HK |
137 | static inline void fsl_espi_write_reg16(struct fsl_espi *espi, int offset, |
138 | u16 val) | |
139 | { | |
7e2ef003 | 140 | iowrite16be(val, espi->reg_base + offset); |
05823432 HK |
141 | } |
142 | ||
35ab046b | 143 | static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset, |
46afd38b HK |
144 | u8 val) |
145 | { | |
35ab046b | 146 | iowrite8(val, espi->reg_base + offset); |
46afd38b HK |
147 | } |
148 | ||
d3152cf1 HK |
149 | static int fsl_espi_check_message(struct spi_message *m) |
150 | { | |
35ab046b | 151 | struct fsl_espi *espi = spi_master_get_devdata(m->spi->master); |
d3152cf1 HK |
152 | struct spi_transfer *t, *first; |
153 | ||
154 | if (m->frame_length > SPCOM_TRANLEN_MAX) { | |
35ab046b | 155 | dev_err(espi->dev, "message too long, size is %u bytes\n", |
d3152cf1 HK |
156 | m->frame_length); |
157 | return -EMSGSIZE; | |
158 | } | |
159 | ||
160 | first = list_first_entry(&m->transfers, struct spi_transfer, | |
161 | transfer_list); | |
e4be7053 | 162 | |
d3152cf1 HK |
163 | list_for_each_entry(t, &m->transfers, transfer_list) { |
164 | if (first->bits_per_word != t->bits_per_word || | |
165 | first->speed_hz != t->speed_hz) { | |
35ab046b | 166 | dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n"); |
d3152cf1 HK |
167 | return -EINVAL; |
168 | } | |
169 | } | |
170 | ||
e4be7053 HK |
171 | /* ESPI supports MSB-first transfers for word size 8 / 16 only */ |
172 | if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 && | |
173 | first->bits_per_word != 16) { | |
35ab046b | 174 | dev_err(espi->dev, |
e4be7053 HK |
175 | "MSB-first transfer not supported for wordsize %u\n", |
176 | first->bits_per_word); | |
177 | return -EINVAL; | |
178 | } | |
179 | ||
d3152cf1 HK |
180 | return 0; |
181 | } | |
182 | ||
aca75157 HK |
183 | static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m) |
184 | { | |
185 | struct spi_transfer *t; | |
186 | unsigned int i = 0, rxskip = 0; | |
187 | ||
188 | /* | |
189 | * prerequisites for ESPI rxskip mode: | |
190 | * - message has two transfers | |
191 | * - first transfer is a write and second is a read | |
192 | * | |
193 | * In addition the current low-level transfer mechanism requires | |
194 | * that the rxskip bytes fit into the TX FIFO. Else the transfer | |
195 | * would hang because after the first FSL_ESPI_FIFO_SIZE bytes | |
196 | * the TX FIFO isn't re-filled. | |
197 | */ | |
198 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
199 | if (i == 0) { | |
200 | if (!t->tx_buf || t->rx_buf || | |
201 | t->len > FSL_ESPI_FIFO_SIZE) | |
202 | return 0; | |
203 | rxskip = t->len; | |
204 | } else if (i == 1) { | |
205 | if (t->tx_buf || !t->rx_buf) | |
206 | return 0; | |
207 | } | |
208 | i++; | |
209 | } | |
210 | ||
211 | return i == 2 ? rxskip : 0; | |
212 | } | |
213 | ||
35ab046b | 214 | static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events) |
54731265 HK |
215 | { |
216 | u32 tx_fifo_avail; | |
05823432 HK |
217 | unsigned int tx_left; |
218 | const void *tx_buf; | |
54731265 HK |
219 | |
220 | /* if events is zero transfer has not started and tx fifo is empty */ | |
221 | tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE; | |
05823432 HK |
222 | start: |
223 | tx_left = espi->tx_t->len - espi->tx_pos; | |
224 | tx_buf = espi->tx_t->tx_buf; | |
225 | while (tx_fifo_avail >= min(4U, tx_left) && tx_left) { | |
226 | if (tx_left >= 4) { | |
227 | if (!tx_buf) | |
228 | fsl_espi_write_reg(espi, ESPI_SPITF, 0); | |
229 | else if (espi->swab) | |
230 | fsl_espi_write_reg(espi, ESPI_SPITF, | |
231 | swahb32p(tx_buf + espi->tx_pos)); | |
232 | else | |
233 | fsl_espi_write_reg(espi, ESPI_SPITF, | |
234 | *(u32 *)(tx_buf + espi->tx_pos)); | |
235 | espi->tx_pos += 4; | |
236 | tx_left -= 4; | |
54731265 | 237 | tx_fifo_avail -= 4; |
05823432 HK |
238 | } else if (tx_left >= 2 && tx_buf && espi->swab) { |
239 | fsl_espi_write_reg16(espi, ESPI_SPITF, | |
240 | swab16p(tx_buf + espi->tx_pos)); | |
241 | espi->tx_pos += 2; | |
242 | tx_left -= 2; | |
243 | tx_fifo_avail -= 2; | |
54731265 | 244 | } else { |
05823432 HK |
245 | if (!tx_buf) |
246 | fsl_espi_write_reg8(espi, ESPI_SPITF, 0); | |
247 | else | |
248 | fsl_espi_write_reg8(espi, ESPI_SPITF, | |
249 | *(u8 *)(tx_buf + espi->tx_pos)); | |
250 | espi->tx_pos += 1; | |
251 | tx_left -= 1; | |
54731265 HK |
252 | tx_fifo_avail -= 1; |
253 | } | |
05823432 HK |
254 | } |
255 | ||
256 | if (!tx_left) { | |
257 | /* Last transfer finished, in rxskip mode only one is needed */ | |
258 | if (list_is_last(&espi->tx_t->transfer_list, | |
259 | espi->m_transfers) || espi->rxskip) { | |
260 | espi->tx_done = true; | |
261 | return; | |
262 | } | |
263 | espi->tx_t = list_next_entry(espi->tx_t, transfer_list); | |
264 | espi->tx_pos = 0; | |
265 | /* continue with next transfer if tx fifo is not full */ | |
266 | if (tx_fifo_avail) | |
267 | goto start; | |
268 | } | |
54731265 HK |
269 | } |
270 | ||
35ab046b | 271 | static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events) |
f05689a6 HK |
272 | { |
273 | u32 rx_fifo_avail = SPIE_RXCNT(events); | |
dcb425f3 HK |
274 | unsigned int rx_left; |
275 | void *rx_buf; | |
f05689a6 | 276 | |
dcb425f3 HK |
277 | start: |
278 | rx_left = espi->rx_t->len - espi->rx_pos; | |
279 | rx_buf = espi->rx_t->rx_buf; | |
280 | while (rx_fifo_avail >= min(4U, rx_left) && rx_left) { | |
281 | if (rx_left >= 4) { | |
282 | u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF); | |
283 | ||
284 | if (rx_buf && espi->swab) | |
285 | *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val); | |
286 | else if (rx_buf) | |
287 | *(u32 *)(rx_buf + espi->rx_pos) = val; | |
288 | espi->rx_pos += 4; | |
289 | rx_left -= 4; | |
f05689a6 | 290 | rx_fifo_avail -= 4; |
dcb425f3 HK |
291 | } else if (rx_left >= 2 && rx_buf && espi->swab) { |
292 | u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF); | |
293 | ||
294 | *(u16 *)(rx_buf + espi->rx_pos) = swab16(val); | |
295 | espi->rx_pos += 2; | |
296 | rx_left -= 2; | |
297 | rx_fifo_avail -= 2; | |
f05689a6 | 298 | } else { |
dcb425f3 HK |
299 | u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF); |
300 | ||
301 | if (rx_buf) | |
302 | *(u8 *)(rx_buf + espi->rx_pos) = val; | |
303 | espi->rx_pos += 1; | |
304 | rx_left -= 1; | |
f05689a6 HK |
305 | rx_fifo_avail -= 1; |
306 | } | |
dcb425f3 HK |
307 | } |
308 | ||
309 | if (!rx_left) { | |
310 | if (list_is_last(&espi->rx_t->transfer_list, | |
311 | espi->m_transfers)) { | |
312 | espi->rx_done = true; | |
313 | return; | |
314 | } | |
315 | espi->rx_t = list_next_entry(espi->rx_t, transfer_list); | |
316 | espi->rx_pos = 0; | |
317 | /* continue with next transfer if rx fifo is not empty */ | |
318 | if (rx_fifo_avail) | |
319 | goto start; | |
320 | } | |
f05689a6 HK |
321 | } |
322 | ||
ea616ee2 | 323 | static void fsl_espi_setup_transfer(struct spi_device *spi, |
8b60d6c2 MH |
324 | struct spi_transfer *t) |
325 | { | |
35ab046b | 326 | struct fsl_espi *espi = spi_master_get_devdata(spi->master); |
d198ebfb | 327 | int bits_per_word = t ? t->bits_per_word : spi->bits_per_word; |
73aaf158 | 328 | u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz; |
219b5e3b | 329 | struct fsl_espi_cs *cs = spi_get_ctldata(spi); |
8f3086d2 | 330 | u32 hw_mode_old = cs->hw_mode; |
8b60d6c2 | 331 | |
8b60d6c2 MH |
332 | /* mask out bits we are going to set */ |
333 | cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); | |
334 | ||
a755af52 | 335 | cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); |
8b60d6c2 | 336 | |
35ab046b | 337 | pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1; |
73aaf158 PZ |
338 | |
339 | if (pm > 15) { | |
8b60d6c2 | 340 | cs->hw_mode |= CSMODE_DIV16; |
35ab046b | 341 | pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1; |
8b60d6c2 | 342 | } |
8b60d6c2 MH |
343 | |
344 | cs->hw_mode |= CSMODE_PM(pm); | |
345 | ||
8f3086d2 HK |
346 | /* don't write the mode register if the mode doesn't change */ |
347 | if (cs->hw_mode != hw_mode_old) | |
35ab046b | 348 | fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select), |
8f3086d2 | 349 | cs->hw_mode); |
8b60d6c2 MH |
350 | } |
351 | ||
8b60d6c2 MH |
352 | static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) |
353 | { | |
35ab046b | 354 | struct fsl_espi *espi = spi_master_get_devdata(spi->master); |
dcb425f3 | 355 | unsigned int rx_len = t->len; |
aca75157 | 356 | u32 mask, spcom; |
8b60d6c2 MH |
357 | int ret; |
358 | ||
35ab046b | 359 | reinit_completion(&espi->done); |
8b60d6c2 MH |
360 | |
361 | /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ | |
aca75157 HK |
362 | spcom = SPCOM_CS(spi->chip_select); |
363 | spcom |= SPCOM_TRANLEN(t->len - 1); | |
364 | ||
365 | /* configure RXSKIP mode */ | |
35ab046b HK |
366 | if (espi->rxskip) { |
367 | spcom |= SPCOM_RXSKIP(espi->rxskip); | |
dcb425f3 | 368 | rx_len = t->len - espi->rxskip; |
8263cb33 HK |
369 | if (t->rx_nbits == SPI_NBITS_DUAL) |
370 | spcom |= SPCOM_DO; | |
aca75157 HK |
371 | } |
372 | ||
35ab046b | 373 | fsl_espi_write_reg(espi, ESPI_SPCOM, spcom); |
8b60d6c2 | 374 | |
e508cea4 HK |
375 | /* enable interrupts */ |
376 | mask = SPIM_DON; | |
dcb425f3 | 377 | if (rx_len > FSL_ESPI_FIFO_SIZE) |
e508cea4 | 378 | mask |= SPIM_RXT; |
35ab046b | 379 | fsl_espi_write_reg(espi, ESPI_SPIM, mask); |
5bcc6a2f | 380 | |
54731265 | 381 | /* Prevent filling the fifo from getting interrupted */ |
35ab046b HK |
382 | spin_lock_irq(&espi->lock); |
383 | fsl_espi_fill_tx_fifo(espi, 0); | |
384 | spin_unlock_irq(&espi->lock); | |
8b60d6c2 | 385 | |
aa70e567 | 386 | /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ |
35ab046b | 387 | ret = wait_for_completion_timeout(&espi->done, 2 * HZ); |
aa70e567 | 388 | if (ret == 0) |
05823432 | 389 | dev_err(espi->dev, "Transfer timed out!\n"); |
8b60d6c2 MH |
390 | |
391 | /* disable rx ints */ | |
35ab046b | 392 | fsl_espi_write_reg(espi, ESPI_SPIM, 0); |
8b60d6c2 | 393 | |
db1b049f | 394 | return ret == 0 ? -ETIMEDOUT : 0; |
8b60d6c2 MH |
395 | } |
396 | ||
38d003f1 | 397 | static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans) |
8b60d6c2 | 398 | { |
35ab046b | 399 | struct fsl_espi *espi = spi_master_get_devdata(m->spi->master); |
8b60d6c2 | 400 | struct spi_device *spi = m->spi; |
38d003f1 | 401 | int ret; |
8b60d6c2 | 402 | |
e1cdee73 HK |
403 | /* In case of LSB-first and bits_per_word > 8 byte-swap all words */ |
404 | espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8; | |
405 | ||
05823432 HK |
406 | espi->m_transfers = &m->transfers; |
407 | espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer, | |
408 | transfer_list); | |
409 | espi->tx_pos = 0; | |
410 | espi->tx_done = false; | |
dcb425f3 HK |
411 | espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer, |
412 | transfer_list); | |
413 | espi->rx_pos = 0; | |
414 | espi->rx_done = false; | |
05823432 | 415 | |
35ab046b HK |
416 | espi->rxskip = fsl_espi_check_rxskip_mode(m); |
417 | if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) { | |
418 | dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n"); | |
8263cb33 HK |
419 | return -EINVAL; |
420 | } | |
421 | ||
dcb425f3 HK |
422 | /* In RXSKIP mode skip first transfer for reads */ |
423 | if (espi->rxskip) | |
424 | espi->rx_t = list_next_entry(espi->rx_t, transfer_list); | |
425 | ||
faceef39 | 426 | fsl_espi_setup_transfer(spi, trans); |
8b60d6c2 | 427 | |
06af115d | 428 | ret = fsl_espi_bufs(spi, trans); |
8b60d6c2 | 429 | |
faceef39 HK |
430 | if (trans->delay_usecs) |
431 | udelay(trans->delay_usecs); | |
8b60d6c2 | 432 | |
e33a3ade | 433 | return ret; |
8b60d6c2 MH |
434 | } |
435 | ||
c592becb HK |
436 | static int fsl_espi_do_one_msg(struct spi_master *master, |
437 | struct spi_message *m) | |
8b60d6c2 | 438 | { |
8263cb33 | 439 | unsigned int delay_usecs = 0, rx_nbits = 0; |
faceef39 | 440 | struct spi_transfer *t, trans = {}; |
e33a3ade | 441 | int ret; |
8b60d6c2 | 442 | |
d3152cf1 HK |
443 | ret = fsl_espi_check_message(m); |
444 | if (ret) | |
445 | goto out; | |
446 | ||
8b60d6c2 | 447 | list_for_each_entry(t, &m->transfers, transfer_list) { |
96361faf HK |
448 | if (t->delay_usecs > delay_usecs) |
449 | delay_usecs = t->delay_usecs; | |
8263cb33 HK |
450 | if (t->rx_nbits > rx_nbits) |
451 | rx_nbits = t->rx_nbits; | |
8b60d6c2 MH |
452 | } |
453 | ||
96361faf HK |
454 | t = list_first_entry(&m->transfers, struct spi_transfer, |
455 | transfer_list); | |
456 | ||
06af115d | 457 | trans.len = m->frame_length; |
96361faf HK |
458 | trans.speed_hz = t->speed_hz; |
459 | trans.bits_per_word = t->bits_per_word; | |
460 | trans.delay_usecs = delay_usecs; | |
8263cb33 | 461 | trans.rx_nbits = rx_nbits; |
8b60d6c2 | 462 | |
06af115d HK |
463 | if (trans.len) |
464 | ret = fsl_espi_trans(m, &trans); | |
8b60d6c2 | 465 | |
faceef39 | 466 | m->actual_length = ret ? 0 : trans.len; |
d3152cf1 | 467 | out: |
0319d499 HK |
468 | if (m->status == -EINPROGRESS) |
469 | m->status = ret; | |
470 | ||
c592becb | 471 | spi_finalize_current_message(master); |
0319d499 HK |
472 | |
473 | return ret; | |
8b60d6c2 MH |
474 | } |
475 | ||
476 | static int fsl_espi_setup(struct spi_device *spi) | |
477 | { | |
35ab046b | 478 | struct fsl_espi *espi; |
8b60d6c2 | 479 | u32 loop_mode; |
219b5e3b | 480 | struct fsl_espi_cs *cs = spi_get_ctldata(spi); |
8b60d6c2 | 481 | |
8b60d6c2 | 482 | if (!cs) { |
d9f26748 | 483 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
8b60d6c2 MH |
484 | if (!cs) |
485 | return -ENOMEM; | |
d9f26748 | 486 | spi_set_ctldata(spi, cs); |
8b60d6c2 MH |
487 | } |
488 | ||
35ab046b | 489 | espi = spi_master_get_devdata(spi->master); |
8b60d6c2 | 490 | |
35ab046b | 491 | pm_runtime_get_sync(espi->dev); |
e9abb4db | 492 | |
35ab046b | 493 | cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select)); |
8b60d6c2 MH |
494 | /* mask out bits we are going to set */ |
495 | cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH | |
496 | | CSMODE_REV); | |
497 | ||
498 | if (spi->mode & SPI_CPHA) | |
499 | cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; | |
500 | if (spi->mode & SPI_CPOL) | |
501 | cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; | |
502 | if (!(spi->mode & SPI_LSB_FIRST)) | |
503 | cs->hw_mode |= CSMODE_REV; | |
504 | ||
505 | /* Handle the loop mode */ | |
35ab046b | 506 | loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE); |
8b60d6c2 MH |
507 | loop_mode &= ~SPMODE_LOOP; |
508 | if (spi->mode & SPI_LOOP) | |
509 | loop_mode |= SPMODE_LOOP; | |
35ab046b | 510 | fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode); |
8b60d6c2 | 511 | |
ea616ee2 | 512 | fsl_espi_setup_transfer(spi, NULL); |
e9abb4db | 513 | |
35ab046b HK |
514 | pm_runtime_mark_last_busy(espi->dev); |
515 | pm_runtime_put_autosuspend(espi->dev); | |
e9abb4db | 516 | |
8b60d6c2 MH |
517 | return 0; |
518 | } | |
519 | ||
d9f26748 AL |
520 | static void fsl_espi_cleanup(struct spi_device *spi) |
521 | { | |
219b5e3b | 522 | struct fsl_espi_cs *cs = spi_get_ctldata(spi); |
d9f26748 AL |
523 | |
524 | kfree(cs); | |
525 | spi_set_ctldata(spi, NULL); | |
526 | } | |
527 | ||
35ab046b | 528 | static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events) |
8b60d6c2 | 529 | { |
dcb425f3 | 530 | if (!espi->rx_done) |
35ab046b | 531 | fsl_espi_read_rx_fifo(espi, events); |
8b60d6c2 | 532 | |
05823432 | 533 | if (!espi->tx_done) |
35ab046b | 534 | fsl_espi_fill_tx_fifo(espi, events); |
8b60d6c2 | 535 | |
dcb425f3 | 536 | if (!espi->tx_done || !espi->rx_done) |
db1b049f HK |
537 | return; |
538 | ||
539 | /* we're done, but check for errors before returning */ | |
35ab046b | 540 | events = fsl_espi_read_reg(espi, ESPI_SPIE); |
db1b049f HK |
541 | |
542 | if (!(events & SPIE_DON)) | |
35ab046b | 543 | dev_err(espi->dev, |
db1b049f HK |
544 | "Transfer done but SPIE_DON isn't set!\n"); |
545 | ||
516ddd79 | 546 | if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) { |
35ab046b | 547 | dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n"); |
516ddd79 TB |
548 | dev_err(espi->dev, "SPIE_RXCNT = %d, SPIE_TXCNT = %d\n", |
549 | SPIE_RXCNT(events), SPIE_TXCNT(events)); | |
550 | } | |
db1b049f | 551 | |
35ab046b | 552 | complete(&espi->done); |
8b60d6c2 MH |
553 | } |
554 | ||
555 | static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) | |
556 | { | |
35ab046b | 557 | struct fsl_espi *espi = context_data; |
8b60d6c2 MH |
558 | u32 events; |
559 | ||
35ab046b | 560 | spin_lock(&espi->lock); |
54731265 | 561 | |
8b60d6c2 | 562 | /* Get interrupt events(tx/rx) */ |
35ab046b | 563 | events = fsl_espi_read_reg(espi, ESPI_SPIE); |
54731265 | 564 | if (!events) { |
35ab046b | 565 | spin_unlock(&espi->lock); |
35f5d71e | 566 | return IRQ_NONE; |
54731265 | 567 | } |
8b60d6c2 | 568 | |
35ab046b | 569 | dev_vdbg(espi->dev, "%s: events %x\n", __func__, events); |
8b60d6c2 | 570 | |
35ab046b | 571 | fsl_espi_cpu_irq(espi, events); |
8b60d6c2 | 572 | |
35f5d71e | 573 | /* Clear the events */ |
35ab046b | 574 | fsl_espi_write_reg(espi, ESPI_SPIE, events); |
35f5d71e | 575 | |
35ab046b | 576 | spin_unlock(&espi->lock); |
54731265 | 577 | |
35f5d71e | 578 | return IRQ_HANDLED; |
8b60d6c2 MH |
579 | } |
580 | ||
e9abb4db HK |
581 | #ifdef CONFIG_PM |
582 | static int fsl_espi_runtime_suspend(struct device *dev) | |
75506d0e | 583 | { |
e9abb4db | 584 | struct spi_master *master = dev_get_drvdata(dev); |
35ab046b | 585 | struct fsl_espi *espi = spi_master_get_devdata(master); |
75506d0e HK |
586 | u32 regval; |
587 | ||
35ab046b | 588 | regval = fsl_espi_read_reg(espi, ESPI_SPMODE); |
75506d0e | 589 | regval &= ~SPMODE_ENABLE; |
35ab046b | 590 | fsl_espi_write_reg(espi, ESPI_SPMODE, regval); |
75506d0e HK |
591 | |
592 | return 0; | |
593 | } | |
594 | ||
e9abb4db | 595 | static int fsl_espi_runtime_resume(struct device *dev) |
75506d0e | 596 | { |
e9abb4db | 597 | struct spi_master *master = dev_get_drvdata(dev); |
35ab046b | 598 | struct fsl_espi *espi = spi_master_get_devdata(master); |
75506d0e HK |
599 | u32 regval; |
600 | ||
35ab046b | 601 | regval = fsl_espi_read_reg(espi, ESPI_SPMODE); |
75506d0e | 602 | regval |= SPMODE_ENABLE; |
35ab046b | 603 | fsl_espi_write_reg(espi, ESPI_SPMODE, regval); |
75506d0e HK |
604 | |
605 | return 0; | |
606 | } | |
e9abb4db | 607 | #endif |
75506d0e | 608 | |
02a595d5 | 609 | static size_t fsl_espi_max_message_size(struct spi_device *spi) |
b541eef1 MS |
610 | { |
611 | return SPCOM_TRANLEN_MAX; | |
612 | } | |
613 | ||
456c742b HK |
614 | static void fsl_espi_init_regs(struct device *dev, bool initial) |
615 | { | |
616 | struct spi_master *master = dev_get_drvdata(dev); | |
35ab046b | 617 | struct fsl_espi *espi = spi_master_get_devdata(master); |
456c742b HK |
618 | struct device_node *nc; |
619 | u32 csmode, cs, prop; | |
620 | int ret; | |
621 | ||
622 | /* SPI controller initializations */ | |
35ab046b HK |
623 | fsl_espi_write_reg(espi, ESPI_SPMODE, 0); |
624 | fsl_espi_write_reg(espi, ESPI_SPIM, 0); | |
625 | fsl_espi_write_reg(espi, ESPI_SPCOM, 0); | |
626 | fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff); | |
456c742b HK |
627 | |
628 | /* Init eSPI CS mode register */ | |
629 | for_each_available_child_of_node(master->dev.of_node, nc) { | |
630 | /* get chip select */ | |
631 | ret = of_property_read_u32(nc, "reg", &cs); | |
632 | if (ret || cs >= master->num_chipselect) | |
633 | continue; | |
634 | ||
635 | csmode = CSMODE_INIT_VAL; | |
636 | ||
637 | /* check if CSBEF is set in device tree */ | |
638 | ret = of_property_read_u32(nc, "fsl,csbef", &prop); | |
639 | if (!ret) { | |
640 | csmode &= ~(CSMODE_BEF(0xf)); | |
641 | csmode |= CSMODE_BEF(prop); | |
642 | } | |
643 | ||
644 | /* check if CSAFT is set in device tree */ | |
645 | ret = of_property_read_u32(nc, "fsl,csaft", &prop); | |
646 | if (!ret) { | |
647 | csmode &= ~(CSMODE_AFT(0xf)); | |
648 | csmode |= CSMODE_AFT(prop); | |
649 | } | |
650 | ||
35ab046b | 651 | fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode); |
456c742b HK |
652 | |
653 | if (initial) | |
654 | dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode); | |
655 | } | |
656 | ||
657 | /* Enable SPI interface */ | |
35ab046b | 658 | fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE); |
456c742b HK |
659 | } |
660 | ||
604042af | 661 | static int fsl_espi_probe(struct device *dev, struct resource *mem, |
7454346b | 662 | unsigned int irq, unsigned int num_cs) |
8b60d6c2 | 663 | { |
8b60d6c2 | 664 | struct spi_master *master; |
35ab046b | 665 | struct fsl_espi *espi; |
b497eb02 | 666 | int ret; |
8b60d6c2 | 667 | |
35ab046b | 668 | master = spi_alloc_master(dev, sizeof(struct fsl_espi)); |
604042af HK |
669 | if (!master) |
670 | return -ENOMEM; | |
8b60d6c2 MH |
671 | |
672 | dev_set_drvdata(dev, master); | |
673 | ||
7cb55577 HK |
674 | master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | |
675 | SPI_LSB_FIRST | SPI_LOOP; | |
676 | master->dev.of_node = dev->of_node; | |
24778be2 | 677 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
8b60d6c2 | 678 | master->setup = fsl_espi_setup; |
d9f26748 | 679 | master->cleanup = fsl_espi_cleanup; |
c592becb | 680 | master->transfer_one_message = fsl_espi_do_one_msg; |
e9abb4db | 681 | master->auto_runtime_pm = true; |
02a595d5 | 682 | master->max_message_size = fsl_espi_max_message_size; |
7454346b | 683 | master->num_chipselect = num_cs; |
8b60d6c2 | 684 | |
35ab046b HK |
685 | espi = spi_master_get_devdata(master); |
686 | spin_lock_init(&espi->lock); | |
8b60d6c2 | 687 | |
35ab046b HK |
688 | espi->dev = dev; |
689 | espi->spibrg = fsl_get_sys_freq(); | |
690 | if (espi->spibrg == -1) { | |
7cb55577 HK |
691 | dev_err(dev, "Can't get sys frequency!\n"); |
692 | ret = -EINVAL; | |
693 | goto err_probe; | |
694 | } | |
f254e65c HK |
695 | /* determined by clock divider fields DIV16/PM in register SPMODEx */ |
696 | master->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16); | |
697 | master->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4); | |
7cb55577 | 698 | |
35ab046b | 699 | init_completion(&espi->done); |
7cb55577 | 700 | |
35ab046b HK |
701 | espi->reg_base = devm_ioremap_resource(dev, mem); |
702 | if (IS_ERR(espi->reg_base)) { | |
703 | ret = PTR_ERR(espi->reg_base); | |
8b60d6c2 MH |
704 | goto err_probe; |
705 | } | |
706 | ||
8b60d6c2 | 707 | /* Register for SPI Interrupt */ |
35ab046b | 708 | ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi); |
8b60d6c2 | 709 | if (ret) |
4178b6b1 | 710 | goto err_probe; |
8b60d6c2 | 711 | |
456c742b | 712 | fsl_espi_init_regs(dev, true); |
8b60d6c2 | 713 | |
e9abb4db HK |
714 | pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT); |
715 | pm_runtime_use_autosuspend(dev); | |
716 | pm_runtime_set_active(dev); | |
717 | pm_runtime_enable(dev); | |
718 | pm_runtime_get_sync(dev); | |
719 | ||
4178b6b1 | 720 | ret = devm_spi_register_master(dev, master); |
8b60d6c2 | 721 | if (ret < 0) |
e9abb4db | 722 | goto err_pm; |
8b60d6c2 | 723 | |
35ab046b | 724 | dev_info(dev, "at 0x%p (irq = %u)\n", espi->reg_base, irq); |
8b60d6c2 | 725 | |
e9abb4db HK |
726 | pm_runtime_mark_last_busy(dev); |
727 | pm_runtime_put_autosuspend(dev); | |
728 | ||
604042af | 729 | return 0; |
8b60d6c2 | 730 | |
e9abb4db HK |
731 | err_pm: |
732 | pm_runtime_put_noidle(dev); | |
733 | pm_runtime_disable(dev); | |
734 | pm_runtime_set_suspended(dev); | |
8b60d6c2 MH |
735 | err_probe: |
736 | spi_master_put(master); | |
604042af | 737 | return ret; |
8b60d6c2 MH |
738 | } |
739 | ||
740 | static int of_fsl_espi_get_chipselects(struct device *dev) | |
741 | { | |
742 | struct device_node *np = dev->of_node; | |
b497eb02 HK |
743 | u32 num_cs; |
744 | int ret; | |
8b60d6c2 | 745 | |
b497eb02 HK |
746 | ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs); |
747 | if (ret) { | |
8b60d6c2 | 748 | dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); |
7454346b | 749 | return 0; |
8b60d6c2 MH |
750 | } |
751 | ||
7454346b | 752 | return num_cs; |
8b60d6c2 MH |
753 | } |
754 | ||
fd4a319b | 755 | static int of_fsl_espi_probe(struct platform_device *ofdev) |
8b60d6c2 MH |
756 | { |
757 | struct device *dev = &ofdev->dev; | |
758 | struct device_node *np = ofdev->dev.of_node; | |
8b60d6c2 | 759 | struct resource mem; |
7454346b | 760 | unsigned int irq, num_cs; |
acf69219 | 761 | int ret; |
8b60d6c2 | 762 | |
e3ce4f44 HK |
763 | if (of_property_read_bool(np, "mode")) { |
764 | dev_err(dev, "mode property is not supported on ESPI!\n"); | |
765 | return -EINVAL; | |
766 | } | |
767 | ||
7454346b HK |
768 | num_cs = of_fsl_espi_get_chipselects(dev); |
769 | if (!num_cs) | |
770 | return -EINVAL; | |
8b60d6c2 MH |
771 | |
772 | ret = of_address_to_resource(np, 0, &mem); | |
773 | if (ret) | |
acf69219 | 774 | return ret; |
8b60d6c2 | 775 | |
f7578496 | 776 | irq = irq_of_parse_and_map(np, 0); |
acf69219 HK |
777 | if (!irq) |
778 | return -EINVAL; | |
8b60d6c2 | 779 | |
7454346b | 780 | return fsl_espi_probe(dev, &mem, irq, num_cs); |
8b60d6c2 MH |
781 | } |
782 | ||
e9abb4db HK |
783 | static int of_fsl_espi_remove(struct platform_device *dev) |
784 | { | |
785 | pm_runtime_disable(&dev->dev); | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
714bb654 HZ |
790 | #ifdef CONFIG_PM_SLEEP |
791 | static int of_fsl_espi_suspend(struct device *dev) | |
792 | { | |
793 | struct spi_master *master = dev_get_drvdata(dev); | |
714bb654 HZ |
794 | int ret; |
795 | ||
714bb654 | 796 | ret = spi_master_suspend(master); |
7c5d8a24 | 797 | if (ret) |
714bb654 | 798 | return ret; |
714bb654 | 799 | |
a9a813dd | 800 | return pm_runtime_force_suspend(dev); |
714bb654 HZ |
801 | } |
802 | ||
803 | static int of_fsl_espi_resume(struct device *dev) | |
804 | { | |
714bb654 | 805 | struct spi_master *master = dev_get_drvdata(dev); |
456c742b | 806 | int ret; |
714bb654 | 807 | |
456c742b | 808 | fsl_espi_init_regs(dev, false); |
714bb654 | 809 | |
e9abb4db HK |
810 | ret = pm_runtime_force_resume(dev); |
811 | if (ret < 0) | |
812 | return ret; | |
813 | ||
714bb654 HZ |
814 | return spi_master_resume(master); |
815 | } | |
816 | #endif /* CONFIG_PM_SLEEP */ | |
817 | ||
818 | static const struct dev_pm_ops espi_pm = { | |
e9abb4db HK |
819 | SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend, |
820 | fsl_espi_runtime_resume, NULL) | |
714bb654 HZ |
821 | SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) |
822 | }; | |
823 | ||
8b60d6c2 MH |
824 | static const struct of_device_id of_fsl_espi_match[] = { |
825 | { .compatible = "fsl,mpc8536-espi" }, | |
826 | {} | |
827 | }; | |
828 | MODULE_DEVICE_TABLE(of, of_fsl_espi_match); | |
829 | ||
18d306d1 | 830 | static struct platform_driver fsl_espi_driver = { |
8b60d6c2 MH |
831 | .driver = { |
832 | .name = "fsl_espi", | |
8b60d6c2 | 833 | .of_match_table = of_fsl_espi_match, |
714bb654 | 834 | .pm = &espi_pm, |
8b60d6c2 MH |
835 | }, |
836 | .probe = of_fsl_espi_probe, | |
e9abb4db | 837 | .remove = of_fsl_espi_remove, |
8b60d6c2 | 838 | }; |
940ab889 | 839 | module_platform_driver(fsl_espi_driver); |
8b60d6c2 MH |
840 | |
841 | MODULE_AUTHOR("Mingkai Hu"); | |
842 | MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); | |
843 | MODULE_LICENSE("GPL"); |