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Commit | Line | Data |
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8b60d6c2 MH |
1 | /* |
2 | * Freescale eSPI controller driver. | |
3 | * | |
4 | * Copyright 2010 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
8b60d6c2 | 11 | #include <linux/delay.h> |
a3108360 | 12 | #include <linux/err.h> |
8b60d6c2 | 13 | #include <linux/fsl_devices.h> |
a3108360 | 14 | #include <linux/interrupt.h> |
a3108360 | 15 | #include <linux/module.h> |
8b60d6c2 MH |
16 | #include <linux/mm.h> |
17 | #include <linux/of.h> | |
5af50730 RH |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_irq.h> | |
8b60d6c2 | 20 | #include <linux/of_platform.h> |
a3108360 XL |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spi/spi.h> | |
e9abb4db | 23 | #include <linux/pm_runtime.h> |
8b60d6c2 MH |
24 | #include <sysdev/fsl_soc.h> |
25 | ||
ca632f55 | 26 | #include "spi-fsl-lib.h" |
8b60d6c2 MH |
27 | |
28 | /* eSPI Controller registers */ | |
46afd38b HK |
29 | #define ESPI_SPMODE 0x00 /* eSPI mode register */ |
30 | #define ESPI_SPIE 0x04 /* eSPI event register */ | |
31 | #define ESPI_SPIM 0x08 /* eSPI mask register */ | |
32 | #define ESPI_SPCOM 0x0c /* eSPI command register */ | |
33 | #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/ | |
34 | #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/ | |
35 | #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */ | |
36 | ||
37 | #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4) | |
8b60d6c2 | 38 | |
8b60d6c2 | 39 | /* eSPI Controller mode register definitions */ |
81abc2ec HK |
40 | #define SPMODE_ENABLE BIT(31) |
41 | #define SPMODE_LOOP BIT(30) | |
8b60d6c2 MH |
42 | #define SPMODE_TXTHR(x) ((x) << 8) |
43 | #define SPMODE_RXTHR(x) ((x) << 0) | |
44 | ||
45 | /* eSPI Controller CS mode register definitions */ | |
81abc2ec HK |
46 | #define CSMODE_CI_INACTIVEHIGH BIT(31) |
47 | #define CSMODE_CP_BEGIN_EDGECLK BIT(30) | |
48 | #define CSMODE_REV BIT(29) | |
49 | #define CSMODE_DIV16 BIT(28) | |
8b60d6c2 | 50 | #define CSMODE_PM(x) ((x) << 24) |
81abc2ec | 51 | #define CSMODE_POL_1 BIT(20) |
8b60d6c2 MH |
52 | #define CSMODE_LEN(x) ((x) << 16) |
53 | #define CSMODE_BEF(x) ((x) << 12) | |
54 | #define CSMODE_AFT(x) ((x) << 8) | |
55 | #define CSMODE_CG(x) ((x) << 3) | |
56 | ||
54731265 | 57 | #define FSL_ESPI_FIFO_SIZE 32 |
e508cea4 | 58 | #define FSL_ESPI_RXTHR 15 |
54731265 | 59 | |
8b60d6c2 | 60 | /* Default mode/csmode for eSPI controller */ |
e508cea4 | 61 | #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR)) |
8b60d6c2 MH |
62 | #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ |
63 | | CSMODE_AFT(0) | CSMODE_CG(1)) | |
64 | ||
65 | /* SPIE register values */ | |
8b60d6c2 MH |
66 | #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) |
67 | #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) | |
81abc2ec HK |
68 | #define SPIE_TXE BIT(15) /* TX FIFO empty */ |
69 | #define SPIE_DON BIT(14) /* TX done */ | |
70 | #define SPIE_RXT BIT(13) /* RX FIFO threshold */ | |
71 | #define SPIE_RXF BIT(12) /* RX FIFO full */ | |
72 | #define SPIE_TXT BIT(11) /* TX FIFO threshold*/ | |
73 | #define SPIE_RNE BIT(9) /* RX FIFO not empty */ | |
74 | #define SPIE_TNF BIT(8) /* TX FIFO not full */ | |
75 | ||
76 | /* SPIM register values */ | |
77 | #define SPIM_TXE BIT(15) /* TX FIFO empty */ | |
78 | #define SPIM_DON BIT(14) /* TX done */ | |
79 | #define SPIM_RXT BIT(13) /* RX FIFO threshold */ | |
80 | #define SPIM_RXF BIT(12) /* RX FIFO full */ | |
81 | #define SPIM_TXT BIT(11) /* TX FIFO threshold*/ | |
82 | #define SPIM_RNE BIT(9) /* RX FIFO not empty */ | |
83 | #define SPIM_TNF BIT(8) /* TX FIFO not full */ | |
8b60d6c2 MH |
84 | |
85 | /* SPCOM register values */ | |
86 | #define SPCOM_CS(x) ((x) << 30) | |
81abc2ec HK |
87 | #define SPCOM_DO BIT(28) /* Dual output */ |
88 | #define SPCOM_TO BIT(27) /* TX only */ | |
89 | #define SPCOM_RXSKIP(x) ((x) << 16) | |
8b60d6c2 | 90 | #define SPCOM_TRANLEN(x) ((x) << 0) |
81abc2ec | 91 | |
5cfa1e4e | 92 | #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */ |
8b60d6c2 | 93 | |
e9abb4db HK |
94 | #define AUTOSUSPEND_TIMEOUT 2000 |
95 | ||
219b5e3b HK |
96 | struct fsl_espi_cs { |
97 | u32 hw_mode; | |
98 | }; | |
99 | ||
46afd38b HK |
100 | static inline u32 fsl_espi_read_reg(struct mpc8xxx_spi *mspi, int offset) |
101 | { | |
102 | return ioread32be(mspi->reg_base + offset); | |
103 | } | |
104 | ||
105 | static inline u8 fsl_espi_read_reg8(struct mpc8xxx_spi *mspi, int offset) | |
106 | { | |
107 | return ioread8(mspi->reg_base + offset); | |
108 | } | |
109 | ||
110 | static inline void fsl_espi_write_reg(struct mpc8xxx_spi *mspi, int offset, | |
111 | u32 val) | |
112 | { | |
113 | iowrite32be(val, mspi->reg_base + offset); | |
114 | } | |
115 | ||
116 | static inline void fsl_espi_write_reg8(struct mpc8xxx_spi *mspi, int offset, | |
117 | u8 val) | |
118 | { | |
119 | iowrite8(val, mspi->reg_base + offset); | |
120 | } | |
121 | ||
923ab15e HK |
122 | static void fsl_espi_memcpy_swab(void *to, const void *from, |
123 | struct spi_message *m, | |
124 | struct spi_transfer *t) | |
125 | { | |
126 | unsigned int len = t->len; | |
127 | ||
128 | if (!(m->spi->mode & SPI_LSB_FIRST) || t->bits_per_word <= 8) { | |
129 | memcpy(to, from, len); | |
130 | return; | |
131 | } | |
132 | ||
133 | /* In case of LSB-first and bits_per_word > 8 byte-swap all words */ | |
134 | while (len) | |
135 | if (len >= 4) { | |
136 | *(u32 *)to = swahb32p(from); | |
137 | to += 4; | |
138 | from += 4; | |
139 | len -= 4; | |
140 | } else { | |
141 | *(u16 *)to = swab16p(from); | |
142 | to += 2; | |
143 | from += 2; | |
144 | len -= 2; | |
145 | } | |
146 | } | |
147 | ||
cce7e3a2 HK |
148 | static void fsl_espi_copy_to_buf(struct spi_message *m, |
149 | struct mpc8xxx_spi *mspi) | |
7c159aa8 | 150 | { |
7c159aa8 HK |
151 | struct spi_transfer *t; |
152 | u8 *buf = mspi->local_buf; | |
153 | ||
154 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
cce7e3a2 | 155 | if (t->tx_buf) |
923ab15e | 156 | fsl_espi_memcpy_swab(buf, t->tx_buf, m, t); |
aca75157 HK |
157 | /* In RXSKIP mode controller shifts out zeros internally */ |
158 | else if (!mspi->rxskip) | |
7c159aa8 | 159 | memset(buf, 0, t->len); |
7c159aa8 HK |
160 | buf += t->len; |
161 | } | |
cce7e3a2 HK |
162 | } |
163 | ||
164 | static void fsl_espi_copy_from_buf(struct spi_message *m, | |
165 | struct mpc8xxx_spi *mspi) | |
166 | { | |
167 | struct spi_transfer *t; | |
168 | u8 *buf = mspi->local_buf; | |
7c159aa8 | 169 | |
cce7e3a2 HK |
170 | list_for_each_entry(t, &m->transfers, transfer_list) { |
171 | if (t->rx_buf) | |
923ab15e | 172 | fsl_espi_memcpy_swab(t->rx_buf, buf, m, t); |
cce7e3a2 HK |
173 | buf += t->len; |
174 | } | |
7c159aa8 HK |
175 | } |
176 | ||
d3152cf1 HK |
177 | static int fsl_espi_check_message(struct spi_message *m) |
178 | { | |
179 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); | |
180 | struct spi_transfer *t, *first; | |
181 | ||
182 | if (m->frame_length > SPCOM_TRANLEN_MAX) { | |
183 | dev_err(mspi->dev, "message too long, size is %u bytes\n", | |
184 | m->frame_length); | |
185 | return -EMSGSIZE; | |
186 | } | |
187 | ||
188 | first = list_first_entry(&m->transfers, struct spi_transfer, | |
189 | transfer_list); | |
e4be7053 | 190 | |
d3152cf1 HK |
191 | list_for_each_entry(t, &m->transfers, transfer_list) { |
192 | if (first->bits_per_word != t->bits_per_word || | |
193 | first->speed_hz != t->speed_hz) { | |
194 | dev_err(mspi->dev, "bits_per_word/speed_hz should be the same for all transfers\n"); | |
195 | return -EINVAL; | |
196 | } | |
197 | } | |
198 | ||
e4be7053 HK |
199 | /* ESPI supports MSB-first transfers for word size 8 / 16 only */ |
200 | if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 && | |
201 | first->bits_per_word != 16) { | |
202 | dev_err(mspi->dev, | |
203 | "MSB-first transfer not supported for wordsize %u\n", | |
204 | first->bits_per_word); | |
205 | return -EINVAL; | |
206 | } | |
207 | ||
d3152cf1 HK |
208 | return 0; |
209 | } | |
210 | ||
aca75157 HK |
211 | static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m) |
212 | { | |
213 | struct spi_transfer *t; | |
214 | unsigned int i = 0, rxskip = 0; | |
215 | ||
216 | /* | |
217 | * prerequisites for ESPI rxskip mode: | |
218 | * - message has two transfers | |
219 | * - first transfer is a write and second is a read | |
220 | * | |
221 | * In addition the current low-level transfer mechanism requires | |
222 | * that the rxskip bytes fit into the TX FIFO. Else the transfer | |
223 | * would hang because after the first FSL_ESPI_FIFO_SIZE bytes | |
224 | * the TX FIFO isn't re-filled. | |
225 | */ | |
226 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
227 | if (i == 0) { | |
228 | if (!t->tx_buf || t->rx_buf || | |
229 | t->len > FSL_ESPI_FIFO_SIZE) | |
230 | return 0; | |
231 | rxskip = t->len; | |
232 | } else if (i == 1) { | |
233 | if (t->tx_buf || !t->rx_buf) | |
234 | return 0; | |
235 | } | |
236 | i++; | |
237 | } | |
238 | ||
239 | return i == 2 ? rxskip : 0; | |
240 | } | |
241 | ||
54731265 HK |
242 | static void fsl_espi_fill_tx_fifo(struct mpc8xxx_spi *mspi, u32 events) |
243 | { | |
244 | u32 tx_fifo_avail; | |
245 | ||
246 | /* if events is zero transfer has not started and tx fifo is empty */ | |
247 | tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE; | |
248 | ||
249 | while (tx_fifo_avail >= min(4U, mspi->tx_len) && mspi->tx_len) | |
250 | if (mspi->tx_len >= 4) { | |
251 | fsl_espi_write_reg(mspi, ESPI_SPITF, *(u32 *)mspi->tx); | |
252 | mspi->tx += 4; | |
253 | mspi->tx_len -= 4; | |
254 | tx_fifo_avail -= 4; | |
255 | } else { | |
256 | fsl_espi_write_reg8(mspi, ESPI_SPITF, *(u8 *)mspi->tx); | |
257 | mspi->tx += 1; | |
258 | mspi->tx_len -= 1; | |
259 | tx_fifo_avail -= 1; | |
260 | } | |
261 | } | |
262 | ||
f05689a6 HK |
263 | static void fsl_espi_read_rx_fifo(struct mpc8xxx_spi *mspi, u32 events) |
264 | { | |
265 | u32 rx_fifo_avail = SPIE_RXCNT(events); | |
266 | ||
267 | while (rx_fifo_avail >= min(4U, mspi->rx_len) && mspi->rx_len) | |
268 | if (mspi->rx_len >= 4) { | |
269 | *(u32 *)mspi->rx = fsl_espi_read_reg(mspi, ESPI_SPIRF); | |
270 | mspi->rx += 4; | |
271 | mspi->rx_len -= 4; | |
272 | rx_fifo_avail -= 4; | |
273 | } else { | |
274 | *(u8 *)mspi->rx = fsl_espi_read_reg8(mspi, ESPI_SPIRF); | |
275 | mspi->rx += 1; | |
276 | mspi->rx_len -= 1; | |
277 | rx_fifo_avail -= 1; | |
278 | } | |
279 | } | |
280 | ||
ea616ee2 | 281 | static void fsl_espi_setup_transfer(struct spi_device *spi, |
8b60d6c2 MH |
282 | struct spi_transfer *t) |
283 | { | |
284 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
d198ebfb | 285 | int bits_per_word = t ? t->bits_per_word : spi->bits_per_word; |
73aaf158 | 286 | u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz; |
219b5e3b | 287 | struct fsl_espi_cs *cs = spi_get_ctldata(spi); |
8f3086d2 | 288 | u32 hw_mode_old = cs->hw_mode; |
8b60d6c2 | 289 | |
8b60d6c2 MH |
290 | /* mask out bits we are going to set */ |
291 | cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); | |
292 | ||
a755af52 | 293 | cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); |
8b60d6c2 | 294 | |
73aaf158 PZ |
295 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4) - 1; |
296 | ||
297 | if (pm > 15) { | |
8b60d6c2 | 298 | cs->hw_mode |= CSMODE_DIV16; |
73aaf158 PZ |
299 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4) - 1; |
300 | ||
301 | WARN_ONCE(pm > 15, | |
302 | "%s: Requested speed is too low: %u Hz. Will use %u Hz instead.\n", | |
303 | dev_name(&spi->dev), hz, | |
304 | mpc8xxx_spi->spibrg / (4 * 16 * (15 + 1))); | |
305 | if (pm > 15) | |
306 | pm = 15; | |
8b60d6c2 | 307 | } |
8b60d6c2 MH |
308 | |
309 | cs->hw_mode |= CSMODE_PM(pm); | |
310 | ||
8f3086d2 HK |
311 | /* don't write the mode register if the mode doesn't change */ |
312 | if (cs->hw_mode != hw_mode_old) | |
313 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(spi->chip_select), | |
314 | cs->hw_mode); | |
8b60d6c2 MH |
315 | } |
316 | ||
8b60d6c2 MH |
317 | static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) |
318 | { | |
319 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
aca75157 | 320 | u32 mask, spcom; |
8b60d6c2 MH |
321 | int ret; |
322 | ||
f895e27f | 323 | mpc8xxx_spi->rx_len = t->len; |
54731265 | 324 | mpc8xxx_spi->tx_len = t->len; |
8b60d6c2 MH |
325 | |
326 | mpc8xxx_spi->tx = t->tx_buf; | |
327 | mpc8xxx_spi->rx = t->rx_buf; | |
328 | ||
16735d02 | 329 | reinit_completion(&mpc8xxx_spi->done); |
8b60d6c2 MH |
330 | |
331 | /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ | |
aca75157 HK |
332 | spcom = SPCOM_CS(spi->chip_select); |
333 | spcom |= SPCOM_TRANLEN(t->len - 1); | |
334 | ||
335 | /* configure RXSKIP mode */ | |
336 | if (mpc8xxx_spi->rxskip) { | |
337 | spcom |= SPCOM_RXSKIP(mpc8xxx_spi->rxskip); | |
338 | mpc8xxx_spi->tx_len = mpc8xxx_spi->rxskip; | |
339 | mpc8xxx_spi->rx_len = t->len - mpc8xxx_spi->rxskip; | |
340 | mpc8xxx_spi->rx = t->rx_buf + mpc8xxx_spi->rxskip; | |
8263cb33 HK |
341 | if (t->rx_nbits == SPI_NBITS_DUAL) |
342 | spcom |= SPCOM_DO; | |
aca75157 HK |
343 | } |
344 | ||
345 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, spcom); | |
8b60d6c2 | 346 | |
e508cea4 HK |
347 | /* enable interrupts */ |
348 | mask = SPIM_DON; | |
349 | if (mpc8xxx_spi->rx_len > FSL_ESPI_FIFO_SIZE) | |
350 | mask |= SPIM_RXT; | |
351 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, mask); | |
5bcc6a2f | 352 | |
54731265 HK |
353 | /* Prevent filling the fifo from getting interrupted */ |
354 | spin_lock_irq(&mpc8xxx_spi->lock); | |
355 | fsl_espi_fill_tx_fifo(mpc8xxx_spi, 0); | |
356 | spin_unlock_irq(&mpc8xxx_spi->lock); | |
8b60d6c2 | 357 | |
aa70e567 NH |
358 | /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ |
359 | ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ); | |
360 | if (ret == 0) | |
361 | dev_err(mpc8xxx_spi->dev, | |
db1b049f HK |
362 | "Transaction hanging up (left %u tx bytes, %u rx bytes)\n", |
363 | mpc8xxx_spi->tx_len, mpc8xxx_spi->rx_len); | |
8b60d6c2 MH |
364 | |
365 | /* disable rx ints */ | |
46afd38b | 366 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); |
8b60d6c2 | 367 | |
db1b049f | 368 | return ret == 0 ? -ETIMEDOUT : 0; |
8b60d6c2 MH |
369 | } |
370 | ||
38d003f1 | 371 | static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans) |
8b60d6c2 | 372 | { |
38d003f1 | 373 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
8b60d6c2 | 374 | struct spi_device *spi = m->spi; |
38d003f1 | 375 | int ret; |
8b60d6c2 | 376 | |
aca75157 | 377 | mspi->rxskip = fsl_espi_check_rxskip_mode(m); |
8263cb33 HK |
378 | if (trans->rx_nbits == SPI_NBITS_DUAL && !mspi->rxskip) { |
379 | dev_err(mspi->dev, "Dual output mode requires RXSKIP mode!\n"); | |
380 | return -EINVAL; | |
381 | } | |
382 | ||
38d003f1 | 383 | fsl_espi_copy_to_buf(m, mspi); |
faceef39 | 384 | fsl_espi_setup_transfer(spi, trans); |
8b60d6c2 | 385 | |
06af115d | 386 | ret = fsl_espi_bufs(spi, trans); |
8b60d6c2 | 387 | |
faceef39 HK |
388 | if (trans->delay_usecs) |
389 | udelay(trans->delay_usecs); | |
8b60d6c2 | 390 | |
cce7e3a2 HK |
391 | if (!ret) |
392 | fsl_espi_copy_from_buf(m, mspi); | |
e33a3ade HK |
393 | |
394 | return ret; | |
8b60d6c2 MH |
395 | } |
396 | ||
c592becb HK |
397 | static int fsl_espi_do_one_msg(struct spi_master *master, |
398 | struct spi_message *m) | |
8b60d6c2 | 399 | { |
96361faf | 400 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
8263cb33 | 401 | unsigned int delay_usecs = 0, rx_nbits = 0; |
faceef39 | 402 | struct spi_transfer *t, trans = {}; |
e33a3ade | 403 | int ret; |
8b60d6c2 | 404 | |
d3152cf1 HK |
405 | ret = fsl_espi_check_message(m); |
406 | if (ret) | |
407 | goto out; | |
408 | ||
8b60d6c2 | 409 | list_for_each_entry(t, &m->transfers, transfer_list) { |
96361faf HK |
410 | if (t->delay_usecs > delay_usecs) |
411 | delay_usecs = t->delay_usecs; | |
8263cb33 HK |
412 | if (t->rx_nbits > rx_nbits) |
413 | rx_nbits = t->rx_nbits; | |
8b60d6c2 MH |
414 | } |
415 | ||
96361faf HK |
416 | t = list_first_entry(&m->transfers, struct spi_transfer, |
417 | transfer_list); | |
418 | ||
06af115d | 419 | trans.len = m->frame_length; |
96361faf HK |
420 | trans.speed_hz = t->speed_hz; |
421 | trans.bits_per_word = t->bits_per_word; | |
422 | trans.delay_usecs = delay_usecs; | |
423 | trans.tx_buf = mspi->local_buf; | |
424 | trans.rx_buf = mspi->local_buf; | |
8263cb33 | 425 | trans.rx_nbits = rx_nbits; |
8b60d6c2 | 426 | |
06af115d HK |
427 | if (trans.len) |
428 | ret = fsl_espi_trans(m, &trans); | |
8b60d6c2 | 429 | |
faceef39 | 430 | m->actual_length = ret ? 0 : trans.len; |
d3152cf1 | 431 | out: |
0319d499 HK |
432 | if (m->status == -EINPROGRESS) |
433 | m->status = ret; | |
434 | ||
c592becb | 435 | spi_finalize_current_message(master); |
0319d499 HK |
436 | |
437 | return ret; | |
8b60d6c2 MH |
438 | } |
439 | ||
440 | static int fsl_espi_setup(struct spi_device *spi) | |
441 | { | |
442 | struct mpc8xxx_spi *mpc8xxx_spi; | |
8b60d6c2 | 443 | u32 loop_mode; |
219b5e3b | 444 | struct fsl_espi_cs *cs = spi_get_ctldata(spi); |
8b60d6c2 MH |
445 | |
446 | if (!spi->max_speed_hz) | |
447 | return -EINVAL; | |
448 | ||
449 | if (!cs) { | |
d9f26748 | 450 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
8b60d6c2 MH |
451 | if (!cs) |
452 | return -ENOMEM; | |
d9f26748 | 453 | spi_set_ctldata(spi, cs); |
8b60d6c2 MH |
454 | } |
455 | ||
456 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
8b60d6c2 | 457 | |
e9abb4db HK |
458 | pm_runtime_get_sync(mpc8xxx_spi->dev); |
459 | ||
46afd38b HK |
460 | cs->hw_mode = fsl_espi_read_reg(mpc8xxx_spi, |
461 | ESPI_SPMODEx(spi->chip_select)); | |
8b60d6c2 MH |
462 | /* mask out bits we are going to set */ |
463 | cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH | |
464 | | CSMODE_REV); | |
465 | ||
466 | if (spi->mode & SPI_CPHA) | |
467 | cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; | |
468 | if (spi->mode & SPI_CPOL) | |
469 | cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; | |
470 | if (!(spi->mode & SPI_LSB_FIRST)) | |
471 | cs->hw_mode |= CSMODE_REV; | |
472 | ||
473 | /* Handle the loop mode */ | |
46afd38b | 474 | loop_mode = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
8b60d6c2 MH |
475 | loop_mode &= ~SPMODE_LOOP; |
476 | if (spi->mode & SPI_LOOP) | |
477 | loop_mode |= SPMODE_LOOP; | |
46afd38b | 478 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, loop_mode); |
8b60d6c2 | 479 | |
ea616ee2 | 480 | fsl_espi_setup_transfer(spi, NULL); |
e9abb4db HK |
481 | |
482 | pm_runtime_mark_last_busy(mpc8xxx_spi->dev); | |
483 | pm_runtime_put_autosuspend(mpc8xxx_spi->dev); | |
484 | ||
8b60d6c2 MH |
485 | return 0; |
486 | } | |
487 | ||
d9f26748 AL |
488 | static void fsl_espi_cleanup(struct spi_device *spi) |
489 | { | |
219b5e3b | 490 | struct fsl_espi_cs *cs = spi_get_ctldata(spi); |
d9f26748 AL |
491 | |
492 | kfree(cs); | |
493 | spi_set_ctldata(spi, NULL); | |
494 | } | |
495 | ||
10ed1e6d | 496 | static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
8b60d6c2 | 497 | { |
f05689a6 HK |
498 | if (mspi->rx_len) |
499 | fsl_espi_read_rx_fifo(mspi, events); | |
8b60d6c2 | 500 | |
54731265 HK |
501 | if (mspi->tx_len) |
502 | fsl_espi_fill_tx_fifo(mspi, events); | |
8b60d6c2 | 503 | |
db1b049f HK |
504 | if (mspi->tx_len || mspi->rx_len) |
505 | return; | |
506 | ||
507 | /* we're done, but check for errors before returning */ | |
508 | events = fsl_espi_read_reg(mspi, ESPI_SPIE); | |
509 | ||
510 | if (!(events & SPIE_DON)) | |
511 | dev_err(mspi->dev, | |
512 | "Transfer done but SPIE_DON isn't set!\n"); | |
513 | ||
514 | if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) | |
515 | dev_err(mspi->dev, "Transfer done but rx/tx fifo's aren't empty!\n"); | |
516 | ||
517 | complete(&mspi->done); | |
8b60d6c2 MH |
518 | } |
519 | ||
520 | static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) | |
521 | { | |
522 | struct mpc8xxx_spi *mspi = context_data; | |
8b60d6c2 MH |
523 | u32 events; |
524 | ||
54731265 HK |
525 | spin_lock(&mspi->lock); |
526 | ||
8b60d6c2 | 527 | /* Get interrupt events(tx/rx) */ |
46afd38b | 528 | events = fsl_espi_read_reg(mspi, ESPI_SPIE); |
54731265 | 529 | if (!events) { |
66b8053e | 530 | spin_unlock(&mspi->lock); |
35f5d71e | 531 | return IRQ_NONE; |
54731265 | 532 | } |
8b60d6c2 MH |
533 | |
534 | dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events); | |
535 | ||
536 | fsl_espi_cpu_irq(mspi, events); | |
537 | ||
35f5d71e | 538 | /* Clear the events */ |
46afd38b | 539 | fsl_espi_write_reg(mspi, ESPI_SPIE, events); |
35f5d71e | 540 | |
54731265 HK |
541 | spin_unlock(&mspi->lock); |
542 | ||
35f5d71e | 543 | return IRQ_HANDLED; |
8b60d6c2 MH |
544 | } |
545 | ||
e9abb4db HK |
546 | #ifdef CONFIG_PM |
547 | static int fsl_espi_runtime_suspend(struct device *dev) | |
75506d0e | 548 | { |
e9abb4db HK |
549 | struct spi_master *master = dev_get_drvdata(dev); |
550 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
75506d0e HK |
551 | u32 regval; |
552 | ||
46afd38b | 553 | regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
75506d0e | 554 | regval &= ~SPMODE_ENABLE; |
46afd38b | 555 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
75506d0e HK |
556 | |
557 | return 0; | |
558 | } | |
559 | ||
e9abb4db | 560 | static int fsl_espi_runtime_resume(struct device *dev) |
75506d0e | 561 | { |
e9abb4db HK |
562 | struct spi_master *master = dev_get_drvdata(dev); |
563 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
75506d0e HK |
564 | u32 regval; |
565 | ||
46afd38b | 566 | regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
75506d0e | 567 | regval |= SPMODE_ENABLE; |
46afd38b | 568 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
75506d0e HK |
569 | |
570 | return 0; | |
571 | } | |
e9abb4db | 572 | #endif |
75506d0e | 573 | |
02a595d5 | 574 | static size_t fsl_espi_max_message_size(struct spi_device *spi) |
b541eef1 MS |
575 | { |
576 | return SPCOM_TRANLEN_MAX; | |
577 | } | |
578 | ||
604042af | 579 | static int fsl_espi_probe(struct device *dev, struct resource *mem, |
7454346b | 580 | unsigned int irq, unsigned int num_cs) |
8b60d6c2 | 581 | { |
8b60d6c2 MH |
582 | struct spi_master *master; |
583 | struct mpc8xxx_spi *mpc8xxx_spi; | |
d0fb47a5 | 584 | struct device_node *nc; |
b497eb02 HK |
585 | u32 regval, csmode, cs, prop; |
586 | int ret; | |
8b60d6c2 MH |
587 | |
588 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); | |
604042af HK |
589 | if (!master) |
590 | return -ENOMEM; | |
8b60d6c2 MH |
591 | |
592 | dev_set_drvdata(dev, master); | |
593 | ||
7cb55577 HK |
594 | master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | |
595 | SPI_LSB_FIRST | SPI_LOOP; | |
596 | master->dev.of_node = dev->of_node; | |
24778be2 | 597 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
8b60d6c2 | 598 | master->setup = fsl_espi_setup; |
d9f26748 | 599 | master->cleanup = fsl_espi_cleanup; |
c592becb | 600 | master->transfer_one_message = fsl_espi_do_one_msg; |
e9abb4db | 601 | master->auto_runtime_pm = true; |
02a595d5 | 602 | master->max_message_size = fsl_espi_max_message_size; |
7454346b | 603 | master->num_chipselect = num_cs; |
8b60d6c2 MH |
604 | |
605 | mpc8xxx_spi = spi_master_get_devdata(master); | |
54731265 | 606 | spin_lock_init(&mpc8xxx_spi->lock); |
8b60d6c2 | 607 | |
7cb55577 HK |
608 | mpc8xxx_spi->dev = dev; |
609 | mpc8xxx_spi->spibrg = fsl_get_sys_freq(); | |
610 | if (mpc8xxx_spi->spibrg == -1) { | |
611 | dev_err(dev, "Can't get sys frequency!\n"); | |
612 | ret = -EINVAL; | |
613 | goto err_probe; | |
614 | } | |
615 | ||
616 | init_completion(&mpc8xxx_spi->done); | |
617 | ||
1423877b HK |
618 | mpc8xxx_spi->local_buf = |
619 | devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL); | |
620 | if (!mpc8xxx_spi->local_buf) { | |
621 | ret = -ENOMEM; | |
622 | goto err_probe; | |
623 | } | |
624 | ||
4178b6b1 | 625 | mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); |
37c5db79 AL |
626 | if (IS_ERR(mpc8xxx_spi->reg_base)) { |
627 | ret = PTR_ERR(mpc8xxx_spi->reg_base); | |
8b60d6c2 MH |
628 | goto err_probe; |
629 | } | |
630 | ||
8b60d6c2 | 631 | /* Register for SPI Interrupt */ |
cdb2f77c HK |
632 | ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", |
633 | mpc8xxx_spi); | |
8b60d6c2 | 634 | if (ret) |
4178b6b1 | 635 | goto err_probe; |
8b60d6c2 | 636 | |
8b60d6c2 | 637 | /* SPI controller initializations */ |
46afd38b HK |
638 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0); |
639 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); | |
640 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0); | |
641 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff); | |
8b60d6c2 MH |
642 | |
643 | /* Init eSPI CS mode register */ | |
d0fb47a5 JW |
644 | for_each_available_child_of_node(master->dev.of_node, nc) { |
645 | /* get chip select */ | |
b497eb02 | 646 | ret = of_property_read_u32(nc, "reg", &cs); |
7454346b | 647 | if (ret || cs >= num_cs) |
d0fb47a5 JW |
648 | continue; |
649 | ||
650 | csmode = CSMODE_INIT_VAL; | |
b497eb02 | 651 | |
d0fb47a5 | 652 | /* check if CSBEF is set in device tree */ |
b497eb02 HK |
653 | ret = of_property_read_u32(nc, "fsl,csbef", &prop); |
654 | if (!ret) { | |
d0fb47a5 | 655 | csmode &= ~(CSMODE_BEF(0xf)); |
b497eb02 | 656 | csmode |= CSMODE_BEF(prop); |
d0fb47a5 | 657 | } |
b497eb02 | 658 | |
d0fb47a5 | 659 | /* check if CSAFT is set in device tree */ |
b497eb02 HK |
660 | ret = of_property_read_u32(nc, "fsl,csaft", &prop); |
661 | if (!ret) { | |
d0fb47a5 | 662 | csmode &= ~(CSMODE_AFT(0xf)); |
b497eb02 | 663 | csmode |= CSMODE_AFT(prop); |
d0fb47a5 | 664 | } |
d0fb47a5 | 665 | |
b497eb02 HK |
666 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(cs), csmode); |
667 | ||
668 | dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode); | |
d0fb47a5 | 669 | } |
8b60d6c2 MH |
670 | |
671 | /* Enable SPI interface */ | |
689d41fb | 672 | regval = SPMODE_INIT_VAL | SPMODE_ENABLE; |
8b60d6c2 | 673 | |
46afd38b | 674 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
8b60d6c2 | 675 | |
e9abb4db HK |
676 | pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT); |
677 | pm_runtime_use_autosuspend(dev); | |
678 | pm_runtime_set_active(dev); | |
679 | pm_runtime_enable(dev); | |
680 | pm_runtime_get_sync(dev); | |
681 | ||
4178b6b1 | 682 | ret = devm_spi_register_master(dev, master); |
8b60d6c2 | 683 | if (ret < 0) |
e9abb4db | 684 | goto err_pm; |
8b60d6c2 | 685 | |
cdb2f77c | 686 | dev_info(dev, "at 0x%p (irq = %u)\n", mpc8xxx_spi->reg_base, irq); |
8b60d6c2 | 687 | |
e9abb4db HK |
688 | pm_runtime_mark_last_busy(dev); |
689 | pm_runtime_put_autosuspend(dev); | |
690 | ||
604042af | 691 | return 0; |
8b60d6c2 | 692 | |
e9abb4db HK |
693 | err_pm: |
694 | pm_runtime_put_noidle(dev); | |
695 | pm_runtime_disable(dev); | |
696 | pm_runtime_set_suspended(dev); | |
8b60d6c2 MH |
697 | err_probe: |
698 | spi_master_put(master); | |
604042af | 699 | return ret; |
8b60d6c2 MH |
700 | } |
701 | ||
702 | static int of_fsl_espi_get_chipselects(struct device *dev) | |
703 | { | |
704 | struct device_node *np = dev->of_node; | |
b497eb02 HK |
705 | u32 num_cs; |
706 | int ret; | |
8b60d6c2 | 707 | |
b497eb02 HK |
708 | ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs); |
709 | if (ret) { | |
8b60d6c2 | 710 | dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); |
7454346b | 711 | return 0; |
8b60d6c2 MH |
712 | } |
713 | ||
7454346b | 714 | return num_cs; |
8b60d6c2 MH |
715 | } |
716 | ||
fd4a319b | 717 | static int of_fsl_espi_probe(struct platform_device *ofdev) |
8b60d6c2 MH |
718 | { |
719 | struct device *dev = &ofdev->dev; | |
720 | struct device_node *np = ofdev->dev.of_node; | |
8b60d6c2 | 721 | struct resource mem; |
7454346b | 722 | unsigned int irq, num_cs; |
acf69219 | 723 | int ret; |
8b60d6c2 | 724 | |
e3ce4f44 HK |
725 | if (of_property_read_bool(np, "mode")) { |
726 | dev_err(dev, "mode property is not supported on ESPI!\n"); | |
727 | return -EINVAL; | |
728 | } | |
729 | ||
7454346b HK |
730 | num_cs = of_fsl_espi_get_chipselects(dev); |
731 | if (!num_cs) | |
732 | return -EINVAL; | |
8b60d6c2 MH |
733 | |
734 | ret = of_address_to_resource(np, 0, &mem); | |
735 | if (ret) | |
acf69219 | 736 | return ret; |
8b60d6c2 | 737 | |
f7578496 | 738 | irq = irq_of_parse_and_map(np, 0); |
acf69219 HK |
739 | if (!irq) |
740 | return -EINVAL; | |
8b60d6c2 | 741 | |
7454346b | 742 | return fsl_espi_probe(dev, &mem, irq, num_cs); |
8b60d6c2 MH |
743 | } |
744 | ||
e9abb4db HK |
745 | static int of_fsl_espi_remove(struct platform_device *dev) |
746 | { | |
747 | pm_runtime_disable(&dev->dev); | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
714bb654 HZ |
752 | #ifdef CONFIG_PM_SLEEP |
753 | static int of_fsl_espi_suspend(struct device *dev) | |
754 | { | |
755 | struct spi_master *master = dev_get_drvdata(dev); | |
714bb654 HZ |
756 | int ret; |
757 | ||
714bb654 HZ |
758 | ret = spi_master_suspend(master); |
759 | if (ret) { | |
760 | dev_warn(dev, "cannot suspend master\n"); | |
761 | return ret; | |
762 | } | |
763 | ||
e9abb4db HK |
764 | ret = pm_runtime_force_suspend(dev); |
765 | if (ret < 0) | |
766 | return ret; | |
767 | ||
768 | return 0; | |
714bb654 HZ |
769 | } |
770 | ||
771 | static int of_fsl_espi_resume(struct device *dev) | |
772 | { | |
714bb654 HZ |
773 | struct spi_master *master = dev_get_drvdata(dev); |
774 | struct mpc8xxx_spi *mpc8xxx_spi; | |
714bb654 | 775 | u32 regval; |
e9abb4db | 776 | int i, ret; |
714bb654 HZ |
777 | |
778 | mpc8xxx_spi = spi_master_get_devdata(master); | |
714bb654 HZ |
779 | |
780 | /* SPI controller initializations */ | |
46afd38b HK |
781 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0); |
782 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); | |
783 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0); | |
784 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff); | |
714bb654 HZ |
785 | |
786 | /* Init eSPI CS mode register */ | |
7454346b | 787 | for (i = 0; i < master->num_chipselect; i++) |
46afd38b HK |
788 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i), |
789 | CSMODE_INIT_VAL); | |
714bb654 HZ |
790 | |
791 | /* Enable SPI interface */ | |
689d41fb | 792 | regval = SPMODE_INIT_VAL | SPMODE_ENABLE; |
714bb654 | 793 | |
46afd38b | 794 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
714bb654 | 795 | |
e9abb4db HK |
796 | ret = pm_runtime_force_resume(dev); |
797 | if (ret < 0) | |
798 | return ret; | |
799 | ||
714bb654 HZ |
800 | return spi_master_resume(master); |
801 | } | |
802 | #endif /* CONFIG_PM_SLEEP */ | |
803 | ||
804 | static const struct dev_pm_ops espi_pm = { | |
e9abb4db HK |
805 | SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend, |
806 | fsl_espi_runtime_resume, NULL) | |
714bb654 HZ |
807 | SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) |
808 | }; | |
809 | ||
8b60d6c2 MH |
810 | static const struct of_device_id of_fsl_espi_match[] = { |
811 | { .compatible = "fsl,mpc8536-espi" }, | |
812 | {} | |
813 | }; | |
814 | MODULE_DEVICE_TABLE(of, of_fsl_espi_match); | |
815 | ||
18d306d1 | 816 | static struct platform_driver fsl_espi_driver = { |
8b60d6c2 MH |
817 | .driver = { |
818 | .name = "fsl_espi", | |
8b60d6c2 | 819 | .of_match_table = of_fsl_espi_match, |
714bb654 | 820 | .pm = &espi_pm, |
8b60d6c2 MH |
821 | }, |
822 | .probe = of_fsl_espi_probe, | |
e9abb4db | 823 | .remove = of_fsl_espi_remove, |
8b60d6c2 | 824 | }; |
940ab889 | 825 | module_platform_driver(fsl_espi_driver); |
8b60d6c2 MH |
826 | |
827 | MODULE_AUTHOR("Mingkai Hu"); | |
828 | MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); | |
829 | MODULE_LICENSE("GPL"); |