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Commit | Line | Data |
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8b60d6c2 MH |
1 | /* |
2 | * Freescale eSPI controller driver. | |
3 | * | |
4 | * Copyright 2010 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
8b60d6c2 | 11 | #include <linux/delay.h> |
a3108360 | 12 | #include <linux/err.h> |
8b60d6c2 | 13 | #include <linux/fsl_devices.h> |
a3108360 | 14 | #include <linux/interrupt.h> |
a3108360 | 15 | #include <linux/module.h> |
8b60d6c2 MH |
16 | #include <linux/mm.h> |
17 | #include <linux/of.h> | |
5af50730 RH |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_irq.h> | |
8b60d6c2 | 20 | #include <linux/of_platform.h> |
a3108360 XL |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spi/spi.h> | |
e9abb4db | 23 | #include <linux/pm_runtime.h> |
8b60d6c2 MH |
24 | #include <sysdev/fsl_soc.h> |
25 | ||
ca632f55 | 26 | #include "spi-fsl-lib.h" |
8b60d6c2 MH |
27 | |
28 | /* eSPI Controller registers */ | |
46afd38b HK |
29 | #define ESPI_SPMODE 0x00 /* eSPI mode register */ |
30 | #define ESPI_SPIE 0x04 /* eSPI event register */ | |
31 | #define ESPI_SPIM 0x08 /* eSPI mask register */ | |
32 | #define ESPI_SPCOM 0x0c /* eSPI command register */ | |
33 | #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/ | |
34 | #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/ | |
35 | #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */ | |
36 | ||
37 | #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4) | |
8b60d6c2 | 38 | |
8b60d6c2 | 39 | /* eSPI Controller mode register definitions */ |
81abc2ec HK |
40 | #define SPMODE_ENABLE BIT(31) |
41 | #define SPMODE_LOOP BIT(30) | |
8b60d6c2 MH |
42 | #define SPMODE_TXTHR(x) ((x) << 8) |
43 | #define SPMODE_RXTHR(x) ((x) << 0) | |
44 | ||
45 | /* eSPI Controller CS mode register definitions */ | |
81abc2ec HK |
46 | #define CSMODE_CI_INACTIVEHIGH BIT(31) |
47 | #define CSMODE_CP_BEGIN_EDGECLK BIT(30) | |
48 | #define CSMODE_REV BIT(29) | |
49 | #define CSMODE_DIV16 BIT(28) | |
8b60d6c2 | 50 | #define CSMODE_PM(x) ((x) << 24) |
81abc2ec | 51 | #define CSMODE_POL_1 BIT(20) |
8b60d6c2 MH |
52 | #define CSMODE_LEN(x) ((x) << 16) |
53 | #define CSMODE_BEF(x) ((x) << 12) | |
54 | #define CSMODE_AFT(x) ((x) << 8) | |
55 | #define CSMODE_CG(x) ((x) << 3) | |
56 | ||
54731265 | 57 | #define FSL_ESPI_FIFO_SIZE 32 |
e508cea4 | 58 | #define FSL_ESPI_RXTHR 15 |
54731265 | 59 | |
8b60d6c2 | 60 | /* Default mode/csmode for eSPI controller */ |
e508cea4 | 61 | #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR)) |
8b60d6c2 MH |
62 | #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ |
63 | | CSMODE_AFT(0) | CSMODE_CG(1)) | |
64 | ||
65 | /* SPIE register values */ | |
8b60d6c2 MH |
66 | #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) |
67 | #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) | |
81abc2ec HK |
68 | #define SPIE_TXE BIT(15) /* TX FIFO empty */ |
69 | #define SPIE_DON BIT(14) /* TX done */ | |
70 | #define SPIE_RXT BIT(13) /* RX FIFO threshold */ | |
71 | #define SPIE_RXF BIT(12) /* RX FIFO full */ | |
72 | #define SPIE_TXT BIT(11) /* TX FIFO threshold*/ | |
73 | #define SPIE_RNE BIT(9) /* RX FIFO not empty */ | |
74 | #define SPIE_TNF BIT(8) /* TX FIFO not full */ | |
75 | ||
76 | /* SPIM register values */ | |
77 | #define SPIM_TXE BIT(15) /* TX FIFO empty */ | |
78 | #define SPIM_DON BIT(14) /* TX done */ | |
79 | #define SPIM_RXT BIT(13) /* RX FIFO threshold */ | |
80 | #define SPIM_RXF BIT(12) /* RX FIFO full */ | |
81 | #define SPIM_TXT BIT(11) /* TX FIFO threshold*/ | |
82 | #define SPIM_RNE BIT(9) /* RX FIFO not empty */ | |
83 | #define SPIM_TNF BIT(8) /* TX FIFO not full */ | |
8b60d6c2 MH |
84 | |
85 | /* SPCOM register values */ | |
86 | #define SPCOM_CS(x) ((x) << 30) | |
81abc2ec HK |
87 | #define SPCOM_DO BIT(28) /* Dual output */ |
88 | #define SPCOM_TO BIT(27) /* TX only */ | |
89 | #define SPCOM_RXSKIP(x) ((x) << 16) | |
8b60d6c2 | 90 | #define SPCOM_TRANLEN(x) ((x) << 0) |
81abc2ec | 91 | |
5cfa1e4e | 92 | #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */ |
8b60d6c2 | 93 | |
e9abb4db HK |
94 | #define AUTOSUSPEND_TIMEOUT 2000 |
95 | ||
46afd38b HK |
96 | static inline u32 fsl_espi_read_reg(struct mpc8xxx_spi *mspi, int offset) |
97 | { | |
98 | return ioread32be(mspi->reg_base + offset); | |
99 | } | |
100 | ||
101 | static inline u8 fsl_espi_read_reg8(struct mpc8xxx_spi *mspi, int offset) | |
102 | { | |
103 | return ioread8(mspi->reg_base + offset); | |
104 | } | |
105 | ||
106 | static inline void fsl_espi_write_reg(struct mpc8xxx_spi *mspi, int offset, | |
107 | u32 val) | |
108 | { | |
109 | iowrite32be(val, mspi->reg_base + offset); | |
110 | } | |
111 | ||
112 | static inline void fsl_espi_write_reg8(struct mpc8xxx_spi *mspi, int offset, | |
113 | u8 val) | |
114 | { | |
115 | iowrite8(val, mspi->reg_base + offset); | |
116 | } | |
117 | ||
923ab15e HK |
118 | static void fsl_espi_memcpy_swab(void *to, const void *from, |
119 | struct spi_message *m, | |
120 | struct spi_transfer *t) | |
121 | { | |
122 | unsigned int len = t->len; | |
123 | ||
124 | if (!(m->spi->mode & SPI_LSB_FIRST) || t->bits_per_word <= 8) { | |
125 | memcpy(to, from, len); | |
126 | return; | |
127 | } | |
128 | ||
129 | /* In case of LSB-first and bits_per_word > 8 byte-swap all words */ | |
130 | while (len) | |
131 | if (len >= 4) { | |
132 | *(u32 *)to = swahb32p(from); | |
133 | to += 4; | |
134 | from += 4; | |
135 | len -= 4; | |
136 | } else { | |
137 | *(u16 *)to = swab16p(from); | |
138 | to += 2; | |
139 | from += 2; | |
140 | len -= 2; | |
141 | } | |
142 | } | |
143 | ||
cce7e3a2 HK |
144 | static void fsl_espi_copy_to_buf(struct spi_message *m, |
145 | struct mpc8xxx_spi *mspi) | |
7c159aa8 | 146 | { |
7c159aa8 HK |
147 | struct spi_transfer *t; |
148 | u8 *buf = mspi->local_buf; | |
149 | ||
150 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
cce7e3a2 | 151 | if (t->tx_buf) |
923ab15e | 152 | fsl_espi_memcpy_swab(buf, t->tx_buf, m, t); |
aca75157 HK |
153 | /* In RXSKIP mode controller shifts out zeros internally */ |
154 | else if (!mspi->rxskip) | |
7c159aa8 | 155 | memset(buf, 0, t->len); |
7c159aa8 HK |
156 | buf += t->len; |
157 | } | |
cce7e3a2 HK |
158 | } |
159 | ||
160 | static void fsl_espi_copy_from_buf(struct spi_message *m, | |
161 | struct mpc8xxx_spi *mspi) | |
162 | { | |
163 | struct spi_transfer *t; | |
164 | u8 *buf = mspi->local_buf; | |
7c159aa8 | 165 | |
cce7e3a2 HK |
166 | list_for_each_entry(t, &m->transfers, transfer_list) { |
167 | if (t->rx_buf) | |
923ab15e | 168 | fsl_espi_memcpy_swab(t->rx_buf, buf, m, t); |
cce7e3a2 HK |
169 | buf += t->len; |
170 | } | |
7c159aa8 HK |
171 | } |
172 | ||
d3152cf1 HK |
173 | static int fsl_espi_check_message(struct spi_message *m) |
174 | { | |
175 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); | |
176 | struct spi_transfer *t, *first; | |
177 | ||
178 | if (m->frame_length > SPCOM_TRANLEN_MAX) { | |
179 | dev_err(mspi->dev, "message too long, size is %u bytes\n", | |
180 | m->frame_length); | |
181 | return -EMSGSIZE; | |
182 | } | |
183 | ||
184 | first = list_first_entry(&m->transfers, struct spi_transfer, | |
185 | transfer_list); | |
e4be7053 | 186 | |
d3152cf1 HK |
187 | list_for_each_entry(t, &m->transfers, transfer_list) { |
188 | if (first->bits_per_word != t->bits_per_word || | |
189 | first->speed_hz != t->speed_hz) { | |
190 | dev_err(mspi->dev, "bits_per_word/speed_hz should be the same for all transfers\n"); | |
191 | return -EINVAL; | |
192 | } | |
193 | } | |
194 | ||
e4be7053 HK |
195 | /* ESPI supports MSB-first transfers for word size 8 / 16 only */ |
196 | if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 && | |
197 | first->bits_per_word != 16) { | |
198 | dev_err(mspi->dev, | |
199 | "MSB-first transfer not supported for wordsize %u\n", | |
200 | first->bits_per_word); | |
201 | return -EINVAL; | |
202 | } | |
203 | ||
d3152cf1 HK |
204 | return 0; |
205 | } | |
206 | ||
aca75157 HK |
207 | static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m) |
208 | { | |
209 | struct spi_transfer *t; | |
210 | unsigned int i = 0, rxskip = 0; | |
211 | ||
212 | /* | |
213 | * prerequisites for ESPI rxskip mode: | |
214 | * - message has two transfers | |
215 | * - first transfer is a write and second is a read | |
216 | * | |
217 | * In addition the current low-level transfer mechanism requires | |
218 | * that the rxskip bytes fit into the TX FIFO. Else the transfer | |
219 | * would hang because after the first FSL_ESPI_FIFO_SIZE bytes | |
220 | * the TX FIFO isn't re-filled. | |
221 | */ | |
222 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
223 | if (i == 0) { | |
224 | if (!t->tx_buf || t->rx_buf || | |
225 | t->len > FSL_ESPI_FIFO_SIZE) | |
226 | return 0; | |
227 | rxskip = t->len; | |
228 | } else if (i == 1) { | |
229 | if (t->tx_buf || !t->rx_buf) | |
230 | return 0; | |
231 | } | |
232 | i++; | |
233 | } | |
234 | ||
235 | return i == 2 ? rxskip : 0; | |
236 | } | |
237 | ||
54731265 HK |
238 | static void fsl_espi_fill_tx_fifo(struct mpc8xxx_spi *mspi, u32 events) |
239 | { | |
240 | u32 tx_fifo_avail; | |
241 | ||
242 | /* if events is zero transfer has not started and tx fifo is empty */ | |
243 | tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE; | |
244 | ||
245 | while (tx_fifo_avail >= min(4U, mspi->tx_len) && mspi->tx_len) | |
246 | if (mspi->tx_len >= 4) { | |
247 | fsl_espi_write_reg(mspi, ESPI_SPITF, *(u32 *)mspi->tx); | |
248 | mspi->tx += 4; | |
249 | mspi->tx_len -= 4; | |
250 | tx_fifo_avail -= 4; | |
251 | } else { | |
252 | fsl_espi_write_reg8(mspi, ESPI_SPITF, *(u8 *)mspi->tx); | |
253 | mspi->tx += 1; | |
254 | mspi->tx_len -= 1; | |
255 | tx_fifo_avail -= 1; | |
256 | } | |
257 | } | |
258 | ||
f05689a6 HK |
259 | static void fsl_espi_read_rx_fifo(struct mpc8xxx_spi *mspi, u32 events) |
260 | { | |
261 | u32 rx_fifo_avail = SPIE_RXCNT(events); | |
262 | ||
263 | while (rx_fifo_avail >= min(4U, mspi->rx_len) && mspi->rx_len) | |
264 | if (mspi->rx_len >= 4) { | |
265 | *(u32 *)mspi->rx = fsl_espi_read_reg(mspi, ESPI_SPIRF); | |
266 | mspi->rx += 4; | |
267 | mspi->rx_len -= 4; | |
268 | rx_fifo_avail -= 4; | |
269 | } else { | |
270 | *(u8 *)mspi->rx = fsl_espi_read_reg8(mspi, ESPI_SPIRF); | |
271 | mspi->rx += 1; | |
272 | mspi->rx_len -= 1; | |
273 | rx_fifo_avail -= 1; | |
274 | } | |
275 | } | |
276 | ||
ea616ee2 | 277 | static void fsl_espi_setup_transfer(struct spi_device *spi, |
8b60d6c2 MH |
278 | struct spi_transfer *t) |
279 | { | |
280 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
d198ebfb | 281 | int bits_per_word = t ? t->bits_per_word : spi->bits_per_word; |
73aaf158 | 282 | u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz; |
8b60d6c2 | 283 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
8f3086d2 | 284 | u32 hw_mode_old = cs->hw_mode; |
8b60d6c2 | 285 | |
8b60d6c2 MH |
286 | /* mask out bits we are going to set */ |
287 | cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); | |
288 | ||
a755af52 | 289 | cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); |
8b60d6c2 | 290 | |
73aaf158 PZ |
291 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4) - 1; |
292 | ||
293 | if (pm > 15) { | |
8b60d6c2 | 294 | cs->hw_mode |= CSMODE_DIV16; |
73aaf158 PZ |
295 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4) - 1; |
296 | ||
297 | WARN_ONCE(pm > 15, | |
298 | "%s: Requested speed is too low: %u Hz. Will use %u Hz instead.\n", | |
299 | dev_name(&spi->dev), hz, | |
300 | mpc8xxx_spi->spibrg / (4 * 16 * (15 + 1))); | |
301 | if (pm > 15) | |
302 | pm = 15; | |
8b60d6c2 | 303 | } |
8b60d6c2 MH |
304 | |
305 | cs->hw_mode |= CSMODE_PM(pm); | |
306 | ||
8f3086d2 HK |
307 | /* don't write the mode register if the mode doesn't change */ |
308 | if (cs->hw_mode != hw_mode_old) | |
309 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(spi->chip_select), | |
310 | cs->hw_mode); | |
8b60d6c2 MH |
311 | } |
312 | ||
8b60d6c2 MH |
313 | static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) |
314 | { | |
315 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
aca75157 | 316 | u32 mask, spcom; |
8b60d6c2 MH |
317 | int ret; |
318 | ||
f895e27f | 319 | mpc8xxx_spi->rx_len = t->len; |
54731265 | 320 | mpc8xxx_spi->tx_len = t->len; |
8b60d6c2 MH |
321 | |
322 | mpc8xxx_spi->tx = t->tx_buf; | |
323 | mpc8xxx_spi->rx = t->rx_buf; | |
324 | ||
16735d02 | 325 | reinit_completion(&mpc8xxx_spi->done); |
8b60d6c2 MH |
326 | |
327 | /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ | |
aca75157 HK |
328 | spcom = SPCOM_CS(spi->chip_select); |
329 | spcom |= SPCOM_TRANLEN(t->len - 1); | |
330 | ||
331 | /* configure RXSKIP mode */ | |
332 | if (mpc8xxx_spi->rxskip) { | |
333 | spcom |= SPCOM_RXSKIP(mpc8xxx_spi->rxskip); | |
334 | mpc8xxx_spi->tx_len = mpc8xxx_spi->rxskip; | |
335 | mpc8xxx_spi->rx_len = t->len - mpc8xxx_spi->rxskip; | |
336 | mpc8xxx_spi->rx = t->rx_buf + mpc8xxx_spi->rxskip; | |
8263cb33 HK |
337 | if (t->rx_nbits == SPI_NBITS_DUAL) |
338 | spcom |= SPCOM_DO; | |
aca75157 HK |
339 | } |
340 | ||
341 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, spcom); | |
8b60d6c2 | 342 | |
e508cea4 HK |
343 | /* enable interrupts */ |
344 | mask = SPIM_DON; | |
345 | if (mpc8xxx_spi->rx_len > FSL_ESPI_FIFO_SIZE) | |
346 | mask |= SPIM_RXT; | |
347 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, mask); | |
5bcc6a2f | 348 | |
54731265 HK |
349 | /* Prevent filling the fifo from getting interrupted */ |
350 | spin_lock_irq(&mpc8xxx_spi->lock); | |
351 | fsl_espi_fill_tx_fifo(mpc8xxx_spi, 0); | |
352 | spin_unlock_irq(&mpc8xxx_spi->lock); | |
8b60d6c2 | 353 | |
aa70e567 NH |
354 | /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ |
355 | ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ); | |
356 | if (ret == 0) | |
357 | dev_err(mpc8xxx_spi->dev, | |
db1b049f HK |
358 | "Transaction hanging up (left %u tx bytes, %u rx bytes)\n", |
359 | mpc8xxx_spi->tx_len, mpc8xxx_spi->rx_len); | |
8b60d6c2 MH |
360 | |
361 | /* disable rx ints */ | |
46afd38b | 362 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); |
8b60d6c2 | 363 | |
db1b049f | 364 | return ret == 0 ? -ETIMEDOUT : 0; |
8b60d6c2 MH |
365 | } |
366 | ||
38d003f1 | 367 | static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans) |
8b60d6c2 | 368 | { |
38d003f1 | 369 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
8b60d6c2 | 370 | struct spi_device *spi = m->spi; |
38d003f1 | 371 | int ret; |
8b60d6c2 | 372 | |
aca75157 | 373 | mspi->rxskip = fsl_espi_check_rxskip_mode(m); |
8263cb33 HK |
374 | if (trans->rx_nbits == SPI_NBITS_DUAL && !mspi->rxskip) { |
375 | dev_err(mspi->dev, "Dual output mode requires RXSKIP mode!\n"); | |
376 | return -EINVAL; | |
377 | } | |
378 | ||
38d003f1 | 379 | fsl_espi_copy_to_buf(m, mspi); |
faceef39 | 380 | fsl_espi_setup_transfer(spi, trans); |
8b60d6c2 | 381 | |
06af115d | 382 | ret = fsl_espi_bufs(spi, trans); |
8b60d6c2 | 383 | |
faceef39 HK |
384 | if (trans->delay_usecs) |
385 | udelay(trans->delay_usecs); | |
8b60d6c2 | 386 | |
cce7e3a2 HK |
387 | if (!ret) |
388 | fsl_espi_copy_from_buf(m, mspi); | |
e33a3ade HK |
389 | |
390 | return ret; | |
8b60d6c2 MH |
391 | } |
392 | ||
c592becb HK |
393 | static int fsl_espi_do_one_msg(struct spi_master *master, |
394 | struct spi_message *m) | |
8b60d6c2 | 395 | { |
96361faf | 396 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
8263cb33 | 397 | unsigned int delay_usecs = 0, rx_nbits = 0; |
faceef39 | 398 | struct spi_transfer *t, trans = {}; |
e33a3ade | 399 | int ret; |
8b60d6c2 | 400 | |
d3152cf1 HK |
401 | ret = fsl_espi_check_message(m); |
402 | if (ret) | |
403 | goto out; | |
404 | ||
8b60d6c2 | 405 | list_for_each_entry(t, &m->transfers, transfer_list) { |
96361faf HK |
406 | if (t->delay_usecs > delay_usecs) |
407 | delay_usecs = t->delay_usecs; | |
8263cb33 HK |
408 | if (t->rx_nbits > rx_nbits) |
409 | rx_nbits = t->rx_nbits; | |
8b60d6c2 MH |
410 | } |
411 | ||
96361faf HK |
412 | t = list_first_entry(&m->transfers, struct spi_transfer, |
413 | transfer_list); | |
414 | ||
06af115d | 415 | trans.len = m->frame_length; |
96361faf HK |
416 | trans.speed_hz = t->speed_hz; |
417 | trans.bits_per_word = t->bits_per_word; | |
418 | trans.delay_usecs = delay_usecs; | |
419 | trans.tx_buf = mspi->local_buf; | |
420 | trans.rx_buf = mspi->local_buf; | |
8263cb33 | 421 | trans.rx_nbits = rx_nbits; |
8b60d6c2 | 422 | |
06af115d HK |
423 | if (trans.len) |
424 | ret = fsl_espi_trans(m, &trans); | |
8b60d6c2 | 425 | |
faceef39 | 426 | m->actual_length = ret ? 0 : trans.len; |
d3152cf1 | 427 | out: |
0319d499 HK |
428 | if (m->status == -EINPROGRESS) |
429 | m->status = ret; | |
430 | ||
c592becb | 431 | spi_finalize_current_message(master); |
0319d499 HK |
432 | |
433 | return ret; | |
8b60d6c2 MH |
434 | } |
435 | ||
436 | static int fsl_espi_setup(struct spi_device *spi) | |
437 | { | |
438 | struct mpc8xxx_spi *mpc8xxx_spi; | |
8b60d6c2 | 439 | u32 loop_mode; |
d9f26748 | 440 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
8b60d6c2 MH |
441 | |
442 | if (!spi->max_speed_hz) | |
443 | return -EINVAL; | |
444 | ||
445 | if (!cs) { | |
d9f26748 | 446 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
8b60d6c2 MH |
447 | if (!cs) |
448 | return -ENOMEM; | |
d9f26748 | 449 | spi_set_ctldata(spi, cs); |
8b60d6c2 MH |
450 | } |
451 | ||
452 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
8b60d6c2 | 453 | |
e9abb4db HK |
454 | pm_runtime_get_sync(mpc8xxx_spi->dev); |
455 | ||
46afd38b HK |
456 | cs->hw_mode = fsl_espi_read_reg(mpc8xxx_spi, |
457 | ESPI_SPMODEx(spi->chip_select)); | |
8b60d6c2 MH |
458 | /* mask out bits we are going to set */ |
459 | cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH | |
460 | | CSMODE_REV); | |
461 | ||
462 | if (spi->mode & SPI_CPHA) | |
463 | cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; | |
464 | if (spi->mode & SPI_CPOL) | |
465 | cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; | |
466 | if (!(spi->mode & SPI_LSB_FIRST)) | |
467 | cs->hw_mode |= CSMODE_REV; | |
468 | ||
469 | /* Handle the loop mode */ | |
46afd38b | 470 | loop_mode = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
8b60d6c2 MH |
471 | loop_mode &= ~SPMODE_LOOP; |
472 | if (spi->mode & SPI_LOOP) | |
473 | loop_mode |= SPMODE_LOOP; | |
46afd38b | 474 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, loop_mode); |
8b60d6c2 | 475 | |
ea616ee2 | 476 | fsl_espi_setup_transfer(spi, NULL); |
e9abb4db HK |
477 | |
478 | pm_runtime_mark_last_busy(mpc8xxx_spi->dev); | |
479 | pm_runtime_put_autosuspend(mpc8xxx_spi->dev); | |
480 | ||
8b60d6c2 MH |
481 | return 0; |
482 | } | |
483 | ||
d9f26748 AL |
484 | static void fsl_espi_cleanup(struct spi_device *spi) |
485 | { | |
486 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); | |
487 | ||
488 | kfree(cs); | |
489 | spi_set_ctldata(spi, NULL); | |
490 | } | |
491 | ||
10ed1e6d | 492 | static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
8b60d6c2 | 493 | { |
f05689a6 HK |
494 | if (mspi->rx_len) |
495 | fsl_espi_read_rx_fifo(mspi, events); | |
8b60d6c2 | 496 | |
54731265 HK |
497 | if (mspi->tx_len) |
498 | fsl_espi_fill_tx_fifo(mspi, events); | |
8b60d6c2 | 499 | |
db1b049f HK |
500 | if (mspi->tx_len || mspi->rx_len) |
501 | return; | |
502 | ||
503 | /* we're done, but check for errors before returning */ | |
504 | events = fsl_espi_read_reg(mspi, ESPI_SPIE); | |
505 | ||
506 | if (!(events & SPIE_DON)) | |
507 | dev_err(mspi->dev, | |
508 | "Transfer done but SPIE_DON isn't set!\n"); | |
509 | ||
510 | if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) | |
511 | dev_err(mspi->dev, "Transfer done but rx/tx fifo's aren't empty!\n"); | |
512 | ||
513 | complete(&mspi->done); | |
8b60d6c2 MH |
514 | } |
515 | ||
516 | static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) | |
517 | { | |
518 | struct mpc8xxx_spi *mspi = context_data; | |
8b60d6c2 MH |
519 | u32 events; |
520 | ||
54731265 HK |
521 | spin_lock(&mspi->lock); |
522 | ||
8b60d6c2 | 523 | /* Get interrupt events(tx/rx) */ |
46afd38b | 524 | events = fsl_espi_read_reg(mspi, ESPI_SPIE); |
54731265 | 525 | if (!events) { |
66b8053e | 526 | spin_unlock(&mspi->lock); |
35f5d71e | 527 | return IRQ_NONE; |
54731265 | 528 | } |
8b60d6c2 MH |
529 | |
530 | dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events); | |
531 | ||
532 | fsl_espi_cpu_irq(mspi, events); | |
533 | ||
35f5d71e | 534 | /* Clear the events */ |
46afd38b | 535 | fsl_espi_write_reg(mspi, ESPI_SPIE, events); |
35f5d71e | 536 | |
54731265 HK |
537 | spin_unlock(&mspi->lock); |
538 | ||
35f5d71e | 539 | return IRQ_HANDLED; |
8b60d6c2 MH |
540 | } |
541 | ||
e9abb4db HK |
542 | #ifdef CONFIG_PM |
543 | static int fsl_espi_runtime_suspend(struct device *dev) | |
75506d0e | 544 | { |
e9abb4db HK |
545 | struct spi_master *master = dev_get_drvdata(dev); |
546 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
75506d0e HK |
547 | u32 regval; |
548 | ||
46afd38b | 549 | regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
75506d0e | 550 | regval &= ~SPMODE_ENABLE; |
46afd38b | 551 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
75506d0e HK |
552 | |
553 | return 0; | |
554 | } | |
555 | ||
e9abb4db | 556 | static int fsl_espi_runtime_resume(struct device *dev) |
75506d0e | 557 | { |
e9abb4db HK |
558 | struct spi_master *master = dev_get_drvdata(dev); |
559 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
75506d0e HK |
560 | u32 regval; |
561 | ||
46afd38b | 562 | regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
75506d0e | 563 | regval |= SPMODE_ENABLE; |
46afd38b | 564 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
75506d0e HK |
565 | |
566 | return 0; | |
567 | } | |
e9abb4db | 568 | #endif |
75506d0e | 569 | |
02a595d5 | 570 | static size_t fsl_espi_max_message_size(struct spi_device *spi) |
b541eef1 MS |
571 | { |
572 | return SPCOM_TRANLEN_MAX; | |
573 | } | |
574 | ||
604042af HK |
575 | static int fsl_espi_probe(struct device *dev, struct resource *mem, |
576 | unsigned int irq) | |
8b60d6c2 | 577 | { |
8074cf06 | 578 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
8b60d6c2 MH |
579 | struct spi_master *master; |
580 | struct mpc8xxx_spi *mpc8xxx_spi; | |
d0fb47a5 | 581 | struct device_node *nc; |
b497eb02 HK |
582 | u32 regval, csmode, cs, prop; |
583 | int ret; | |
8b60d6c2 MH |
584 | |
585 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); | |
604042af HK |
586 | if (!master) |
587 | return -ENOMEM; | |
8b60d6c2 MH |
588 | |
589 | dev_set_drvdata(dev, master); | |
590 | ||
c592becb | 591 | mpc8xxx_spi_probe(dev, mem, irq); |
8b60d6c2 | 592 | |
8263cb33 | 593 | master->mode_bits |= SPI_RX_DUAL; |
24778be2 | 594 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
8b60d6c2 | 595 | master->setup = fsl_espi_setup; |
d9f26748 | 596 | master->cleanup = fsl_espi_cleanup; |
c592becb | 597 | master->transfer_one_message = fsl_espi_do_one_msg; |
e9abb4db | 598 | master->auto_runtime_pm = true; |
02a595d5 | 599 | master->max_message_size = fsl_espi_max_message_size; |
8b60d6c2 MH |
600 | |
601 | mpc8xxx_spi = spi_master_get_devdata(master); | |
54731265 | 602 | spin_lock_init(&mpc8xxx_spi->lock); |
8b60d6c2 | 603 | |
1423877b HK |
604 | mpc8xxx_spi->local_buf = |
605 | devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL); | |
606 | if (!mpc8xxx_spi->local_buf) { | |
607 | ret = -ENOMEM; | |
608 | goto err_probe; | |
609 | } | |
610 | ||
4178b6b1 | 611 | mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); |
37c5db79 AL |
612 | if (IS_ERR(mpc8xxx_spi->reg_base)) { |
613 | ret = PTR_ERR(mpc8xxx_spi->reg_base); | |
8b60d6c2 MH |
614 | goto err_probe; |
615 | } | |
616 | ||
8b60d6c2 | 617 | /* Register for SPI Interrupt */ |
4178b6b1 | 618 | ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq, |
8b60d6c2 MH |
619 | 0, "fsl_espi", mpc8xxx_spi); |
620 | if (ret) | |
4178b6b1 | 621 | goto err_probe; |
8b60d6c2 MH |
622 | |
623 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { | |
e9e128a6 HK |
624 | dev_err(dev, "SPI_QE_CPU_MODE is not supported on ESPI!\n"); |
625 | ret = -EINVAL; | |
626 | goto err_probe; | |
8b60d6c2 MH |
627 | } |
628 | ||
629 | /* SPI controller initializations */ | |
46afd38b HK |
630 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0); |
631 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); | |
632 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0); | |
633 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff); | |
8b60d6c2 MH |
634 | |
635 | /* Init eSPI CS mode register */ | |
d0fb47a5 JW |
636 | for_each_available_child_of_node(master->dev.of_node, nc) { |
637 | /* get chip select */ | |
b497eb02 HK |
638 | ret = of_property_read_u32(nc, "reg", &cs); |
639 | if (ret || cs >= pdata->max_chipselect) | |
d0fb47a5 JW |
640 | continue; |
641 | ||
642 | csmode = CSMODE_INIT_VAL; | |
b497eb02 | 643 | |
d0fb47a5 | 644 | /* check if CSBEF is set in device tree */ |
b497eb02 HK |
645 | ret = of_property_read_u32(nc, "fsl,csbef", &prop); |
646 | if (!ret) { | |
d0fb47a5 | 647 | csmode &= ~(CSMODE_BEF(0xf)); |
b497eb02 | 648 | csmode |= CSMODE_BEF(prop); |
d0fb47a5 | 649 | } |
b497eb02 | 650 | |
d0fb47a5 | 651 | /* check if CSAFT is set in device tree */ |
b497eb02 HK |
652 | ret = of_property_read_u32(nc, "fsl,csaft", &prop); |
653 | if (!ret) { | |
d0fb47a5 | 654 | csmode &= ~(CSMODE_AFT(0xf)); |
b497eb02 | 655 | csmode |= CSMODE_AFT(prop); |
d0fb47a5 | 656 | } |
d0fb47a5 | 657 | |
b497eb02 HK |
658 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(cs), csmode); |
659 | ||
660 | dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode); | |
d0fb47a5 | 661 | } |
8b60d6c2 MH |
662 | |
663 | /* Enable SPI interface */ | |
689d41fb | 664 | regval = SPMODE_INIT_VAL | SPMODE_ENABLE; |
8b60d6c2 | 665 | |
46afd38b | 666 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
8b60d6c2 | 667 | |
e9abb4db HK |
668 | pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT); |
669 | pm_runtime_use_autosuspend(dev); | |
670 | pm_runtime_set_active(dev); | |
671 | pm_runtime_enable(dev); | |
672 | pm_runtime_get_sync(dev); | |
673 | ||
4178b6b1 | 674 | ret = devm_spi_register_master(dev, master); |
8b60d6c2 | 675 | if (ret < 0) |
e9abb4db | 676 | goto err_pm; |
8b60d6c2 | 677 | |
46afd38b HK |
678 | dev_info(dev, "at 0x%p (irq = %d)\n", mpc8xxx_spi->reg_base, |
679 | mpc8xxx_spi->irq); | |
8b60d6c2 | 680 | |
e9abb4db HK |
681 | pm_runtime_mark_last_busy(dev); |
682 | pm_runtime_put_autosuspend(dev); | |
683 | ||
604042af | 684 | return 0; |
8b60d6c2 | 685 | |
e9abb4db HK |
686 | err_pm: |
687 | pm_runtime_put_noidle(dev); | |
688 | pm_runtime_disable(dev); | |
689 | pm_runtime_set_suspended(dev); | |
8b60d6c2 MH |
690 | err_probe: |
691 | spi_master_put(master); | |
604042af | 692 | return ret; |
8b60d6c2 MH |
693 | } |
694 | ||
695 | static int of_fsl_espi_get_chipselects(struct device *dev) | |
696 | { | |
697 | struct device_node *np = dev->of_node; | |
8074cf06 | 698 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
b497eb02 HK |
699 | u32 num_cs; |
700 | int ret; | |
8b60d6c2 | 701 | |
b497eb02 HK |
702 | ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs); |
703 | if (ret) { | |
8b60d6c2 MH |
704 | dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); |
705 | return -EINVAL; | |
706 | } | |
707 | ||
b497eb02 | 708 | pdata->max_chipselect = num_cs; |
8b60d6c2 MH |
709 | |
710 | return 0; | |
711 | } | |
712 | ||
fd4a319b | 713 | static int of_fsl_espi_probe(struct platform_device *ofdev) |
8b60d6c2 MH |
714 | { |
715 | struct device *dev = &ofdev->dev; | |
716 | struct device_node *np = ofdev->dev.of_node; | |
8b60d6c2 | 717 | struct resource mem; |
f7578496 | 718 | unsigned int irq; |
acf69219 | 719 | int ret; |
8b60d6c2 | 720 | |
18d306d1 | 721 | ret = of_mpc8xxx_spi_probe(ofdev); |
8b60d6c2 MH |
722 | if (ret) |
723 | return ret; | |
724 | ||
725 | ret = of_fsl_espi_get_chipselects(dev); | |
726 | if (ret) | |
acf69219 | 727 | return ret; |
8b60d6c2 MH |
728 | |
729 | ret = of_address_to_resource(np, 0, &mem); | |
730 | if (ret) | |
acf69219 | 731 | return ret; |
8b60d6c2 | 732 | |
f7578496 | 733 | irq = irq_of_parse_and_map(np, 0); |
acf69219 HK |
734 | if (!irq) |
735 | return -EINVAL; | |
8b60d6c2 | 736 | |
604042af | 737 | return fsl_espi_probe(dev, &mem, irq); |
8b60d6c2 MH |
738 | } |
739 | ||
e9abb4db HK |
740 | static int of_fsl_espi_remove(struct platform_device *dev) |
741 | { | |
742 | pm_runtime_disable(&dev->dev); | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
714bb654 HZ |
747 | #ifdef CONFIG_PM_SLEEP |
748 | static int of_fsl_espi_suspend(struct device *dev) | |
749 | { | |
750 | struct spi_master *master = dev_get_drvdata(dev); | |
714bb654 HZ |
751 | int ret; |
752 | ||
714bb654 HZ |
753 | ret = spi_master_suspend(master); |
754 | if (ret) { | |
755 | dev_warn(dev, "cannot suspend master\n"); | |
756 | return ret; | |
757 | } | |
758 | ||
e9abb4db HK |
759 | ret = pm_runtime_force_suspend(dev); |
760 | if (ret < 0) | |
761 | return ret; | |
762 | ||
763 | return 0; | |
714bb654 HZ |
764 | } |
765 | ||
766 | static int of_fsl_espi_resume(struct device *dev) | |
767 | { | |
768 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); | |
769 | struct spi_master *master = dev_get_drvdata(dev); | |
770 | struct mpc8xxx_spi *mpc8xxx_spi; | |
714bb654 | 771 | u32 regval; |
e9abb4db | 772 | int i, ret; |
714bb654 HZ |
773 | |
774 | mpc8xxx_spi = spi_master_get_devdata(master); | |
714bb654 HZ |
775 | |
776 | /* SPI controller initializations */ | |
46afd38b HK |
777 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0); |
778 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); | |
779 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0); | |
780 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff); | |
714bb654 HZ |
781 | |
782 | /* Init eSPI CS mode register */ | |
783 | for (i = 0; i < pdata->max_chipselect; i++) | |
46afd38b HK |
784 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i), |
785 | CSMODE_INIT_VAL); | |
714bb654 HZ |
786 | |
787 | /* Enable SPI interface */ | |
689d41fb | 788 | regval = SPMODE_INIT_VAL | SPMODE_ENABLE; |
714bb654 | 789 | |
46afd38b | 790 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
714bb654 | 791 | |
e9abb4db HK |
792 | ret = pm_runtime_force_resume(dev); |
793 | if (ret < 0) | |
794 | return ret; | |
795 | ||
714bb654 HZ |
796 | return spi_master_resume(master); |
797 | } | |
798 | #endif /* CONFIG_PM_SLEEP */ | |
799 | ||
800 | static const struct dev_pm_ops espi_pm = { | |
e9abb4db HK |
801 | SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend, |
802 | fsl_espi_runtime_resume, NULL) | |
714bb654 HZ |
803 | SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) |
804 | }; | |
805 | ||
8b60d6c2 MH |
806 | static const struct of_device_id of_fsl_espi_match[] = { |
807 | { .compatible = "fsl,mpc8536-espi" }, | |
808 | {} | |
809 | }; | |
810 | MODULE_DEVICE_TABLE(of, of_fsl_espi_match); | |
811 | ||
18d306d1 | 812 | static struct platform_driver fsl_espi_driver = { |
8b60d6c2 MH |
813 | .driver = { |
814 | .name = "fsl_espi", | |
8b60d6c2 | 815 | .of_match_table = of_fsl_espi_match, |
714bb654 | 816 | .pm = &espi_pm, |
8b60d6c2 MH |
817 | }, |
818 | .probe = of_fsl_espi_probe, | |
e9abb4db | 819 | .remove = of_fsl_espi_remove, |
8b60d6c2 | 820 | }; |
940ab889 | 821 | module_platform_driver(fsl_espi_driver); |
8b60d6c2 MH |
822 | |
823 | MODULE_AUTHOR("Mingkai Hu"); | |
824 | MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); | |
825 | MODULE_LICENSE("GPL"); |