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Commit | Line | Data |
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8b60d6c2 MH |
1 | /* |
2 | * Freescale eSPI controller driver. | |
3 | * | |
4 | * Copyright 2010 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
8b60d6c2 | 11 | #include <linux/delay.h> |
a3108360 | 12 | #include <linux/err.h> |
8b60d6c2 | 13 | #include <linux/fsl_devices.h> |
a3108360 | 14 | #include <linux/interrupt.h> |
a3108360 | 15 | #include <linux/module.h> |
8b60d6c2 MH |
16 | #include <linux/mm.h> |
17 | #include <linux/of.h> | |
5af50730 RH |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_irq.h> | |
8b60d6c2 | 20 | #include <linux/of_platform.h> |
a3108360 XL |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spi/spi.h> | |
e9abb4db | 23 | #include <linux/pm_runtime.h> |
8b60d6c2 MH |
24 | #include <sysdev/fsl_soc.h> |
25 | ||
ca632f55 | 26 | #include "spi-fsl-lib.h" |
8b60d6c2 MH |
27 | |
28 | /* eSPI Controller registers */ | |
46afd38b HK |
29 | #define ESPI_SPMODE 0x00 /* eSPI mode register */ |
30 | #define ESPI_SPIE 0x04 /* eSPI event register */ | |
31 | #define ESPI_SPIM 0x08 /* eSPI mask register */ | |
32 | #define ESPI_SPCOM 0x0c /* eSPI command register */ | |
33 | #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/ | |
34 | #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/ | |
35 | #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */ | |
36 | ||
37 | #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4) | |
8b60d6c2 | 38 | |
8b60d6c2 | 39 | /* eSPI Controller mode register definitions */ |
81abc2ec HK |
40 | #define SPMODE_ENABLE BIT(31) |
41 | #define SPMODE_LOOP BIT(30) | |
8b60d6c2 MH |
42 | #define SPMODE_TXTHR(x) ((x) << 8) |
43 | #define SPMODE_RXTHR(x) ((x) << 0) | |
44 | ||
45 | /* eSPI Controller CS mode register definitions */ | |
81abc2ec HK |
46 | #define CSMODE_CI_INACTIVEHIGH BIT(31) |
47 | #define CSMODE_CP_BEGIN_EDGECLK BIT(30) | |
48 | #define CSMODE_REV BIT(29) | |
49 | #define CSMODE_DIV16 BIT(28) | |
8b60d6c2 | 50 | #define CSMODE_PM(x) ((x) << 24) |
81abc2ec | 51 | #define CSMODE_POL_1 BIT(20) |
8b60d6c2 MH |
52 | #define CSMODE_LEN(x) ((x) << 16) |
53 | #define CSMODE_BEF(x) ((x) << 12) | |
54 | #define CSMODE_AFT(x) ((x) << 8) | |
55 | #define CSMODE_CG(x) ((x) << 3) | |
56 | ||
54731265 | 57 | #define FSL_ESPI_FIFO_SIZE 32 |
e508cea4 | 58 | #define FSL_ESPI_RXTHR 15 |
54731265 | 59 | |
8b60d6c2 | 60 | /* Default mode/csmode for eSPI controller */ |
e508cea4 | 61 | #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR)) |
8b60d6c2 MH |
62 | #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ |
63 | | CSMODE_AFT(0) | CSMODE_CG(1)) | |
64 | ||
65 | /* SPIE register values */ | |
8b60d6c2 MH |
66 | #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) |
67 | #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) | |
81abc2ec HK |
68 | #define SPIE_TXE BIT(15) /* TX FIFO empty */ |
69 | #define SPIE_DON BIT(14) /* TX done */ | |
70 | #define SPIE_RXT BIT(13) /* RX FIFO threshold */ | |
71 | #define SPIE_RXF BIT(12) /* RX FIFO full */ | |
72 | #define SPIE_TXT BIT(11) /* TX FIFO threshold*/ | |
73 | #define SPIE_RNE BIT(9) /* RX FIFO not empty */ | |
74 | #define SPIE_TNF BIT(8) /* TX FIFO not full */ | |
75 | ||
76 | /* SPIM register values */ | |
77 | #define SPIM_TXE BIT(15) /* TX FIFO empty */ | |
78 | #define SPIM_DON BIT(14) /* TX done */ | |
79 | #define SPIM_RXT BIT(13) /* RX FIFO threshold */ | |
80 | #define SPIM_RXF BIT(12) /* RX FIFO full */ | |
81 | #define SPIM_TXT BIT(11) /* TX FIFO threshold*/ | |
82 | #define SPIM_RNE BIT(9) /* RX FIFO not empty */ | |
83 | #define SPIM_TNF BIT(8) /* TX FIFO not full */ | |
8b60d6c2 MH |
84 | |
85 | /* SPCOM register values */ | |
86 | #define SPCOM_CS(x) ((x) << 30) | |
81abc2ec HK |
87 | #define SPCOM_DO BIT(28) /* Dual output */ |
88 | #define SPCOM_TO BIT(27) /* TX only */ | |
89 | #define SPCOM_RXSKIP(x) ((x) << 16) | |
8b60d6c2 | 90 | #define SPCOM_TRANLEN(x) ((x) << 0) |
81abc2ec | 91 | |
5cfa1e4e | 92 | #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */ |
8b60d6c2 | 93 | |
e9abb4db HK |
94 | #define AUTOSUSPEND_TIMEOUT 2000 |
95 | ||
46afd38b HK |
96 | static inline u32 fsl_espi_read_reg(struct mpc8xxx_spi *mspi, int offset) |
97 | { | |
98 | return ioread32be(mspi->reg_base + offset); | |
99 | } | |
100 | ||
101 | static inline u8 fsl_espi_read_reg8(struct mpc8xxx_spi *mspi, int offset) | |
102 | { | |
103 | return ioread8(mspi->reg_base + offset); | |
104 | } | |
105 | ||
106 | static inline void fsl_espi_write_reg(struct mpc8xxx_spi *mspi, int offset, | |
107 | u32 val) | |
108 | { | |
109 | iowrite32be(val, mspi->reg_base + offset); | |
110 | } | |
111 | ||
112 | static inline void fsl_espi_write_reg8(struct mpc8xxx_spi *mspi, int offset, | |
113 | u8 val) | |
114 | { | |
115 | iowrite8(val, mspi->reg_base + offset); | |
116 | } | |
117 | ||
923ab15e HK |
118 | static void fsl_espi_memcpy_swab(void *to, const void *from, |
119 | struct spi_message *m, | |
120 | struct spi_transfer *t) | |
121 | { | |
122 | unsigned int len = t->len; | |
123 | ||
124 | if (!(m->spi->mode & SPI_LSB_FIRST) || t->bits_per_word <= 8) { | |
125 | memcpy(to, from, len); | |
126 | return; | |
127 | } | |
128 | ||
129 | /* In case of LSB-first and bits_per_word > 8 byte-swap all words */ | |
130 | while (len) | |
131 | if (len >= 4) { | |
132 | *(u32 *)to = swahb32p(from); | |
133 | to += 4; | |
134 | from += 4; | |
135 | len -= 4; | |
136 | } else { | |
137 | *(u16 *)to = swab16p(from); | |
138 | to += 2; | |
139 | from += 2; | |
140 | len -= 2; | |
141 | } | |
142 | } | |
143 | ||
cce7e3a2 HK |
144 | static void fsl_espi_copy_to_buf(struct spi_message *m, |
145 | struct mpc8xxx_spi *mspi) | |
7c159aa8 | 146 | { |
7c159aa8 HK |
147 | struct spi_transfer *t; |
148 | u8 *buf = mspi->local_buf; | |
149 | ||
150 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
cce7e3a2 | 151 | if (t->tx_buf) |
923ab15e | 152 | fsl_espi_memcpy_swab(buf, t->tx_buf, m, t); |
cce7e3a2 | 153 | else |
7c159aa8 | 154 | memset(buf, 0, t->len); |
7c159aa8 HK |
155 | buf += t->len; |
156 | } | |
cce7e3a2 HK |
157 | } |
158 | ||
159 | static void fsl_espi_copy_from_buf(struct spi_message *m, | |
160 | struct mpc8xxx_spi *mspi) | |
161 | { | |
162 | struct spi_transfer *t; | |
163 | u8 *buf = mspi->local_buf; | |
7c159aa8 | 164 | |
cce7e3a2 HK |
165 | list_for_each_entry(t, &m->transfers, transfer_list) { |
166 | if (t->rx_buf) | |
923ab15e | 167 | fsl_espi_memcpy_swab(t->rx_buf, buf, m, t); |
cce7e3a2 HK |
168 | buf += t->len; |
169 | } | |
7c159aa8 HK |
170 | } |
171 | ||
d3152cf1 HK |
172 | static int fsl_espi_check_message(struct spi_message *m) |
173 | { | |
174 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); | |
175 | struct spi_transfer *t, *first; | |
176 | ||
177 | if (m->frame_length > SPCOM_TRANLEN_MAX) { | |
178 | dev_err(mspi->dev, "message too long, size is %u bytes\n", | |
179 | m->frame_length); | |
180 | return -EMSGSIZE; | |
181 | } | |
182 | ||
183 | first = list_first_entry(&m->transfers, struct spi_transfer, | |
184 | transfer_list); | |
e4be7053 | 185 | |
d3152cf1 HK |
186 | list_for_each_entry(t, &m->transfers, transfer_list) { |
187 | if (first->bits_per_word != t->bits_per_word || | |
188 | first->speed_hz != t->speed_hz) { | |
189 | dev_err(mspi->dev, "bits_per_word/speed_hz should be the same for all transfers\n"); | |
190 | return -EINVAL; | |
191 | } | |
192 | } | |
193 | ||
e4be7053 HK |
194 | /* ESPI supports MSB-first transfers for word size 8 / 16 only */ |
195 | if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 && | |
196 | first->bits_per_word != 16) { | |
197 | dev_err(mspi->dev, | |
198 | "MSB-first transfer not supported for wordsize %u\n", | |
199 | first->bits_per_word); | |
200 | return -EINVAL; | |
201 | } | |
202 | ||
d3152cf1 HK |
203 | return 0; |
204 | } | |
205 | ||
54731265 HK |
206 | static void fsl_espi_fill_tx_fifo(struct mpc8xxx_spi *mspi, u32 events) |
207 | { | |
208 | u32 tx_fifo_avail; | |
209 | ||
210 | /* if events is zero transfer has not started and tx fifo is empty */ | |
211 | tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE; | |
212 | ||
213 | while (tx_fifo_avail >= min(4U, mspi->tx_len) && mspi->tx_len) | |
214 | if (mspi->tx_len >= 4) { | |
215 | fsl_espi_write_reg(mspi, ESPI_SPITF, *(u32 *)mspi->tx); | |
216 | mspi->tx += 4; | |
217 | mspi->tx_len -= 4; | |
218 | tx_fifo_avail -= 4; | |
219 | } else { | |
220 | fsl_espi_write_reg8(mspi, ESPI_SPITF, *(u8 *)mspi->tx); | |
221 | mspi->tx += 1; | |
222 | mspi->tx_len -= 1; | |
223 | tx_fifo_avail -= 1; | |
224 | } | |
225 | } | |
226 | ||
f05689a6 HK |
227 | static void fsl_espi_read_rx_fifo(struct mpc8xxx_spi *mspi, u32 events) |
228 | { | |
229 | u32 rx_fifo_avail = SPIE_RXCNT(events); | |
230 | ||
231 | while (rx_fifo_avail >= min(4U, mspi->rx_len) && mspi->rx_len) | |
232 | if (mspi->rx_len >= 4) { | |
233 | *(u32 *)mspi->rx = fsl_espi_read_reg(mspi, ESPI_SPIRF); | |
234 | mspi->rx += 4; | |
235 | mspi->rx_len -= 4; | |
236 | rx_fifo_avail -= 4; | |
237 | } else { | |
238 | *(u8 *)mspi->rx = fsl_espi_read_reg8(mspi, ESPI_SPIRF); | |
239 | mspi->rx += 1; | |
240 | mspi->rx_len -= 1; | |
241 | rx_fifo_avail -= 1; | |
242 | } | |
243 | } | |
244 | ||
ea616ee2 | 245 | static void fsl_espi_setup_transfer(struct spi_device *spi, |
8b60d6c2 MH |
246 | struct spi_transfer *t) |
247 | { | |
248 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
d198ebfb HK |
249 | int bits_per_word = t ? t->bits_per_word : spi->bits_per_word; |
250 | u32 hz = t ? t->speed_hz : spi->max_speed_hz; | |
8b60d6c2 | 251 | u8 pm; |
8b60d6c2 MH |
252 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
253 | ||
8b60d6c2 MH |
254 | /* mask out bits we are going to set */ |
255 | cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); | |
256 | ||
a755af52 | 257 | cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); |
8b60d6c2 MH |
258 | |
259 | if ((mpc8xxx_spi->spibrg / hz) > 64) { | |
260 | cs->hw_mode |= CSMODE_DIV16; | |
35faa55c | 261 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4); |
8b60d6c2 | 262 | |
87bf5ab8 | 263 | WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. " |
8b60d6c2 | 264 | "Will use %d Hz instead.\n", dev_name(&spi->dev), |
87bf5ab8 SAS |
265 | hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1))); |
266 | if (pm > 33) | |
267 | pm = 33; | |
8b60d6c2 | 268 | } else { |
35faa55c | 269 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4); |
8b60d6c2 MH |
270 | } |
271 | if (pm) | |
272 | pm--; | |
87bf5ab8 SAS |
273 | if (pm < 2) |
274 | pm = 2; | |
8b60d6c2 MH |
275 | |
276 | cs->hw_mode |= CSMODE_PM(pm); | |
277 | ||
b3bec5f9 HK |
278 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(spi->chip_select), |
279 | cs->hw_mode); | |
8b60d6c2 MH |
280 | } |
281 | ||
8b60d6c2 MH |
282 | static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) |
283 | { | |
284 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
e508cea4 | 285 | u32 mask; |
8b60d6c2 MH |
286 | int ret; |
287 | ||
f895e27f | 288 | mpc8xxx_spi->rx_len = t->len; |
54731265 | 289 | mpc8xxx_spi->tx_len = t->len; |
8b60d6c2 MH |
290 | |
291 | mpc8xxx_spi->tx = t->tx_buf; | |
292 | mpc8xxx_spi->rx = t->rx_buf; | |
293 | ||
16735d02 | 294 | reinit_completion(&mpc8xxx_spi->done); |
8b60d6c2 MH |
295 | |
296 | /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ | |
46afd38b | 297 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, |
8b60d6c2 MH |
298 | (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1))); |
299 | ||
e508cea4 HK |
300 | /* enable interrupts */ |
301 | mask = SPIM_DON; | |
302 | if (mpc8xxx_spi->rx_len > FSL_ESPI_FIFO_SIZE) | |
303 | mask |= SPIM_RXT; | |
304 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, mask); | |
5bcc6a2f | 305 | |
54731265 HK |
306 | /* Prevent filling the fifo from getting interrupted */ |
307 | spin_lock_irq(&mpc8xxx_spi->lock); | |
308 | fsl_espi_fill_tx_fifo(mpc8xxx_spi, 0); | |
309 | spin_unlock_irq(&mpc8xxx_spi->lock); | |
8b60d6c2 | 310 | |
aa70e567 NH |
311 | /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ |
312 | ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ); | |
313 | if (ret == 0) | |
314 | dev_err(mpc8xxx_spi->dev, | |
db1b049f HK |
315 | "Transaction hanging up (left %u tx bytes, %u rx bytes)\n", |
316 | mpc8xxx_spi->tx_len, mpc8xxx_spi->rx_len); | |
8b60d6c2 MH |
317 | |
318 | /* disable rx ints */ | |
46afd38b | 319 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); |
8b60d6c2 | 320 | |
db1b049f | 321 | return ret == 0 ? -ETIMEDOUT : 0; |
8b60d6c2 MH |
322 | } |
323 | ||
38d003f1 | 324 | static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans) |
8b60d6c2 | 325 | { |
38d003f1 | 326 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
8b60d6c2 | 327 | struct spi_device *spi = m->spi; |
38d003f1 | 328 | int ret; |
8b60d6c2 | 329 | |
38d003f1 | 330 | fsl_espi_copy_to_buf(m, mspi); |
faceef39 | 331 | fsl_espi_setup_transfer(spi, trans); |
8b60d6c2 | 332 | |
06af115d | 333 | ret = fsl_espi_bufs(spi, trans); |
8b60d6c2 | 334 | |
faceef39 HK |
335 | if (trans->delay_usecs) |
336 | udelay(trans->delay_usecs); | |
8b60d6c2 | 337 | |
8b60d6c2 | 338 | fsl_espi_setup_transfer(spi, NULL); |
e33a3ade | 339 | |
cce7e3a2 HK |
340 | if (!ret) |
341 | fsl_espi_copy_from_buf(m, mspi); | |
e33a3ade HK |
342 | |
343 | return ret; | |
8b60d6c2 MH |
344 | } |
345 | ||
c592becb HK |
346 | static int fsl_espi_do_one_msg(struct spi_master *master, |
347 | struct spi_message *m) | |
8b60d6c2 | 348 | { |
96361faf | 349 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
06af115d | 350 | unsigned int delay_usecs = 0; |
faceef39 | 351 | struct spi_transfer *t, trans = {}; |
e33a3ade | 352 | int ret; |
8b60d6c2 | 353 | |
d3152cf1 HK |
354 | ret = fsl_espi_check_message(m); |
355 | if (ret) | |
356 | goto out; | |
357 | ||
8b60d6c2 | 358 | list_for_each_entry(t, &m->transfers, transfer_list) { |
96361faf HK |
359 | if (t->delay_usecs > delay_usecs) |
360 | delay_usecs = t->delay_usecs; | |
8b60d6c2 MH |
361 | } |
362 | ||
96361faf HK |
363 | t = list_first_entry(&m->transfers, struct spi_transfer, |
364 | transfer_list); | |
365 | ||
06af115d | 366 | trans.len = m->frame_length; |
96361faf HK |
367 | trans.speed_hz = t->speed_hz; |
368 | trans.bits_per_word = t->bits_per_word; | |
369 | trans.delay_usecs = delay_usecs; | |
370 | trans.tx_buf = mspi->local_buf; | |
371 | trans.rx_buf = mspi->local_buf; | |
8b60d6c2 | 372 | |
06af115d HK |
373 | if (trans.len) |
374 | ret = fsl_espi_trans(m, &trans); | |
8b60d6c2 | 375 | |
faceef39 | 376 | m->actual_length = ret ? 0 : trans.len; |
d3152cf1 | 377 | out: |
0319d499 HK |
378 | if (m->status == -EINPROGRESS) |
379 | m->status = ret; | |
380 | ||
c592becb | 381 | spi_finalize_current_message(master); |
0319d499 HK |
382 | |
383 | return ret; | |
8b60d6c2 MH |
384 | } |
385 | ||
386 | static int fsl_espi_setup(struct spi_device *spi) | |
387 | { | |
388 | struct mpc8xxx_spi *mpc8xxx_spi; | |
8b60d6c2 | 389 | u32 loop_mode; |
d9f26748 | 390 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
8b60d6c2 MH |
391 | |
392 | if (!spi->max_speed_hz) | |
393 | return -EINVAL; | |
394 | ||
395 | if (!cs) { | |
d9f26748 | 396 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
8b60d6c2 MH |
397 | if (!cs) |
398 | return -ENOMEM; | |
d9f26748 | 399 | spi_set_ctldata(spi, cs); |
8b60d6c2 MH |
400 | } |
401 | ||
402 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
8b60d6c2 | 403 | |
e9abb4db HK |
404 | pm_runtime_get_sync(mpc8xxx_spi->dev); |
405 | ||
46afd38b HK |
406 | cs->hw_mode = fsl_espi_read_reg(mpc8xxx_spi, |
407 | ESPI_SPMODEx(spi->chip_select)); | |
8b60d6c2 MH |
408 | /* mask out bits we are going to set */ |
409 | cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH | |
410 | | CSMODE_REV); | |
411 | ||
412 | if (spi->mode & SPI_CPHA) | |
413 | cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; | |
414 | if (spi->mode & SPI_CPOL) | |
415 | cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; | |
416 | if (!(spi->mode & SPI_LSB_FIRST)) | |
417 | cs->hw_mode |= CSMODE_REV; | |
418 | ||
419 | /* Handle the loop mode */ | |
46afd38b | 420 | loop_mode = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
8b60d6c2 MH |
421 | loop_mode &= ~SPMODE_LOOP; |
422 | if (spi->mode & SPI_LOOP) | |
423 | loop_mode |= SPMODE_LOOP; | |
46afd38b | 424 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, loop_mode); |
8b60d6c2 | 425 | |
ea616ee2 | 426 | fsl_espi_setup_transfer(spi, NULL); |
e9abb4db HK |
427 | |
428 | pm_runtime_mark_last_busy(mpc8xxx_spi->dev); | |
429 | pm_runtime_put_autosuspend(mpc8xxx_spi->dev); | |
430 | ||
8b60d6c2 MH |
431 | return 0; |
432 | } | |
433 | ||
d9f26748 AL |
434 | static void fsl_espi_cleanup(struct spi_device *spi) |
435 | { | |
436 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); | |
437 | ||
438 | kfree(cs); | |
439 | spi_set_ctldata(spi, NULL); | |
440 | } | |
441 | ||
10ed1e6d | 442 | static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
8b60d6c2 | 443 | { |
f05689a6 HK |
444 | if (mspi->rx_len) |
445 | fsl_espi_read_rx_fifo(mspi, events); | |
8b60d6c2 | 446 | |
54731265 HK |
447 | if (mspi->tx_len) |
448 | fsl_espi_fill_tx_fifo(mspi, events); | |
8b60d6c2 | 449 | |
db1b049f HK |
450 | if (mspi->tx_len || mspi->rx_len) |
451 | return; | |
452 | ||
453 | /* we're done, but check for errors before returning */ | |
454 | events = fsl_espi_read_reg(mspi, ESPI_SPIE); | |
455 | ||
456 | if (!(events & SPIE_DON)) | |
457 | dev_err(mspi->dev, | |
458 | "Transfer done but SPIE_DON isn't set!\n"); | |
459 | ||
460 | if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) | |
461 | dev_err(mspi->dev, "Transfer done but rx/tx fifo's aren't empty!\n"); | |
462 | ||
463 | complete(&mspi->done); | |
8b60d6c2 MH |
464 | } |
465 | ||
466 | static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) | |
467 | { | |
468 | struct mpc8xxx_spi *mspi = context_data; | |
8b60d6c2 MH |
469 | u32 events; |
470 | ||
54731265 HK |
471 | spin_lock(&mspi->lock); |
472 | ||
8b60d6c2 | 473 | /* Get interrupt events(tx/rx) */ |
46afd38b | 474 | events = fsl_espi_read_reg(mspi, ESPI_SPIE); |
54731265 | 475 | if (!events) { |
66b8053e | 476 | spin_unlock(&mspi->lock); |
35f5d71e | 477 | return IRQ_NONE; |
54731265 | 478 | } |
8b60d6c2 MH |
479 | |
480 | dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events); | |
481 | ||
482 | fsl_espi_cpu_irq(mspi, events); | |
483 | ||
35f5d71e | 484 | /* Clear the events */ |
46afd38b | 485 | fsl_espi_write_reg(mspi, ESPI_SPIE, events); |
35f5d71e | 486 | |
54731265 HK |
487 | spin_unlock(&mspi->lock); |
488 | ||
35f5d71e | 489 | return IRQ_HANDLED; |
8b60d6c2 MH |
490 | } |
491 | ||
e9abb4db HK |
492 | #ifdef CONFIG_PM |
493 | static int fsl_espi_runtime_suspend(struct device *dev) | |
75506d0e | 494 | { |
e9abb4db HK |
495 | struct spi_master *master = dev_get_drvdata(dev); |
496 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
75506d0e HK |
497 | u32 regval; |
498 | ||
46afd38b | 499 | regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
75506d0e | 500 | regval &= ~SPMODE_ENABLE; |
46afd38b | 501 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
75506d0e HK |
502 | |
503 | return 0; | |
504 | } | |
505 | ||
e9abb4db | 506 | static int fsl_espi_runtime_resume(struct device *dev) |
75506d0e | 507 | { |
e9abb4db HK |
508 | struct spi_master *master = dev_get_drvdata(dev); |
509 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
75506d0e HK |
510 | u32 regval; |
511 | ||
46afd38b | 512 | regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
75506d0e | 513 | regval |= SPMODE_ENABLE; |
46afd38b | 514 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
75506d0e HK |
515 | |
516 | return 0; | |
517 | } | |
e9abb4db | 518 | #endif |
75506d0e | 519 | |
02a595d5 | 520 | static size_t fsl_espi_max_message_size(struct spi_device *spi) |
b541eef1 MS |
521 | { |
522 | return SPCOM_TRANLEN_MAX; | |
523 | } | |
524 | ||
604042af HK |
525 | static int fsl_espi_probe(struct device *dev, struct resource *mem, |
526 | unsigned int irq) | |
8b60d6c2 | 527 | { |
8074cf06 | 528 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
8b60d6c2 MH |
529 | struct spi_master *master; |
530 | struct mpc8xxx_spi *mpc8xxx_spi; | |
d0fb47a5 | 531 | struct device_node *nc; |
b497eb02 HK |
532 | u32 regval, csmode, cs, prop; |
533 | int ret; | |
8b60d6c2 MH |
534 | |
535 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); | |
604042af HK |
536 | if (!master) |
537 | return -ENOMEM; | |
8b60d6c2 MH |
538 | |
539 | dev_set_drvdata(dev, master); | |
540 | ||
c592becb | 541 | mpc8xxx_spi_probe(dev, mem, irq); |
8b60d6c2 | 542 | |
24778be2 | 543 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
8b60d6c2 | 544 | master->setup = fsl_espi_setup; |
d9f26748 | 545 | master->cleanup = fsl_espi_cleanup; |
c592becb | 546 | master->transfer_one_message = fsl_espi_do_one_msg; |
e9abb4db | 547 | master->auto_runtime_pm = true; |
02a595d5 | 548 | master->max_message_size = fsl_espi_max_message_size; |
8b60d6c2 MH |
549 | |
550 | mpc8xxx_spi = spi_master_get_devdata(master); | |
54731265 | 551 | spin_lock_init(&mpc8xxx_spi->lock); |
8b60d6c2 | 552 | |
1423877b HK |
553 | mpc8xxx_spi->local_buf = |
554 | devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL); | |
555 | if (!mpc8xxx_spi->local_buf) { | |
556 | ret = -ENOMEM; | |
557 | goto err_probe; | |
558 | } | |
559 | ||
4178b6b1 | 560 | mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); |
37c5db79 AL |
561 | if (IS_ERR(mpc8xxx_spi->reg_base)) { |
562 | ret = PTR_ERR(mpc8xxx_spi->reg_base); | |
8b60d6c2 MH |
563 | goto err_probe; |
564 | } | |
565 | ||
8b60d6c2 | 566 | /* Register for SPI Interrupt */ |
4178b6b1 | 567 | ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq, |
8b60d6c2 MH |
568 | 0, "fsl_espi", mpc8xxx_spi); |
569 | if (ret) | |
4178b6b1 | 570 | goto err_probe; |
8b60d6c2 MH |
571 | |
572 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { | |
e9e128a6 HK |
573 | dev_err(dev, "SPI_QE_CPU_MODE is not supported on ESPI!\n"); |
574 | ret = -EINVAL; | |
575 | goto err_probe; | |
8b60d6c2 MH |
576 | } |
577 | ||
578 | /* SPI controller initializations */ | |
46afd38b HK |
579 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0); |
580 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); | |
581 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0); | |
582 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff); | |
8b60d6c2 MH |
583 | |
584 | /* Init eSPI CS mode register */ | |
d0fb47a5 JW |
585 | for_each_available_child_of_node(master->dev.of_node, nc) { |
586 | /* get chip select */ | |
b497eb02 HK |
587 | ret = of_property_read_u32(nc, "reg", &cs); |
588 | if (ret || cs >= pdata->max_chipselect) | |
d0fb47a5 JW |
589 | continue; |
590 | ||
591 | csmode = CSMODE_INIT_VAL; | |
b497eb02 | 592 | |
d0fb47a5 | 593 | /* check if CSBEF is set in device tree */ |
b497eb02 HK |
594 | ret = of_property_read_u32(nc, "fsl,csbef", &prop); |
595 | if (!ret) { | |
d0fb47a5 | 596 | csmode &= ~(CSMODE_BEF(0xf)); |
b497eb02 | 597 | csmode |= CSMODE_BEF(prop); |
d0fb47a5 | 598 | } |
b497eb02 | 599 | |
d0fb47a5 | 600 | /* check if CSAFT is set in device tree */ |
b497eb02 HK |
601 | ret = of_property_read_u32(nc, "fsl,csaft", &prop); |
602 | if (!ret) { | |
d0fb47a5 | 603 | csmode &= ~(CSMODE_AFT(0xf)); |
b497eb02 | 604 | csmode |= CSMODE_AFT(prop); |
d0fb47a5 | 605 | } |
d0fb47a5 | 606 | |
b497eb02 HK |
607 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(cs), csmode); |
608 | ||
609 | dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode); | |
d0fb47a5 | 610 | } |
8b60d6c2 MH |
611 | |
612 | /* Enable SPI interface */ | |
613 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
614 | ||
46afd38b | 615 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
8b60d6c2 | 616 | |
e9abb4db HK |
617 | pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT); |
618 | pm_runtime_use_autosuspend(dev); | |
619 | pm_runtime_set_active(dev); | |
620 | pm_runtime_enable(dev); | |
621 | pm_runtime_get_sync(dev); | |
622 | ||
4178b6b1 | 623 | ret = devm_spi_register_master(dev, master); |
8b60d6c2 | 624 | if (ret < 0) |
e9abb4db | 625 | goto err_pm; |
8b60d6c2 | 626 | |
46afd38b HK |
627 | dev_info(dev, "at 0x%p (irq = %d)\n", mpc8xxx_spi->reg_base, |
628 | mpc8xxx_spi->irq); | |
8b60d6c2 | 629 | |
e9abb4db HK |
630 | pm_runtime_mark_last_busy(dev); |
631 | pm_runtime_put_autosuspend(dev); | |
632 | ||
604042af | 633 | return 0; |
8b60d6c2 | 634 | |
e9abb4db HK |
635 | err_pm: |
636 | pm_runtime_put_noidle(dev); | |
637 | pm_runtime_disable(dev); | |
638 | pm_runtime_set_suspended(dev); | |
8b60d6c2 MH |
639 | err_probe: |
640 | spi_master_put(master); | |
604042af | 641 | return ret; |
8b60d6c2 MH |
642 | } |
643 | ||
644 | static int of_fsl_espi_get_chipselects(struct device *dev) | |
645 | { | |
646 | struct device_node *np = dev->of_node; | |
8074cf06 | 647 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
b497eb02 HK |
648 | u32 num_cs; |
649 | int ret; | |
8b60d6c2 | 650 | |
b497eb02 HK |
651 | ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs); |
652 | if (ret) { | |
8b60d6c2 MH |
653 | dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); |
654 | return -EINVAL; | |
655 | } | |
656 | ||
b497eb02 | 657 | pdata->max_chipselect = num_cs; |
8b60d6c2 MH |
658 | pdata->cs_control = NULL; |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
fd4a319b | 663 | static int of_fsl_espi_probe(struct platform_device *ofdev) |
8b60d6c2 MH |
664 | { |
665 | struct device *dev = &ofdev->dev; | |
666 | struct device_node *np = ofdev->dev.of_node; | |
8b60d6c2 | 667 | struct resource mem; |
f7578496 | 668 | unsigned int irq; |
acf69219 | 669 | int ret; |
8b60d6c2 | 670 | |
18d306d1 | 671 | ret = of_mpc8xxx_spi_probe(ofdev); |
8b60d6c2 MH |
672 | if (ret) |
673 | return ret; | |
674 | ||
675 | ret = of_fsl_espi_get_chipselects(dev); | |
676 | if (ret) | |
acf69219 | 677 | return ret; |
8b60d6c2 MH |
678 | |
679 | ret = of_address_to_resource(np, 0, &mem); | |
680 | if (ret) | |
acf69219 | 681 | return ret; |
8b60d6c2 | 682 | |
f7578496 | 683 | irq = irq_of_parse_and_map(np, 0); |
acf69219 HK |
684 | if (!irq) |
685 | return -EINVAL; | |
8b60d6c2 | 686 | |
604042af | 687 | return fsl_espi_probe(dev, &mem, irq); |
8b60d6c2 MH |
688 | } |
689 | ||
e9abb4db HK |
690 | static int of_fsl_espi_remove(struct platform_device *dev) |
691 | { | |
692 | pm_runtime_disable(&dev->dev); | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
714bb654 HZ |
697 | #ifdef CONFIG_PM_SLEEP |
698 | static int of_fsl_espi_suspend(struct device *dev) | |
699 | { | |
700 | struct spi_master *master = dev_get_drvdata(dev); | |
714bb654 HZ |
701 | int ret; |
702 | ||
714bb654 HZ |
703 | ret = spi_master_suspend(master); |
704 | if (ret) { | |
705 | dev_warn(dev, "cannot suspend master\n"); | |
706 | return ret; | |
707 | } | |
708 | ||
e9abb4db HK |
709 | ret = pm_runtime_force_suspend(dev); |
710 | if (ret < 0) | |
711 | return ret; | |
712 | ||
713 | return 0; | |
714bb654 HZ |
714 | } |
715 | ||
716 | static int of_fsl_espi_resume(struct device *dev) | |
717 | { | |
718 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); | |
719 | struct spi_master *master = dev_get_drvdata(dev); | |
720 | struct mpc8xxx_spi *mpc8xxx_spi; | |
714bb654 | 721 | u32 regval; |
e9abb4db | 722 | int i, ret; |
714bb654 HZ |
723 | |
724 | mpc8xxx_spi = spi_master_get_devdata(master); | |
714bb654 HZ |
725 | |
726 | /* SPI controller initializations */ | |
46afd38b HK |
727 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0); |
728 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); | |
729 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0); | |
730 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff); | |
714bb654 HZ |
731 | |
732 | /* Init eSPI CS mode register */ | |
733 | for (i = 0; i < pdata->max_chipselect; i++) | |
46afd38b HK |
734 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i), |
735 | CSMODE_INIT_VAL); | |
714bb654 HZ |
736 | |
737 | /* Enable SPI interface */ | |
738 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
739 | ||
46afd38b | 740 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
714bb654 | 741 | |
e9abb4db HK |
742 | ret = pm_runtime_force_resume(dev); |
743 | if (ret < 0) | |
744 | return ret; | |
745 | ||
714bb654 HZ |
746 | return spi_master_resume(master); |
747 | } | |
748 | #endif /* CONFIG_PM_SLEEP */ | |
749 | ||
750 | static const struct dev_pm_ops espi_pm = { | |
e9abb4db HK |
751 | SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend, |
752 | fsl_espi_runtime_resume, NULL) | |
714bb654 HZ |
753 | SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) |
754 | }; | |
755 | ||
8b60d6c2 MH |
756 | static const struct of_device_id of_fsl_espi_match[] = { |
757 | { .compatible = "fsl,mpc8536-espi" }, | |
758 | {} | |
759 | }; | |
760 | MODULE_DEVICE_TABLE(of, of_fsl_espi_match); | |
761 | ||
18d306d1 | 762 | static struct platform_driver fsl_espi_driver = { |
8b60d6c2 MH |
763 | .driver = { |
764 | .name = "fsl_espi", | |
8b60d6c2 | 765 | .of_match_table = of_fsl_espi_match, |
714bb654 | 766 | .pm = &espi_pm, |
8b60d6c2 MH |
767 | }, |
768 | .probe = of_fsl_espi_probe, | |
e9abb4db | 769 | .remove = of_fsl_espi_remove, |
8b60d6c2 | 770 | }; |
940ab889 | 771 | module_platform_driver(fsl_espi_driver); |
8b60d6c2 MH |
772 | |
773 | MODULE_AUTHOR("Mingkai Hu"); | |
774 | MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); | |
775 | MODULE_LICENSE("GPL"); |