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Commit | Line | Data |
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8b60d6c2 MH |
1 | /* |
2 | * Freescale eSPI controller driver. | |
3 | * | |
4 | * Copyright 2010 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
8b60d6c2 | 11 | #include <linux/delay.h> |
a3108360 | 12 | #include <linux/err.h> |
8b60d6c2 | 13 | #include <linux/fsl_devices.h> |
a3108360 | 14 | #include <linux/interrupt.h> |
a3108360 | 15 | #include <linux/module.h> |
8b60d6c2 MH |
16 | #include <linux/mm.h> |
17 | #include <linux/of.h> | |
5af50730 RH |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_irq.h> | |
8b60d6c2 | 20 | #include <linux/of_platform.h> |
a3108360 XL |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spi/spi.h> | |
e9abb4db | 23 | #include <linux/pm_runtime.h> |
8b60d6c2 MH |
24 | #include <sysdev/fsl_soc.h> |
25 | ||
ca632f55 | 26 | #include "spi-fsl-lib.h" |
8b60d6c2 MH |
27 | |
28 | /* eSPI Controller registers */ | |
29 | struct fsl_espi_reg { | |
30 | __be32 mode; /* 0x000 - eSPI mode register */ | |
31 | __be32 event; /* 0x004 - eSPI event register */ | |
32 | __be32 mask; /* 0x008 - eSPI mask register */ | |
33 | __be32 command; /* 0x00c - eSPI command register */ | |
34 | __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/ | |
35 | __be32 receive; /* 0x014 - eSPI receive FIFO access register*/ | |
36 | u8 res[8]; /* 0x018 - 0x01c reserved */ | |
37 | __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */ | |
38 | }; | |
39 | ||
8b60d6c2 MH |
40 | /* eSPI Controller mode register definitions */ |
41 | #define SPMODE_ENABLE (1 << 31) | |
42 | #define SPMODE_LOOP (1 << 30) | |
43 | #define SPMODE_TXTHR(x) ((x) << 8) | |
44 | #define SPMODE_RXTHR(x) ((x) << 0) | |
45 | ||
46 | /* eSPI Controller CS mode register definitions */ | |
47 | #define CSMODE_CI_INACTIVEHIGH (1 << 31) | |
48 | #define CSMODE_CP_BEGIN_EDGECLK (1 << 30) | |
49 | #define CSMODE_REV (1 << 29) | |
50 | #define CSMODE_DIV16 (1 << 28) | |
51 | #define CSMODE_PM(x) ((x) << 24) | |
52 | #define CSMODE_POL_1 (1 << 20) | |
53 | #define CSMODE_LEN(x) ((x) << 16) | |
54 | #define CSMODE_BEF(x) ((x) << 12) | |
55 | #define CSMODE_AFT(x) ((x) << 8) | |
56 | #define CSMODE_CG(x) ((x) << 3) | |
57 | ||
58 | /* Default mode/csmode for eSPI controller */ | |
59 | #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3)) | |
60 | #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ | |
61 | | CSMODE_AFT(0) | CSMODE_CG(1)) | |
62 | ||
63 | /* SPIE register values */ | |
64 | #define SPIE_NE 0x00000200 /* Not empty */ | |
65 | #define SPIE_NF 0x00000100 /* Not full */ | |
66 | ||
67 | /* SPIM register values */ | |
68 | #define SPIM_NE 0x00000200 /* Not empty */ | |
69 | #define SPIM_NF 0x00000100 /* Not full */ | |
70 | #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) | |
71 | #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) | |
72 | ||
73 | /* SPCOM register values */ | |
74 | #define SPCOM_CS(x) ((x) << 30) | |
75 | #define SPCOM_TRANLEN(x) ((x) << 0) | |
5cfa1e4e | 76 | #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */ |
8b60d6c2 | 77 | |
e9abb4db HK |
78 | #define AUTOSUSPEND_TIMEOUT 2000 |
79 | ||
cce7e3a2 HK |
80 | static void fsl_espi_copy_to_buf(struct spi_message *m, |
81 | struct mpc8xxx_spi *mspi) | |
7c159aa8 | 82 | { |
7c159aa8 HK |
83 | struct spi_transfer *t; |
84 | u8 *buf = mspi->local_buf; | |
85 | ||
86 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
cce7e3a2 | 87 | if (t->tx_buf) |
7c159aa8 | 88 | memcpy(buf, t->tx_buf, t->len); |
cce7e3a2 | 89 | else |
7c159aa8 | 90 | memset(buf, 0, t->len); |
7c159aa8 HK |
91 | buf += t->len; |
92 | } | |
cce7e3a2 HK |
93 | } |
94 | ||
95 | static void fsl_espi_copy_from_buf(struct spi_message *m, | |
96 | struct mpc8xxx_spi *mspi) | |
97 | { | |
98 | struct spi_transfer *t; | |
99 | u8 *buf = mspi->local_buf; | |
7c159aa8 | 100 | |
cce7e3a2 HK |
101 | list_for_each_entry(t, &m->transfers, transfer_list) { |
102 | if (t->rx_buf) | |
103 | memcpy(t->rx_buf, buf, t->len); | |
104 | buf += t->len; | |
105 | } | |
7c159aa8 HK |
106 | } |
107 | ||
d3152cf1 HK |
108 | static int fsl_espi_check_message(struct spi_message *m) |
109 | { | |
110 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); | |
111 | struct spi_transfer *t, *first; | |
112 | ||
113 | if (m->frame_length > SPCOM_TRANLEN_MAX) { | |
114 | dev_err(mspi->dev, "message too long, size is %u bytes\n", | |
115 | m->frame_length); | |
116 | return -EMSGSIZE; | |
117 | } | |
118 | ||
119 | first = list_first_entry(&m->transfers, struct spi_transfer, | |
120 | transfer_list); | |
121 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
122 | if (first->bits_per_word != t->bits_per_word || | |
123 | first->speed_hz != t->speed_hz) { | |
124 | dev_err(mspi->dev, "bits_per_word/speed_hz should be the same for all transfers\n"); | |
125 | return -EINVAL; | |
126 | } | |
127 | } | |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
8b60d6c2 MH |
132 | static void fsl_espi_change_mode(struct spi_device *spi) |
133 | { | |
134 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
135 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
136 | struct fsl_espi_reg *reg_base = mspi->reg_base; | |
137 | __be32 __iomem *mode = ®_base->csmode[spi->chip_select]; | |
138 | __be32 __iomem *espi_mode = ®_base->mode; | |
139 | u32 tmp; | |
140 | unsigned long flags; | |
141 | ||
142 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
143 | local_irq_save(flags); | |
144 | ||
145 | /* Turn off SPI unit prior changing mode */ | |
146 | tmp = mpc8xxx_spi_read_reg(espi_mode); | |
147 | mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE); | |
148 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); | |
149 | mpc8xxx_spi_write_reg(espi_mode, tmp); | |
150 | ||
151 | local_irq_restore(flags); | |
152 | } | |
153 | ||
154 | static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi) | |
155 | { | |
156 | u32 data; | |
157 | u16 data_h; | |
158 | u16 data_l; | |
159 | const u32 *tx = mpc8xxx_spi->tx; | |
160 | ||
161 | if (!tx) | |
162 | return 0; | |
163 | ||
164 | data = *tx++ << mpc8xxx_spi->tx_shift; | |
165 | data_l = data & 0xffff; | |
166 | data_h = (data >> 16) & 0xffff; | |
167 | swab16s(&data_l); | |
168 | swab16s(&data_h); | |
169 | data = data_h | data_l; | |
170 | ||
171 | mpc8xxx_spi->tx = tx; | |
172 | return data; | |
173 | } | |
174 | ||
ea616ee2 | 175 | static void fsl_espi_setup_transfer(struct spi_device *spi, |
8b60d6c2 MH |
176 | struct spi_transfer *t) |
177 | { | |
178 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
179 | int bits_per_word = 0; | |
180 | u8 pm; | |
181 | u32 hz = 0; | |
182 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
183 | ||
184 | if (t) { | |
185 | bits_per_word = t->bits_per_word; | |
186 | hz = t->speed_hz; | |
187 | } | |
188 | ||
189 | /* spi_transfer level calls that work per-word */ | |
190 | if (!bits_per_word) | |
191 | bits_per_word = spi->bits_per_word; | |
192 | ||
8b60d6c2 MH |
193 | if (!hz) |
194 | hz = spi->max_speed_hz; | |
195 | ||
196 | cs->rx_shift = 0; | |
197 | cs->tx_shift = 0; | |
198 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; | |
199 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
200 | if (bits_per_word <= 8) { | |
201 | cs->rx_shift = 8 - bits_per_word; | |
51faed69 | 202 | } else { |
8b60d6c2 MH |
203 | cs->rx_shift = 16 - bits_per_word; |
204 | if (spi->mode & SPI_LSB_FIRST) | |
205 | cs->get_tx = fsl_espi_tx_buf_lsb; | |
8b60d6c2 MH |
206 | } |
207 | ||
208 | mpc8xxx_spi->rx_shift = cs->rx_shift; | |
209 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
210 | mpc8xxx_spi->get_rx = cs->get_rx; | |
211 | mpc8xxx_spi->get_tx = cs->get_tx; | |
212 | ||
8b60d6c2 MH |
213 | /* mask out bits we are going to set */ |
214 | cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); | |
215 | ||
a755af52 | 216 | cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); |
8b60d6c2 MH |
217 | |
218 | if ((mpc8xxx_spi->spibrg / hz) > 64) { | |
219 | cs->hw_mode |= CSMODE_DIV16; | |
35faa55c | 220 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4); |
8b60d6c2 | 221 | |
87bf5ab8 | 222 | WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. " |
8b60d6c2 | 223 | "Will use %d Hz instead.\n", dev_name(&spi->dev), |
87bf5ab8 SAS |
224 | hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1))); |
225 | if (pm > 33) | |
226 | pm = 33; | |
8b60d6c2 | 227 | } else { |
35faa55c | 228 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4); |
8b60d6c2 MH |
229 | } |
230 | if (pm) | |
231 | pm--; | |
87bf5ab8 SAS |
232 | if (pm < 2) |
233 | pm = 2; | |
8b60d6c2 MH |
234 | |
235 | cs->hw_mode |= CSMODE_PM(pm); | |
236 | ||
237 | fsl_espi_change_mode(spi); | |
8b60d6c2 MH |
238 | } |
239 | ||
8b60d6c2 MH |
240 | static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) |
241 | { | |
242 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
243 | struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; | |
5bcc6a2f | 244 | u32 word; |
8b60d6c2 MH |
245 | int ret; |
246 | ||
8b60d6c2 | 247 | mpc8xxx_spi->len = t->len; |
5bcc6a2f | 248 | mpc8xxx_spi->count = roundup(t->len, 4) / 4; |
8b60d6c2 MH |
249 | |
250 | mpc8xxx_spi->tx = t->tx_buf; | |
251 | mpc8xxx_spi->rx = t->rx_buf; | |
252 | ||
16735d02 | 253 | reinit_completion(&mpc8xxx_spi->done); |
8b60d6c2 MH |
254 | |
255 | /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ | |
8b60d6c2 MH |
256 | mpc8xxx_spi_write_reg(®_base->command, |
257 | (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1))); | |
258 | ||
5bcc6a2f HK |
259 | /* enable rx ints */ |
260 | mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); | |
261 | ||
262 | /* transmit word */ | |
263 | word = mpc8xxx_spi->get_tx(mpc8xxx_spi); | |
264 | mpc8xxx_spi_write_reg(®_base->transmit, word); | |
8b60d6c2 | 265 | |
aa70e567 NH |
266 | /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ |
267 | ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ); | |
268 | if (ret == 0) | |
269 | dev_err(mpc8xxx_spi->dev, | |
270 | "Transaction hanging up (left %d bytes)\n", | |
271 | mpc8xxx_spi->count); | |
8b60d6c2 MH |
272 | |
273 | /* disable rx ints */ | |
274 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
275 | ||
84ccfc37 | 276 | return mpc8xxx_spi->count > 0 ? -EMSGSIZE : 0; |
8b60d6c2 MH |
277 | } |
278 | ||
faceef39 | 279 | static int fsl_espi_do_trans(struct spi_message *m, struct spi_transfer *trans) |
8b60d6c2 MH |
280 | { |
281 | struct spi_device *spi = m->spi; | |
e33a3ade | 282 | int ret = 0; |
8b60d6c2 | 283 | |
faceef39 | 284 | fsl_espi_setup_transfer(spi, trans); |
8b60d6c2 | 285 | |
faceef39 HK |
286 | if (trans->len) |
287 | ret = fsl_espi_bufs(spi, trans); | |
8b60d6c2 | 288 | |
faceef39 HK |
289 | if (trans->delay_usecs) |
290 | udelay(trans->delay_usecs); | |
8b60d6c2 | 291 | |
8b60d6c2 | 292 | fsl_espi_setup_transfer(spi, NULL); |
e33a3ade HK |
293 | |
294 | return ret; | |
8b60d6c2 MH |
295 | } |
296 | ||
cce7e3a2 | 297 | static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans) |
8b60d6c2 | 298 | { |
1423877b | 299 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
e33a3ade | 300 | int ret; |
8b60d6c2 | 301 | |
cce7e3a2 | 302 | fsl_espi_copy_to_buf(m, mspi); |
8b60d6c2 | 303 | |
e33a3ade | 304 | ret = fsl_espi_do_trans(m, trans); |
8b60d6c2 | 305 | |
cce7e3a2 HK |
306 | if (!ret) |
307 | fsl_espi_copy_from_buf(m, mspi); | |
e33a3ade HK |
308 | |
309 | return ret; | |
8b60d6c2 MH |
310 | } |
311 | ||
c592becb HK |
312 | static int fsl_espi_do_one_msg(struct spi_master *master, |
313 | struct spi_message *m) | |
8b60d6c2 | 314 | { |
96361faf | 315 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
96361faf | 316 | unsigned int delay_usecs = 0, xfer_len = 0; |
faceef39 | 317 | struct spi_transfer *t, trans = {}; |
e33a3ade | 318 | int ret; |
8b60d6c2 | 319 | |
d3152cf1 HK |
320 | ret = fsl_espi_check_message(m); |
321 | if (ret) | |
322 | goto out; | |
323 | ||
8b60d6c2 | 324 | list_for_each_entry(t, &m->transfers, transfer_list) { |
2000058e JR |
325 | if ((t->tx_buf) || (t->rx_buf)) |
326 | xfer_len += t->len; | |
96361faf HK |
327 | if (t->delay_usecs > delay_usecs) |
328 | delay_usecs = t->delay_usecs; | |
8b60d6c2 MH |
329 | } |
330 | ||
96361faf HK |
331 | t = list_first_entry(&m->transfers, struct spi_transfer, |
332 | transfer_list); | |
333 | ||
faceef39 | 334 | trans.len = xfer_len; |
96361faf HK |
335 | trans.speed_hz = t->speed_hz; |
336 | trans.bits_per_word = t->bits_per_word; | |
337 | trans.delay_usecs = delay_usecs; | |
338 | trans.tx_buf = mspi->local_buf; | |
339 | trans.rx_buf = mspi->local_buf; | |
8b60d6c2 | 340 | |
cce7e3a2 | 341 | ret = fsl_espi_trans(m, &trans); |
8b60d6c2 | 342 | |
faceef39 | 343 | m->actual_length = ret ? 0 : trans.len; |
d3152cf1 | 344 | out: |
0319d499 HK |
345 | if (m->status == -EINPROGRESS) |
346 | m->status = ret; | |
347 | ||
c592becb | 348 | spi_finalize_current_message(master); |
0319d499 HK |
349 | |
350 | return ret; | |
8b60d6c2 MH |
351 | } |
352 | ||
353 | static int fsl_espi_setup(struct spi_device *spi) | |
354 | { | |
355 | struct mpc8xxx_spi *mpc8xxx_spi; | |
356 | struct fsl_espi_reg *reg_base; | |
8b60d6c2 MH |
357 | u32 hw_mode; |
358 | u32 loop_mode; | |
d9f26748 | 359 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
8b60d6c2 MH |
360 | |
361 | if (!spi->max_speed_hz) | |
362 | return -EINVAL; | |
363 | ||
364 | if (!cs) { | |
d9f26748 | 365 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
8b60d6c2 MH |
366 | if (!cs) |
367 | return -ENOMEM; | |
d9f26748 | 368 | spi_set_ctldata(spi, cs); |
8b60d6c2 MH |
369 | } |
370 | ||
371 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
372 | reg_base = mpc8xxx_spi->reg_base; | |
373 | ||
e9abb4db HK |
374 | pm_runtime_get_sync(mpc8xxx_spi->dev); |
375 | ||
25985edc | 376 | hw_mode = cs->hw_mode; /* Save original settings */ |
8b60d6c2 MH |
377 | cs->hw_mode = mpc8xxx_spi_read_reg( |
378 | ®_base->csmode[spi->chip_select]); | |
379 | /* mask out bits we are going to set */ | |
380 | cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH | |
381 | | CSMODE_REV); | |
382 | ||
383 | if (spi->mode & SPI_CPHA) | |
384 | cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; | |
385 | if (spi->mode & SPI_CPOL) | |
386 | cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; | |
387 | if (!(spi->mode & SPI_LSB_FIRST)) | |
388 | cs->hw_mode |= CSMODE_REV; | |
389 | ||
390 | /* Handle the loop mode */ | |
391 | loop_mode = mpc8xxx_spi_read_reg(®_base->mode); | |
392 | loop_mode &= ~SPMODE_LOOP; | |
393 | if (spi->mode & SPI_LOOP) | |
394 | loop_mode |= SPMODE_LOOP; | |
395 | mpc8xxx_spi_write_reg(®_base->mode, loop_mode); | |
396 | ||
ea616ee2 | 397 | fsl_espi_setup_transfer(spi, NULL); |
e9abb4db HK |
398 | |
399 | pm_runtime_mark_last_busy(mpc8xxx_spi->dev); | |
400 | pm_runtime_put_autosuspend(mpc8xxx_spi->dev); | |
401 | ||
8b60d6c2 MH |
402 | return 0; |
403 | } | |
404 | ||
d9f26748 AL |
405 | static void fsl_espi_cleanup(struct spi_device *spi) |
406 | { | |
407 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); | |
408 | ||
409 | kfree(cs); | |
410 | spi_set_ctldata(spi, NULL); | |
411 | } | |
412 | ||
10ed1e6d | 413 | static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
8b60d6c2 MH |
414 | { |
415 | struct fsl_espi_reg *reg_base = mspi->reg_base; | |
416 | ||
417 | /* We need handle RX first */ | |
418 | if (events & SPIE_NE) { | |
e6289d63 MH |
419 | u32 rx_data, tmp; |
420 | u8 rx_data_8; | |
6319a680 | 421 | int rx_nr_bytes = 4; |
a12ddd60 | 422 | int ret; |
8b60d6c2 MH |
423 | |
424 | /* Spin until RX is done */ | |
a12ddd60 NH |
425 | if (SPIE_RXCNT(events) < min(4, mspi->len)) { |
426 | ret = spin_event_timeout( | |
427 | !(SPIE_RXCNT(events = | |
428 | mpc8xxx_spi_read_reg(®_base->event)) < | |
429 | min(4, mspi->len)), | |
430 | 10000, 0); /* 10 msec */ | |
431 | if (!ret) | |
432 | dev_err(mspi->dev, | |
433 | "tired waiting for SPIE_RXCNT\n"); | |
8b60d6c2 | 434 | } |
8b60d6c2 | 435 | |
e6289d63 MH |
436 | if (mspi->len >= 4) { |
437 | rx_data = mpc8xxx_spi_read_reg(®_base->receive); | |
6319a680 NH |
438 | } else if (mspi->len <= 0) { |
439 | dev_err(mspi->dev, | |
440 | "unexpected RX(SPIE_NE) interrupt occurred,\n" | |
441 | "(local rxlen %d bytes, reg rxlen %d bytes)\n", | |
442 | min(4, mspi->len), SPIE_RXCNT(events)); | |
443 | rx_nr_bytes = 0; | |
e6289d63 | 444 | } else { |
6319a680 | 445 | rx_nr_bytes = mspi->len; |
e6289d63 MH |
446 | tmp = mspi->len; |
447 | rx_data = 0; | |
448 | while (tmp--) { | |
449 | rx_data_8 = in_8((u8 *)®_base->receive); | |
450 | rx_data |= (rx_data_8 << (tmp * 8)); | |
451 | } | |
452 | ||
453 | rx_data <<= (4 - mspi->len) * 8; | |
454 | } | |
455 | ||
6319a680 | 456 | mspi->len -= rx_nr_bytes; |
8b60d6c2 MH |
457 | |
458 | if (mspi->rx) | |
459 | mspi->get_rx(rx_data, mspi); | |
460 | } | |
461 | ||
462 | if (!(events & SPIE_NF)) { | |
463 | int ret; | |
464 | ||
465 | /* spin until TX is done */ | |
466 | ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg( | |
7a0a1759 | 467 | ®_base->event)) & SPIE_NF), 1000, 0); |
8b60d6c2 MH |
468 | if (!ret) { |
469 | dev_err(mspi->dev, "tired waiting for SPIE_NF\n"); | |
7a0a1759 JW |
470 | |
471 | /* Clear the SPIE bits */ | |
472 | mpc8xxx_spi_write_reg(®_base->event, events); | |
473 | complete(&mspi->done); | |
8b60d6c2 MH |
474 | return; |
475 | } | |
476 | } | |
477 | ||
478 | /* Clear the events */ | |
479 | mpc8xxx_spi_write_reg(®_base->event, events); | |
480 | ||
481 | mspi->count -= 1; | |
482 | if (mspi->count) { | |
483 | u32 word = mspi->get_tx(mspi); | |
484 | ||
485 | mpc8xxx_spi_write_reg(®_base->transmit, word); | |
486 | } else { | |
487 | complete(&mspi->done); | |
488 | } | |
489 | } | |
490 | ||
491 | static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) | |
492 | { | |
493 | struct mpc8xxx_spi *mspi = context_data; | |
494 | struct fsl_espi_reg *reg_base = mspi->reg_base; | |
495 | irqreturn_t ret = IRQ_NONE; | |
496 | u32 events; | |
497 | ||
498 | /* Get interrupt events(tx/rx) */ | |
499 | events = mpc8xxx_spi_read_reg(®_base->event); | |
500 | if (events) | |
501 | ret = IRQ_HANDLED; | |
502 | ||
503 | dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events); | |
504 | ||
505 | fsl_espi_cpu_irq(mspi, events); | |
506 | ||
507 | return ret; | |
508 | } | |
509 | ||
e9abb4db HK |
510 | #ifdef CONFIG_PM |
511 | static int fsl_espi_runtime_suspend(struct device *dev) | |
75506d0e | 512 | { |
e9abb4db HK |
513 | struct spi_master *master = dev_get_drvdata(dev); |
514 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
515 | struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; | |
75506d0e HK |
516 | u32 regval; |
517 | ||
75506d0e HK |
518 | regval = mpc8xxx_spi_read_reg(®_base->mode); |
519 | regval &= ~SPMODE_ENABLE; | |
520 | mpc8xxx_spi_write_reg(®_base->mode, regval); | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
e9abb4db | 525 | static int fsl_espi_runtime_resume(struct device *dev) |
75506d0e | 526 | { |
e9abb4db HK |
527 | struct spi_master *master = dev_get_drvdata(dev); |
528 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
529 | struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; | |
75506d0e HK |
530 | u32 regval; |
531 | ||
75506d0e HK |
532 | regval = mpc8xxx_spi_read_reg(®_base->mode); |
533 | regval |= SPMODE_ENABLE; | |
534 | mpc8xxx_spi_write_reg(®_base->mode, regval); | |
535 | ||
536 | return 0; | |
537 | } | |
e9abb4db | 538 | #endif |
75506d0e | 539 | |
02a595d5 | 540 | static size_t fsl_espi_max_message_size(struct spi_device *spi) |
b541eef1 MS |
541 | { |
542 | return SPCOM_TRANLEN_MAX; | |
543 | } | |
544 | ||
fd4a319b | 545 | static struct spi_master * fsl_espi_probe(struct device *dev, |
8b60d6c2 MH |
546 | struct resource *mem, unsigned int irq) |
547 | { | |
8074cf06 | 548 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
8b60d6c2 MH |
549 | struct spi_master *master; |
550 | struct mpc8xxx_spi *mpc8xxx_spi; | |
551 | struct fsl_espi_reg *reg_base; | |
d0fb47a5 JW |
552 | struct device_node *nc; |
553 | const __be32 *prop; | |
554 | u32 regval, csmode; | |
555 | int i, len, ret = 0; | |
8b60d6c2 MH |
556 | |
557 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); | |
558 | if (!master) { | |
559 | ret = -ENOMEM; | |
560 | goto err; | |
561 | } | |
562 | ||
563 | dev_set_drvdata(dev, master); | |
564 | ||
c592becb | 565 | mpc8xxx_spi_probe(dev, mem, irq); |
8b60d6c2 | 566 | |
24778be2 | 567 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
8b60d6c2 | 568 | master->setup = fsl_espi_setup; |
d9f26748 | 569 | master->cleanup = fsl_espi_cleanup; |
c592becb | 570 | master->transfer_one_message = fsl_espi_do_one_msg; |
e9abb4db | 571 | master->auto_runtime_pm = true; |
02a595d5 | 572 | master->max_message_size = fsl_espi_max_message_size; |
8b60d6c2 MH |
573 | |
574 | mpc8xxx_spi = spi_master_get_devdata(master); | |
8b60d6c2 | 575 | |
1423877b HK |
576 | mpc8xxx_spi->local_buf = |
577 | devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL); | |
578 | if (!mpc8xxx_spi->local_buf) { | |
579 | ret = -ENOMEM; | |
580 | goto err_probe; | |
581 | } | |
582 | ||
4178b6b1 | 583 | mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); |
37c5db79 AL |
584 | if (IS_ERR(mpc8xxx_spi->reg_base)) { |
585 | ret = PTR_ERR(mpc8xxx_spi->reg_base); | |
8b60d6c2 MH |
586 | goto err_probe; |
587 | } | |
588 | ||
589 | reg_base = mpc8xxx_spi->reg_base; | |
590 | ||
591 | /* Register for SPI Interrupt */ | |
4178b6b1 | 592 | ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq, |
8b60d6c2 MH |
593 | 0, "fsl_espi", mpc8xxx_spi); |
594 | if (ret) | |
4178b6b1 | 595 | goto err_probe; |
8b60d6c2 MH |
596 | |
597 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { | |
598 | mpc8xxx_spi->rx_shift = 16; | |
599 | mpc8xxx_spi->tx_shift = 24; | |
600 | } | |
601 | ||
602 | /* SPI controller initializations */ | |
603 | mpc8xxx_spi_write_reg(®_base->mode, 0); | |
604 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
605 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
606 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
607 | ||
608 | /* Init eSPI CS mode register */ | |
d0fb47a5 JW |
609 | for_each_available_child_of_node(master->dev.of_node, nc) { |
610 | /* get chip select */ | |
611 | prop = of_get_property(nc, "reg", &len); | |
612 | if (!prop || len < sizeof(*prop)) | |
613 | continue; | |
614 | i = be32_to_cpup(prop); | |
615 | if (i < 0 || i >= pdata->max_chipselect) | |
616 | continue; | |
617 | ||
618 | csmode = CSMODE_INIT_VAL; | |
619 | /* check if CSBEF is set in device tree */ | |
620 | prop = of_get_property(nc, "fsl,csbef", &len); | |
621 | if (prop && len >= sizeof(*prop)) { | |
622 | csmode &= ~(CSMODE_BEF(0xf)); | |
623 | csmode |= CSMODE_BEF(be32_to_cpup(prop)); | |
624 | } | |
625 | /* check if CSAFT is set in device tree */ | |
626 | prop = of_get_property(nc, "fsl,csaft", &len); | |
627 | if (prop && len >= sizeof(*prop)) { | |
628 | csmode &= ~(CSMODE_AFT(0xf)); | |
629 | csmode |= CSMODE_AFT(be32_to_cpup(prop)); | |
630 | } | |
631 | mpc8xxx_spi_write_reg(®_base->csmode[i], csmode); | |
632 | ||
633 | dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode); | |
634 | } | |
8b60d6c2 MH |
635 | |
636 | /* Enable SPI interface */ | |
637 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
638 | ||
639 | mpc8xxx_spi_write_reg(®_base->mode, regval); | |
640 | ||
e9abb4db HK |
641 | pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT); |
642 | pm_runtime_use_autosuspend(dev); | |
643 | pm_runtime_set_active(dev); | |
644 | pm_runtime_enable(dev); | |
645 | pm_runtime_get_sync(dev); | |
646 | ||
4178b6b1 | 647 | ret = devm_spi_register_master(dev, master); |
8b60d6c2 | 648 | if (ret < 0) |
e9abb4db | 649 | goto err_pm; |
8b60d6c2 MH |
650 | |
651 | dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq); | |
652 | ||
e9abb4db HK |
653 | pm_runtime_mark_last_busy(dev); |
654 | pm_runtime_put_autosuspend(dev); | |
655 | ||
8b60d6c2 MH |
656 | return master; |
657 | ||
e9abb4db HK |
658 | err_pm: |
659 | pm_runtime_put_noidle(dev); | |
660 | pm_runtime_disable(dev); | |
661 | pm_runtime_set_suspended(dev); | |
8b60d6c2 MH |
662 | err_probe: |
663 | spi_master_put(master); | |
664 | err: | |
665 | return ERR_PTR(ret); | |
666 | } | |
667 | ||
668 | static int of_fsl_espi_get_chipselects(struct device *dev) | |
669 | { | |
670 | struct device_node *np = dev->of_node; | |
8074cf06 | 671 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
8b60d6c2 MH |
672 | const u32 *prop; |
673 | int len; | |
674 | ||
675 | prop = of_get_property(np, "fsl,espi-num-chipselects", &len); | |
676 | if (!prop || len < sizeof(*prop)) { | |
677 | dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); | |
678 | return -EINVAL; | |
679 | } | |
680 | ||
681 | pdata->max_chipselect = *prop; | |
682 | pdata->cs_control = NULL; | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
fd4a319b | 687 | static int of_fsl_espi_probe(struct platform_device *ofdev) |
8b60d6c2 MH |
688 | { |
689 | struct device *dev = &ofdev->dev; | |
690 | struct device_node *np = ofdev->dev.of_node; | |
691 | struct spi_master *master; | |
692 | struct resource mem; | |
f7578496 | 693 | unsigned int irq; |
8b60d6c2 MH |
694 | int ret = -ENOMEM; |
695 | ||
18d306d1 | 696 | ret = of_mpc8xxx_spi_probe(ofdev); |
8b60d6c2 MH |
697 | if (ret) |
698 | return ret; | |
699 | ||
700 | ret = of_fsl_espi_get_chipselects(dev); | |
701 | if (ret) | |
702 | goto err; | |
703 | ||
704 | ret = of_address_to_resource(np, 0, &mem); | |
705 | if (ret) | |
706 | goto err; | |
707 | ||
f7578496 | 708 | irq = irq_of_parse_and_map(np, 0); |
7227cd18 | 709 | if (!irq) { |
8b60d6c2 MH |
710 | ret = -EINVAL; |
711 | goto err; | |
712 | } | |
713 | ||
f7578496 | 714 | master = fsl_espi_probe(dev, &mem, irq); |
8b60d6c2 MH |
715 | if (IS_ERR(master)) { |
716 | ret = PTR_ERR(master); | |
717 | goto err; | |
718 | } | |
719 | ||
720 | return 0; | |
721 | ||
722 | err: | |
723 | return ret; | |
724 | } | |
725 | ||
e9abb4db HK |
726 | static int of_fsl_espi_remove(struct platform_device *dev) |
727 | { | |
728 | pm_runtime_disable(&dev->dev); | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
714bb654 HZ |
733 | #ifdef CONFIG_PM_SLEEP |
734 | static int of_fsl_espi_suspend(struct device *dev) | |
735 | { | |
736 | struct spi_master *master = dev_get_drvdata(dev); | |
714bb654 HZ |
737 | int ret; |
738 | ||
714bb654 HZ |
739 | ret = spi_master_suspend(master); |
740 | if (ret) { | |
741 | dev_warn(dev, "cannot suspend master\n"); | |
742 | return ret; | |
743 | } | |
744 | ||
e9abb4db HK |
745 | ret = pm_runtime_force_suspend(dev); |
746 | if (ret < 0) | |
747 | return ret; | |
748 | ||
749 | return 0; | |
714bb654 HZ |
750 | } |
751 | ||
752 | static int of_fsl_espi_resume(struct device *dev) | |
753 | { | |
754 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); | |
755 | struct spi_master *master = dev_get_drvdata(dev); | |
756 | struct mpc8xxx_spi *mpc8xxx_spi; | |
757 | struct fsl_espi_reg *reg_base; | |
758 | u32 regval; | |
e9abb4db | 759 | int i, ret; |
714bb654 HZ |
760 | |
761 | mpc8xxx_spi = spi_master_get_devdata(master); | |
762 | reg_base = mpc8xxx_spi->reg_base; | |
763 | ||
764 | /* SPI controller initializations */ | |
765 | mpc8xxx_spi_write_reg(®_base->mode, 0); | |
766 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
767 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
768 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
769 | ||
770 | /* Init eSPI CS mode register */ | |
771 | for (i = 0; i < pdata->max_chipselect; i++) | |
772 | mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL); | |
773 | ||
774 | /* Enable SPI interface */ | |
775 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
776 | ||
777 | mpc8xxx_spi_write_reg(®_base->mode, regval); | |
778 | ||
e9abb4db HK |
779 | ret = pm_runtime_force_resume(dev); |
780 | if (ret < 0) | |
781 | return ret; | |
782 | ||
714bb654 HZ |
783 | return spi_master_resume(master); |
784 | } | |
785 | #endif /* CONFIG_PM_SLEEP */ | |
786 | ||
787 | static const struct dev_pm_ops espi_pm = { | |
e9abb4db HK |
788 | SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend, |
789 | fsl_espi_runtime_resume, NULL) | |
714bb654 HZ |
790 | SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) |
791 | }; | |
792 | ||
8b60d6c2 MH |
793 | static const struct of_device_id of_fsl_espi_match[] = { |
794 | { .compatible = "fsl,mpc8536-espi" }, | |
795 | {} | |
796 | }; | |
797 | MODULE_DEVICE_TABLE(of, of_fsl_espi_match); | |
798 | ||
18d306d1 | 799 | static struct platform_driver fsl_espi_driver = { |
8b60d6c2 MH |
800 | .driver = { |
801 | .name = "fsl_espi", | |
8b60d6c2 | 802 | .of_match_table = of_fsl_espi_match, |
714bb654 | 803 | .pm = &espi_pm, |
8b60d6c2 MH |
804 | }, |
805 | .probe = of_fsl_espi_probe, | |
e9abb4db | 806 | .remove = of_fsl_espi_remove, |
8b60d6c2 | 807 | }; |
940ab889 | 808 | module_platform_driver(fsl_espi_driver); |
8b60d6c2 MH |
809 | |
810 | MODULE_AUTHOR("Mingkai Hu"); | |
811 | MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); | |
812 | MODULE_LICENSE("GPL"); |