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Commit | Line | Data |
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8b60d6c2 MH |
1 | /* |
2 | * Freescale eSPI controller driver. | |
3 | * | |
4 | * Copyright 2010 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
8b60d6c2 | 11 | #include <linux/delay.h> |
a3108360 | 12 | #include <linux/err.h> |
8b60d6c2 | 13 | #include <linux/fsl_devices.h> |
a3108360 | 14 | #include <linux/interrupt.h> |
a3108360 | 15 | #include <linux/module.h> |
8b60d6c2 MH |
16 | #include <linux/mm.h> |
17 | #include <linux/of.h> | |
5af50730 RH |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_irq.h> | |
8b60d6c2 | 20 | #include <linux/of_platform.h> |
a3108360 XL |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spi/spi.h> | |
e9abb4db | 23 | #include <linux/pm_runtime.h> |
8b60d6c2 MH |
24 | #include <sysdev/fsl_soc.h> |
25 | ||
ca632f55 | 26 | #include "spi-fsl-lib.h" |
8b60d6c2 MH |
27 | |
28 | /* eSPI Controller registers */ | |
46afd38b HK |
29 | #define ESPI_SPMODE 0x00 /* eSPI mode register */ |
30 | #define ESPI_SPIE 0x04 /* eSPI event register */ | |
31 | #define ESPI_SPIM 0x08 /* eSPI mask register */ | |
32 | #define ESPI_SPCOM 0x0c /* eSPI command register */ | |
33 | #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/ | |
34 | #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/ | |
35 | #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */ | |
36 | ||
37 | #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4) | |
8b60d6c2 | 38 | |
8b60d6c2 | 39 | /* eSPI Controller mode register definitions */ |
81abc2ec HK |
40 | #define SPMODE_ENABLE BIT(31) |
41 | #define SPMODE_LOOP BIT(30) | |
8b60d6c2 MH |
42 | #define SPMODE_TXTHR(x) ((x) << 8) |
43 | #define SPMODE_RXTHR(x) ((x) << 0) | |
44 | ||
45 | /* eSPI Controller CS mode register definitions */ | |
81abc2ec HK |
46 | #define CSMODE_CI_INACTIVEHIGH BIT(31) |
47 | #define CSMODE_CP_BEGIN_EDGECLK BIT(30) | |
48 | #define CSMODE_REV BIT(29) | |
49 | #define CSMODE_DIV16 BIT(28) | |
8b60d6c2 | 50 | #define CSMODE_PM(x) ((x) << 24) |
81abc2ec | 51 | #define CSMODE_POL_1 BIT(20) |
8b60d6c2 MH |
52 | #define CSMODE_LEN(x) ((x) << 16) |
53 | #define CSMODE_BEF(x) ((x) << 12) | |
54 | #define CSMODE_AFT(x) ((x) << 8) | |
55 | #define CSMODE_CG(x) ((x) << 3) | |
56 | ||
57 | /* Default mode/csmode for eSPI controller */ | |
58 | #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3)) | |
59 | #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ | |
60 | | CSMODE_AFT(0) | CSMODE_CG(1)) | |
61 | ||
62 | /* SPIE register values */ | |
8b60d6c2 MH |
63 | #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) |
64 | #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) | |
81abc2ec HK |
65 | #define SPIE_TXE BIT(15) /* TX FIFO empty */ |
66 | #define SPIE_DON BIT(14) /* TX done */ | |
67 | #define SPIE_RXT BIT(13) /* RX FIFO threshold */ | |
68 | #define SPIE_RXF BIT(12) /* RX FIFO full */ | |
69 | #define SPIE_TXT BIT(11) /* TX FIFO threshold*/ | |
70 | #define SPIE_RNE BIT(9) /* RX FIFO not empty */ | |
71 | #define SPIE_TNF BIT(8) /* TX FIFO not full */ | |
72 | ||
73 | /* SPIM register values */ | |
74 | #define SPIM_TXE BIT(15) /* TX FIFO empty */ | |
75 | #define SPIM_DON BIT(14) /* TX done */ | |
76 | #define SPIM_RXT BIT(13) /* RX FIFO threshold */ | |
77 | #define SPIM_RXF BIT(12) /* RX FIFO full */ | |
78 | #define SPIM_TXT BIT(11) /* TX FIFO threshold*/ | |
79 | #define SPIM_RNE BIT(9) /* RX FIFO not empty */ | |
80 | #define SPIM_TNF BIT(8) /* TX FIFO not full */ | |
8b60d6c2 MH |
81 | |
82 | /* SPCOM register values */ | |
83 | #define SPCOM_CS(x) ((x) << 30) | |
81abc2ec HK |
84 | #define SPCOM_DO BIT(28) /* Dual output */ |
85 | #define SPCOM_TO BIT(27) /* TX only */ | |
86 | #define SPCOM_RXSKIP(x) ((x) << 16) | |
8b60d6c2 | 87 | #define SPCOM_TRANLEN(x) ((x) << 0) |
81abc2ec | 88 | |
5cfa1e4e | 89 | #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */ |
8b60d6c2 | 90 | |
e9abb4db HK |
91 | #define AUTOSUSPEND_TIMEOUT 2000 |
92 | ||
46afd38b HK |
93 | static inline u32 fsl_espi_read_reg(struct mpc8xxx_spi *mspi, int offset) |
94 | { | |
95 | return ioread32be(mspi->reg_base + offset); | |
96 | } | |
97 | ||
98 | static inline u8 fsl_espi_read_reg8(struct mpc8xxx_spi *mspi, int offset) | |
99 | { | |
100 | return ioread8(mspi->reg_base + offset); | |
101 | } | |
102 | ||
103 | static inline void fsl_espi_write_reg(struct mpc8xxx_spi *mspi, int offset, | |
104 | u32 val) | |
105 | { | |
106 | iowrite32be(val, mspi->reg_base + offset); | |
107 | } | |
108 | ||
109 | static inline void fsl_espi_write_reg8(struct mpc8xxx_spi *mspi, int offset, | |
110 | u8 val) | |
111 | { | |
112 | iowrite8(val, mspi->reg_base + offset); | |
113 | } | |
114 | ||
923ab15e HK |
115 | static void fsl_espi_memcpy_swab(void *to, const void *from, |
116 | struct spi_message *m, | |
117 | struct spi_transfer *t) | |
118 | { | |
119 | unsigned int len = t->len; | |
120 | ||
121 | if (!(m->spi->mode & SPI_LSB_FIRST) || t->bits_per_word <= 8) { | |
122 | memcpy(to, from, len); | |
123 | return; | |
124 | } | |
125 | ||
126 | /* In case of LSB-first and bits_per_word > 8 byte-swap all words */ | |
127 | while (len) | |
128 | if (len >= 4) { | |
129 | *(u32 *)to = swahb32p(from); | |
130 | to += 4; | |
131 | from += 4; | |
132 | len -= 4; | |
133 | } else { | |
134 | *(u16 *)to = swab16p(from); | |
135 | to += 2; | |
136 | from += 2; | |
137 | len -= 2; | |
138 | } | |
139 | } | |
140 | ||
cce7e3a2 HK |
141 | static void fsl_espi_copy_to_buf(struct spi_message *m, |
142 | struct mpc8xxx_spi *mspi) | |
7c159aa8 | 143 | { |
7c159aa8 HK |
144 | struct spi_transfer *t; |
145 | u8 *buf = mspi->local_buf; | |
146 | ||
147 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
cce7e3a2 | 148 | if (t->tx_buf) |
923ab15e | 149 | fsl_espi_memcpy_swab(buf, t->tx_buf, m, t); |
cce7e3a2 | 150 | else |
7c159aa8 | 151 | memset(buf, 0, t->len); |
7c159aa8 HK |
152 | buf += t->len; |
153 | } | |
cce7e3a2 HK |
154 | } |
155 | ||
156 | static void fsl_espi_copy_from_buf(struct spi_message *m, | |
157 | struct mpc8xxx_spi *mspi) | |
158 | { | |
159 | struct spi_transfer *t; | |
160 | u8 *buf = mspi->local_buf; | |
7c159aa8 | 161 | |
cce7e3a2 HK |
162 | list_for_each_entry(t, &m->transfers, transfer_list) { |
163 | if (t->rx_buf) | |
923ab15e | 164 | fsl_espi_memcpy_swab(t->rx_buf, buf, m, t); |
cce7e3a2 HK |
165 | buf += t->len; |
166 | } | |
7c159aa8 HK |
167 | } |
168 | ||
d3152cf1 HK |
169 | static int fsl_espi_check_message(struct spi_message *m) |
170 | { | |
171 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); | |
172 | struct spi_transfer *t, *first; | |
173 | ||
174 | if (m->frame_length > SPCOM_TRANLEN_MAX) { | |
175 | dev_err(mspi->dev, "message too long, size is %u bytes\n", | |
176 | m->frame_length); | |
177 | return -EMSGSIZE; | |
178 | } | |
179 | ||
180 | first = list_first_entry(&m->transfers, struct spi_transfer, | |
181 | transfer_list); | |
e4be7053 | 182 | |
d3152cf1 HK |
183 | list_for_each_entry(t, &m->transfers, transfer_list) { |
184 | if (first->bits_per_word != t->bits_per_word || | |
185 | first->speed_hz != t->speed_hz) { | |
186 | dev_err(mspi->dev, "bits_per_word/speed_hz should be the same for all transfers\n"); | |
187 | return -EINVAL; | |
188 | } | |
189 | } | |
190 | ||
e4be7053 HK |
191 | /* ESPI supports MSB-first transfers for word size 8 / 16 only */ |
192 | if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 && | |
193 | first->bits_per_word != 16) { | |
194 | dev_err(mspi->dev, | |
195 | "MSB-first transfer not supported for wordsize %u\n", | |
196 | first->bits_per_word); | |
197 | return -EINVAL; | |
198 | } | |
199 | ||
d3152cf1 HK |
200 | return 0; |
201 | } | |
202 | ||
8b60d6c2 MH |
203 | static void fsl_espi_change_mode(struct spi_device *spi) |
204 | { | |
205 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
206 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
8b60d6c2 MH |
207 | u32 tmp; |
208 | unsigned long flags; | |
209 | ||
210 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
211 | local_irq_save(flags); | |
212 | ||
213 | /* Turn off SPI unit prior changing mode */ | |
46afd38b HK |
214 | tmp = fsl_espi_read_reg(mspi, ESPI_SPMODE); |
215 | fsl_espi_write_reg(mspi, ESPI_SPMODE, tmp & ~SPMODE_ENABLE); | |
216 | fsl_espi_write_reg(mspi, ESPI_SPMODEx(spi->chip_select), | |
217 | cs->hw_mode); | |
218 | fsl_espi_write_reg(mspi, ESPI_SPMODE, tmp); | |
8b60d6c2 MH |
219 | |
220 | local_irq_restore(flags); | |
221 | } | |
222 | ||
ea616ee2 | 223 | static void fsl_espi_setup_transfer(struct spi_device *spi, |
8b60d6c2 MH |
224 | struct spi_transfer *t) |
225 | { | |
226 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
d198ebfb HK |
227 | int bits_per_word = t ? t->bits_per_word : spi->bits_per_word; |
228 | u32 hz = t ? t->speed_hz : spi->max_speed_hz; | |
8b60d6c2 | 229 | u8 pm; |
8b60d6c2 MH |
230 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
231 | ||
8b60d6c2 MH |
232 | /* mask out bits we are going to set */ |
233 | cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); | |
234 | ||
a755af52 | 235 | cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); |
8b60d6c2 MH |
236 | |
237 | if ((mpc8xxx_spi->spibrg / hz) > 64) { | |
238 | cs->hw_mode |= CSMODE_DIV16; | |
35faa55c | 239 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4); |
8b60d6c2 | 240 | |
87bf5ab8 | 241 | WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. " |
8b60d6c2 | 242 | "Will use %d Hz instead.\n", dev_name(&spi->dev), |
87bf5ab8 SAS |
243 | hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1))); |
244 | if (pm > 33) | |
245 | pm = 33; | |
8b60d6c2 | 246 | } else { |
35faa55c | 247 | pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4); |
8b60d6c2 MH |
248 | } |
249 | if (pm) | |
250 | pm--; | |
87bf5ab8 SAS |
251 | if (pm < 2) |
252 | pm = 2; | |
8b60d6c2 MH |
253 | |
254 | cs->hw_mode |= CSMODE_PM(pm); | |
255 | ||
256 | fsl_espi_change_mode(spi); | |
8b60d6c2 MH |
257 | } |
258 | ||
8b60d6c2 MH |
259 | static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) |
260 | { | |
261 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
8b60d6c2 MH |
262 | int ret; |
263 | ||
8b60d6c2 | 264 | mpc8xxx_spi->len = t->len; |
5bcc6a2f | 265 | mpc8xxx_spi->count = roundup(t->len, 4) / 4; |
8b60d6c2 MH |
266 | |
267 | mpc8xxx_spi->tx = t->tx_buf; | |
268 | mpc8xxx_spi->rx = t->rx_buf; | |
269 | ||
16735d02 | 270 | reinit_completion(&mpc8xxx_spi->done); |
8b60d6c2 MH |
271 | |
272 | /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ | |
46afd38b | 273 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, |
8b60d6c2 MH |
274 | (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1))); |
275 | ||
5bcc6a2f | 276 | /* enable rx ints */ |
81abc2ec | 277 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, SPIM_RNE); |
5bcc6a2f HK |
278 | |
279 | /* transmit word */ | |
923ab15e HK |
280 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPITF, *(u32 *)mpc8xxx_spi->tx); |
281 | mpc8xxx_spi->tx += 4; | |
8b60d6c2 | 282 | |
aa70e567 NH |
283 | /* Won't hang up forever, SPI bus sometimes got lost interrupts... */ |
284 | ret = wait_for_completion_timeout(&mpc8xxx_spi->done, 2 * HZ); | |
285 | if (ret == 0) | |
286 | dev_err(mpc8xxx_spi->dev, | |
287 | "Transaction hanging up (left %d bytes)\n", | |
288 | mpc8xxx_spi->count); | |
8b60d6c2 MH |
289 | |
290 | /* disable rx ints */ | |
46afd38b | 291 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); |
8b60d6c2 | 292 | |
84ccfc37 | 293 | return mpc8xxx_spi->count > 0 ? -EMSGSIZE : 0; |
8b60d6c2 MH |
294 | } |
295 | ||
38d003f1 | 296 | static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans) |
8b60d6c2 | 297 | { |
38d003f1 | 298 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
8b60d6c2 | 299 | struct spi_device *spi = m->spi; |
38d003f1 | 300 | int ret; |
8b60d6c2 | 301 | |
38d003f1 | 302 | fsl_espi_copy_to_buf(m, mspi); |
faceef39 | 303 | fsl_espi_setup_transfer(spi, trans); |
8b60d6c2 | 304 | |
06af115d | 305 | ret = fsl_espi_bufs(spi, trans); |
8b60d6c2 | 306 | |
faceef39 HK |
307 | if (trans->delay_usecs) |
308 | udelay(trans->delay_usecs); | |
8b60d6c2 | 309 | |
8b60d6c2 | 310 | fsl_espi_setup_transfer(spi, NULL); |
e33a3ade | 311 | |
cce7e3a2 HK |
312 | if (!ret) |
313 | fsl_espi_copy_from_buf(m, mspi); | |
e33a3ade HK |
314 | |
315 | return ret; | |
8b60d6c2 MH |
316 | } |
317 | ||
c592becb HK |
318 | static int fsl_espi_do_one_msg(struct spi_master *master, |
319 | struct spi_message *m) | |
8b60d6c2 | 320 | { |
96361faf | 321 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(m->spi->master); |
06af115d | 322 | unsigned int delay_usecs = 0; |
faceef39 | 323 | struct spi_transfer *t, trans = {}; |
e33a3ade | 324 | int ret; |
8b60d6c2 | 325 | |
d3152cf1 HK |
326 | ret = fsl_espi_check_message(m); |
327 | if (ret) | |
328 | goto out; | |
329 | ||
8b60d6c2 | 330 | list_for_each_entry(t, &m->transfers, transfer_list) { |
96361faf HK |
331 | if (t->delay_usecs > delay_usecs) |
332 | delay_usecs = t->delay_usecs; | |
8b60d6c2 MH |
333 | } |
334 | ||
96361faf HK |
335 | t = list_first_entry(&m->transfers, struct spi_transfer, |
336 | transfer_list); | |
337 | ||
06af115d | 338 | trans.len = m->frame_length; |
96361faf HK |
339 | trans.speed_hz = t->speed_hz; |
340 | trans.bits_per_word = t->bits_per_word; | |
341 | trans.delay_usecs = delay_usecs; | |
342 | trans.tx_buf = mspi->local_buf; | |
343 | trans.rx_buf = mspi->local_buf; | |
8b60d6c2 | 344 | |
06af115d HK |
345 | if (trans.len) |
346 | ret = fsl_espi_trans(m, &trans); | |
8b60d6c2 | 347 | |
faceef39 | 348 | m->actual_length = ret ? 0 : trans.len; |
d3152cf1 | 349 | out: |
0319d499 HK |
350 | if (m->status == -EINPROGRESS) |
351 | m->status = ret; | |
352 | ||
c592becb | 353 | spi_finalize_current_message(master); |
0319d499 HK |
354 | |
355 | return ret; | |
8b60d6c2 MH |
356 | } |
357 | ||
358 | static int fsl_espi_setup(struct spi_device *spi) | |
359 | { | |
360 | struct mpc8xxx_spi *mpc8xxx_spi; | |
8b60d6c2 | 361 | u32 loop_mode; |
d9f26748 | 362 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
8b60d6c2 MH |
363 | |
364 | if (!spi->max_speed_hz) | |
365 | return -EINVAL; | |
366 | ||
367 | if (!cs) { | |
d9f26748 | 368 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
8b60d6c2 MH |
369 | if (!cs) |
370 | return -ENOMEM; | |
d9f26748 | 371 | spi_set_ctldata(spi, cs); |
8b60d6c2 MH |
372 | } |
373 | ||
374 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
8b60d6c2 | 375 | |
e9abb4db HK |
376 | pm_runtime_get_sync(mpc8xxx_spi->dev); |
377 | ||
46afd38b HK |
378 | cs->hw_mode = fsl_espi_read_reg(mpc8xxx_spi, |
379 | ESPI_SPMODEx(spi->chip_select)); | |
8b60d6c2 MH |
380 | /* mask out bits we are going to set */ |
381 | cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH | |
382 | | CSMODE_REV); | |
383 | ||
384 | if (spi->mode & SPI_CPHA) | |
385 | cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; | |
386 | if (spi->mode & SPI_CPOL) | |
387 | cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; | |
388 | if (!(spi->mode & SPI_LSB_FIRST)) | |
389 | cs->hw_mode |= CSMODE_REV; | |
390 | ||
391 | /* Handle the loop mode */ | |
46afd38b | 392 | loop_mode = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
8b60d6c2 MH |
393 | loop_mode &= ~SPMODE_LOOP; |
394 | if (spi->mode & SPI_LOOP) | |
395 | loop_mode |= SPMODE_LOOP; | |
46afd38b | 396 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, loop_mode); |
8b60d6c2 | 397 | |
ea616ee2 | 398 | fsl_espi_setup_transfer(spi, NULL); |
e9abb4db HK |
399 | |
400 | pm_runtime_mark_last_busy(mpc8xxx_spi->dev); | |
401 | pm_runtime_put_autosuspend(mpc8xxx_spi->dev); | |
402 | ||
8b60d6c2 MH |
403 | return 0; |
404 | } | |
405 | ||
d9f26748 AL |
406 | static void fsl_espi_cleanup(struct spi_device *spi) |
407 | { | |
408 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); | |
409 | ||
410 | kfree(cs); | |
411 | spi_set_ctldata(spi, NULL); | |
412 | } | |
413 | ||
10ed1e6d | 414 | static void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
8b60d6c2 | 415 | { |
8b60d6c2 | 416 | /* We need handle RX first */ |
81abc2ec | 417 | if (events & SPIE_RNE) { |
e6289d63 MH |
418 | u32 rx_data, tmp; |
419 | u8 rx_data_8; | |
6319a680 | 420 | int rx_nr_bytes = 4; |
a12ddd60 | 421 | int ret; |
8b60d6c2 MH |
422 | |
423 | /* Spin until RX is done */ | |
a12ddd60 NH |
424 | if (SPIE_RXCNT(events) < min(4, mspi->len)) { |
425 | ret = spin_event_timeout( | |
426 | !(SPIE_RXCNT(events = | |
46afd38b | 427 | fsl_espi_read_reg(mspi, ESPI_SPIE)) < |
a12ddd60 NH |
428 | min(4, mspi->len)), |
429 | 10000, 0); /* 10 msec */ | |
430 | if (!ret) | |
431 | dev_err(mspi->dev, | |
432 | "tired waiting for SPIE_RXCNT\n"); | |
8b60d6c2 | 433 | } |
8b60d6c2 | 434 | |
e6289d63 | 435 | if (mspi->len >= 4) { |
46afd38b | 436 | rx_data = fsl_espi_read_reg(mspi, ESPI_SPIRF); |
6319a680 NH |
437 | } else if (mspi->len <= 0) { |
438 | dev_err(mspi->dev, | |
81abc2ec | 439 | "unexpected RX(SPIE_RNE) interrupt occurred,\n" |
6319a680 NH |
440 | "(local rxlen %d bytes, reg rxlen %d bytes)\n", |
441 | min(4, mspi->len), SPIE_RXCNT(events)); | |
442 | rx_nr_bytes = 0; | |
e6289d63 | 443 | } else { |
6319a680 | 444 | rx_nr_bytes = mspi->len; |
e6289d63 MH |
445 | tmp = mspi->len; |
446 | rx_data = 0; | |
447 | while (tmp--) { | |
46afd38b HK |
448 | rx_data_8 = fsl_espi_read_reg8(mspi, |
449 | ESPI_SPIRF); | |
e6289d63 MH |
450 | rx_data |= (rx_data_8 << (tmp * 8)); |
451 | } | |
452 | ||
453 | rx_data <<= (4 - mspi->len) * 8; | |
454 | } | |
455 | ||
6319a680 | 456 | mspi->len -= rx_nr_bytes; |
8b60d6c2 | 457 | |
f9ce28f9 | 458 | if (rx_nr_bytes && mspi->rx) { |
e3cd6cf4 | 459 | *(u32 *)mspi->rx = rx_data; |
923ab15e HK |
460 | mspi->rx += 4; |
461 | } | |
8b60d6c2 MH |
462 | } |
463 | ||
81abc2ec | 464 | if (!(events & SPIE_TNF)) { |
8b60d6c2 MH |
465 | int ret; |
466 | ||
467 | /* spin until TX is done */ | |
46afd38b | 468 | ret = spin_event_timeout(((events = fsl_espi_read_reg( |
81abc2ec | 469 | mspi, ESPI_SPIE)) & SPIE_TNF), 1000, 0); |
8b60d6c2 | 470 | if (!ret) { |
81abc2ec | 471 | dev_err(mspi->dev, "tired waiting for SPIE_TNF\n"); |
7a0a1759 | 472 | complete(&mspi->done); |
8b60d6c2 MH |
473 | return; |
474 | } | |
475 | } | |
476 | ||
8b60d6c2 MH |
477 | mspi->count -= 1; |
478 | if (mspi->count) { | |
923ab15e HK |
479 | fsl_espi_write_reg(mspi, ESPI_SPITF, *(u32 *)mspi->tx); |
480 | mspi->tx += 4; | |
8b60d6c2 MH |
481 | } else { |
482 | complete(&mspi->done); | |
483 | } | |
484 | } | |
485 | ||
486 | static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) | |
487 | { | |
488 | struct mpc8xxx_spi *mspi = context_data; | |
8b60d6c2 MH |
489 | u32 events; |
490 | ||
491 | /* Get interrupt events(tx/rx) */ | |
46afd38b | 492 | events = fsl_espi_read_reg(mspi, ESPI_SPIE); |
35f5d71e HK |
493 | if (!events) |
494 | return IRQ_NONE; | |
8b60d6c2 MH |
495 | |
496 | dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events); | |
497 | ||
498 | fsl_espi_cpu_irq(mspi, events); | |
499 | ||
35f5d71e | 500 | /* Clear the events */ |
46afd38b | 501 | fsl_espi_write_reg(mspi, ESPI_SPIE, events); |
35f5d71e HK |
502 | |
503 | return IRQ_HANDLED; | |
8b60d6c2 MH |
504 | } |
505 | ||
e9abb4db HK |
506 | #ifdef CONFIG_PM |
507 | static int fsl_espi_runtime_suspend(struct device *dev) | |
75506d0e | 508 | { |
e9abb4db HK |
509 | struct spi_master *master = dev_get_drvdata(dev); |
510 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
75506d0e HK |
511 | u32 regval; |
512 | ||
46afd38b | 513 | regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
75506d0e | 514 | regval &= ~SPMODE_ENABLE; |
46afd38b | 515 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
75506d0e HK |
516 | |
517 | return 0; | |
518 | } | |
519 | ||
e9abb4db | 520 | static int fsl_espi_runtime_resume(struct device *dev) |
75506d0e | 521 | { |
e9abb4db HK |
522 | struct spi_master *master = dev_get_drvdata(dev); |
523 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
75506d0e HK |
524 | u32 regval; |
525 | ||
46afd38b | 526 | regval = fsl_espi_read_reg(mpc8xxx_spi, ESPI_SPMODE); |
75506d0e | 527 | regval |= SPMODE_ENABLE; |
46afd38b | 528 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
75506d0e HK |
529 | |
530 | return 0; | |
531 | } | |
e9abb4db | 532 | #endif |
75506d0e | 533 | |
02a595d5 | 534 | static size_t fsl_espi_max_message_size(struct spi_device *spi) |
b541eef1 MS |
535 | { |
536 | return SPCOM_TRANLEN_MAX; | |
537 | } | |
538 | ||
604042af HK |
539 | static int fsl_espi_probe(struct device *dev, struct resource *mem, |
540 | unsigned int irq) | |
8b60d6c2 | 541 | { |
8074cf06 | 542 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
8b60d6c2 MH |
543 | struct spi_master *master; |
544 | struct mpc8xxx_spi *mpc8xxx_spi; | |
d0fb47a5 | 545 | struct device_node *nc; |
b497eb02 HK |
546 | u32 regval, csmode, cs, prop; |
547 | int ret; | |
8b60d6c2 MH |
548 | |
549 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); | |
604042af HK |
550 | if (!master) |
551 | return -ENOMEM; | |
8b60d6c2 MH |
552 | |
553 | dev_set_drvdata(dev, master); | |
554 | ||
c592becb | 555 | mpc8xxx_spi_probe(dev, mem, irq); |
8b60d6c2 | 556 | |
24778be2 | 557 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
8b60d6c2 | 558 | master->setup = fsl_espi_setup; |
d9f26748 | 559 | master->cleanup = fsl_espi_cleanup; |
c592becb | 560 | master->transfer_one_message = fsl_espi_do_one_msg; |
e9abb4db | 561 | master->auto_runtime_pm = true; |
02a595d5 | 562 | master->max_message_size = fsl_espi_max_message_size; |
8b60d6c2 MH |
563 | |
564 | mpc8xxx_spi = spi_master_get_devdata(master); | |
8b60d6c2 | 565 | |
1423877b HK |
566 | mpc8xxx_spi->local_buf = |
567 | devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL); | |
568 | if (!mpc8xxx_spi->local_buf) { | |
569 | ret = -ENOMEM; | |
570 | goto err_probe; | |
571 | } | |
572 | ||
4178b6b1 | 573 | mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); |
37c5db79 AL |
574 | if (IS_ERR(mpc8xxx_spi->reg_base)) { |
575 | ret = PTR_ERR(mpc8xxx_spi->reg_base); | |
8b60d6c2 MH |
576 | goto err_probe; |
577 | } | |
578 | ||
8b60d6c2 | 579 | /* Register for SPI Interrupt */ |
4178b6b1 | 580 | ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq, |
8b60d6c2 MH |
581 | 0, "fsl_espi", mpc8xxx_spi); |
582 | if (ret) | |
4178b6b1 | 583 | goto err_probe; |
8b60d6c2 MH |
584 | |
585 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { | |
e9e128a6 HK |
586 | dev_err(dev, "SPI_QE_CPU_MODE is not supported on ESPI!\n"); |
587 | ret = -EINVAL; | |
588 | goto err_probe; | |
8b60d6c2 MH |
589 | } |
590 | ||
591 | /* SPI controller initializations */ | |
46afd38b HK |
592 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0); |
593 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); | |
594 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0); | |
595 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff); | |
8b60d6c2 MH |
596 | |
597 | /* Init eSPI CS mode register */ | |
d0fb47a5 JW |
598 | for_each_available_child_of_node(master->dev.of_node, nc) { |
599 | /* get chip select */ | |
b497eb02 HK |
600 | ret = of_property_read_u32(nc, "reg", &cs); |
601 | if (ret || cs >= pdata->max_chipselect) | |
d0fb47a5 JW |
602 | continue; |
603 | ||
604 | csmode = CSMODE_INIT_VAL; | |
b497eb02 | 605 | |
d0fb47a5 | 606 | /* check if CSBEF is set in device tree */ |
b497eb02 HK |
607 | ret = of_property_read_u32(nc, "fsl,csbef", &prop); |
608 | if (!ret) { | |
d0fb47a5 | 609 | csmode &= ~(CSMODE_BEF(0xf)); |
b497eb02 | 610 | csmode |= CSMODE_BEF(prop); |
d0fb47a5 | 611 | } |
b497eb02 | 612 | |
d0fb47a5 | 613 | /* check if CSAFT is set in device tree */ |
b497eb02 HK |
614 | ret = of_property_read_u32(nc, "fsl,csaft", &prop); |
615 | if (!ret) { | |
d0fb47a5 | 616 | csmode &= ~(CSMODE_AFT(0xf)); |
b497eb02 | 617 | csmode |= CSMODE_AFT(prop); |
d0fb47a5 | 618 | } |
d0fb47a5 | 619 | |
b497eb02 HK |
620 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(cs), csmode); |
621 | ||
622 | dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode); | |
d0fb47a5 | 623 | } |
8b60d6c2 MH |
624 | |
625 | /* Enable SPI interface */ | |
626 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
627 | ||
46afd38b | 628 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
8b60d6c2 | 629 | |
e9abb4db HK |
630 | pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT); |
631 | pm_runtime_use_autosuspend(dev); | |
632 | pm_runtime_set_active(dev); | |
633 | pm_runtime_enable(dev); | |
634 | pm_runtime_get_sync(dev); | |
635 | ||
4178b6b1 | 636 | ret = devm_spi_register_master(dev, master); |
8b60d6c2 | 637 | if (ret < 0) |
e9abb4db | 638 | goto err_pm; |
8b60d6c2 | 639 | |
46afd38b HK |
640 | dev_info(dev, "at 0x%p (irq = %d)\n", mpc8xxx_spi->reg_base, |
641 | mpc8xxx_spi->irq); | |
8b60d6c2 | 642 | |
e9abb4db HK |
643 | pm_runtime_mark_last_busy(dev); |
644 | pm_runtime_put_autosuspend(dev); | |
645 | ||
604042af | 646 | return 0; |
8b60d6c2 | 647 | |
e9abb4db HK |
648 | err_pm: |
649 | pm_runtime_put_noidle(dev); | |
650 | pm_runtime_disable(dev); | |
651 | pm_runtime_set_suspended(dev); | |
8b60d6c2 MH |
652 | err_probe: |
653 | spi_master_put(master); | |
604042af | 654 | return ret; |
8b60d6c2 MH |
655 | } |
656 | ||
657 | static int of_fsl_espi_get_chipselects(struct device *dev) | |
658 | { | |
659 | struct device_node *np = dev->of_node; | |
8074cf06 | 660 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
b497eb02 HK |
661 | u32 num_cs; |
662 | int ret; | |
8b60d6c2 | 663 | |
b497eb02 HK |
664 | ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs); |
665 | if (ret) { | |
8b60d6c2 MH |
666 | dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); |
667 | return -EINVAL; | |
668 | } | |
669 | ||
b497eb02 | 670 | pdata->max_chipselect = num_cs; |
8b60d6c2 MH |
671 | pdata->cs_control = NULL; |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
fd4a319b | 676 | static int of_fsl_espi_probe(struct platform_device *ofdev) |
8b60d6c2 MH |
677 | { |
678 | struct device *dev = &ofdev->dev; | |
679 | struct device_node *np = ofdev->dev.of_node; | |
8b60d6c2 | 680 | struct resource mem; |
f7578496 | 681 | unsigned int irq; |
acf69219 | 682 | int ret; |
8b60d6c2 | 683 | |
18d306d1 | 684 | ret = of_mpc8xxx_spi_probe(ofdev); |
8b60d6c2 MH |
685 | if (ret) |
686 | return ret; | |
687 | ||
688 | ret = of_fsl_espi_get_chipselects(dev); | |
689 | if (ret) | |
acf69219 | 690 | return ret; |
8b60d6c2 MH |
691 | |
692 | ret = of_address_to_resource(np, 0, &mem); | |
693 | if (ret) | |
acf69219 | 694 | return ret; |
8b60d6c2 | 695 | |
f7578496 | 696 | irq = irq_of_parse_and_map(np, 0); |
acf69219 HK |
697 | if (!irq) |
698 | return -EINVAL; | |
8b60d6c2 | 699 | |
604042af | 700 | return fsl_espi_probe(dev, &mem, irq); |
8b60d6c2 MH |
701 | } |
702 | ||
e9abb4db HK |
703 | static int of_fsl_espi_remove(struct platform_device *dev) |
704 | { | |
705 | pm_runtime_disable(&dev->dev); | |
706 | ||
707 | return 0; | |
708 | } | |
709 | ||
714bb654 HZ |
710 | #ifdef CONFIG_PM_SLEEP |
711 | static int of_fsl_espi_suspend(struct device *dev) | |
712 | { | |
713 | struct spi_master *master = dev_get_drvdata(dev); | |
714bb654 HZ |
714 | int ret; |
715 | ||
714bb654 HZ |
716 | ret = spi_master_suspend(master); |
717 | if (ret) { | |
718 | dev_warn(dev, "cannot suspend master\n"); | |
719 | return ret; | |
720 | } | |
721 | ||
e9abb4db HK |
722 | ret = pm_runtime_force_suspend(dev); |
723 | if (ret < 0) | |
724 | return ret; | |
725 | ||
726 | return 0; | |
714bb654 HZ |
727 | } |
728 | ||
729 | static int of_fsl_espi_resume(struct device *dev) | |
730 | { | |
731 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); | |
732 | struct spi_master *master = dev_get_drvdata(dev); | |
733 | struct mpc8xxx_spi *mpc8xxx_spi; | |
714bb654 | 734 | u32 regval; |
e9abb4db | 735 | int i, ret; |
714bb654 HZ |
736 | |
737 | mpc8xxx_spi = spi_master_get_devdata(master); | |
714bb654 HZ |
738 | |
739 | /* SPI controller initializations */ | |
46afd38b HK |
740 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, 0); |
741 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIM, 0); | |
742 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPCOM, 0); | |
743 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPIE, 0xffffffff); | |
714bb654 HZ |
744 | |
745 | /* Init eSPI CS mode register */ | |
746 | for (i = 0; i < pdata->max_chipselect; i++) | |
46afd38b HK |
747 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODEx(i), |
748 | CSMODE_INIT_VAL); | |
714bb654 HZ |
749 | |
750 | /* Enable SPI interface */ | |
751 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
752 | ||
46afd38b | 753 | fsl_espi_write_reg(mpc8xxx_spi, ESPI_SPMODE, regval); |
714bb654 | 754 | |
e9abb4db HK |
755 | ret = pm_runtime_force_resume(dev); |
756 | if (ret < 0) | |
757 | return ret; | |
758 | ||
714bb654 HZ |
759 | return spi_master_resume(master); |
760 | } | |
761 | #endif /* CONFIG_PM_SLEEP */ | |
762 | ||
763 | static const struct dev_pm_ops espi_pm = { | |
e9abb4db HK |
764 | SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend, |
765 | fsl_espi_runtime_resume, NULL) | |
714bb654 HZ |
766 | SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) |
767 | }; | |
768 | ||
8b60d6c2 MH |
769 | static const struct of_device_id of_fsl_espi_match[] = { |
770 | { .compatible = "fsl,mpc8536-espi" }, | |
771 | {} | |
772 | }; | |
773 | MODULE_DEVICE_TABLE(of, of_fsl_espi_match); | |
774 | ||
18d306d1 | 775 | static struct platform_driver fsl_espi_driver = { |
8b60d6c2 MH |
776 | .driver = { |
777 | .name = "fsl_espi", | |
8b60d6c2 | 778 | .of_match_table = of_fsl_espi_match, |
714bb654 | 779 | .pm = &espi_pm, |
8b60d6c2 MH |
780 | }, |
781 | .probe = of_fsl_espi_probe, | |
e9abb4db | 782 | .remove = of_fsl_espi_remove, |
8b60d6c2 | 783 | }; |
940ab889 | 784 | module_platform_driver(fsl_espi_driver); |
8b60d6c2 MH |
785 | |
786 | MODULE_AUTHOR("Mingkai Hu"); | |
787 | MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); | |
788 | MODULE_LICENSE("GPL"); |