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Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
ccf06998 | 2 | /* |
b36ece83 | 3 | * Freescale SPI controller driver. |
ccf06998 KG |
4 | * |
5 | * Maintainer: Kumar Gala | |
6 | * | |
7 | * Copyright (C) 2006 Polycom, Inc. | |
b36ece83 | 8 | * Copyright 2010 Freescale Semiconductor, Inc. |
ccf06998 | 9 | * |
4c1fba44 AV |
10 | * CPM SPI and QE buffer descriptors mode support: |
11 | * Copyright (c) 2009 MontaVista Software, Inc. | |
12 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
13 | * | |
447b0c7b AL |
14 | * GRLIB support: |
15 | * Copyright (c) 2012 Aeroflex Gaisler AB. | |
16 | * Author: Andreas Larsson <andreas@gaisler.com> | |
ccf06998 | 17 | */ |
ccf06998 | 18 | #include <linux/delay.h> |
4c1fba44 | 19 | #include <linux/dma-mapping.h> |
a3108360 XL |
20 | #include <linux/fsl_devices.h> |
21 | #include <linux/gpio.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/kernel.h> | |
4c1fba44 | 25 | #include <linux/mm.h> |
a3108360 | 26 | #include <linux/module.h> |
4c1fba44 | 27 | #include <linux/mutex.h> |
35b4b3c0 | 28 | #include <linux/of.h> |
e8beacbb AL |
29 | #include <linux/of_address.h> |
30 | #include <linux/of_irq.h> | |
35b4b3c0 | 31 | #include <linux/of_gpio.h> |
a3108360 XL |
32 | #include <linux/of_platform.h> |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/spi/spi.h> | |
35 | #include <linux/spi/spi_bitbang.h> | |
36 | #include <linux/types.h> | |
ccf06998 | 37 | |
69b921ac RV |
38 | #ifdef CONFIG_FSL_SOC |
39 | #include <sysdev/fsl_soc.h> | |
40 | #endif | |
41 | ||
42 | /* Specific to the MPC8306/MPC8309 */ | |
43 | #define IMMR_SPI_CS_OFFSET 0x14c | |
44 | #define SPI_BOOT_SEL_BIT 0x80000000 | |
45 | ||
ca632f55 | 46 | #include "spi-fsl-lib.h" |
e8beacbb AL |
47 | #include "spi-fsl-cpm.h" |
48 | #include "spi-fsl-spi.h" | |
ccf06998 | 49 | |
c3f3e771 | 50 | #define TYPE_FSL 0 |
447b0c7b | 51 | #define TYPE_GRLIB 1 |
c3f3e771 AL |
52 | |
53 | struct fsl_spi_match_data { | |
54 | int type; | |
55 | }; | |
56 | ||
57 | static struct fsl_spi_match_data of_fsl_spi_fsl_config = { | |
58 | .type = TYPE_FSL, | |
59 | }; | |
60 | ||
447b0c7b AL |
61 | static struct fsl_spi_match_data of_fsl_spi_grlib_config = { |
62 | .type = TYPE_GRLIB, | |
63 | }; | |
64 | ||
3aea901d | 65 | static const struct of_device_id of_fsl_spi_match[] = { |
c3f3e771 AL |
66 | { |
67 | .compatible = "fsl,spi", | |
68 | .data = &of_fsl_spi_fsl_config, | |
69 | }, | |
447b0c7b AL |
70 | { |
71 | .compatible = "aeroflexgaisler,spictrl", | |
72 | .data = &of_fsl_spi_grlib_config, | |
73 | }, | |
c3f3e771 AL |
74 | {} |
75 | }; | |
76 | MODULE_DEVICE_TABLE(of, of_fsl_spi_match); | |
77 | ||
78 | static int fsl_spi_get_type(struct device *dev) | |
79 | { | |
80 | const struct of_device_id *match; | |
81 | ||
82 | if (dev->of_node) { | |
83 | match = of_match_node(of_fsl_spi_match, dev->of_node); | |
84 | if (match && match->data) | |
85 | return ((struct fsl_spi_match_data *)match->data)->type; | |
86 | } | |
87 | return TYPE_FSL; | |
88 | } | |
89 | ||
b36ece83 | 90 | static void fsl_spi_change_mode(struct spi_device *spi) |
a35c1710 AV |
91 | { |
92 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
93 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
b36ece83 MH |
94 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
95 | __be32 __iomem *mode = ®_base->mode; | |
a35c1710 AV |
96 | unsigned long flags; |
97 | ||
98 | if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) | |
99 | return; | |
100 | ||
101 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
102 | local_irq_save(flags); | |
103 | ||
104 | /* Turn off SPI unit prior changing mode */ | |
105 | mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); | |
a35c1710 | 106 | |
4c1fba44 AV |
107 | /* When in CPM mode, we need to reinit tx and rx. */ |
108 | if (mspi->flags & SPI_CPM_MODE) { | |
e8beacbb | 109 | fsl_spi_cpm_reinit_txrx(mspi); |
4c1fba44 | 110 | } |
f9218c2a | 111 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); |
a35c1710 AV |
112 | local_irq_restore(flags); |
113 | } | |
114 | ||
b36ece83 | 115 | static void fsl_spi_chipselect(struct spi_device *spi, int value) |
ccf06998 | 116 | { |
575c5807 | 117 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
5039a869 | 118 | struct fsl_spi_platform_data *pdata; |
364fdbc0 | 119 | bool pol = spi->mode & SPI_CS_HIGH; |
575c5807 | 120 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 | 121 | |
5039a869 KE |
122 | pdata = spi->dev.parent->parent->platform_data; |
123 | ||
ccf06998 | 124 | if (value == BITBANG_CS_INACTIVE) { |
364fdbc0 AV |
125 | if (pdata->cs_control) |
126 | pdata->cs_control(spi, !pol); | |
ccf06998 KG |
127 | } |
128 | ||
129 | if (value == BITBANG_CS_ACTIVE) { | |
575c5807 AV |
130 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
131 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
132 | mpc8xxx_spi->get_rx = cs->get_rx; | |
133 | mpc8xxx_spi->get_tx = cs->get_tx; | |
c9bfcb31 | 134 | |
b36ece83 | 135 | fsl_spi_change_mode(spi); |
a35c1710 | 136 | |
364fdbc0 AV |
137 | if (pdata->cs_control) |
138 | pdata->cs_control(spi, pol); | |
ccf06998 KG |
139 | } |
140 | } | |
141 | ||
b48c4e3c AL |
142 | static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, |
143 | int bits_per_word, int msb_first) | |
144 | { | |
145 | *rx_shift = 0; | |
146 | *tx_shift = 0; | |
147 | if (msb_first) { | |
148 | if (bits_per_word <= 8) { | |
149 | *rx_shift = 16; | |
150 | *tx_shift = 24; | |
151 | } else if (bits_per_word <= 16) { | |
152 | *rx_shift = 16; | |
153 | *tx_shift = 16; | |
154 | } | |
155 | } else { | |
156 | if (bits_per_word <= 8) | |
157 | *rx_shift = 8; | |
158 | } | |
159 | } | |
160 | ||
447b0c7b AL |
161 | static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift, |
162 | int bits_per_word, int msb_first) | |
163 | { | |
164 | *rx_shift = 0; | |
165 | *tx_shift = 0; | |
166 | if (bits_per_word <= 16) { | |
167 | if (msb_first) { | |
168 | *rx_shift = 16; /* LSB in bit 16 */ | |
169 | *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ | |
170 | } else { | |
171 | *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ | |
172 | } | |
173 | } | |
174 | } | |
175 | ||
b36ece83 MH |
176 | static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, |
177 | struct spi_device *spi, | |
178 | struct mpc8xxx_spi *mpc8xxx_spi, | |
179 | int bits_per_word) | |
ccf06998 | 180 | { |
c9bfcb31 JT |
181 | cs->rx_shift = 0; |
182 | cs->tx_shift = 0; | |
ccf06998 | 183 | if (bits_per_word <= 8) { |
575c5807 AV |
184 | cs->get_rx = mpc8xxx_spi_rx_buf_u8; |
185 | cs->get_tx = mpc8xxx_spi_tx_buf_u8; | |
ccf06998 | 186 | } else if (bits_per_word <= 16) { |
575c5807 AV |
187 | cs->get_rx = mpc8xxx_spi_rx_buf_u16; |
188 | cs->get_tx = mpc8xxx_spi_tx_buf_u16; | |
ccf06998 | 189 | } else if (bits_per_word <= 32) { |
575c5807 AV |
190 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; |
191 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
ccf06998 KG |
192 | } else |
193 | return -EINVAL; | |
194 | ||
b48c4e3c AL |
195 | if (mpc8xxx_spi->set_shifts) |
196 | mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, | |
197 | bits_per_word, | |
198 | !(spi->mode & SPI_LSB_FIRST)); | |
199 | ||
575c5807 AV |
200 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
201 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
202 | mpc8xxx_spi->get_rx = cs->get_rx; | |
203 | mpc8xxx_spi->get_tx = cs->get_tx; | |
ccf06998 | 204 | |
0398fb70 JT |
205 | return bits_per_word; |
206 | } | |
207 | ||
b36ece83 MH |
208 | static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, |
209 | struct spi_device *spi, | |
210 | int bits_per_word) | |
0398fb70 JT |
211 | { |
212 | /* QE uses Little Endian for words > 8 | |
213 | * so transform all words > 8 into 8 bits | |
214 | * Unfortnatly that doesn't work for LSB so | |
215 | * reject these for now */ | |
216 | /* Note: 32 bits word, LSB works iff | |
217 | * tfcr/rfcr is set to CPMFCR_GBL */ | |
218 | if (spi->mode & SPI_LSB_FIRST && | |
219 | bits_per_word > 8) | |
220 | return -EINVAL; | |
221 | if (bits_per_word > 8) | |
222 | return 8; /* pretend its 8 bits */ | |
223 | return bits_per_word; | |
224 | } | |
225 | ||
b36ece83 MH |
226 | static int fsl_spi_setup_transfer(struct spi_device *spi, |
227 | struct spi_transfer *t) | |
0398fb70 JT |
228 | { |
229 | struct mpc8xxx_spi *mpc8xxx_spi; | |
b36ece83 | 230 | int bits_per_word = 0; |
0398fb70 | 231 | u8 pm; |
b36ece83 | 232 | u32 hz = 0; |
0398fb70 JT |
233 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
234 | ||
235 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
236 | ||
237 | if (t) { | |
238 | bits_per_word = t->bits_per_word; | |
239 | hz = t->speed_hz; | |
0398fb70 JT |
240 | } |
241 | ||
242 | /* spi_transfer level calls that work per-word */ | |
243 | if (!bits_per_word) | |
244 | bits_per_word = spi->bits_per_word; | |
245 | ||
0398fb70 JT |
246 | if (!hz) |
247 | hz = spi->max_speed_hz; | |
248 | ||
249 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) | |
250 | bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, | |
251 | mpc8xxx_spi, | |
252 | bits_per_word); | |
253 | else if (mpc8xxx_spi->flags & SPI_QE) | |
254 | bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, | |
255 | bits_per_word); | |
256 | ||
257 | if (bits_per_word < 0) | |
258 | return bits_per_word; | |
259 | ||
ccf06998 KG |
260 | if (bits_per_word == 32) |
261 | bits_per_word = 0; | |
262 | else | |
263 | bits_per_word = bits_per_word - 1; | |
264 | ||
32421daa | 265 | /* mask out bits we are going to set */ |
c9bfcb31 JT |
266 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
267 | | SPMODE_PM(0xF)); | |
268 | ||
269 | cs->hw_mode |= SPMODE_LEN(bits_per_word); | |
270 | ||
575c5807 | 271 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
53604dbe | 272 | cs->hw_mode |= SPMODE_DIV16; |
4f4517c4 | 273 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; |
31ae7794 ME |
274 | WARN_ONCE(pm > 16, |
275 | "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n", | |
276 | dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024); | |
fd8a11e1 | 277 | if (pm > 16) |
53604dbe | 278 | pm = 16; |
b36ece83 | 279 | } else { |
4f4517c4 | 280 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; |
b36ece83 | 281 | } |
a61f5345 CG |
282 | if (pm) |
283 | pm--; | |
284 | ||
285 | cs->hw_mode |= SPMODE_PM(pm); | |
a35c1710 | 286 | |
b36ece83 | 287 | fsl_spi_change_mode(spi); |
c9bfcb31 JT |
288 | return 0; |
289 | } | |
ccf06998 | 290 | |
b36ece83 | 291 | static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, |
4c1fba44 AV |
292 | struct spi_transfer *t, unsigned int len) |
293 | { | |
294 | u32 word; | |
b36ece83 | 295 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
296 | |
297 | mspi->count = len; | |
298 | ||
299 | /* enable rx ints */ | |
b36ece83 | 300 | mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); |
4c1fba44 AV |
301 | |
302 | /* transmit word */ | |
303 | word = mspi->get_tx(mspi); | |
b36ece83 | 304 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
4c1fba44 AV |
305 | |
306 | return 0; | |
307 | } | |
308 | ||
b36ece83 | 309 | static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, |
4c1fba44 AV |
310 | bool is_dma_mapped) |
311 | { | |
312 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
b36ece83 | 313 | struct fsl_spi_reg *reg_base; |
4c1fba44 AV |
314 | unsigned int len = t->len; |
315 | u8 bits_per_word; | |
316 | int ret; | |
c9bfcb31 | 317 | |
b36ece83 | 318 | reg_base = mpc8xxx_spi->reg_base; |
c9bfcb31 JT |
319 | bits_per_word = spi->bits_per_word; |
320 | if (t->bits_per_word) | |
321 | bits_per_word = t->bits_per_word; | |
4c1fba44 | 322 | |
aa77d96b PK |
323 | if (bits_per_word > 8) { |
324 | /* invalid length? */ | |
325 | if (len & 1) | |
326 | return -EINVAL; | |
c9bfcb31 | 327 | len /= 2; |
aa77d96b PK |
328 | } |
329 | if (bits_per_word > 16) { | |
330 | /* invalid length? */ | |
331 | if (len & 1) | |
332 | return -EINVAL; | |
c9bfcb31 | 333 | len /= 2; |
aa77d96b | 334 | } |
aa77d96b | 335 | |
4c1fba44 AV |
336 | mpc8xxx_spi->tx = t->tx_buf; |
337 | mpc8xxx_spi->rx = t->rx_buf; | |
c9bfcb31 | 338 | |
16735d02 | 339 | reinit_completion(&mpc8xxx_spi->done); |
c9bfcb31 | 340 | |
4c1fba44 | 341 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 342 | ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); |
4c1fba44 | 343 | else |
b36ece83 | 344 | ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); |
4c1fba44 AV |
345 | if (ret) |
346 | return ret; | |
c9bfcb31 | 347 | |
575c5807 | 348 | wait_for_completion(&mpc8xxx_spi->done); |
c9bfcb31 JT |
349 | |
350 | /* disable rx ints */ | |
b36ece83 | 351 | mpc8xxx_spi_write_reg(®_base->mask, 0); |
c9bfcb31 | 352 | |
4c1fba44 | 353 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 354 | fsl_spi_cpm_bufs_complete(mpc8xxx_spi); |
4c1fba44 | 355 | |
575c5807 | 356 | return mpc8xxx_spi->count; |
c9bfcb31 JT |
357 | } |
358 | ||
c592becb HK |
359 | static int fsl_spi_do_one_msg(struct spi_master *master, |
360 | struct spi_message *m) | |
c9bfcb31 | 361 | { |
af0e6242 | 362 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); |
b9b9af11 | 363 | struct spi_device *spi = m->spi; |
4302a596 | 364 | struct spi_transfer *t, *first; |
b9b9af11 AV |
365 | unsigned int cs_change; |
366 | const int nsecs = 50; | |
a798a708 | 367 | int status, last_bpw; |
b9b9af11 | 368 | |
af0e6242 RV |
369 | /* |
370 | * In CPU mode, optimize large byte transfers to use larger | |
371 | * bits_per_word values to reduce number of interrupts taken. | |
372 | */ | |
373 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { | |
374 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
375 | if (t->len < 256 || t->bits_per_word != 8) | |
376 | continue; | |
377 | if ((t->len & 3) == 0) | |
378 | t->bits_per_word = 32; | |
379 | else if ((t->len & 1) == 0) | |
380 | t->bits_per_word = 16; | |
381 | } | |
382 | } | |
383 | ||
4302a596 | 384 | /* Don't allow changes if CS is active */ |
17ecffa2 | 385 | cs_change = 1; |
b9b9af11 | 386 | list_for_each_entry(t, &m->transfers, transfer_list) { |
17ecffa2 RV |
387 | if (cs_change) |
388 | first = t; | |
389 | cs_change = t->cs_change; | |
a798a708 | 390 | if (first->speed_hz != t->speed_hz) { |
4302a596 | 391 | dev_err(&spi->dev, |
a798a708 | 392 | "speed_hz cannot change while CS is active\n"); |
75c41088 | 393 | return -EINVAL; |
4302a596 SR |
394 | } |
395 | } | |
b9b9af11 | 396 | |
a798a708 | 397 | last_bpw = -1; |
4302a596 SR |
398 | cs_change = 1; |
399 | status = -EINVAL; | |
400 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
a798a708 | 401 | if (cs_change || last_bpw != t->bits_per_word) |
24c36362 RV |
402 | status = fsl_spi_setup_transfer(spi, t); |
403 | if (status < 0) | |
404 | break; | |
a798a708 | 405 | last_bpw = t->bits_per_word; |
c9bfcb31 | 406 | |
b9b9af11 | 407 | if (cs_change) { |
b36ece83 | 408 | fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); |
b9b9af11 AV |
409 | ndelay(nsecs); |
410 | } | |
411 | cs_change = t->cs_change; | |
412 | if (t->len) | |
b36ece83 | 413 | status = fsl_spi_bufs(spi, t, m->is_dma_mapped); |
b9b9af11 AV |
414 | if (status) { |
415 | status = -EMSGSIZE; | |
416 | break; | |
c9bfcb31 | 417 | } |
b9b9af11 | 418 | m->actual_length += t->len; |
c9bfcb31 | 419 | |
b9b9af11 AV |
420 | if (t->delay_usecs) |
421 | udelay(t->delay_usecs); | |
c9bfcb31 | 422 | |
b9b9af11 | 423 | if (cs_change) { |
c9bfcb31 | 424 | ndelay(nsecs); |
b36ece83 | 425 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 | 426 | ndelay(nsecs); |
c9bfcb31 | 427 | } |
b9b9af11 AV |
428 | } |
429 | ||
430 | m->status = status; | |
b9b9af11 AV |
431 | |
432 | if (status || !cs_change) { | |
433 | ndelay(nsecs); | |
b36ece83 | 434 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 AV |
435 | } |
436 | ||
b36ece83 | 437 | fsl_spi_setup_transfer(spi, NULL); |
44a04218 | 438 | spi_finalize_current_message(master); |
c592becb | 439 | return 0; |
ccf06998 KG |
440 | } |
441 | ||
b36ece83 | 442 | static int fsl_spi_setup(struct spi_device *spi) |
ccf06998 | 443 | { |
575c5807 | 444 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 445 | struct fsl_spi_reg *reg_base; |
ccf06998 | 446 | int retval; |
c9bfcb31 | 447 | u32 hw_mode; |
d9f26748 | 448 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
ccf06998 KG |
449 | |
450 | if (!spi->max_speed_hz) | |
451 | return -EINVAL; | |
452 | ||
c9bfcb31 | 453 | if (!cs) { |
d9f26748 | 454 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); |
c9bfcb31 JT |
455 | if (!cs) |
456 | return -ENOMEM; | |
d9f26748 | 457 | spi_set_ctldata(spi, cs); |
c9bfcb31 | 458 | } |
575c5807 | 459 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
ccf06998 | 460 | |
b36ece83 MH |
461 | reg_base = mpc8xxx_spi->reg_base; |
462 | ||
88393161 | 463 | hw_mode = cs->hw_mode; /* Save original settings */ |
b36ece83 | 464 | cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); |
c9bfcb31 JT |
465 | /* mask out bits we are going to set */ |
466 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH | |
467 | | SPMODE_REV | SPMODE_LOOP); | |
468 | ||
469 | if (spi->mode & SPI_CPHA) | |
470 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; | |
471 | if (spi->mode & SPI_CPOL) | |
472 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; | |
473 | if (!(spi->mode & SPI_LSB_FIRST)) | |
474 | cs->hw_mode |= SPMODE_REV; | |
475 | if (spi->mode & SPI_LOOP) | |
476 | cs->hw_mode |= SPMODE_LOOP; | |
477 | ||
b36ece83 | 478 | retval = fsl_spi_setup_transfer(spi, NULL); |
c9bfcb31 JT |
479 | if (retval < 0) { |
480 | cs->hw_mode = hw_mode; /* Restore settings */ | |
ccf06998 | 481 | return retval; |
c9bfcb31 | 482 | } |
f482cd0f | 483 | |
76a7498f AL |
484 | if (mpc8xxx_spi->type == TYPE_GRLIB) { |
485 | if (gpio_is_valid(spi->cs_gpio)) { | |
486 | int desel; | |
487 | ||
488 | retval = gpio_request(spi->cs_gpio, | |
489 | dev_name(&spi->dev)); | |
490 | if (retval) | |
491 | return retval; | |
492 | ||
493 | desel = !(spi->mode & SPI_CS_HIGH); | |
494 | retval = gpio_direction_output(spi->cs_gpio, desel); | |
495 | if (retval) { | |
496 | gpio_free(spi->cs_gpio); | |
497 | return retval; | |
498 | } | |
499 | } else if (spi->cs_gpio != -ENOENT) { | |
500 | if (spi->cs_gpio < 0) | |
501 | return spi->cs_gpio; | |
502 | return -EINVAL; | |
503 | } | |
504 | /* When spi->cs_gpio == -ENOENT, a hole in the phandle list | |
505 | * indicates to use native chipselect if present, or allow for | |
506 | * an always selected chip | |
507 | */ | |
508 | } | |
509 | ||
f482cd0f AL |
510 | /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ |
511 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); | |
512 | ||
ccf06998 KG |
513 | return 0; |
514 | } | |
515 | ||
76a7498f AL |
516 | static void fsl_spi_cleanup(struct spi_device *spi) |
517 | { | |
518 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
d9f26748 | 519 | struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); |
76a7498f AL |
520 | |
521 | if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio)) | |
522 | gpio_free(spi->cs_gpio); | |
d9f26748 AL |
523 | |
524 | kfree(cs); | |
525 | spi_set_ctldata(spi, NULL); | |
76a7498f AL |
526 | } |
527 | ||
b36ece83 | 528 | static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
4c1fba44 | 529 | { |
b36ece83 MH |
530 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
531 | ||
4c1fba44 AV |
532 | /* We need handle RX first */ |
533 | if (events & SPIE_NE) { | |
b36ece83 | 534 | u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); |
4c1fba44 AV |
535 | |
536 | if (mspi->rx) | |
537 | mspi->get_rx(rx_data, mspi); | |
ccf06998 KG |
538 | } |
539 | ||
4c1fba44 | 540 | if ((events & SPIE_NF) == 0) |
ccf06998 | 541 | /* spin until TX is done */ |
4c1fba44 | 542 | while (((events = |
b36ece83 | 543 | mpc8xxx_spi_read_reg(®_base->event)) & |
ccf06998 | 544 | SPIE_NF) == 0) |
9effb959 | 545 | cpu_relax(); |
ccf06998 | 546 | |
4c1fba44 | 547 | /* Clear the events */ |
b36ece83 | 548 | mpc8xxx_spi_write_reg(®_base->event, events); |
4c1fba44 AV |
549 | |
550 | mspi->count -= 1; | |
551 | if (mspi->count) { | |
552 | u32 word = mspi->get_tx(mspi); | |
553 | ||
b36ece83 | 554 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
ccf06998 | 555 | } else { |
4c1fba44 | 556 | complete(&mspi->done); |
ccf06998 | 557 | } |
4c1fba44 | 558 | } |
ccf06998 | 559 | |
b36ece83 | 560 | static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) |
4c1fba44 AV |
561 | { |
562 | struct mpc8xxx_spi *mspi = context_data; | |
563 | irqreturn_t ret = IRQ_NONE; | |
564 | u32 events; | |
b36ece83 | 565 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
566 | |
567 | /* Get interrupt events(tx/rx) */ | |
b36ece83 | 568 | events = mpc8xxx_spi_read_reg(®_base->event); |
4c1fba44 AV |
569 | if (events) |
570 | ret = IRQ_HANDLED; | |
571 | ||
572 | dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); | |
573 | ||
574 | if (mspi->flags & SPI_CPM_MODE) | |
b36ece83 | 575 | fsl_spi_cpm_irq(mspi, events); |
4c1fba44 | 576 | else |
b36ece83 | 577 | fsl_spi_cpu_irq(mspi, events); |
ccf06998 KG |
578 | |
579 | return ret; | |
580 | } | |
4c1fba44 | 581 | |
447b0c7b AL |
582 | static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) |
583 | { | |
584 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
585 | struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; | |
586 | u32 slvsel; | |
587 | u16 cs = spi->chip_select; | |
588 | ||
76a7498f AL |
589 | if (gpio_is_valid(spi->cs_gpio)) { |
590 | gpio_set_value(spi->cs_gpio, on); | |
591 | } else if (cs < mpc8xxx_spi->native_chipselects) { | |
592 | slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); | |
593 | slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); | |
594 | mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); | |
595 | } | |
447b0c7b AL |
596 | } |
597 | ||
598 | static void fsl_spi_grlib_probe(struct device *dev) | |
599 | { | |
8074cf06 | 600 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
447b0c7b AL |
601 | struct spi_master *master = dev_get_drvdata(dev); |
602 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
603 | struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; | |
604 | int mbits; | |
605 | u32 capabilities; | |
606 | ||
607 | capabilities = mpc8xxx_spi_read_reg(®_base->cap); | |
608 | ||
609 | mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; | |
610 | mbits = SPCAP_MAXWLEN(capabilities); | |
611 | if (mbits) | |
612 | mpc8xxx_spi->max_bits_per_word = mbits + 1; | |
613 | ||
76a7498f | 614 | mpc8xxx_spi->native_chipselects = 0; |
447b0c7b | 615 | if (SPCAP_SSEN(capabilities)) { |
76a7498f | 616 | mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); |
447b0c7b AL |
617 | mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); |
618 | } | |
76a7498f | 619 | master->num_chipselect = mpc8xxx_spi->native_chipselects; |
447b0c7b AL |
620 | pdata->cs_control = fsl_spi_grlib_cs_control; |
621 | } | |
622 | ||
fd4a319b | 623 | static struct spi_master * fsl_spi_probe(struct device *dev, |
b36ece83 | 624 | struct resource *mem, unsigned int irq) |
ccf06998 | 625 | { |
8074cf06 | 626 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
ccf06998 | 627 | struct spi_master *master; |
575c5807 | 628 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 629 | struct fsl_spi_reg *reg_base; |
ccf06998 KG |
630 | u32 regval; |
631 | int ret = 0; | |
632 | ||
575c5807 | 633 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); |
ccf06998 KG |
634 | if (master == NULL) { |
635 | ret = -ENOMEM; | |
636 | goto err; | |
637 | } | |
638 | ||
35b4b3c0 | 639 | dev_set_drvdata(dev, master); |
ccf06998 | 640 | |
c592becb | 641 | mpc8xxx_spi_probe(dev, mem, irq); |
e7db06b5 | 642 | |
b36ece83 | 643 | master->setup = fsl_spi_setup; |
76a7498f | 644 | master->cleanup = fsl_spi_cleanup; |
c592becb | 645 | master->transfer_one_message = fsl_spi_do_one_msg; |
575c5807 AV |
646 | |
647 | mpc8xxx_spi = spi_master_get_devdata(master); | |
8922a366 | 648 | mpc8xxx_spi->max_bits_per_word = 32; |
c3f3e771 | 649 | mpc8xxx_spi->type = fsl_spi_get_type(dev); |
575c5807 | 650 | |
b36ece83 | 651 | ret = fsl_spi_cpm_init(mpc8xxx_spi); |
4c1fba44 AV |
652 | if (ret) |
653 | goto err_cpm_init; | |
654 | ||
4178b6b1 | 655 | mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); |
37c5db79 AL |
656 | if (IS_ERR(mpc8xxx_spi->reg_base)) { |
657 | ret = PTR_ERR(mpc8xxx_spi->reg_base); | |
4178b6b1 | 658 | goto err_probe; |
447b0c7b AL |
659 | } |
660 | ||
661 | if (mpc8xxx_spi->type == TYPE_GRLIB) | |
662 | fsl_spi_grlib_probe(dev); | |
663 | ||
f734394d AL |
664 | master->bits_per_word_mask = |
665 | (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) & | |
666 | SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); | |
667 | ||
b48c4e3c AL |
668 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
669 | mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; | |
670 | ||
671 | if (mpc8xxx_spi->set_shifts) | |
672 | /* 8 bits per word and MSB first */ | |
673 | mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, | |
674 | &mpc8xxx_spi->tx_shift, 8, 1); | |
f29ba280 | 675 | |
ccf06998 | 676 | /* Register for SPI Interrupt */ |
4178b6b1 HK |
677 | ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq, |
678 | 0, "fsl_spi", mpc8xxx_spi); | |
ccf06998 KG |
679 | |
680 | if (ret != 0) | |
4178b6b1 | 681 | goto err_probe; |
ccf06998 | 682 | |
b36ece83 | 683 | reg_base = mpc8xxx_spi->reg_base; |
ccf06998 KG |
684 | |
685 | /* SPI controller initializations */ | |
b36ece83 MH |
686 | mpc8xxx_spi_write_reg(®_base->mode, 0); |
687 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
688 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
689 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
ccf06998 KG |
690 | |
691 | /* Enable SPI interface */ | |
692 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
8922a366 AL |
693 | if (mpc8xxx_spi->max_bits_per_word < 8) { |
694 | regval &= ~SPMODE_LEN(0xF); | |
695 | regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); | |
696 | } | |
87ec0e98 | 697 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
f29ba280 JT |
698 | regval |= SPMODE_OP; |
699 | ||
b36ece83 | 700 | mpc8xxx_spi_write_reg(®_base->mode, regval); |
c9bfcb31 | 701 | |
4178b6b1 | 702 | ret = devm_spi_register_master(dev, master); |
c9bfcb31 | 703 | if (ret < 0) |
4178b6b1 | 704 | goto err_probe; |
ccf06998 | 705 | |
b36ece83 | 706 | dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, |
87ec0e98 | 707 | mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); |
ccf06998 | 708 | |
35b4b3c0 | 709 | return master; |
ccf06998 | 710 | |
4178b6b1 | 711 | err_probe: |
b36ece83 | 712 | fsl_spi_cpm_free(mpc8xxx_spi); |
4c1fba44 | 713 | err_cpm_init: |
ccf06998 | 714 | spi_master_put(master); |
ccf06998 | 715 | err: |
35b4b3c0 | 716 | return ERR_PTR(ret); |
ccf06998 KG |
717 | } |
718 | ||
b36ece83 | 719 | static void fsl_spi_cs_control(struct spi_device *spi, bool on) |
35b4b3c0 | 720 | { |
067aa481 | 721 | struct device *dev = spi->dev.parent->parent; |
8074cf06 JH |
722 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
723 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); | |
35b4b3c0 | 724 | u16 cs = spi->chip_select; |
35b4b3c0 | 725 | |
69b921ac RV |
726 | if (cs < pinfo->ngpios) { |
727 | int gpio = pinfo->gpios[cs]; | |
728 | bool alow = pinfo->alow_flags[cs]; | |
729 | ||
730 | gpio_set_value(gpio, on ^ alow); | |
731 | } else { | |
732 | if (WARN_ON_ONCE(cs > pinfo->ngpios || !pinfo->immr_spi_cs)) | |
733 | return; | |
734 | iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs); | |
735 | } | |
35b4b3c0 AV |
736 | } |
737 | ||
b36ece83 | 738 | static int of_fsl_spi_get_chipselects(struct device *dev) |
35b4b3c0 | 739 | { |
61c7a080 | 740 | struct device_node *np = dev->of_node; |
8074cf06 | 741 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
575c5807 | 742 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
69b921ac RV |
743 | bool spisel_boot = IS_ENABLED(CONFIG_FSL_SOC) && |
744 | of_property_read_bool(np, "fsl,spisel_boot"); | |
e80beb27 | 745 | int ngpios; |
35b4b3c0 AV |
746 | int i = 0; |
747 | int ret; | |
748 | ||
749 | ngpios = of_gpio_count(np); | |
69b921ac RV |
750 | ngpios = max(ngpios, 0); |
751 | if (ngpios == 0 && !spisel_boot) { | |
35b4b3c0 AV |
752 | /* |
753 | * SPI w/o chip-select line. One SPI device is still permitted | |
754 | * though. | |
755 | */ | |
756 | pdata->max_chipselect = 1; | |
757 | return 0; | |
758 | } | |
759 | ||
69b921ac | 760 | pinfo->ngpios = ngpios; |
d9bc4a85 ME |
761 | pinfo->gpios = kmalloc_array(ngpios, sizeof(*pinfo->gpios), |
762 | GFP_KERNEL); | |
35b4b3c0 AV |
763 | if (!pinfo->gpios) |
764 | return -ENOMEM; | |
02141546 | 765 | memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); |
35b4b3c0 | 766 | |
5223db0b | 767 | pinfo->alow_flags = kcalloc(ngpios, sizeof(*pinfo->alow_flags), |
35b4b3c0 AV |
768 | GFP_KERNEL); |
769 | if (!pinfo->alow_flags) { | |
770 | ret = -ENOMEM; | |
771 | goto err_alloc_flags; | |
772 | } | |
773 | ||
774 | for (; i < ngpios; i++) { | |
775 | int gpio; | |
776 | enum of_gpio_flags flags; | |
777 | ||
778 | gpio = of_get_gpio_flags(np, i, &flags); | |
779 | if (!gpio_is_valid(gpio)) { | |
780 | dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); | |
783058fd | 781 | ret = gpio; |
35b4b3c0 AV |
782 | goto err_loop; |
783 | } | |
784 | ||
785 | ret = gpio_request(gpio, dev_name(dev)); | |
786 | if (ret) { | |
787 | dev_err(dev, "can't request gpio #%d: %d\n", i, ret); | |
788 | goto err_loop; | |
789 | } | |
790 | ||
791 | pinfo->gpios[i] = gpio; | |
792 | pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; | |
793 | ||
794 | ret = gpio_direction_output(pinfo->gpios[i], | |
795 | pinfo->alow_flags[i]); | |
796 | if (ret) { | |
31ae7794 ME |
797 | dev_err(dev, |
798 | "can't set output direction for gpio #%d: %d\n", | |
799 | i, ret); | |
35b4b3c0 AV |
800 | goto err_loop; |
801 | } | |
802 | } | |
803 | ||
69b921ac RV |
804 | #if IS_ENABLED(CONFIG_FSL_SOC) |
805 | if (spisel_boot) { | |
806 | pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4); | |
807 | if (!pinfo->immr_spi_cs) { | |
808 | ret = -ENOMEM; | |
809 | i = ngpios - 1; | |
810 | goto err_loop; | |
811 | } | |
812 | } | |
813 | #endif | |
814 | ||
815 | pdata->max_chipselect = ngpios + spisel_boot; | |
b36ece83 | 816 | pdata->cs_control = fsl_spi_cs_control; |
35b4b3c0 AV |
817 | |
818 | return 0; | |
819 | ||
820 | err_loop: | |
821 | while (i >= 0) { | |
822 | if (gpio_is_valid(pinfo->gpios[i])) | |
823 | gpio_free(pinfo->gpios[i]); | |
824 | i--; | |
825 | } | |
826 | ||
827 | kfree(pinfo->alow_flags); | |
828 | pinfo->alow_flags = NULL; | |
829 | err_alloc_flags: | |
830 | kfree(pinfo->gpios); | |
831 | pinfo->gpios = NULL; | |
832 | return ret; | |
833 | } | |
834 | ||
b36ece83 | 835 | static int of_fsl_spi_free_chipselects(struct device *dev) |
35b4b3c0 | 836 | { |
8074cf06 | 837 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
575c5807 | 838 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
839 | int i; |
840 | ||
841 | if (!pinfo->gpios) | |
842 | return 0; | |
843 | ||
844 | for (i = 0; i < pdata->max_chipselect; i++) { | |
845 | if (gpio_is_valid(pinfo->gpios[i])) | |
846 | gpio_free(pinfo->gpios[i]); | |
847 | } | |
848 | ||
849 | kfree(pinfo->gpios); | |
850 | kfree(pinfo->alow_flags); | |
851 | return 0; | |
852 | } | |
853 | ||
fd4a319b | 854 | static int of_fsl_spi_probe(struct platform_device *ofdev) |
35b4b3c0 AV |
855 | { |
856 | struct device *dev = &ofdev->dev; | |
61c7a080 | 857 | struct device_node *np = ofdev->dev.of_node; |
35b4b3c0 AV |
858 | struct spi_master *master; |
859 | struct resource mem; | |
500a32ab | 860 | int irq = 0, type; |
35b4b3c0 AV |
861 | int ret = -ENOMEM; |
862 | ||
18d306d1 | 863 | ret = of_mpc8xxx_spi_probe(ofdev); |
b36ece83 MH |
864 | if (ret) |
865 | return ret; | |
35b4b3c0 | 866 | |
447b0c7b AL |
867 | type = fsl_spi_get_type(&ofdev->dev); |
868 | if (type == TYPE_FSL) { | |
869 | ret = of_fsl_spi_get_chipselects(dev); | |
870 | if (ret) | |
871 | goto err; | |
872 | } | |
35b4b3c0 AV |
873 | |
874 | ret = of_address_to_resource(np, 0, &mem); | |
875 | if (ret) | |
876 | goto err; | |
877 | ||
e8beacbb AL |
878 | irq = irq_of_parse_and_map(np, 0); |
879 | if (!irq) { | |
35b4b3c0 AV |
880 | ret = -EINVAL; |
881 | goto err; | |
882 | } | |
883 | ||
e8beacbb | 884 | master = fsl_spi_probe(dev, &mem, irq); |
35b4b3c0 AV |
885 | if (IS_ERR(master)) { |
886 | ret = PTR_ERR(master); | |
887 | goto err; | |
888 | } | |
889 | ||
35b4b3c0 AV |
890 | return 0; |
891 | ||
892 | err: | |
500a32ab | 893 | irq_dispose_mapping(irq); |
447b0c7b AL |
894 | if (type == TYPE_FSL) |
895 | of_fsl_spi_free_chipselects(dev); | |
35b4b3c0 AV |
896 | return ret; |
897 | } | |
898 | ||
fd4a319b | 899 | static int of_fsl_spi_remove(struct platform_device *ofdev) |
35b4b3c0 | 900 | { |
24b5a82c | 901 | struct spi_master *master = platform_get_drvdata(ofdev); |
447b0c7b | 902 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); |
35b4b3c0 | 903 | |
3c5395b6 | 904 | fsl_spi_cpm_free(mpc8xxx_spi); |
447b0c7b AL |
905 | if (mpc8xxx_spi->type == TYPE_FSL) |
906 | of_fsl_spi_free_chipselects(&ofdev->dev); | |
35b4b3c0 AV |
907 | return 0; |
908 | } | |
909 | ||
18d306d1 | 910 | static struct platform_driver of_fsl_spi_driver = { |
4018294b | 911 | .driver = { |
b36ece83 | 912 | .name = "fsl_spi", |
b36ece83 | 913 | .of_match_table = of_fsl_spi_match, |
4018294b | 914 | }, |
b36ece83 | 915 | .probe = of_fsl_spi_probe, |
fd4a319b | 916 | .remove = of_fsl_spi_remove, |
35b4b3c0 AV |
917 | }; |
918 | ||
919 | #ifdef CONFIG_MPC832x_RDB | |
920 | /* | |
b36ece83 | 921 | * XXX XXX XXX |
35b4b3c0 AV |
922 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards |
923 | * only. The driver should go away soon, since newer MPC8323E-RDB's device | |
924 | * tree can work with OpenFirmware driver. But for now we support old trees | |
925 | * as well. | |
926 | */ | |
fd4a319b | 927 | static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
35b4b3c0 AV |
928 | { |
929 | struct resource *mem; | |
e9a172f0 | 930 | int irq; |
35b4b3c0 AV |
931 | struct spi_master *master; |
932 | ||
8074cf06 | 933 | if (!dev_get_platdata(&pdev->dev)) |
35b4b3c0 AV |
934 | return -EINVAL; |
935 | ||
936 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
937 | if (!mem) | |
938 | return -EINVAL; | |
939 | ||
940 | irq = platform_get_irq(pdev, 0); | |
e9a172f0 | 941 | if (irq <= 0) |
35b4b3c0 AV |
942 | return -EINVAL; |
943 | ||
b36ece83 | 944 | master = fsl_spi_probe(&pdev->dev, mem, irq); |
8c6ffba0 | 945 | return PTR_ERR_OR_ZERO(master); |
35b4b3c0 AV |
946 | } |
947 | ||
fd4a319b | 948 | static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
35b4b3c0 | 949 | { |
3c5395b6 HK |
950 | struct spi_master *master = platform_get_drvdata(pdev); |
951 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); | |
952 | ||
953 | fsl_spi_cpm_free(mpc8xxx_spi); | |
954 | ||
955 | return 0; | |
35b4b3c0 AV |
956 | } |
957 | ||
575c5807 AV |
958 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
959 | static struct platform_driver mpc8xxx_spi_driver = { | |
960 | .probe = plat_mpc8xxx_spi_probe, | |
fd4a319b | 961 | .remove = plat_mpc8xxx_spi_remove, |
ccf06998 | 962 | .driver = { |
575c5807 | 963 | .name = "mpc8xxx_spi", |
ccf06998 KG |
964 | }, |
965 | }; | |
966 | ||
35b4b3c0 AV |
967 | static bool legacy_driver_failed; |
968 | ||
969 | static void __init legacy_driver_register(void) | |
970 | { | |
575c5807 | 971 | legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
972 | } |
973 | ||
974 | static void __exit legacy_driver_unregister(void) | |
975 | { | |
976 | if (legacy_driver_failed) | |
977 | return; | |
575c5807 | 978 | platform_driver_unregister(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
979 | } |
980 | #else | |
981 | static void __init legacy_driver_register(void) {} | |
982 | static void __exit legacy_driver_unregister(void) {} | |
983 | #endif /* CONFIG_MPC832x_RDB */ | |
984 | ||
b36ece83 | 985 | static int __init fsl_spi_init(void) |
ccf06998 | 986 | { |
35b4b3c0 | 987 | legacy_driver_register(); |
18d306d1 | 988 | return platform_driver_register(&of_fsl_spi_driver); |
ccf06998 | 989 | } |
b36ece83 | 990 | module_init(fsl_spi_init); |
ccf06998 | 991 | |
b36ece83 | 992 | static void __exit fsl_spi_exit(void) |
ccf06998 | 993 | { |
18d306d1 | 994 | platform_driver_unregister(&of_fsl_spi_driver); |
35b4b3c0 | 995 | legacy_driver_unregister(); |
ccf06998 | 996 | } |
b36ece83 | 997 | module_exit(fsl_spi_exit); |
ccf06998 KG |
998 | |
999 | MODULE_AUTHOR("Kumar Gala"); | |
b36ece83 | 1000 | MODULE_DESCRIPTION("Simple Freescale SPI Driver"); |
ccf06998 | 1001 | MODULE_LICENSE("GPL"); |