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Commit | Line | Data |
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deba2580 AB |
1 | /* |
2 | * IMG SPFI controller driver | |
3 | * | |
4 | * Copyright (C) 2007,2008,2013 Imagination Technologies Ltd. | |
5 | * Copyright (C) 2014 Google, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/dmaengine.h> | |
8c2c8c03 | 15 | #include <linux/gpio.h> |
deba2580 AB |
16 | #include <linux/interrupt.h> |
17 | #include <linux/io.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/pm_runtime.h> | |
23 | #include <linux/scatterlist.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/spi/spi.h> | |
26 | #include <linux/spinlock.h> | |
27 | ||
28 | #define SPFI_DEVICE_PARAMETER(x) (0x00 + 0x4 * (x)) | |
29 | #define SPFI_DEVICE_PARAMETER_BITCLK_SHIFT 24 | |
30 | #define SPFI_DEVICE_PARAMETER_BITCLK_MASK 0xff | |
31 | #define SPFI_DEVICE_PARAMETER_CSSETUP_SHIFT 16 | |
32 | #define SPFI_DEVICE_PARAMETER_CSSETUP_MASK 0xff | |
33 | #define SPFI_DEVICE_PARAMETER_CSHOLD_SHIFT 8 | |
34 | #define SPFI_DEVICE_PARAMETER_CSHOLD_MASK 0xff | |
35 | #define SPFI_DEVICE_PARAMETER_CSDELAY_SHIFT 0 | |
36 | #define SPFI_DEVICE_PARAMETER_CSDELAY_MASK 0xff | |
37 | ||
38 | #define SPFI_CONTROL 0x14 | |
39 | #define SPFI_CONTROL_CONTINUE BIT(12) | |
40 | #define SPFI_CONTROL_SOFT_RESET BIT(11) | |
41 | #define SPFI_CONTROL_SEND_DMA BIT(10) | |
42 | #define SPFI_CONTROL_GET_DMA BIT(9) | |
43 | #define SPFI_CONTROL_TMODE_SHIFT 5 | |
44 | #define SPFI_CONTROL_TMODE_MASK 0x7 | |
45 | #define SPFI_CONTROL_TMODE_SINGLE 0 | |
46 | #define SPFI_CONTROL_TMODE_DUAL 1 | |
47 | #define SPFI_CONTROL_TMODE_QUAD 2 | |
48 | #define SPFI_CONTROL_SPFI_EN BIT(0) | |
49 | ||
50 | #define SPFI_TRANSACTION 0x18 | |
51 | #define SPFI_TRANSACTION_TSIZE_SHIFT 16 | |
52 | #define SPFI_TRANSACTION_TSIZE_MASK 0xffff | |
53 | ||
54 | #define SPFI_PORT_STATE 0x1c | |
55 | #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20 | |
56 | #define SPFI_PORT_STATE_DEV_SEL_MASK 0x7 | |
57 | #define SPFI_PORT_STATE_CK_POL(x) BIT(19 - (x)) | |
58 | #define SPFI_PORT_STATE_CK_PHASE(x) BIT(14 - (x)) | |
59 | ||
60 | #define SPFI_TX_32BIT_VALID_DATA 0x20 | |
61 | #define SPFI_TX_8BIT_VALID_DATA 0x24 | |
62 | #define SPFI_RX_32BIT_VALID_DATA 0x28 | |
63 | #define SPFI_RX_8BIT_VALID_DATA 0x2c | |
64 | ||
65 | #define SPFI_INTERRUPT_STATUS 0x30 | |
66 | #define SPFI_INTERRUPT_ENABLE 0x34 | |
67 | #define SPFI_INTERRUPT_CLEAR 0x38 | |
68 | #define SPFI_INTERRUPT_IACCESS BIT(12) | |
69 | #define SPFI_INTERRUPT_GDEX8BIT BIT(11) | |
70 | #define SPFI_INTERRUPT_ALLDONETRIG BIT(9) | |
71 | #define SPFI_INTERRUPT_GDFUL BIT(8) | |
72 | #define SPFI_INTERRUPT_GDHF BIT(7) | |
73 | #define SPFI_INTERRUPT_GDEX32BIT BIT(6) | |
74 | #define SPFI_INTERRUPT_GDTRIG BIT(5) | |
75 | #define SPFI_INTERRUPT_SDFUL BIT(3) | |
76 | #define SPFI_INTERRUPT_SDHF BIT(2) | |
77 | #define SPFI_INTERRUPT_SDE BIT(1) | |
78 | #define SPFI_INTERRUPT_SDTRIG BIT(0) | |
79 | ||
80 | /* | |
81 | * There are four parallel FIFOs of 16 bytes each. The word buffer | |
82 | * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an | |
83 | * effective FIFO size of 64 bytes. The byte buffer (*_8BIT_VALID_DATA) | |
84 | * accesses only a single FIFO, resulting in an effective FIFO size of | |
85 | * 16 bytes. | |
86 | */ | |
87 | #define SPFI_32BIT_FIFO_SIZE 64 | |
88 | #define SPFI_8BIT_FIFO_SIZE 16 | |
89 | ||
90 | struct img_spfi { | |
91 | struct device *dev; | |
92 | struct spi_master *master; | |
93 | spinlock_t lock; | |
94 | ||
95 | void __iomem *regs; | |
96 | phys_addr_t phys; | |
97 | int irq; | |
98 | struct clk *spfi_clk; | |
99 | struct clk *sys_clk; | |
100 | ||
101 | struct dma_chan *rx_ch; | |
102 | struct dma_chan *tx_ch; | |
103 | bool tx_dma_busy; | |
104 | bool rx_dma_busy; | |
105 | }; | |
106 | ||
b03ba9e3 SN |
107 | struct img_spfi_device_data { |
108 | bool gpio_requested; | |
109 | }; | |
110 | ||
deba2580 AB |
111 | static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg) |
112 | { | |
113 | return readl(spfi->regs + reg); | |
114 | } | |
115 | ||
116 | static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg) | |
117 | { | |
118 | writel(val, spfi->regs + reg); | |
119 | } | |
120 | ||
121 | static inline void spfi_start(struct img_spfi *spfi) | |
122 | { | |
123 | u32 val; | |
124 | ||
125 | val = spfi_readl(spfi, SPFI_CONTROL); | |
126 | val |= SPFI_CONTROL_SPFI_EN; | |
127 | spfi_writel(spfi, val, SPFI_CONTROL); | |
128 | } | |
129 | ||
deba2580 AB |
130 | static inline void spfi_reset(struct img_spfi *spfi) |
131 | { | |
132 | spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL); | |
deba2580 AB |
133 | spfi_writel(spfi, 0, SPFI_CONTROL); |
134 | } | |
135 | ||
8c2c8c03 | 136 | static int spfi_wait_all_done(struct img_spfi *spfi) |
deba2580 | 137 | { |
8c2c8c03 | 138 | unsigned long timeout = jiffies + msecs_to_jiffies(50); |
deba2580 | 139 | |
deba2580 | 140 | while (time_before(jiffies, timeout)) { |
8c2c8c03 EG |
141 | u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); |
142 | ||
143 | if (status & SPFI_INTERRUPT_ALLDONETRIG) { | |
144 | spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG, | |
145 | SPFI_INTERRUPT_CLEAR); | |
146 | return 0; | |
147 | } | |
deba2580 AB |
148 | cpu_relax(); |
149 | } | |
150 | ||
8c2c8c03 | 151 | dev_err(spfi->dev, "Timed out waiting for transaction to complete\n"); |
deba2580 | 152 | spfi_reset(spfi); |
8c2c8c03 EG |
153 | |
154 | return -ETIMEDOUT; | |
deba2580 AB |
155 | } |
156 | ||
157 | static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf, | |
158 | unsigned int max) | |
159 | { | |
160 | unsigned int count = 0; | |
161 | u32 status; | |
162 | ||
549858ce | 163 | while (count < max / 4) { |
deba2580 AB |
164 | spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR); |
165 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); | |
166 | if (status & SPFI_INTERRUPT_SDFUL) | |
167 | break; | |
549858ce AB |
168 | spfi_writel(spfi, buf[count], SPFI_TX_32BIT_VALID_DATA); |
169 | count++; | |
deba2580 AB |
170 | } |
171 | ||
549858ce | 172 | return count * 4; |
deba2580 AB |
173 | } |
174 | ||
175 | static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf, | |
176 | unsigned int max) | |
177 | { | |
178 | unsigned int count = 0; | |
179 | u32 status; | |
180 | ||
181 | while (count < max) { | |
182 | spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR); | |
183 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); | |
184 | if (status & SPFI_INTERRUPT_SDFUL) | |
185 | break; | |
186 | spfi_writel(spfi, buf[count], SPFI_TX_8BIT_VALID_DATA); | |
187 | count++; | |
188 | } | |
189 | ||
190 | return count; | |
191 | } | |
192 | ||
193 | static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf, | |
194 | unsigned int max) | |
195 | { | |
196 | unsigned int count = 0; | |
197 | u32 status; | |
198 | ||
549858ce | 199 | while (count < max / 4) { |
deba2580 AB |
200 | spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT, |
201 | SPFI_INTERRUPT_CLEAR); | |
202 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); | |
203 | if (!(status & SPFI_INTERRUPT_GDEX32BIT)) | |
204 | break; | |
549858ce AB |
205 | buf[count] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA); |
206 | count++; | |
deba2580 AB |
207 | } |
208 | ||
549858ce | 209 | return count * 4; |
deba2580 AB |
210 | } |
211 | ||
212 | static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf, | |
213 | unsigned int max) | |
214 | { | |
215 | unsigned int count = 0; | |
216 | u32 status; | |
217 | ||
218 | while (count < max) { | |
219 | spfi_writel(spfi, SPFI_INTERRUPT_GDEX8BIT, | |
220 | SPFI_INTERRUPT_CLEAR); | |
221 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); | |
222 | if (!(status & SPFI_INTERRUPT_GDEX8BIT)) | |
223 | break; | |
224 | buf[count] = spfi_readl(spfi, SPFI_RX_8BIT_VALID_DATA); | |
225 | count++; | |
226 | } | |
227 | ||
228 | return count; | |
229 | } | |
230 | ||
231 | static int img_spfi_start_pio(struct spi_master *master, | |
232 | struct spi_device *spi, | |
233 | struct spi_transfer *xfer) | |
234 | { | |
235 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); | |
236 | unsigned int tx_bytes = 0, rx_bytes = 0; | |
237 | const void *tx_buf = xfer->tx_buf; | |
238 | void *rx_buf = xfer->rx_buf; | |
239 | unsigned long timeout; | |
8c2c8c03 | 240 | int ret; |
deba2580 AB |
241 | |
242 | if (tx_buf) | |
243 | tx_bytes = xfer->len; | |
244 | if (rx_buf) | |
245 | rx_bytes = xfer->len; | |
246 | ||
247 | spfi_start(spfi); | |
248 | ||
249 | timeout = jiffies + | |
250 | msecs_to_jiffies(xfer->len * 8 * 1000 / xfer->speed_hz + 100); | |
251 | while ((tx_bytes > 0 || rx_bytes > 0) && | |
252 | time_before(jiffies, timeout)) { | |
253 | unsigned int tx_count, rx_count; | |
254 | ||
549858ce | 255 | if (tx_bytes >= 4) |
deba2580 | 256 | tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes); |
549858ce | 257 | else |
deba2580 | 258 | tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes); |
549858ce AB |
259 | |
260 | if (rx_bytes >= 4) | |
261 | rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes); | |
262 | else | |
deba2580 | 263 | rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes); |
deba2580 AB |
264 | |
265 | tx_buf += tx_count; | |
266 | rx_buf += rx_count; | |
267 | tx_bytes -= tx_count; | |
268 | rx_bytes -= rx_count; | |
269 | ||
270 | cpu_relax(); | |
271 | } | |
272 | ||
273 | if (rx_bytes > 0 || tx_bytes > 0) { | |
274 | dev_err(spfi->dev, "PIO transfer timed out\n"); | |
deba2580 AB |
275 | return -ETIMEDOUT; |
276 | } | |
277 | ||
011710e2 SN |
278 | ret = spfi_wait_all_done(spfi); |
279 | if (ret < 0) | |
280 | return ret; | |
281 | ||
deba2580 AB |
282 | return 0; |
283 | } | |
284 | ||
285 | static void img_spfi_dma_rx_cb(void *data) | |
286 | { | |
287 | struct img_spfi *spfi = data; | |
288 | unsigned long flags; | |
289 | ||
8c2c8c03 | 290 | spfi_wait_all_done(spfi); |
deba2580 | 291 | |
8c2c8c03 | 292 | spin_lock_irqsave(&spfi->lock, flags); |
deba2580 | 293 | spfi->rx_dma_busy = false; |
8c2c8c03 | 294 | if (!spfi->tx_dma_busy) |
deba2580 | 295 | spi_finalize_current_transfer(spfi->master); |
deba2580 AB |
296 | spin_unlock_irqrestore(&spfi->lock, flags); |
297 | } | |
298 | ||
299 | static void img_spfi_dma_tx_cb(void *data) | |
300 | { | |
301 | struct img_spfi *spfi = data; | |
302 | unsigned long flags; | |
303 | ||
8c2c8c03 | 304 | spfi_wait_all_done(spfi); |
deba2580 AB |
305 | |
306 | spin_lock_irqsave(&spfi->lock, flags); | |
deba2580 | 307 | spfi->tx_dma_busy = false; |
8c2c8c03 | 308 | if (!spfi->rx_dma_busy) |
deba2580 | 309 | spi_finalize_current_transfer(spfi->master); |
deba2580 AB |
310 | spin_unlock_irqrestore(&spfi->lock, flags); |
311 | } | |
312 | ||
313 | static int img_spfi_start_dma(struct spi_master *master, | |
314 | struct spi_device *spi, | |
315 | struct spi_transfer *xfer) | |
316 | { | |
317 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); | |
318 | struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL; | |
319 | struct dma_slave_config rxconf, txconf; | |
320 | ||
321 | spfi->rx_dma_busy = false; | |
322 | spfi->tx_dma_busy = false; | |
323 | ||
324 | if (xfer->rx_buf) { | |
325 | rxconf.direction = DMA_DEV_TO_MEM; | |
549858ce | 326 | if (xfer->len % 4 == 0) { |
deba2580 AB |
327 | rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA; |
328 | rxconf.src_addr_width = 4; | |
329 | rxconf.src_maxburst = 4; | |
549858ce | 330 | } else { |
deba2580 AB |
331 | rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA; |
332 | rxconf.src_addr_width = 1; | |
76fe5e95 | 333 | rxconf.src_maxburst = 4; |
deba2580 AB |
334 | } |
335 | dmaengine_slave_config(spfi->rx_ch, &rxconf); | |
336 | ||
337 | rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl, | |
338 | xfer->rx_sg.nents, | |
339 | DMA_DEV_TO_MEM, | |
340 | DMA_PREP_INTERRUPT); | |
341 | if (!rxdesc) | |
342 | goto stop_dma; | |
343 | ||
344 | rxdesc->callback = img_spfi_dma_rx_cb; | |
345 | rxdesc->callback_param = spfi; | |
346 | } | |
347 | ||
348 | if (xfer->tx_buf) { | |
349 | txconf.direction = DMA_MEM_TO_DEV; | |
549858ce | 350 | if (xfer->len % 4 == 0) { |
deba2580 AB |
351 | txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA; |
352 | txconf.dst_addr_width = 4; | |
353 | txconf.dst_maxburst = 4; | |
549858ce | 354 | } else { |
deba2580 AB |
355 | txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA; |
356 | txconf.dst_addr_width = 1; | |
76fe5e95 | 357 | txconf.dst_maxburst = 4; |
deba2580 AB |
358 | } |
359 | dmaengine_slave_config(spfi->tx_ch, &txconf); | |
360 | ||
361 | txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl, | |
362 | xfer->tx_sg.nents, | |
363 | DMA_MEM_TO_DEV, | |
364 | DMA_PREP_INTERRUPT); | |
365 | if (!txdesc) | |
366 | goto stop_dma; | |
367 | ||
368 | txdesc->callback = img_spfi_dma_tx_cb; | |
369 | txdesc->callback_param = spfi; | |
370 | } | |
371 | ||
372 | if (xfer->rx_buf) { | |
373 | spfi->rx_dma_busy = true; | |
374 | dmaengine_submit(rxdesc); | |
375 | dma_async_issue_pending(spfi->rx_ch); | |
376 | } | |
377 | ||
c0e7dc21 AB |
378 | spfi_start(spfi); |
379 | ||
deba2580 AB |
380 | if (xfer->tx_buf) { |
381 | spfi->tx_dma_busy = true; | |
382 | dmaengine_submit(txdesc); | |
383 | dma_async_issue_pending(spfi->tx_ch); | |
384 | } | |
385 | ||
deba2580 AB |
386 | return 1; |
387 | ||
388 | stop_dma: | |
389 | dmaengine_terminate_all(spfi->rx_ch); | |
390 | dmaengine_terminate_all(spfi->tx_ch); | |
391 | return -EIO; | |
392 | } | |
393 | ||
824ab37d EG |
394 | static void img_spfi_handle_err(struct spi_master *master, |
395 | struct spi_message *msg) | |
396 | { | |
397 | struct img_spfi *spfi = spi_master_get_devdata(master); | |
398 | unsigned long flags; | |
399 | ||
400 | /* | |
401 | * Stop all DMA and reset the controller if the previous transaction | |
402 | * timed-out and never completed it's DMA. | |
403 | */ | |
404 | spin_lock_irqsave(&spfi->lock, flags); | |
405 | if (spfi->tx_dma_busy || spfi->rx_dma_busy) { | |
406 | spfi->tx_dma_busy = false; | |
407 | spfi->rx_dma_busy = false; | |
408 | ||
409 | dmaengine_terminate_all(spfi->tx_ch); | |
410 | dmaengine_terminate_all(spfi->rx_ch); | |
411 | } | |
412 | spin_unlock_irqrestore(&spfi->lock, flags); | |
824ab37d EG |
413 | } |
414 | ||
b6fe3977 EG |
415 | static int img_spfi_prepare(struct spi_master *master, struct spi_message *msg) |
416 | { | |
417 | struct img_spfi *spfi = spi_master_get_devdata(master); | |
418 | u32 val; | |
419 | ||
420 | val = spfi_readl(spfi, SPFI_PORT_STATE); | |
421 | if (msg->spi->mode & SPI_CPHA) | |
422 | val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); | |
423 | else | |
424 | val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); | |
425 | if (msg->spi->mode & SPI_CPOL) | |
426 | val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select); | |
427 | else | |
428 | val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select); | |
429 | spfi_writel(spfi, val, SPFI_PORT_STATE); | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
ba33d8ac AB |
434 | static int img_spfi_unprepare(struct spi_master *master, |
435 | struct spi_message *msg) | |
436 | { | |
437 | struct img_spfi *spfi = spi_master_get_devdata(master); | |
438 | ||
439 | spfi_reset(spfi); | |
440 | ||
441 | return 0; | |
442 | } | |
443 | ||
8c2c8c03 EG |
444 | static int img_spfi_setup(struct spi_device *spi) |
445 | { | |
446 | int ret; | |
b03ba9e3 SN |
447 | struct img_spfi_device_data *spfi_data = spi_get_ctldata(spi); |
448 | ||
449 | if (!spfi_data) { | |
450 | spfi_data = kzalloc(sizeof(*spfi_data), GFP_KERNEL); | |
451 | if (!spfi_data) | |
452 | return -ENOMEM; | |
453 | spfi_data->gpio_requested = false; | |
454 | spi_set_ctldata(spi, spfi_data); | |
455 | } | |
456 | if (!spfi_data->gpio_requested) { | |
457 | ret = gpio_request_one(spi->cs_gpio, | |
458 | (spi->mode & SPI_CS_HIGH) ? | |
459 | GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH, | |
460 | dev_name(&spi->dev)); | |
461 | if (ret) | |
462 | dev_err(&spi->dev, "can't request chipselect gpio %d\n", | |
8c2c8c03 | 463 | spi->cs_gpio); |
b03ba9e3 SN |
464 | else |
465 | spfi_data->gpio_requested = true; | |
466 | } else { | |
467 | if (gpio_is_valid(spi->cs_gpio)) { | |
468 | int mode = ((spi->mode & SPI_CS_HIGH) ? | |
469 | GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH); | |
470 | ||
471 | ret = gpio_direction_output(spi->cs_gpio, mode); | |
472 | if (ret) | |
473 | dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n", | |
474 | spi->cs_gpio, ret); | |
475 | } | |
476 | } | |
8c2c8c03 EG |
477 | return ret; |
478 | } | |
479 | ||
480 | static void img_spfi_cleanup(struct spi_device *spi) | |
481 | { | |
b03ba9e3 SN |
482 | struct img_spfi_device_data *spfi_data = spi_get_ctldata(spi); |
483 | ||
484 | if (spfi_data) { | |
485 | if (spfi_data->gpio_requested) | |
486 | gpio_free(spi->cs_gpio); | |
487 | kfree(spfi_data); | |
488 | spi_set_ctldata(spi, NULL); | |
489 | } | |
8c2c8c03 EG |
490 | } |
491 | ||
deba2580 AB |
492 | static void img_spfi_config(struct spi_master *master, struct spi_device *spi, |
493 | struct spi_transfer *xfer) | |
494 | { | |
495 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); | |
496 | u32 val, div; | |
497 | ||
498 | /* | |
499 | * output = spfi_clk * (BITCLK / 512), where BITCLK must be a | |
8543d0e7 | 500 | * power of 2 up to 128 |
deba2580 | 501 | */ |
8543d0e7 AB |
502 | div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz); |
503 | div = clamp(512 / (1 << get_count_order(div)), 1, 128); | |
deba2580 AB |
504 | |
505 | val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select)); | |
506 | val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK << | |
507 | SPFI_DEVICE_PARAMETER_BITCLK_SHIFT); | |
508 | val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; | |
509 | spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select)); | |
510 | ||
ede8342b SN |
511 | spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT, |
512 | SPFI_TRANSACTION); | |
513 | ||
deba2580 AB |
514 | val = spfi_readl(spfi, SPFI_CONTROL); |
515 | val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA); | |
516 | if (xfer->tx_buf) | |
517 | val |= SPFI_CONTROL_SEND_DMA; | |
518 | if (xfer->rx_buf) | |
519 | val |= SPFI_CONTROL_GET_DMA; | |
520 | val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT); | |
521 | if (xfer->tx_nbits == SPI_NBITS_DUAL && | |
522 | xfer->rx_nbits == SPI_NBITS_DUAL) | |
523 | val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT; | |
524 | else if (xfer->tx_nbits == SPI_NBITS_QUAD && | |
525 | xfer->rx_nbits == SPI_NBITS_QUAD) | |
526 | val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT; | |
deba2580 | 527 | spfi_writel(spfi, val, SPFI_CONTROL); |
deba2580 AB |
528 | } |
529 | ||
530 | static int img_spfi_transfer_one(struct spi_master *master, | |
531 | struct spi_device *spi, | |
532 | struct spi_transfer *xfer) | |
533 | { | |
534 | struct img_spfi *spfi = spi_master_get_devdata(spi->master); | |
deba2580 AB |
535 | int ret; |
536 | ||
f165ed63 SN |
537 | if (xfer->len > SPFI_TRANSACTION_TSIZE_MASK) { |
538 | dev_err(spfi->dev, | |
539 | "Transfer length (%d) is greater than the max supported (%d)", | |
540 | xfer->len, SPFI_TRANSACTION_TSIZE_MASK); | |
541 | return -EINVAL; | |
542 | } | |
543 | ||
deba2580 AB |
544 | img_spfi_config(master, spi, xfer); |
545 | if (master->can_dma && master->can_dma(master, spi, xfer)) | |
546 | ret = img_spfi_start_dma(master, spi, xfer); | |
547 | else | |
548 | ret = img_spfi_start_pio(master, spi, xfer); | |
549 | ||
550 | return ret; | |
551 | } | |
552 | ||
deba2580 AB |
553 | static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi, |
554 | struct spi_transfer *xfer) | |
555 | { | |
549858ce | 556 | if (xfer->len > SPFI_32BIT_FIFO_SIZE) |
deba2580 AB |
557 | return true; |
558 | return false; | |
559 | } | |
560 | ||
561 | static irqreturn_t img_spfi_irq(int irq, void *dev_id) | |
562 | { | |
563 | struct img_spfi *spfi = (struct img_spfi *)dev_id; | |
564 | u32 status; | |
565 | ||
566 | status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); | |
567 | if (status & SPFI_INTERRUPT_IACCESS) { | |
568 | spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_CLEAR); | |
569 | dev_err(spfi->dev, "Illegal access interrupt"); | |
570 | return IRQ_HANDLED; | |
571 | } | |
572 | ||
573 | return IRQ_NONE; | |
574 | } | |
575 | ||
576 | static int img_spfi_probe(struct platform_device *pdev) | |
577 | { | |
578 | struct spi_master *master; | |
579 | struct img_spfi *spfi; | |
580 | struct resource *res; | |
581 | int ret; | |
582 | ||
583 | master = spi_alloc_master(&pdev->dev, sizeof(*spfi)); | |
584 | if (!master) | |
585 | return -ENOMEM; | |
586 | platform_set_drvdata(pdev, master); | |
587 | ||
588 | spfi = spi_master_get_devdata(master); | |
589 | spfi->dev = &pdev->dev; | |
590 | spfi->master = master; | |
591 | spin_lock_init(&spfi->lock); | |
592 | ||
593 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
594 | spfi->regs = devm_ioremap_resource(spfi->dev, res); | |
595 | if (IS_ERR(spfi->regs)) { | |
596 | ret = PTR_ERR(spfi->regs); | |
597 | goto put_spi; | |
598 | } | |
599 | spfi->phys = res->start; | |
600 | ||
601 | spfi->irq = platform_get_irq(pdev, 0); | |
602 | if (spfi->irq < 0) { | |
603 | ret = spfi->irq; | |
604 | goto put_spi; | |
605 | } | |
606 | ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq, | |
607 | IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi); | |
608 | if (ret) | |
609 | goto put_spi; | |
610 | ||
611 | spfi->sys_clk = devm_clk_get(spfi->dev, "sys"); | |
612 | if (IS_ERR(spfi->sys_clk)) { | |
613 | ret = PTR_ERR(spfi->sys_clk); | |
614 | goto put_spi; | |
615 | } | |
616 | spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi"); | |
617 | if (IS_ERR(spfi->spfi_clk)) { | |
618 | ret = PTR_ERR(spfi->spfi_clk); | |
619 | goto put_spi; | |
620 | } | |
621 | ||
622 | ret = clk_prepare_enable(spfi->sys_clk); | |
623 | if (ret) | |
624 | goto put_spi; | |
625 | ret = clk_prepare_enable(spfi->spfi_clk); | |
626 | if (ret) | |
627 | goto disable_pclk; | |
628 | ||
629 | spfi_reset(spfi); | |
630 | /* | |
631 | * Only enable the error (IACCESS) interrupt. In PIO mode we'll | |
632 | * poll the status of the FIFOs. | |
633 | */ | |
634 | spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE); | |
635 | ||
636 | master->auto_runtime_pm = true; | |
637 | master->bus_num = pdev->id; | |
638 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL; | |
639 | if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode")) | |
640 | master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD; | |
deba2580 AB |
641 | master->dev.of_node = pdev->dev.of_node; |
642 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8); | |
8543d0e7 AB |
643 | master->max_speed_hz = clk_get_rate(spfi->spfi_clk) / 4; |
644 | master->min_speed_hz = clk_get_rate(spfi->spfi_clk) / 512; | |
deba2580 | 645 | |
8c2c8c03 EG |
646 | master->setup = img_spfi_setup; |
647 | master->cleanup = img_spfi_cleanup; | |
deba2580 | 648 | master->transfer_one = img_spfi_transfer_one; |
b6fe3977 | 649 | master->prepare_message = img_spfi_prepare; |
ba33d8ac | 650 | master->unprepare_message = img_spfi_unprepare; |
824ab37d | 651 | master->handle_err = img_spfi_handle_err; |
deba2580 AB |
652 | |
653 | spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx"); | |
654 | spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx"); | |
655 | if (!spfi->tx_ch || !spfi->rx_ch) { | |
656 | if (spfi->tx_ch) | |
657 | dma_release_channel(spfi->tx_ch); | |
658 | if (spfi->rx_ch) | |
659 | dma_release_channel(spfi->rx_ch); | |
660 | dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n"); | |
661 | } else { | |
662 | master->dma_tx = spfi->tx_ch; | |
663 | master->dma_rx = spfi->rx_ch; | |
664 | master->can_dma = img_spfi_can_dma; | |
665 | } | |
666 | ||
667 | pm_runtime_set_active(spfi->dev); | |
668 | pm_runtime_enable(spfi->dev); | |
669 | ||
670 | ret = devm_spi_register_master(spfi->dev, master); | |
671 | if (ret) | |
672 | goto disable_pm; | |
673 | ||
674 | return 0; | |
675 | ||
676 | disable_pm: | |
677 | pm_runtime_disable(spfi->dev); | |
678 | if (spfi->rx_ch) | |
679 | dma_release_channel(spfi->rx_ch); | |
680 | if (spfi->tx_ch) | |
681 | dma_release_channel(spfi->tx_ch); | |
682 | clk_disable_unprepare(spfi->spfi_clk); | |
683 | disable_pclk: | |
684 | clk_disable_unprepare(spfi->sys_clk); | |
685 | put_spi: | |
686 | spi_master_put(master); | |
687 | ||
688 | return ret; | |
689 | } | |
690 | ||
691 | static int img_spfi_remove(struct platform_device *pdev) | |
692 | { | |
693 | struct spi_master *master = platform_get_drvdata(pdev); | |
694 | struct img_spfi *spfi = spi_master_get_devdata(master); | |
695 | ||
696 | if (spfi->tx_ch) | |
697 | dma_release_channel(spfi->tx_ch); | |
698 | if (spfi->rx_ch) | |
699 | dma_release_channel(spfi->rx_ch); | |
700 | ||
701 | pm_runtime_disable(spfi->dev); | |
702 | if (!pm_runtime_status_suspended(spfi->dev)) { | |
703 | clk_disable_unprepare(spfi->spfi_clk); | |
704 | clk_disable_unprepare(spfi->sys_clk); | |
705 | } | |
706 | ||
707 | spi_master_put(master); | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
47164fdb | 712 | #ifdef CONFIG_PM |
deba2580 AB |
713 | static int img_spfi_runtime_suspend(struct device *dev) |
714 | { | |
715 | struct spi_master *master = dev_get_drvdata(dev); | |
716 | struct img_spfi *spfi = spi_master_get_devdata(master); | |
717 | ||
718 | clk_disable_unprepare(spfi->spfi_clk); | |
719 | clk_disable_unprepare(spfi->sys_clk); | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
724 | static int img_spfi_runtime_resume(struct device *dev) | |
725 | { | |
726 | struct spi_master *master = dev_get_drvdata(dev); | |
727 | struct img_spfi *spfi = spi_master_get_devdata(master); | |
728 | int ret; | |
729 | ||
730 | ret = clk_prepare_enable(spfi->sys_clk); | |
731 | if (ret) | |
732 | return ret; | |
733 | ret = clk_prepare_enable(spfi->spfi_clk); | |
734 | if (ret) { | |
735 | clk_disable_unprepare(spfi->sys_clk); | |
736 | return ret; | |
737 | } | |
738 | ||
739 | return 0; | |
740 | } | |
47164fdb | 741 | #endif /* CONFIG_PM */ |
deba2580 AB |
742 | |
743 | #ifdef CONFIG_PM_SLEEP | |
744 | static int img_spfi_suspend(struct device *dev) | |
745 | { | |
746 | struct spi_master *master = dev_get_drvdata(dev); | |
747 | ||
748 | return spi_master_suspend(master); | |
749 | } | |
750 | ||
751 | static int img_spfi_resume(struct device *dev) | |
752 | { | |
753 | struct spi_master *master = dev_get_drvdata(dev); | |
754 | struct img_spfi *spfi = spi_master_get_devdata(master); | |
755 | int ret; | |
756 | ||
757 | ret = pm_runtime_get_sync(dev); | |
758 | if (ret) | |
759 | return ret; | |
760 | spfi_reset(spfi); | |
761 | pm_runtime_put(dev); | |
762 | ||
763 | return spi_master_resume(master); | |
764 | } | |
765 | #endif /* CONFIG_PM_SLEEP */ | |
766 | ||
767 | static const struct dev_pm_ops img_spfi_pm_ops = { | |
768 | SET_RUNTIME_PM_OPS(img_spfi_runtime_suspend, img_spfi_runtime_resume, | |
769 | NULL) | |
770 | SET_SYSTEM_SLEEP_PM_OPS(img_spfi_suspend, img_spfi_resume) | |
771 | }; | |
772 | ||
773 | static const struct of_device_id img_spfi_of_match[] = { | |
774 | { .compatible = "img,spfi", }, | |
775 | { }, | |
776 | }; | |
777 | MODULE_DEVICE_TABLE(of, img_spfi_of_match); | |
778 | ||
779 | static struct platform_driver img_spfi_driver = { | |
780 | .driver = { | |
781 | .name = "img-spfi", | |
782 | .pm = &img_spfi_pm_ops, | |
783 | .of_match_table = of_match_ptr(img_spfi_of_match), | |
784 | }, | |
785 | .probe = img_spfi_probe, | |
786 | .remove = img_spfi_remove, | |
787 | }; | |
788 | module_platform_driver(img_spfi_driver); | |
789 | ||
790 | MODULE_DESCRIPTION("IMG SPFI controller driver"); | |
791 | MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); | |
792 | MODULE_LICENSE("GPL v2"); |