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b5f3294f SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright (C) 2008 Juergen Beisert | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the | |
16 | * Free Software Foundation | |
17 | * 51 Franklin Street, Fifth Floor | |
18 | * Boston, MA 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/completion.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/gpio.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/platform_device.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
b5f3294f SH |
34 | #include <linux/spi/spi.h> |
35 | #include <linux/spi/spi_bitbang.h> | |
36 | #include <linux/types.h> | |
22a85e4c SG |
37 | #include <linux/of.h> |
38 | #include <linux/of_device.h> | |
39 | #include <linux/of_gpio.h> | |
dffa27e7 | 40 | #include <linux/pinctrl/consumer.h> |
b5f3294f SH |
41 | |
42 | #include <mach/spi.h> | |
43 | ||
44 | #define DRIVER_NAME "spi_imx" | |
45 | ||
46 | #define MXC_CSPIRXDATA 0x00 | |
47 | #define MXC_CSPITXDATA 0x04 | |
48 | #define MXC_CSPICTRL 0x08 | |
49 | #define MXC_CSPIINT 0x0c | |
50 | #define MXC_RESET 0x1c | |
51 | ||
52 | /* generic defines to abstract from the different register layouts */ | |
53 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | |
54 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | |
55 | ||
6cdeb002 | 56 | struct spi_imx_config { |
b5f3294f SH |
57 | unsigned int speed_hz; |
58 | unsigned int bpw; | |
59 | unsigned int mode; | |
3b2aa89e | 60 | u8 cs; |
b5f3294f SH |
61 | }; |
62 | ||
f4ba6315 | 63 | enum spi_imx_devtype { |
04ee5854 SG |
64 | IMX1_CSPI, |
65 | IMX21_CSPI, | |
66 | IMX27_CSPI, | |
67 | IMX31_CSPI, | |
68 | IMX35_CSPI, /* CSPI on all i.mx except above */ | |
69 | IMX51_ECSPI, /* ECSPI on i.mx51 and later */ | |
f4ba6315 UKK |
70 | }; |
71 | ||
72 | struct spi_imx_data; | |
73 | ||
74 | struct spi_imx_devtype_data { | |
75 | void (*intctrl)(struct spi_imx_data *, int); | |
76 | int (*config)(struct spi_imx_data *, struct spi_imx_config *); | |
77 | void (*trigger)(struct spi_imx_data *); | |
78 | int (*rx_available)(struct spi_imx_data *); | |
1723e66b | 79 | void (*reset)(struct spi_imx_data *); |
04ee5854 | 80 | enum spi_imx_devtype devtype; |
f4ba6315 UKK |
81 | }; |
82 | ||
6cdeb002 | 83 | struct spi_imx_data { |
b5f3294f SH |
84 | struct spi_bitbang bitbang; |
85 | ||
86 | struct completion xfer_done; | |
cc4d22ae | 87 | void __iomem *base; |
b5f3294f | 88 | int irq; |
aa29d840 SH |
89 | struct clk *clk_per; |
90 | struct clk *clk_ipg; | |
b5f3294f | 91 | unsigned long spi_clk; |
b5f3294f SH |
92 | |
93 | unsigned int count; | |
6cdeb002 UKK |
94 | void (*tx)(struct spi_imx_data *); |
95 | void (*rx)(struct spi_imx_data *); | |
b5f3294f SH |
96 | void *rx_buf; |
97 | const void *tx_buf; | |
98 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | |
99 | ||
edd501bb | 100 | struct spi_imx_devtype_data *devtype_data; |
c2387cb9 | 101 | int chipselect[0]; |
b5f3294f SH |
102 | }; |
103 | ||
04ee5854 SG |
104 | static inline int is_imx27_cspi(struct spi_imx_data *d) |
105 | { | |
106 | return d->devtype_data->devtype == IMX27_CSPI; | |
107 | } | |
108 | ||
109 | static inline int is_imx35_cspi(struct spi_imx_data *d) | |
110 | { | |
111 | return d->devtype_data->devtype == IMX35_CSPI; | |
112 | } | |
113 | ||
114 | static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) | |
115 | { | |
116 | return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8; | |
117 | } | |
118 | ||
b5f3294f | 119 | #define MXC_SPI_BUF_RX(type) \ |
6cdeb002 | 120 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f | 121 | { \ |
6cdeb002 | 122 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
b5f3294f | 123 | \ |
6cdeb002 UKK |
124 | if (spi_imx->rx_buf) { \ |
125 | *(type *)spi_imx->rx_buf = val; \ | |
126 | spi_imx->rx_buf += sizeof(type); \ | |
b5f3294f SH |
127 | } \ |
128 | } | |
129 | ||
130 | #define MXC_SPI_BUF_TX(type) \ | |
6cdeb002 | 131 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f SH |
132 | { \ |
133 | type val = 0; \ | |
134 | \ | |
6cdeb002 UKK |
135 | if (spi_imx->tx_buf) { \ |
136 | val = *(type *)spi_imx->tx_buf; \ | |
137 | spi_imx->tx_buf += sizeof(type); \ | |
b5f3294f SH |
138 | } \ |
139 | \ | |
6cdeb002 | 140 | spi_imx->count -= sizeof(type); \ |
b5f3294f | 141 | \ |
6cdeb002 | 142 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
b5f3294f SH |
143 | } |
144 | ||
145 | MXC_SPI_BUF_RX(u8) | |
146 | MXC_SPI_BUF_TX(u8) | |
147 | MXC_SPI_BUF_RX(u16) | |
148 | MXC_SPI_BUF_TX(u16) | |
149 | MXC_SPI_BUF_RX(u32) | |
150 | MXC_SPI_BUF_TX(u32) | |
151 | ||
152 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set | |
153 | * (which is currently not the case in this driver) | |
154 | */ | |
155 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |
156 | 256, 384, 512, 768, 1024}; | |
157 | ||
158 | /* MX21, MX27 */ | |
6cdeb002 | 159 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
04ee5854 | 160 | unsigned int fspi, unsigned int max) |
b5f3294f | 161 | { |
04ee5854 | 162 | int i; |
b5f3294f SH |
163 | |
164 | for (i = 2; i < max; i++) | |
165 | if (fspi * mxc_clkdivs[i] >= fin) | |
166 | return i; | |
167 | ||
168 | return max; | |
169 | } | |
170 | ||
0b599603 | 171 | /* MX1, MX31, MX35, MX51 CSPI */ |
6cdeb002 | 172 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
b5f3294f SH |
173 | unsigned int fspi) |
174 | { | |
175 | int i, div = 4; | |
176 | ||
177 | for (i = 0; i < 7; i++) { | |
178 | if (fspi * div >= fin) | |
179 | return i; | |
180 | div <<= 1; | |
181 | } | |
182 | ||
183 | return 7; | |
184 | } | |
185 | ||
66de757c SG |
186 | #define MX51_ECSPI_CTRL 0x08 |
187 | #define MX51_ECSPI_CTRL_ENABLE (1 << 0) | |
188 | #define MX51_ECSPI_CTRL_XCH (1 << 2) | |
189 | #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) | |
190 | #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 | |
191 | #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 | |
192 | #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) | |
193 | #define MX51_ECSPI_CTRL_BL_OFFSET 20 | |
194 | ||
195 | #define MX51_ECSPI_CONFIG 0x0c | |
196 | #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) | |
197 | #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) | |
198 | #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) | |
199 | #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) | |
200 | ||
201 | #define MX51_ECSPI_INT 0x10 | |
202 | #define MX51_ECSPI_INT_TEEN (1 << 0) | |
203 | #define MX51_ECSPI_INT_RREN (1 << 3) | |
204 | ||
205 | #define MX51_ECSPI_STAT 0x18 | |
206 | #define MX51_ECSPI_STAT_RR (1 << 3) | |
0b599603 UKK |
207 | |
208 | /* MX51 eCSPI */ | |
66de757c | 209 | static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi) |
0b599603 UKK |
210 | { |
211 | /* | |
212 | * there are two 4-bit dividers, the pre-divider divides by | |
213 | * $pre, the post-divider by 2^$post | |
214 | */ | |
215 | unsigned int pre, post; | |
216 | ||
217 | if (unlikely(fspi > fin)) | |
218 | return 0; | |
219 | ||
220 | post = fls(fin) - fls(fspi); | |
221 | if (fin > fspi << post) | |
222 | post++; | |
223 | ||
224 | /* now we have: (fin <= fspi << post) with post being minimal */ | |
225 | ||
226 | post = max(4U, post) - 4; | |
227 | if (unlikely(post > 0xf)) { | |
228 | pr_err("%s: cannot set clock freq: %u (base freq: %u)\n", | |
229 | __func__, fspi, fin); | |
230 | return 0xff; | |
231 | } | |
232 | ||
233 | pre = DIV_ROUND_UP(fin, fspi << post) - 1; | |
234 | ||
235 | pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n", | |
236 | __func__, fin, fspi, post, pre); | |
66de757c SG |
237 | return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | |
238 | (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); | |
0b599603 UKK |
239 | } |
240 | ||
66de757c | 241 | static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) |
0b599603 UKK |
242 | { |
243 | unsigned val = 0; | |
244 | ||
245 | if (enable & MXC_INT_TE) | |
66de757c | 246 | val |= MX51_ECSPI_INT_TEEN; |
0b599603 UKK |
247 | |
248 | if (enable & MXC_INT_RR) | |
66de757c | 249 | val |= MX51_ECSPI_INT_RREN; |
0b599603 | 250 | |
66de757c | 251 | writel(val, spi_imx->base + MX51_ECSPI_INT); |
0b599603 UKK |
252 | } |
253 | ||
66de757c | 254 | static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) |
0b599603 UKK |
255 | { |
256 | u32 reg; | |
257 | ||
66de757c SG |
258 | reg = readl(spi_imx->base + MX51_ECSPI_CTRL); |
259 | reg |= MX51_ECSPI_CTRL_XCH; | |
260 | writel(reg, spi_imx->base + MX51_ECSPI_CTRL); | |
0b599603 UKK |
261 | } |
262 | ||
66de757c | 263 | static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, |
0b599603 UKK |
264 | struct spi_imx_config *config) |
265 | { | |
66de757c | 266 | u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0; |
0b599603 | 267 | |
f020c39e SH |
268 | /* |
269 | * The hardware seems to have a race condition when changing modes. The | |
270 | * current assumption is that the selection of the channel arrives | |
271 | * earlier in the hardware than the mode bits when they are written at | |
272 | * the same time. | |
273 | * So set master mode for all channels as we do not support slave mode. | |
274 | */ | |
66de757c | 275 | ctrl |= MX51_ECSPI_CTRL_MODE_MASK; |
0b599603 UKK |
276 | |
277 | /* set clock speed */ | |
66de757c | 278 | ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz); |
0b599603 UKK |
279 | |
280 | /* set chip select to use */ | |
66de757c | 281 | ctrl |= MX51_ECSPI_CTRL_CS(config->cs); |
0b599603 | 282 | |
66de757c | 283 | ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; |
0b599603 | 284 | |
66de757c | 285 | cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); |
0b599603 UKK |
286 | |
287 | if (config->mode & SPI_CPHA) | |
66de757c | 288 | cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); |
0b599603 UKK |
289 | |
290 | if (config->mode & SPI_CPOL) | |
66de757c | 291 | cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); |
0b599603 UKK |
292 | |
293 | if (config->mode & SPI_CS_HIGH) | |
66de757c | 294 | cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); |
0b599603 | 295 | |
66de757c SG |
296 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); |
297 | writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); | |
0b599603 UKK |
298 | |
299 | return 0; | |
300 | } | |
301 | ||
66de757c | 302 | static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) |
0b599603 | 303 | { |
66de757c | 304 | return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; |
0b599603 UKK |
305 | } |
306 | ||
66de757c | 307 | static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) |
0b599603 UKK |
308 | { |
309 | /* drain receive buffer */ | |
66de757c | 310 | while (mx51_ecspi_rx_available(spi_imx)) |
0b599603 UKK |
311 | readl(spi_imx->base + MXC_CSPIRXDATA); |
312 | } | |
313 | ||
b5f3294f SH |
314 | #define MX31_INTREG_TEEN (1 << 0) |
315 | #define MX31_INTREG_RREN (1 << 3) | |
316 | ||
317 | #define MX31_CSPICTRL_ENABLE (1 << 0) | |
318 | #define MX31_CSPICTRL_MASTER (1 << 1) | |
319 | #define MX31_CSPICTRL_XCH (1 << 2) | |
320 | #define MX31_CSPICTRL_POL (1 << 4) | |
321 | #define MX31_CSPICTRL_PHA (1 << 5) | |
322 | #define MX31_CSPICTRL_SSCTL (1 << 6) | |
323 | #define MX31_CSPICTRL_SSPOL (1 << 7) | |
324 | #define MX31_CSPICTRL_BC_SHIFT 8 | |
325 | #define MX35_CSPICTRL_BL_SHIFT 20 | |
326 | #define MX31_CSPICTRL_CS_SHIFT 24 | |
327 | #define MX35_CSPICTRL_CS_SHIFT 12 | |
328 | #define MX31_CSPICTRL_DR_SHIFT 16 | |
329 | ||
330 | #define MX31_CSPISTATUS 0x14 | |
331 | #define MX31_STATUS_RR (1 << 3) | |
332 | ||
333 | /* These functions also work for the i.MX35, but be aware that | |
334 | * the i.MX35 has a slightly different register layout for bits | |
335 | * we do not use here. | |
336 | */ | |
f4ba6315 | 337 | static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
338 | { |
339 | unsigned int val = 0; | |
340 | ||
341 | if (enable & MXC_INT_TE) | |
342 | val |= MX31_INTREG_TEEN; | |
343 | if (enable & MXC_INT_RR) | |
344 | val |= MX31_INTREG_RREN; | |
345 | ||
6cdeb002 | 346 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
347 | } |
348 | ||
f4ba6315 | 349 | static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
350 | { |
351 | unsigned int reg; | |
352 | ||
6cdeb002 | 353 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 354 | reg |= MX31_CSPICTRL_XCH; |
6cdeb002 | 355 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
356 | } |
357 | ||
2a64a90a | 358 | static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, |
1723e66b UKK |
359 | struct spi_imx_config *config) |
360 | { | |
361 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; | |
3b2aa89e | 362 | int cs = spi_imx->chipselect[config->cs]; |
1723e66b UKK |
363 | |
364 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << | |
365 | MX31_CSPICTRL_DR_SHIFT; | |
366 | ||
04ee5854 | 367 | if (is_imx35_cspi(spi_imx)) { |
2a64a90a SG |
368 | reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; |
369 | reg |= MX31_CSPICTRL_SSCTL; | |
370 | } else { | |
371 | reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; | |
372 | } | |
1723e66b UKK |
373 | |
374 | if (config->mode & SPI_CPHA) | |
375 | reg |= MX31_CSPICTRL_PHA; | |
376 | if (config->mode & SPI_CPOL) | |
377 | reg |= MX31_CSPICTRL_POL; | |
378 | if (config->mode & SPI_CS_HIGH) | |
379 | reg |= MX31_CSPICTRL_SSPOL; | |
3b2aa89e | 380 | if (cs < 0) |
2a64a90a | 381 | reg |= (cs + 32) << |
04ee5854 SG |
382 | (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : |
383 | MX31_CSPICTRL_CS_SHIFT); | |
1723e66b UKK |
384 | |
385 | writel(reg, spi_imx->base + MXC_CSPICTRL); | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
f4ba6315 | 390 | static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 391 | { |
6cdeb002 | 392 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
b5f3294f SH |
393 | } |
394 | ||
2a64a90a | 395 | static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
396 | { |
397 | /* drain receive buffer */ | |
2a64a90a | 398 | while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) |
1723e66b UKK |
399 | readl(spi_imx->base + MXC_CSPIRXDATA); |
400 | } | |
401 | ||
3451fb15 SG |
402 | #define MX21_INTREG_RR (1 << 4) |
403 | #define MX21_INTREG_TEEN (1 << 9) | |
404 | #define MX21_INTREG_RREN (1 << 13) | |
405 | ||
406 | #define MX21_CSPICTRL_POL (1 << 5) | |
407 | #define MX21_CSPICTRL_PHA (1 << 6) | |
408 | #define MX21_CSPICTRL_SSPOL (1 << 8) | |
409 | #define MX21_CSPICTRL_XCH (1 << 9) | |
410 | #define MX21_CSPICTRL_ENABLE (1 << 10) | |
411 | #define MX21_CSPICTRL_MASTER (1 << 11) | |
412 | #define MX21_CSPICTRL_DR_SHIFT 14 | |
413 | #define MX21_CSPICTRL_CS_SHIFT 19 | |
414 | ||
415 | static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable) | |
b5f3294f SH |
416 | { |
417 | unsigned int val = 0; | |
418 | ||
419 | if (enable & MXC_INT_TE) | |
3451fb15 | 420 | val |= MX21_INTREG_TEEN; |
b5f3294f | 421 | if (enable & MXC_INT_RR) |
3451fb15 | 422 | val |= MX21_INTREG_RREN; |
b5f3294f | 423 | |
6cdeb002 | 424 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
425 | } |
426 | ||
3451fb15 | 427 | static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
428 | { |
429 | unsigned int reg; | |
430 | ||
6cdeb002 | 431 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
3451fb15 | 432 | reg |= MX21_CSPICTRL_XCH; |
6cdeb002 | 433 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
434 | } |
435 | ||
3451fb15 | 436 | static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx, |
6cdeb002 | 437 | struct spi_imx_config *config) |
b5f3294f | 438 | { |
3451fb15 | 439 | unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; |
3b2aa89e | 440 | int cs = spi_imx->chipselect[config->cs]; |
04ee5854 | 441 | unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; |
b5f3294f | 442 | |
04ee5854 | 443 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) << |
3451fb15 | 444 | MX21_CSPICTRL_DR_SHIFT; |
b5f3294f SH |
445 | reg |= config->bpw - 1; |
446 | ||
447 | if (config->mode & SPI_CPHA) | |
3451fb15 | 448 | reg |= MX21_CSPICTRL_PHA; |
b5f3294f | 449 | if (config->mode & SPI_CPOL) |
3451fb15 | 450 | reg |= MX21_CSPICTRL_POL; |
b5f3294f | 451 | if (config->mode & SPI_CS_HIGH) |
3451fb15 | 452 | reg |= MX21_CSPICTRL_SSPOL; |
3b2aa89e | 453 | if (cs < 0) |
3451fb15 | 454 | reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; |
b5f3294f | 455 | |
6cdeb002 | 456 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
457 | |
458 | return 0; | |
459 | } | |
460 | ||
3451fb15 | 461 | static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 462 | { |
3451fb15 | 463 | return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; |
b5f3294f SH |
464 | } |
465 | ||
3451fb15 | 466 | static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
467 | { |
468 | writel(1, spi_imx->base + MXC_RESET); | |
469 | } | |
470 | ||
b5f3294f SH |
471 | #define MX1_INTREG_RR (1 << 3) |
472 | #define MX1_INTREG_TEEN (1 << 8) | |
473 | #define MX1_INTREG_RREN (1 << 11) | |
474 | ||
475 | #define MX1_CSPICTRL_POL (1 << 4) | |
476 | #define MX1_CSPICTRL_PHA (1 << 5) | |
477 | #define MX1_CSPICTRL_XCH (1 << 8) | |
478 | #define MX1_CSPICTRL_ENABLE (1 << 9) | |
479 | #define MX1_CSPICTRL_MASTER (1 << 10) | |
480 | #define MX1_CSPICTRL_DR_SHIFT 13 | |
481 | ||
f4ba6315 | 482 | static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
483 | { |
484 | unsigned int val = 0; | |
485 | ||
486 | if (enable & MXC_INT_TE) | |
487 | val |= MX1_INTREG_TEEN; | |
488 | if (enable & MXC_INT_RR) | |
489 | val |= MX1_INTREG_RREN; | |
490 | ||
6cdeb002 | 491 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
492 | } |
493 | ||
f4ba6315 | 494 | static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
495 | { |
496 | unsigned int reg; | |
497 | ||
6cdeb002 | 498 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 499 | reg |= MX1_CSPICTRL_XCH; |
6cdeb002 | 500 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
501 | } |
502 | ||
f4ba6315 | 503 | static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, |
6cdeb002 | 504 | struct spi_imx_config *config) |
b5f3294f SH |
505 | { |
506 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; | |
507 | ||
6cdeb002 | 508 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
b5f3294f SH |
509 | MX1_CSPICTRL_DR_SHIFT; |
510 | reg |= config->bpw - 1; | |
511 | ||
512 | if (config->mode & SPI_CPHA) | |
513 | reg |= MX1_CSPICTRL_PHA; | |
514 | if (config->mode & SPI_CPOL) | |
515 | reg |= MX1_CSPICTRL_POL; | |
516 | ||
6cdeb002 | 517 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
518 | |
519 | return 0; | |
520 | } | |
521 | ||
f4ba6315 | 522 | static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 523 | { |
6cdeb002 | 524 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
b5f3294f SH |
525 | } |
526 | ||
1723e66b UKK |
527 | static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) |
528 | { | |
529 | writel(1, spi_imx->base + MXC_RESET); | |
530 | } | |
531 | ||
04ee5854 SG |
532 | static struct spi_imx_devtype_data imx1_cspi_devtype_data = { |
533 | .intctrl = mx1_intctrl, | |
534 | .config = mx1_config, | |
535 | .trigger = mx1_trigger, | |
536 | .rx_available = mx1_rx_available, | |
537 | .reset = mx1_reset, | |
538 | .devtype = IMX1_CSPI, | |
539 | }; | |
540 | ||
541 | static struct spi_imx_devtype_data imx21_cspi_devtype_data = { | |
542 | .intctrl = mx21_intctrl, | |
543 | .config = mx21_config, | |
544 | .trigger = mx21_trigger, | |
545 | .rx_available = mx21_rx_available, | |
546 | .reset = mx21_reset, | |
547 | .devtype = IMX21_CSPI, | |
548 | }; | |
549 | ||
550 | static struct spi_imx_devtype_data imx27_cspi_devtype_data = { | |
551 | /* i.mx27 cspi shares the functions with i.mx21 one */ | |
552 | .intctrl = mx21_intctrl, | |
553 | .config = mx21_config, | |
554 | .trigger = mx21_trigger, | |
555 | .rx_available = mx21_rx_available, | |
556 | .reset = mx21_reset, | |
557 | .devtype = IMX27_CSPI, | |
558 | }; | |
559 | ||
560 | static struct spi_imx_devtype_data imx31_cspi_devtype_data = { | |
561 | .intctrl = mx31_intctrl, | |
562 | .config = mx31_config, | |
563 | .trigger = mx31_trigger, | |
564 | .rx_available = mx31_rx_available, | |
565 | .reset = mx31_reset, | |
566 | .devtype = IMX31_CSPI, | |
567 | }; | |
568 | ||
569 | static struct spi_imx_devtype_data imx35_cspi_devtype_data = { | |
570 | /* i.mx35 and later cspi shares the functions with i.mx31 one */ | |
571 | .intctrl = mx31_intctrl, | |
572 | .config = mx31_config, | |
573 | .trigger = mx31_trigger, | |
574 | .rx_available = mx31_rx_available, | |
575 | .reset = mx31_reset, | |
576 | .devtype = IMX35_CSPI, | |
577 | }; | |
578 | ||
579 | static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { | |
580 | .intctrl = mx51_ecspi_intctrl, | |
581 | .config = mx51_ecspi_config, | |
582 | .trigger = mx51_ecspi_trigger, | |
583 | .rx_available = mx51_ecspi_rx_available, | |
584 | .reset = mx51_ecspi_reset, | |
585 | .devtype = IMX51_ECSPI, | |
586 | }; | |
587 | ||
588 | static struct platform_device_id spi_imx_devtype[] = { | |
589 | { | |
590 | .name = "imx1-cspi", | |
591 | .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, | |
592 | }, { | |
593 | .name = "imx21-cspi", | |
594 | .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, | |
595 | }, { | |
596 | .name = "imx27-cspi", | |
597 | .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, | |
598 | }, { | |
599 | .name = "imx31-cspi", | |
600 | .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, | |
601 | }, { | |
602 | .name = "imx35-cspi", | |
603 | .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, | |
604 | }, { | |
605 | .name = "imx51-ecspi", | |
606 | .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, | |
607 | }, { | |
608 | /* sentinel */ | |
609 | } | |
f4ba6315 UKK |
610 | }; |
611 | ||
22a85e4c SG |
612 | static const struct of_device_id spi_imx_dt_ids[] = { |
613 | { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, | |
614 | { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, | |
615 | { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, | |
616 | { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, | |
617 | { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, | |
618 | { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, | |
619 | { /* sentinel */ } | |
620 | }; | |
621 | ||
6cdeb002 | 622 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
b5f3294f | 623 | { |
6cdeb002 | 624 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
6cdeb002 | 625 | int gpio = spi_imx->chipselect[spi->chip_select]; |
e6a0a8bf UKK |
626 | int active = is_active != BITBANG_CS_INACTIVE; |
627 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); | |
b5f3294f | 628 | |
8b17e055 | 629 | if (!gpio_is_valid(gpio)) |
b5f3294f | 630 | return; |
b5f3294f | 631 | |
e6a0a8bf | 632 | gpio_set_value(gpio, dev_is_lowactive ^ active); |
b5f3294f SH |
633 | } |
634 | ||
6cdeb002 | 635 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
b5f3294f | 636 | { |
04ee5854 | 637 | while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { |
6cdeb002 | 638 | if (!spi_imx->count) |
b5f3294f | 639 | break; |
6cdeb002 UKK |
640 | spi_imx->tx(spi_imx); |
641 | spi_imx->txfifo++; | |
b5f3294f SH |
642 | } |
643 | ||
edd501bb | 644 | spi_imx->devtype_data->trigger(spi_imx); |
b5f3294f SH |
645 | } |
646 | ||
6cdeb002 | 647 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
b5f3294f | 648 | { |
6cdeb002 | 649 | struct spi_imx_data *spi_imx = dev_id; |
b5f3294f | 650 | |
edd501bb | 651 | while (spi_imx->devtype_data->rx_available(spi_imx)) { |
6cdeb002 UKK |
652 | spi_imx->rx(spi_imx); |
653 | spi_imx->txfifo--; | |
b5f3294f SH |
654 | } |
655 | ||
6cdeb002 UKK |
656 | if (spi_imx->count) { |
657 | spi_imx_push(spi_imx); | |
b5f3294f SH |
658 | return IRQ_HANDLED; |
659 | } | |
660 | ||
6cdeb002 | 661 | if (spi_imx->txfifo) { |
b5f3294f SH |
662 | /* No data left to push, but still waiting for rx data, |
663 | * enable receive data available interrupt. | |
664 | */ | |
edd501bb | 665 | spi_imx->devtype_data->intctrl( |
f4ba6315 | 666 | spi_imx, MXC_INT_RR); |
b5f3294f SH |
667 | return IRQ_HANDLED; |
668 | } | |
669 | ||
edd501bb | 670 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
6cdeb002 | 671 | complete(&spi_imx->xfer_done); |
b5f3294f SH |
672 | |
673 | return IRQ_HANDLED; | |
674 | } | |
675 | ||
6cdeb002 | 676 | static int spi_imx_setupxfer(struct spi_device *spi, |
b5f3294f SH |
677 | struct spi_transfer *t) |
678 | { | |
6cdeb002 UKK |
679 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
680 | struct spi_imx_config config; | |
b5f3294f SH |
681 | |
682 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; | |
683 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; | |
684 | config.mode = spi->mode; | |
3b2aa89e | 685 | config.cs = spi->chip_select; |
b5f3294f | 686 | |
462d26b5 SH |
687 | if (!config.speed_hz) |
688 | config.speed_hz = spi->max_speed_hz; | |
689 | if (!config.bpw) | |
690 | config.bpw = spi->bits_per_word; | |
462d26b5 | 691 | |
e6a0a8bf UKK |
692 | /* Initialize the functions for transfer */ |
693 | if (config.bpw <= 8) { | |
694 | spi_imx->rx = spi_imx_buf_rx_u8; | |
695 | spi_imx->tx = spi_imx_buf_tx_u8; | |
696 | } else if (config.bpw <= 16) { | |
697 | spi_imx->rx = spi_imx_buf_rx_u16; | |
698 | spi_imx->tx = spi_imx_buf_tx_u16; | |
699 | } else if (config.bpw <= 32) { | |
700 | spi_imx->rx = spi_imx_buf_rx_u32; | |
701 | spi_imx->tx = spi_imx_buf_tx_u32; | |
702 | } else | |
703 | BUG(); | |
704 | ||
edd501bb | 705 | spi_imx->devtype_data->config(spi_imx, &config); |
b5f3294f SH |
706 | |
707 | return 0; | |
708 | } | |
709 | ||
6cdeb002 | 710 | static int spi_imx_transfer(struct spi_device *spi, |
b5f3294f SH |
711 | struct spi_transfer *transfer) |
712 | { | |
6cdeb002 | 713 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
b5f3294f | 714 | |
6cdeb002 UKK |
715 | spi_imx->tx_buf = transfer->tx_buf; |
716 | spi_imx->rx_buf = transfer->rx_buf; | |
717 | spi_imx->count = transfer->len; | |
718 | spi_imx->txfifo = 0; | |
b5f3294f | 719 | |
6cdeb002 | 720 | init_completion(&spi_imx->xfer_done); |
b5f3294f | 721 | |
6cdeb002 | 722 | spi_imx_push(spi_imx); |
b5f3294f | 723 | |
edd501bb | 724 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); |
b5f3294f | 725 | |
6cdeb002 | 726 | wait_for_completion(&spi_imx->xfer_done); |
b5f3294f SH |
727 | |
728 | return transfer->len; | |
729 | } | |
730 | ||
6cdeb002 | 731 | static int spi_imx_setup(struct spi_device *spi) |
b5f3294f | 732 | { |
6c23e5d4 SH |
733 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
734 | int gpio = spi_imx->chipselect[spi->chip_select]; | |
735 | ||
f4d4ecfe | 736 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
b5f3294f SH |
737 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
738 | ||
8b17e055 | 739 | if (gpio_is_valid(gpio)) |
6c23e5d4 SH |
740 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); |
741 | ||
6cdeb002 | 742 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
b5f3294f SH |
743 | |
744 | return 0; | |
745 | } | |
746 | ||
6cdeb002 | 747 | static void spi_imx_cleanup(struct spi_device *spi) |
b5f3294f SH |
748 | { |
749 | } | |
750 | ||
965346e3 | 751 | static int __devinit spi_imx_probe(struct platform_device *pdev) |
b5f3294f | 752 | { |
22a85e4c SG |
753 | struct device_node *np = pdev->dev.of_node; |
754 | const struct of_device_id *of_id = | |
755 | of_match_device(spi_imx_dt_ids, &pdev->dev); | |
756 | struct spi_imx_master *mxc_platform_info = | |
757 | dev_get_platdata(&pdev->dev); | |
b5f3294f | 758 | struct spi_master *master; |
6cdeb002 | 759 | struct spi_imx_data *spi_imx; |
b5f3294f | 760 | struct resource *res; |
dffa27e7 | 761 | struct pinctrl *pinctrl; |
c2387cb9 | 762 | int i, ret, num_cs; |
b5f3294f | 763 | |
22a85e4c | 764 | if (!np && !mxc_platform_info) { |
b5f3294f SH |
765 | dev_err(&pdev->dev, "can't get the platform data\n"); |
766 | return -EINVAL; | |
767 | } | |
768 | ||
22a85e4c | 769 | ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); |
39ec0d38 LW |
770 | if (ret < 0) { |
771 | if (mxc_platform_info) | |
772 | num_cs = mxc_platform_info->num_chipselect; | |
773 | else | |
774 | return ret; | |
775 | } | |
22a85e4c | 776 | |
c2387cb9 SG |
777 | master = spi_alloc_master(&pdev->dev, |
778 | sizeof(struct spi_imx_data) + sizeof(int) * num_cs); | |
b5f3294f SH |
779 | if (!master) |
780 | return -ENOMEM; | |
781 | ||
782 | platform_set_drvdata(pdev, master); | |
783 | ||
784 | master->bus_num = pdev->id; | |
c2387cb9 | 785 | master->num_chipselect = num_cs; |
b5f3294f | 786 | |
6cdeb002 UKK |
787 | spi_imx = spi_master_get_devdata(master); |
788 | spi_imx->bitbang.master = spi_master_get(master); | |
b5f3294f SH |
789 | |
790 | for (i = 0; i < master->num_chipselect; i++) { | |
22a85e4c | 791 | int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); |
8b17e055 | 792 | if (!gpio_is_valid(cs_gpio) && mxc_platform_info) |
22a85e4c | 793 | cs_gpio = mxc_platform_info->chipselect[i]; |
4cc122ac FE |
794 | |
795 | spi_imx->chipselect[i] = cs_gpio; | |
8b17e055 | 796 | if (!gpio_is_valid(cs_gpio)) |
b5f3294f | 797 | continue; |
4cc122ac | 798 | |
6cdeb002 | 799 | ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME); |
b5f3294f | 800 | if (ret) { |
bbd050af | 801 | dev_err(&pdev->dev, "can't get cs gpios\n"); |
00ffc13f | 802 | goto out_gpio_free; |
b5f3294f | 803 | } |
b5f3294f SH |
804 | } |
805 | ||
6cdeb002 UKK |
806 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
807 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; | |
808 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; | |
809 | spi_imx->bitbang.master->setup = spi_imx_setup; | |
810 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; | |
3910f2cf | 811 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
b5f3294f | 812 | |
6cdeb002 | 813 | init_completion(&spi_imx->xfer_done); |
b5f3294f | 814 | |
22a85e4c | 815 | spi_imx->devtype_data = of_id ? of_id->data : |
04ee5854 | 816 | (struct spi_imx_devtype_data *) pdev->id_entry->driver_data; |
f4ba6315 | 817 | |
b5f3294f SH |
818 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
819 | if (!res) { | |
820 | dev_err(&pdev->dev, "can't get platform resource\n"); | |
821 | ret = -ENOMEM; | |
822 | goto out_gpio_free; | |
823 | } | |
824 | ||
825 | if (!request_mem_region(res->start, resource_size(res), pdev->name)) { | |
826 | dev_err(&pdev->dev, "request_mem_region failed\n"); | |
827 | ret = -EBUSY; | |
828 | goto out_gpio_free; | |
829 | } | |
830 | ||
6cdeb002 UKK |
831 | spi_imx->base = ioremap(res->start, resource_size(res)); |
832 | if (!spi_imx->base) { | |
b5f3294f SH |
833 | ret = -EINVAL; |
834 | goto out_release_mem; | |
835 | } | |
836 | ||
6cdeb002 | 837 | spi_imx->irq = platform_get_irq(pdev, 0); |
73575938 | 838 | if (spi_imx->irq < 0) { |
b5f3294f SH |
839 | ret = -EINVAL; |
840 | goto out_iounmap; | |
841 | } | |
842 | ||
6cdeb002 | 843 | ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx); |
b5f3294f | 844 | if (ret) { |
6cdeb002 | 845 | dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); |
b5f3294f SH |
846 | goto out_iounmap; |
847 | } | |
848 | ||
dffa27e7 SG |
849 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
850 | if (IS_ERR(pinctrl)) { | |
851 | ret = PTR_ERR(pinctrl); | |
852 | goto out_free_irq; | |
853 | } | |
854 | ||
aa29d840 SH |
855 | spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
856 | if (IS_ERR(spi_imx->clk_ipg)) { | |
857 | ret = PTR_ERR(spi_imx->clk_ipg); | |
b5f3294f SH |
858 | goto out_free_irq; |
859 | } | |
860 | ||
aa29d840 SH |
861 | spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); |
862 | if (IS_ERR(spi_imx->clk_per)) { | |
863 | ret = PTR_ERR(spi_imx->clk_per); | |
864 | goto out_free_irq; | |
865 | } | |
866 | ||
867 | clk_prepare_enable(spi_imx->clk_per); | |
868 | clk_prepare_enable(spi_imx->clk_ipg); | |
869 | ||
870 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); | |
b5f3294f | 871 | |
edd501bb | 872 | spi_imx->devtype_data->reset(spi_imx); |
ce1807b2 | 873 | |
edd501bb | 874 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
b5f3294f | 875 | |
22a85e4c | 876 | master->dev.of_node = pdev->dev.of_node; |
6cdeb002 | 877 | ret = spi_bitbang_start(&spi_imx->bitbang); |
b5f3294f SH |
878 | if (ret) { |
879 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); | |
880 | goto out_clk_put; | |
881 | } | |
882 | ||
883 | dev_info(&pdev->dev, "probed\n"); | |
884 | ||
885 | return ret; | |
886 | ||
887 | out_clk_put: | |
aa29d840 SH |
888 | clk_disable_unprepare(spi_imx->clk_per); |
889 | clk_disable_unprepare(spi_imx->clk_ipg); | |
b5f3294f | 890 | out_free_irq: |
6cdeb002 | 891 | free_irq(spi_imx->irq, spi_imx); |
b5f3294f | 892 | out_iounmap: |
6cdeb002 | 893 | iounmap(spi_imx->base); |
b5f3294f SH |
894 | out_release_mem: |
895 | release_mem_region(res->start, resource_size(res)); | |
896 | out_gpio_free: | |
00ffc13f | 897 | while (--i >= 0) { |
8b17e055 | 898 | if (gpio_is_valid(spi_imx->chipselect[i])) |
6cdeb002 | 899 | gpio_free(spi_imx->chipselect[i]); |
00ffc13f | 900 | } |
b5f3294f SH |
901 | spi_master_put(master); |
902 | kfree(master); | |
903 | platform_set_drvdata(pdev, NULL); | |
904 | return ret; | |
905 | } | |
906 | ||
965346e3 | 907 | static int __devexit spi_imx_remove(struct platform_device *pdev) |
b5f3294f SH |
908 | { |
909 | struct spi_master *master = platform_get_drvdata(pdev); | |
910 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6cdeb002 | 911 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
b5f3294f SH |
912 | int i; |
913 | ||
6cdeb002 | 914 | spi_bitbang_stop(&spi_imx->bitbang); |
b5f3294f | 915 | |
6cdeb002 | 916 | writel(0, spi_imx->base + MXC_CSPICTRL); |
aa29d840 SH |
917 | clk_disable_unprepare(spi_imx->clk_per); |
918 | clk_disable_unprepare(spi_imx->clk_ipg); | |
6cdeb002 UKK |
919 | free_irq(spi_imx->irq, spi_imx); |
920 | iounmap(spi_imx->base); | |
b5f3294f SH |
921 | |
922 | for (i = 0; i < master->num_chipselect; i++) | |
8b17e055 | 923 | if (gpio_is_valid(spi_imx->chipselect[i])) |
6cdeb002 | 924 | gpio_free(spi_imx->chipselect[i]); |
b5f3294f SH |
925 | |
926 | spi_master_put(master); | |
927 | ||
928 | release_mem_region(res->start, resource_size(res)); | |
929 | ||
930 | platform_set_drvdata(pdev, NULL); | |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
6cdeb002 | 935 | static struct platform_driver spi_imx_driver = { |
b5f3294f SH |
936 | .driver = { |
937 | .name = DRIVER_NAME, | |
938 | .owner = THIS_MODULE, | |
22a85e4c | 939 | .of_match_table = spi_imx_dt_ids, |
b5f3294f | 940 | }, |
f4ba6315 | 941 | .id_table = spi_imx_devtype, |
6cdeb002 | 942 | .probe = spi_imx_probe, |
965346e3 | 943 | .remove = __devexit_p(spi_imx_remove), |
b5f3294f | 944 | }; |
940ab889 | 945 | module_platform_driver(spi_imx_driver); |
b5f3294f SH |
946 | |
947 | MODULE_DESCRIPTION("SPI Master Controller driver"); | |
948 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
949 | MODULE_LICENSE("GPL"); |