]>
Commit | Line | Data |
---|---|---|
b5f3294f SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright (C) 2008 Juergen Beisert | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the | |
16 | * Free Software Foundation | |
17 | * 51 Franklin Street, Fifth Floor | |
18 | * Boston, MA 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/completion.h> | |
23 | #include <linux/delay.h> | |
f62caccd RG |
24 | #include <linux/dmaengine.h> |
25 | #include <linux/dma-mapping.h> | |
b5f3294f SH |
26 | #include <linux/err.h> |
27 | #include <linux/gpio.h> | |
b5f3294f SH |
28 | #include <linux/interrupt.h> |
29 | #include <linux/io.h> | |
30 | #include <linux/irq.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/platform_device.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
b5f3294f SH |
35 | #include <linux/spi/spi.h> |
36 | #include <linux/spi/spi_bitbang.h> | |
37 | #include <linux/types.h> | |
22a85e4c SG |
38 | #include <linux/of.h> |
39 | #include <linux/of_device.h> | |
40 | #include <linux/of_gpio.h> | |
b5f3294f | 41 | |
f62caccd | 42 | #include <linux/platform_data/dma-imx.h> |
82906b13 | 43 | #include <linux/platform_data/spi-imx.h> |
b5f3294f SH |
44 | |
45 | #define DRIVER_NAME "spi_imx" | |
46 | ||
47 | #define MXC_CSPIRXDATA 0x00 | |
48 | #define MXC_CSPITXDATA 0x04 | |
49 | #define MXC_CSPICTRL 0x08 | |
50 | #define MXC_CSPIINT 0x0c | |
51 | #define MXC_RESET 0x1c | |
52 | ||
53 | /* generic defines to abstract from the different register layouts */ | |
54 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | |
55 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | |
56 | ||
f62caccd RG |
57 | /* The maximum bytes that a sdma BD can transfer.*/ |
58 | #define MAX_SDMA_BD_BYTES (1 << 15) | |
6cdeb002 | 59 | struct spi_imx_config { |
b5f3294f SH |
60 | unsigned int speed_hz; |
61 | unsigned int bpw; | |
b5f3294f SH |
62 | }; |
63 | ||
f4ba6315 | 64 | enum spi_imx_devtype { |
04ee5854 SG |
65 | IMX1_CSPI, |
66 | IMX21_CSPI, | |
67 | IMX27_CSPI, | |
68 | IMX31_CSPI, | |
69 | IMX35_CSPI, /* CSPI on all i.mx except above */ | |
70 | IMX51_ECSPI, /* ECSPI on i.mx51 and later */ | |
f4ba6315 UKK |
71 | }; |
72 | ||
73 | struct spi_imx_data; | |
74 | ||
75 | struct spi_imx_devtype_data { | |
76 | void (*intctrl)(struct spi_imx_data *, int); | |
b36581df | 77 | int (*config)(struct spi_device *, struct spi_imx_config *); |
f4ba6315 UKK |
78 | void (*trigger)(struct spi_imx_data *); |
79 | int (*rx_available)(struct spi_imx_data *); | |
1723e66b | 80 | void (*reset)(struct spi_imx_data *); |
04ee5854 | 81 | enum spi_imx_devtype devtype; |
f4ba6315 UKK |
82 | }; |
83 | ||
6cdeb002 | 84 | struct spi_imx_data { |
b5f3294f | 85 | struct spi_bitbang bitbang; |
6aa800ca | 86 | struct device *dev; |
b5f3294f SH |
87 | |
88 | struct completion xfer_done; | |
cc4d22ae | 89 | void __iomem *base; |
f12ae171 AB |
90 | unsigned long base_phys; |
91 | ||
aa29d840 SH |
92 | struct clk *clk_per; |
93 | struct clk *clk_ipg; | |
b5f3294f | 94 | unsigned long spi_clk; |
4bfe927a | 95 | unsigned int spi_bus_clk; |
b5f3294f | 96 | |
f12ae171 AB |
97 | unsigned int bytes_per_word; |
98 | ||
b5f3294f | 99 | unsigned int count; |
6cdeb002 UKK |
100 | void (*tx)(struct spi_imx_data *); |
101 | void (*rx)(struct spi_imx_data *); | |
b5f3294f SH |
102 | void *rx_buf; |
103 | const void *tx_buf; | |
104 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | |
105 | ||
f62caccd | 106 | /* DMA */ |
f62caccd | 107 | bool usedma; |
0dfbaa89 | 108 | u32 wml; |
f62caccd RG |
109 | struct completion dma_rx_completion; |
110 | struct completion dma_tx_completion; | |
111 | ||
80023cb3 | 112 | const struct spi_imx_devtype_data *devtype_data; |
b5f3294f SH |
113 | }; |
114 | ||
04ee5854 SG |
115 | static inline int is_imx27_cspi(struct spi_imx_data *d) |
116 | { | |
117 | return d->devtype_data->devtype == IMX27_CSPI; | |
118 | } | |
119 | ||
120 | static inline int is_imx35_cspi(struct spi_imx_data *d) | |
121 | { | |
122 | return d->devtype_data->devtype == IMX35_CSPI; | |
123 | } | |
124 | ||
f8a87617 AB |
125 | static inline int is_imx51_ecspi(struct spi_imx_data *d) |
126 | { | |
127 | return d->devtype_data->devtype == IMX51_ECSPI; | |
128 | } | |
129 | ||
04ee5854 SG |
130 | static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) |
131 | { | |
f8a87617 | 132 | return is_imx51_ecspi(d) ? 64 : 8; |
04ee5854 SG |
133 | } |
134 | ||
b5f3294f | 135 | #define MXC_SPI_BUF_RX(type) \ |
6cdeb002 | 136 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f | 137 | { \ |
6cdeb002 | 138 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
b5f3294f | 139 | \ |
6cdeb002 UKK |
140 | if (spi_imx->rx_buf) { \ |
141 | *(type *)spi_imx->rx_buf = val; \ | |
142 | spi_imx->rx_buf += sizeof(type); \ | |
b5f3294f SH |
143 | } \ |
144 | } | |
145 | ||
146 | #define MXC_SPI_BUF_TX(type) \ | |
6cdeb002 | 147 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f SH |
148 | { \ |
149 | type val = 0; \ | |
150 | \ | |
6cdeb002 UKK |
151 | if (spi_imx->tx_buf) { \ |
152 | val = *(type *)spi_imx->tx_buf; \ | |
153 | spi_imx->tx_buf += sizeof(type); \ | |
b5f3294f SH |
154 | } \ |
155 | \ | |
6cdeb002 | 156 | spi_imx->count -= sizeof(type); \ |
b5f3294f | 157 | \ |
6cdeb002 | 158 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
b5f3294f SH |
159 | } |
160 | ||
161 | MXC_SPI_BUF_RX(u8) | |
162 | MXC_SPI_BUF_TX(u8) | |
163 | MXC_SPI_BUF_RX(u16) | |
164 | MXC_SPI_BUF_TX(u16) | |
165 | MXC_SPI_BUF_RX(u32) | |
166 | MXC_SPI_BUF_TX(u32) | |
167 | ||
168 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set | |
169 | * (which is currently not the case in this driver) | |
170 | */ | |
171 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |
172 | 256, 384, 512, 768, 1024}; | |
173 | ||
174 | /* MX21, MX27 */ | |
6cdeb002 | 175 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
32df9ff2 | 176 | unsigned int fspi, unsigned int max, unsigned int *fres) |
b5f3294f | 177 | { |
04ee5854 | 178 | int i; |
b5f3294f SH |
179 | |
180 | for (i = 2; i < max; i++) | |
181 | if (fspi * mxc_clkdivs[i] >= fin) | |
32df9ff2 | 182 | break; |
b5f3294f | 183 | |
32df9ff2 RB |
184 | *fres = fin / mxc_clkdivs[i]; |
185 | return i; | |
b5f3294f SH |
186 | } |
187 | ||
0b599603 | 188 | /* MX1, MX31, MX35, MX51 CSPI */ |
6cdeb002 | 189 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
2636ba8f | 190 | unsigned int fspi, unsigned int *fres) |
b5f3294f SH |
191 | { |
192 | int i, div = 4; | |
193 | ||
194 | for (i = 0; i < 7; i++) { | |
195 | if (fspi * div >= fin) | |
2636ba8f | 196 | goto out; |
b5f3294f SH |
197 | div <<= 1; |
198 | } | |
199 | ||
2636ba8f MK |
200 | out: |
201 | *fres = fin / div; | |
202 | return i; | |
b5f3294f SH |
203 | } |
204 | ||
f12ae171 AB |
205 | static int spi_imx_bytes_per_word(const int bpw) |
206 | { | |
207 | return DIV_ROUND_UP(bpw, BITS_PER_BYTE); | |
208 | } | |
209 | ||
f62caccd RG |
210 | static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, |
211 | struct spi_transfer *transfer) | |
212 | { | |
213 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
cd8dd41a | 214 | unsigned int bpw; |
f12ae171 AB |
215 | |
216 | if (!master->dma_rx) | |
217 | return false; | |
218 | ||
cd8dd41a SH |
219 | if (!transfer) |
220 | return false; | |
221 | ||
222 | bpw = transfer->bits_per_word; | |
f12ae171 AB |
223 | if (!bpw) |
224 | bpw = spi->bits_per_word; | |
225 | ||
226 | bpw = spi_imx_bytes_per_word(bpw); | |
227 | ||
228 | if (bpw != 1 && bpw != 2 && bpw != 4) | |
229 | return false; | |
230 | ||
231 | if (transfer->len < spi_imx->wml * bpw) | |
232 | return false; | |
233 | ||
234 | if (transfer->len % (spi_imx->wml * bpw)) | |
235 | return false; | |
f62caccd | 236 | |
f12ae171 | 237 | return true; |
f62caccd RG |
238 | } |
239 | ||
66de757c SG |
240 | #define MX51_ECSPI_CTRL 0x08 |
241 | #define MX51_ECSPI_CTRL_ENABLE (1 << 0) | |
242 | #define MX51_ECSPI_CTRL_XCH (1 << 2) | |
f62caccd | 243 | #define MX51_ECSPI_CTRL_SMC (1 << 3) |
66de757c SG |
244 | #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) |
245 | #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 | |
246 | #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 | |
247 | #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) | |
248 | #define MX51_ECSPI_CTRL_BL_OFFSET 20 | |
249 | ||
250 | #define MX51_ECSPI_CONFIG 0x0c | |
251 | #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) | |
252 | #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) | |
253 | #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) | |
254 | #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) | |
c09b890b | 255 | #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) |
66de757c SG |
256 | |
257 | #define MX51_ECSPI_INT 0x10 | |
258 | #define MX51_ECSPI_INT_TEEN (1 << 0) | |
259 | #define MX51_ECSPI_INT_RREN (1 << 3) | |
260 | ||
f62caccd | 261 | #define MX51_ECSPI_DMA 0x14 |
d629c2a0 SH |
262 | #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) |
263 | #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) | |
264 | #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) | |
f62caccd | 265 | |
2b0fd069 SH |
266 | #define MX51_ECSPI_DMA_TEDEN (1 << 7) |
267 | #define MX51_ECSPI_DMA_RXDEN (1 << 23) | |
268 | #define MX51_ECSPI_DMA_RXTDEN (1 << 31) | |
f62caccd | 269 | |
66de757c SG |
270 | #define MX51_ECSPI_STAT 0x18 |
271 | #define MX51_ECSPI_STAT_RR (1 << 3) | |
0b599603 | 272 | |
9f6aa42b FE |
273 | #define MX51_ECSPI_TESTREG 0x20 |
274 | #define MX51_ECSPI_TESTREG_LBC BIT(31) | |
275 | ||
0b599603 | 276 | /* MX51 eCSPI */ |
6aa800ca SH |
277 | static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, |
278 | unsigned int fspi, unsigned int *fres) | |
0b599603 UKK |
279 | { |
280 | /* | |
281 | * there are two 4-bit dividers, the pre-divider divides by | |
282 | * $pre, the post-divider by 2^$post | |
283 | */ | |
284 | unsigned int pre, post; | |
6aa800ca | 285 | unsigned int fin = spi_imx->spi_clk; |
0b599603 UKK |
286 | |
287 | if (unlikely(fspi > fin)) | |
288 | return 0; | |
289 | ||
290 | post = fls(fin) - fls(fspi); | |
291 | if (fin > fspi << post) | |
292 | post++; | |
293 | ||
294 | /* now we have: (fin <= fspi << post) with post being minimal */ | |
295 | ||
296 | post = max(4U, post) - 4; | |
297 | if (unlikely(post > 0xf)) { | |
6aa800ca SH |
298 | dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", |
299 | fspi, fin); | |
0b599603 UKK |
300 | return 0xff; |
301 | } | |
302 | ||
303 | pre = DIV_ROUND_UP(fin, fspi << post) - 1; | |
304 | ||
6aa800ca | 305 | dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", |
0b599603 | 306 | __func__, fin, fspi, post, pre); |
6fd8b850 MV |
307 | |
308 | /* Resulting frequency for the SCLK line. */ | |
309 | *fres = (fin / (pre + 1)) >> post; | |
310 | ||
66de757c SG |
311 | return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | |
312 | (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); | |
0b599603 UKK |
313 | } |
314 | ||
f989bc69 | 315 | static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) |
0b599603 UKK |
316 | { |
317 | unsigned val = 0; | |
318 | ||
319 | if (enable & MXC_INT_TE) | |
66de757c | 320 | val |= MX51_ECSPI_INT_TEEN; |
0b599603 UKK |
321 | |
322 | if (enable & MXC_INT_RR) | |
66de757c | 323 | val |= MX51_ECSPI_INT_RREN; |
0b599603 | 324 | |
66de757c | 325 | writel(val, spi_imx->base + MX51_ECSPI_INT); |
0b599603 UKK |
326 | } |
327 | ||
f989bc69 | 328 | static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) |
0b599603 | 329 | { |
b03c3884 | 330 | u32 reg; |
f62caccd | 331 | |
b03c3884 SH |
332 | reg = readl(spi_imx->base + MX51_ECSPI_CTRL); |
333 | reg |= MX51_ECSPI_CTRL_XCH; | |
66de757c | 334 | writel(reg, spi_imx->base + MX51_ECSPI_CTRL); |
0b599603 UKK |
335 | } |
336 | ||
f989bc69 AS |
337 | static int mx51_ecspi_config(struct spi_device *spi, |
338 | struct spi_imx_config *config) | |
0b599603 | 339 | { |
b36581df | 340 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
793c7f92 | 341 | u32 ctrl = MX51_ECSPI_CTRL_ENABLE; |
9f6aa42b | 342 | u32 clk = config->speed_hz, delay, reg; |
793c7f92 | 343 | u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); |
0b599603 | 344 | |
f020c39e SH |
345 | /* |
346 | * The hardware seems to have a race condition when changing modes. The | |
347 | * current assumption is that the selection of the channel arrives | |
348 | * earlier in the hardware than the mode bits when they are written at | |
349 | * the same time. | |
350 | * So set master mode for all channels as we do not support slave mode. | |
351 | */ | |
66de757c | 352 | ctrl |= MX51_ECSPI_CTRL_MODE_MASK; |
0b599603 UKK |
353 | |
354 | /* set clock speed */ | |
6aa800ca | 355 | ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk); |
4bfe927a | 356 | spi_imx->spi_bus_clk = clk; |
0b599603 UKK |
357 | |
358 | /* set chip select to use */ | |
b36581df | 359 | ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); |
0b599603 | 360 | |
66de757c | 361 | ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; |
0b599603 | 362 | |
b36581df | 363 | cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); |
0b599603 | 364 | |
c0c7a5d7 | 365 | if (spi->mode & SPI_CPHA) |
b36581df | 366 | cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); |
793c7f92 | 367 | else |
b36581df | 368 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); |
0b599603 | 369 | |
c0c7a5d7 | 370 | if (spi->mode & SPI_CPOL) { |
b36581df AS |
371 | cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); |
372 | cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); | |
793c7f92 | 373 | } else { |
b36581df AS |
374 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); |
375 | cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); | |
c09b890b | 376 | } |
c0c7a5d7 | 377 | if (spi->mode & SPI_CS_HIGH) |
b36581df | 378 | cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); |
793c7f92 | 379 | else |
b36581df | 380 | cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); |
0b599603 | 381 | |
b03c3884 SH |
382 | if (spi_imx->usedma) |
383 | ctrl |= MX51_ECSPI_CTRL_SMC; | |
384 | ||
f677f17c AB |
385 | /* CTRL register always go first to bring out controller from reset */ |
386 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
387 | ||
9f6aa42b | 388 | reg = readl(spi_imx->base + MX51_ECSPI_TESTREG); |
c0c7a5d7 | 389 | if (spi->mode & SPI_LOOP) |
9f6aa42b FE |
390 | reg |= MX51_ECSPI_TESTREG_LBC; |
391 | else | |
392 | reg &= ~MX51_ECSPI_TESTREG_LBC; | |
393 | writel(reg, spi_imx->base + MX51_ECSPI_TESTREG); | |
394 | ||
66de757c | 395 | writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); |
0b599603 | 396 | |
6fd8b850 MV |
397 | /* |
398 | * Wait until the changes in the configuration register CONFIGREG | |
399 | * propagate into the hardware. It takes exactly one tick of the | |
400 | * SCLK clock, but we will wait two SCLK clock just to be sure. The | |
401 | * effect of the delay it takes for the hardware to apply changes | |
402 | * is noticable if the SCLK clock run very slow. In such a case, if | |
403 | * the polarity of SCLK should be inverted, the GPIO ChipSelect might | |
404 | * be asserted before the SCLK polarity changes, which would disrupt | |
405 | * the SPI communication as the device on the other end would consider | |
406 | * the change of SCLK polarity as a clock tick already. | |
407 | */ | |
408 | delay = (2 * 1000000) / clk; | |
409 | if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ | |
410 | udelay(delay); | |
411 | else /* SCLK is _very_ slow */ | |
412 | usleep_range(delay, delay + 10); | |
413 | ||
f62caccd RG |
414 | /* |
415 | * Configure the DMA register: setup the watermark | |
416 | * and enable DMA request. | |
417 | */ | |
2b0fd069 | 418 | |
d629c2a0 SH |
419 | writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) | |
420 | MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | | |
421 | MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | | |
2b0fd069 SH |
422 | MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | |
423 | MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); | |
f62caccd | 424 | |
0b599603 UKK |
425 | return 0; |
426 | } | |
427 | ||
f989bc69 | 428 | static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) |
0b599603 | 429 | { |
66de757c | 430 | return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; |
0b599603 UKK |
431 | } |
432 | ||
f989bc69 | 433 | static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) |
0b599603 UKK |
434 | { |
435 | /* drain receive buffer */ | |
66de757c | 436 | while (mx51_ecspi_rx_available(spi_imx)) |
0b599603 UKK |
437 | readl(spi_imx->base + MXC_CSPIRXDATA); |
438 | } | |
439 | ||
b5f3294f SH |
440 | #define MX31_INTREG_TEEN (1 << 0) |
441 | #define MX31_INTREG_RREN (1 << 3) | |
442 | ||
443 | #define MX31_CSPICTRL_ENABLE (1 << 0) | |
444 | #define MX31_CSPICTRL_MASTER (1 << 1) | |
445 | #define MX31_CSPICTRL_XCH (1 << 2) | |
2dd33f9c | 446 | #define MX31_CSPICTRL_SMC (1 << 3) |
b5f3294f SH |
447 | #define MX31_CSPICTRL_POL (1 << 4) |
448 | #define MX31_CSPICTRL_PHA (1 << 5) | |
449 | #define MX31_CSPICTRL_SSCTL (1 << 6) | |
450 | #define MX31_CSPICTRL_SSPOL (1 << 7) | |
451 | #define MX31_CSPICTRL_BC_SHIFT 8 | |
452 | #define MX35_CSPICTRL_BL_SHIFT 20 | |
453 | #define MX31_CSPICTRL_CS_SHIFT 24 | |
454 | #define MX35_CSPICTRL_CS_SHIFT 12 | |
455 | #define MX31_CSPICTRL_DR_SHIFT 16 | |
456 | ||
2dd33f9c MK |
457 | #define MX31_CSPI_DMAREG 0x10 |
458 | #define MX31_DMAREG_RH_DEN (1<<4) | |
459 | #define MX31_DMAREG_TH_DEN (1<<1) | |
460 | ||
b5f3294f SH |
461 | #define MX31_CSPISTATUS 0x14 |
462 | #define MX31_STATUS_RR (1 << 3) | |
463 | ||
15ca9215 MK |
464 | #define MX31_CSPI_TESTREG 0x1C |
465 | #define MX31_TEST_LBC (1 << 14) | |
466 | ||
b5f3294f SH |
467 | /* These functions also work for the i.MX35, but be aware that |
468 | * the i.MX35 has a slightly different register layout for bits | |
469 | * we do not use here. | |
470 | */ | |
f989bc69 | 471 | static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
472 | { |
473 | unsigned int val = 0; | |
474 | ||
475 | if (enable & MXC_INT_TE) | |
476 | val |= MX31_INTREG_TEEN; | |
477 | if (enable & MXC_INT_RR) | |
478 | val |= MX31_INTREG_RREN; | |
479 | ||
6cdeb002 | 480 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
481 | } |
482 | ||
f989bc69 | 483 | static void mx31_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
484 | { |
485 | unsigned int reg; | |
486 | ||
6cdeb002 | 487 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 488 | reg |= MX31_CSPICTRL_XCH; |
6cdeb002 | 489 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
490 | } |
491 | ||
f989bc69 | 492 | static int mx31_config(struct spi_device *spi, struct spi_imx_config *config) |
1723e66b | 493 | { |
b36581df | 494 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
1723e66b | 495 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; |
2636ba8f | 496 | unsigned int clk; |
1723e66b | 497 | |
2636ba8f | 498 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz, &clk) << |
1723e66b | 499 | MX31_CSPICTRL_DR_SHIFT; |
2636ba8f | 500 | spi_imx->spi_bus_clk = clk; |
1723e66b | 501 | |
04ee5854 | 502 | if (is_imx35_cspi(spi_imx)) { |
2a64a90a SG |
503 | reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; |
504 | reg |= MX31_CSPICTRL_SSCTL; | |
505 | } else { | |
506 | reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; | |
507 | } | |
1723e66b | 508 | |
c0c7a5d7 | 509 | if (spi->mode & SPI_CPHA) |
1723e66b | 510 | reg |= MX31_CSPICTRL_PHA; |
c0c7a5d7 | 511 | if (spi->mode & SPI_CPOL) |
1723e66b | 512 | reg |= MX31_CSPICTRL_POL; |
c0c7a5d7 | 513 | if (spi->mode & SPI_CS_HIGH) |
1723e66b | 514 | reg |= MX31_CSPICTRL_SSPOL; |
b36581df AS |
515 | if (spi->cs_gpio < 0) |
516 | reg |= (spi->cs_gpio + 32) << | |
04ee5854 SG |
517 | (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : |
518 | MX31_CSPICTRL_CS_SHIFT); | |
1723e66b | 519 | |
2dd33f9c MK |
520 | if (spi_imx->usedma) |
521 | reg |= MX31_CSPICTRL_SMC; | |
522 | ||
1723e66b UKK |
523 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
524 | ||
15ca9215 MK |
525 | reg = readl(spi_imx->base + MX31_CSPI_TESTREG); |
526 | if (spi->mode & SPI_LOOP) | |
527 | reg |= MX31_TEST_LBC; | |
528 | else | |
529 | reg &= ~MX31_TEST_LBC; | |
530 | writel(reg, spi_imx->base + MX31_CSPI_TESTREG); | |
531 | ||
2dd33f9c MK |
532 | if (spi_imx->usedma) { |
533 | /* configure DMA requests when RXFIFO is half full and | |
534 | when TXFIFO is half empty */ | |
535 | writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, | |
536 | spi_imx->base + MX31_CSPI_DMAREG); | |
537 | } | |
538 | ||
1723e66b UKK |
539 | return 0; |
540 | } | |
541 | ||
f989bc69 | 542 | static int mx31_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 543 | { |
6cdeb002 | 544 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
b5f3294f SH |
545 | } |
546 | ||
f989bc69 | 547 | static void mx31_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
548 | { |
549 | /* drain receive buffer */ | |
2a64a90a | 550 | while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) |
1723e66b UKK |
551 | readl(spi_imx->base + MXC_CSPIRXDATA); |
552 | } | |
553 | ||
3451fb15 SG |
554 | #define MX21_INTREG_RR (1 << 4) |
555 | #define MX21_INTREG_TEEN (1 << 9) | |
556 | #define MX21_INTREG_RREN (1 << 13) | |
557 | ||
558 | #define MX21_CSPICTRL_POL (1 << 5) | |
559 | #define MX21_CSPICTRL_PHA (1 << 6) | |
560 | #define MX21_CSPICTRL_SSPOL (1 << 8) | |
561 | #define MX21_CSPICTRL_XCH (1 << 9) | |
562 | #define MX21_CSPICTRL_ENABLE (1 << 10) | |
563 | #define MX21_CSPICTRL_MASTER (1 << 11) | |
564 | #define MX21_CSPICTRL_DR_SHIFT 14 | |
565 | #define MX21_CSPICTRL_CS_SHIFT 19 | |
566 | ||
f989bc69 | 567 | static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
568 | { |
569 | unsigned int val = 0; | |
570 | ||
571 | if (enable & MXC_INT_TE) | |
3451fb15 | 572 | val |= MX21_INTREG_TEEN; |
b5f3294f | 573 | if (enable & MXC_INT_RR) |
3451fb15 | 574 | val |= MX21_INTREG_RREN; |
b5f3294f | 575 | |
6cdeb002 | 576 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
577 | } |
578 | ||
f989bc69 | 579 | static void mx21_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
580 | { |
581 | unsigned int reg; | |
582 | ||
6cdeb002 | 583 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
3451fb15 | 584 | reg |= MX21_CSPICTRL_XCH; |
6cdeb002 | 585 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
586 | } |
587 | ||
f989bc69 | 588 | static int mx21_config(struct spi_device *spi, struct spi_imx_config *config) |
b5f3294f | 589 | { |
b36581df | 590 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
3451fb15 | 591 | unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; |
04ee5854 | 592 | unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; |
32df9ff2 RB |
593 | unsigned int clk; |
594 | ||
595 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max, &clk) | |
596 | << MX21_CSPICTRL_DR_SHIFT; | |
597 | spi_imx->spi_bus_clk = clk; | |
b5f3294f | 598 | |
b5f3294f SH |
599 | reg |= config->bpw - 1; |
600 | ||
c0c7a5d7 | 601 | if (spi->mode & SPI_CPHA) |
3451fb15 | 602 | reg |= MX21_CSPICTRL_PHA; |
c0c7a5d7 | 603 | if (spi->mode & SPI_CPOL) |
3451fb15 | 604 | reg |= MX21_CSPICTRL_POL; |
c0c7a5d7 | 605 | if (spi->mode & SPI_CS_HIGH) |
3451fb15 | 606 | reg |= MX21_CSPICTRL_SSPOL; |
b36581df AS |
607 | if (spi->cs_gpio < 0) |
608 | reg |= (spi->cs_gpio + 32) << MX21_CSPICTRL_CS_SHIFT; | |
b5f3294f | 609 | |
6cdeb002 | 610 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
611 | |
612 | return 0; | |
613 | } | |
614 | ||
f989bc69 | 615 | static int mx21_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 616 | { |
3451fb15 | 617 | return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; |
b5f3294f SH |
618 | } |
619 | ||
f989bc69 | 620 | static void mx21_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
621 | { |
622 | writel(1, spi_imx->base + MXC_RESET); | |
623 | } | |
624 | ||
b5f3294f SH |
625 | #define MX1_INTREG_RR (1 << 3) |
626 | #define MX1_INTREG_TEEN (1 << 8) | |
627 | #define MX1_INTREG_RREN (1 << 11) | |
628 | ||
629 | #define MX1_CSPICTRL_POL (1 << 4) | |
630 | #define MX1_CSPICTRL_PHA (1 << 5) | |
631 | #define MX1_CSPICTRL_XCH (1 << 8) | |
632 | #define MX1_CSPICTRL_ENABLE (1 << 9) | |
633 | #define MX1_CSPICTRL_MASTER (1 << 10) | |
634 | #define MX1_CSPICTRL_DR_SHIFT 13 | |
635 | ||
f989bc69 | 636 | static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
637 | { |
638 | unsigned int val = 0; | |
639 | ||
640 | if (enable & MXC_INT_TE) | |
641 | val |= MX1_INTREG_TEEN; | |
642 | if (enable & MXC_INT_RR) | |
643 | val |= MX1_INTREG_RREN; | |
644 | ||
6cdeb002 | 645 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
646 | } |
647 | ||
f989bc69 | 648 | static void mx1_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
649 | { |
650 | unsigned int reg; | |
651 | ||
6cdeb002 | 652 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 653 | reg |= MX1_CSPICTRL_XCH; |
6cdeb002 | 654 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
655 | } |
656 | ||
f989bc69 | 657 | static int mx1_config(struct spi_device *spi, struct spi_imx_config *config) |
b5f3294f | 658 | { |
b36581df | 659 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
b5f3294f | 660 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; |
2636ba8f | 661 | unsigned int clk; |
b5f3294f | 662 | |
2636ba8f | 663 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz, &clk) << |
b5f3294f | 664 | MX1_CSPICTRL_DR_SHIFT; |
2636ba8f MK |
665 | spi_imx->spi_bus_clk = clk; |
666 | ||
b5f3294f SH |
667 | reg |= config->bpw - 1; |
668 | ||
c0c7a5d7 | 669 | if (spi->mode & SPI_CPHA) |
b5f3294f | 670 | reg |= MX1_CSPICTRL_PHA; |
c0c7a5d7 | 671 | if (spi->mode & SPI_CPOL) |
b5f3294f SH |
672 | reg |= MX1_CSPICTRL_POL; |
673 | ||
6cdeb002 | 674 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
675 | |
676 | return 0; | |
677 | } | |
678 | ||
f989bc69 | 679 | static int mx1_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 680 | { |
6cdeb002 | 681 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
b5f3294f SH |
682 | } |
683 | ||
f989bc69 | 684 | static void mx1_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
685 | { |
686 | writel(1, spi_imx->base + MXC_RESET); | |
687 | } | |
688 | ||
04ee5854 SG |
689 | static struct spi_imx_devtype_data imx1_cspi_devtype_data = { |
690 | .intctrl = mx1_intctrl, | |
691 | .config = mx1_config, | |
692 | .trigger = mx1_trigger, | |
693 | .rx_available = mx1_rx_available, | |
694 | .reset = mx1_reset, | |
695 | .devtype = IMX1_CSPI, | |
696 | }; | |
697 | ||
698 | static struct spi_imx_devtype_data imx21_cspi_devtype_data = { | |
699 | .intctrl = mx21_intctrl, | |
700 | .config = mx21_config, | |
701 | .trigger = mx21_trigger, | |
702 | .rx_available = mx21_rx_available, | |
703 | .reset = mx21_reset, | |
704 | .devtype = IMX21_CSPI, | |
705 | }; | |
706 | ||
707 | static struct spi_imx_devtype_data imx27_cspi_devtype_data = { | |
708 | /* i.mx27 cspi shares the functions with i.mx21 one */ | |
709 | .intctrl = mx21_intctrl, | |
710 | .config = mx21_config, | |
711 | .trigger = mx21_trigger, | |
712 | .rx_available = mx21_rx_available, | |
713 | .reset = mx21_reset, | |
714 | .devtype = IMX27_CSPI, | |
715 | }; | |
716 | ||
717 | static struct spi_imx_devtype_data imx31_cspi_devtype_data = { | |
718 | .intctrl = mx31_intctrl, | |
719 | .config = mx31_config, | |
720 | .trigger = mx31_trigger, | |
721 | .rx_available = mx31_rx_available, | |
722 | .reset = mx31_reset, | |
723 | .devtype = IMX31_CSPI, | |
724 | }; | |
725 | ||
726 | static struct spi_imx_devtype_data imx35_cspi_devtype_data = { | |
727 | /* i.mx35 and later cspi shares the functions with i.mx31 one */ | |
728 | .intctrl = mx31_intctrl, | |
729 | .config = mx31_config, | |
730 | .trigger = mx31_trigger, | |
731 | .rx_available = mx31_rx_available, | |
732 | .reset = mx31_reset, | |
733 | .devtype = IMX35_CSPI, | |
734 | }; | |
735 | ||
736 | static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { | |
737 | .intctrl = mx51_ecspi_intctrl, | |
738 | .config = mx51_ecspi_config, | |
739 | .trigger = mx51_ecspi_trigger, | |
740 | .rx_available = mx51_ecspi_rx_available, | |
741 | .reset = mx51_ecspi_reset, | |
742 | .devtype = IMX51_ECSPI, | |
743 | }; | |
744 | ||
db1b8200 | 745 | static const struct platform_device_id spi_imx_devtype[] = { |
04ee5854 SG |
746 | { |
747 | .name = "imx1-cspi", | |
748 | .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, | |
749 | }, { | |
750 | .name = "imx21-cspi", | |
751 | .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, | |
752 | }, { | |
753 | .name = "imx27-cspi", | |
754 | .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, | |
755 | }, { | |
756 | .name = "imx31-cspi", | |
757 | .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, | |
758 | }, { | |
759 | .name = "imx35-cspi", | |
760 | .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, | |
761 | }, { | |
762 | .name = "imx51-ecspi", | |
763 | .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, | |
764 | }, { | |
765 | /* sentinel */ | |
766 | } | |
f4ba6315 UKK |
767 | }; |
768 | ||
22a85e4c SG |
769 | static const struct of_device_id spi_imx_dt_ids[] = { |
770 | { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, | |
771 | { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, | |
772 | { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, | |
773 | { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, | |
774 | { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, | |
775 | { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, | |
776 | { /* sentinel */ } | |
777 | }; | |
27743e0b | 778 | MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); |
22a85e4c | 779 | |
6cdeb002 | 780 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
b5f3294f | 781 | { |
e6a0a8bf UKK |
782 | int active = is_active != BITBANG_CS_INACTIVE; |
783 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); | |
b5f3294f | 784 | |
b36581df | 785 | if (!gpio_is_valid(spi->cs_gpio)) |
b5f3294f | 786 | return; |
b5f3294f | 787 | |
b36581df | 788 | gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active); |
b5f3294f SH |
789 | } |
790 | ||
6cdeb002 | 791 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
b5f3294f | 792 | { |
04ee5854 | 793 | while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { |
6cdeb002 | 794 | if (!spi_imx->count) |
b5f3294f | 795 | break; |
6cdeb002 UKK |
796 | spi_imx->tx(spi_imx); |
797 | spi_imx->txfifo++; | |
b5f3294f SH |
798 | } |
799 | ||
edd501bb | 800 | spi_imx->devtype_data->trigger(spi_imx); |
b5f3294f SH |
801 | } |
802 | ||
6cdeb002 | 803 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
b5f3294f | 804 | { |
6cdeb002 | 805 | struct spi_imx_data *spi_imx = dev_id; |
b5f3294f | 806 | |
edd501bb | 807 | while (spi_imx->devtype_data->rx_available(spi_imx)) { |
6cdeb002 UKK |
808 | spi_imx->rx(spi_imx); |
809 | spi_imx->txfifo--; | |
b5f3294f SH |
810 | } |
811 | ||
6cdeb002 UKK |
812 | if (spi_imx->count) { |
813 | spi_imx_push(spi_imx); | |
b5f3294f SH |
814 | return IRQ_HANDLED; |
815 | } | |
816 | ||
6cdeb002 | 817 | if (spi_imx->txfifo) { |
b5f3294f SH |
818 | /* No data left to push, but still waiting for rx data, |
819 | * enable receive data available interrupt. | |
820 | */ | |
edd501bb | 821 | spi_imx->devtype_data->intctrl( |
f4ba6315 | 822 | spi_imx, MXC_INT_RR); |
b5f3294f SH |
823 | return IRQ_HANDLED; |
824 | } | |
825 | ||
edd501bb | 826 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
6cdeb002 | 827 | complete(&spi_imx->xfer_done); |
b5f3294f SH |
828 | |
829 | return IRQ_HANDLED; | |
830 | } | |
831 | ||
f12ae171 AB |
832 | static int spi_imx_dma_configure(struct spi_master *master, |
833 | int bytes_per_word) | |
834 | { | |
835 | int ret; | |
836 | enum dma_slave_buswidth buswidth; | |
837 | struct dma_slave_config rx = {}, tx = {}; | |
838 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
839 | ||
840 | if (bytes_per_word == spi_imx->bytes_per_word) | |
841 | /* Same as last time */ | |
842 | return 0; | |
843 | ||
844 | switch (bytes_per_word) { | |
845 | case 4: | |
846 | buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
847 | break; | |
848 | case 2: | |
849 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
850 | break; | |
851 | case 1: | |
852 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
853 | break; | |
854 | default: | |
855 | return -EINVAL; | |
856 | } | |
857 | ||
858 | tx.direction = DMA_MEM_TO_DEV; | |
859 | tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; | |
860 | tx.dst_addr_width = buswidth; | |
861 | tx.dst_maxburst = spi_imx->wml; | |
862 | ret = dmaengine_slave_config(master->dma_tx, &tx); | |
863 | if (ret) { | |
864 | dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); | |
865 | return ret; | |
866 | } | |
867 | ||
868 | rx.direction = DMA_DEV_TO_MEM; | |
869 | rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; | |
870 | rx.src_addr_width = buswidth; | |
871 | rx.src_maxburst = spi_imx->wml; | |
872 | ret = dmaengine_slave_config(master->dma_rx, &rx); | |
873 | if (ret) { | |
874 | dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); | |
875 | return ret; | |
876 | } | |
877 | ||
878 | spi_imx->bytes_per_word = bytes_per_word; | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
6cdeb002 | 883 | static int spi_imx_setupxfer(struct spi_device *spi, |
b5f3294f SH |
884 | struct spi_transfer *t) |
885 | { | |
6cdeb002 UKK |
886 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
887 | struct spi_imx_config config; | |
f12ae171 | 888 | int ret; |
b5f3294f SH |
889 | |
890 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; | |
891 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; | |
b5f3294f | 892 | |
462d26b5 SH |
893 | if (!config.speed_hz) |
894 | config.speed_hz = spi->max_speed_hz; | |
895 | if (!config.bpw) | |
896 | config.bpw = spi->bits_per_word; | |
462d26b5 | 897 | |
e6a0a8bf UKK |
898 | /* Initialize the functions for transfer */ |
899 | if (config.bpw <= 8) { | |
900 | spi_imx->rx = spi_imx_buf_rx_u8; | |
901 | spi_imx->tx = spi_imx_buf_tx_u8; | |
902 | } else if (config.bpw <= 16) { | |
903 | spi_imx->rx = spi_imx_buf_rx_u16; | |
904 | spi_imx->tx = spi_imx_buf_tx_u16; | |
6051426f | 905 | } else { |
e6a0a8bf UKK |
906 | spi_imx->rx = spi_imx_buf_rx_u32; |
907 | spi_imx->tx = spi_imx_buf_tx_u32; | |
24778be2 | 908 | } |
e6a0a8bf | 909 | |
c008a800 SH |
910 | if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) |
911 | spi_imx->usedma = 1; | |
912 | else | |
913 | spi_imx->usedma = 0; | |
914 | ||
f12ae171 AB |
915 | if (spi_imx->usedma) { |
916 | ret = spi_imx_dma_configure(spi->master, | |
917 | spi_imx_bytes_per_word(config.bpw)); | |
918 | if (ret) | |
919 | return ret; | |
920 | } | |
921 | ||
b36581df | 922 | spi_imx->devtype_data->config(spi, &config); |
b5f3294f SH |
923 | |
924 | return 0; | |
925 | } | |
926 | ||
f62caccd RG |
927 | static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) |
928 | { | |
929 | struct spi_master *master = spi_imx->bitbang.master; | |
930 | ||
931 | if (master->dma_rx) { | |
932 | dma_release_channel(master->dma_rx); | |
933 | master->dma_rx = NULL; | |
934 | } | |
935 | ||
936 | if (master->dma_tx) { | |
937 | dma_release_channel(master->dma_tx); | |
938 | master->dma_tx = NULL; | |
939 | } | |
f62caccd RG |
940 | } |
941 | ||
942 | static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, | |
f12ae171 | 943 | struct spi_master *master) |
f62caccd | 944 | { |
f62caccd RG |
945 | int ret; |
946 | ||
a02bb401 RG |
947 | /* use pio mode for i.mx6dl chip TKT238285 */ |
948 | if (of_machine_is_compatible("fsl,imx6dl")) | |
949 | return 0; | |
950 | ||
0dfbaa89 AB |
951 | spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2; |
952 | ||
f62caccd | 953 | /* Prepare for TX DMA: */ |
3760047a AB |
954 | master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); |
955 | if (IS_ERR(master->dma_tx)) { | |
956 | ret = PTR_ERR(master->dma_tx); | |
957 | dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); | |
958 | master->dma_tx = NULL; | |
f62caccd RG |
959 | goto err; |
960 | } | |
961 | ||
f62caccd | 962 | /* Prepare for RX : */ |
3760047a AB |
963 | master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); |
964 | if (IS_ERR(master->dma_rx)) { | |
965 | ret = PTR_ERR(master->dma_rx); | |
966 | dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); | |
967 | master->dma_rx = NULL; | |
f62caccd RG |
968 | goto err; |
969 | } | |
970 | ||
f12ae171 | 971 | spi_imx_dma_configure(master, 1); |
f62caccd RG |
972 | |
973 | init_completion(&spi_imx->dma_rx_completion); | |
974 | init_completion(&spi_imx->dma_tx_completion); | |
975 | master->can_dma = spi_imx_can_dma; | |
976 | master->max_dma_len = MAX_SDMA_BD_BYTES; | |
977 | spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | | |
978 | SPI_MASTER_MUST_TX; | |
f62caccd RG |
979 | |
980 | return 0; | |
981 | err: | |
982 | spi_imx_sdma_exit(spi_imx); | |
983 | return ret; | |
984 | } | |
985 | ||
986 | static void spi_imx_dma_rx_callback(void *cookie) | |
987 | { | |
988 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; | |
989 | ||
990 | complete(&spi_imx->dma_rx_completion); | |
991 | } | |
992 | ||
993 | static void spi_imx_dma_tx_callback(void *cookie) | |
994 | { | |
995 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; | |
996 | ||
997 | complete(&spi_imx->dma_tx_completion); | |
998 | } | |
999 | ||
4bfe927a AB |
1000 | static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) |
1001 | { | |
1002 | unsigned long timeout = 0; | |
1003 | ||
1004 | /* Time with actual data transfer and CS change delay related to HW */ | |
1005 | timeout = (8 + 4) * size / spi_imx->spi_bus_clk; | |
1006 | ||
1007 | /* Add extra second for scheduler related activities */ | |
1008 | timeout += 1; | |
1009 | ||
1010 | /* Double calculated timeout */ | |
1011 | return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); | |
1012 | } | |
1013 | ||
f62caccd RG |
1014 | static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, |
1015 | struct spi_transfer *transfer) | |
1016 | { | |
6b6192c0 | 1017 | struct dma_async_tx_descriptor *desc_tx, *desc_rx; |
4bfe927a | 1018 | unsigned long transfer_timeout; |
56536a7f | 1019 | unsigned long timeout; |
f62caccd RG |
1020 | struct spi_master *master = spi_imx->bitbang.master; |
1021 | struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; | |
1022 | ||
6b6192c0 SH |
1023 | /* |
1024 | * The TX DMA setup starts the transfer, so make sure RX is configured | |
1025 | * before TX. | |
1026 | */ | |
1027 | desc_rx = dmaengine_prep_slave_sg(master->dma_rx, | |
1028 | rx->sgl, rx->nents, DMA_DEV_TO_MEM, | |
1029 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1030 | if (!desc_rx) | |
1031 | return -EINVAL; | |
f62caccd | 1032 | |
6b6192c0 SH |
1033 | desc_rx->callback = spi_imx_dma_rx_callback; |
1034 | desc_rx->callback_param = (void *)spi_imx; | |
1035 | dmaengine_submit(desc_rx); | |
1036 | reinit_completion(&spi_imx->dma_rx_completion); | |
1037 | dma_async_issue_pending(master->dma_rx); | |
f62caccd | 1038 | |
6b6192c0 SH |
1039 | desc_tx = dmaengine_prep_slave_sg(master->dma_tx, |
1040 | tx->sgl, tx->nents, DMA_MEM_TO_DEV, | |
1041 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1042 | if (!desc_tx) { | |
1043 | dmaengine_terminate_all(master->dma_tx); | |
1044 | return -EINVAL; | |
f62caccd RG |
1045 | } |
1046 | ||
6b6192c0 SH |
1047 | desc_tx->callback = spi_imx_dma_tx_callback; |
1048 | desc_tx->callback_param = (void *)spi_imx; | |
1049 | dmaengine_submit(desc_tx); | |
f62caccd | 1050 | reinit_completion(&spi_imx->dma_tx_completion); |
fab44ef1 | 1051 | dma_async_issue_pending(master->dma_tx); |
f62caccd | 1052 | |
4bfe927a AB |
1053 | transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); |
1054 | ||
f62caccd | 1055 | /* Wait SDMA to finish the data transfer.*/ |
56536a7f | 1056 | timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, |
4bfe927a | 1057 | transfer_timeout); |
56536a7f | 1058 | if (!timeout) { |
6aa800ca | 1059 | dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); |
f62caccd | 1060 | dmaengine_terminate_all(master->dma_tx); |
e47b33c0 | 1061 | dmaengine_terminate_all(master->dma_rx); |
6b6192c0 | 1062 | return -ETIMEDOUT; |
f62caccd RG |
1063 | } |
1064 | ||
6b6192c0 SH |
1065 | timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, |
1066 | transfer_timeout); | |
1067 | if (!timeout) { | |
1068 | dev_err(&master->dev, "I/O Error in DMA RX\n"); | |
1069 | spi_imx->devtype_data->reset(spi_imx); | |
1070 | dmaengine_terminate_all(master->dma_rx); | |
1071 | return -ETIMEDOUT; | |
1072 | } | |
f62caccd | 1073 | |
6b6192c0 | 1074 | return transfer->len; |
f62caccd RG |
1075 | } |
1076 | ||
1077 | static int spi_imx_pio_transfer(struct spi_device *spi, | |
b5f3294f SH |
1078 | struct spi_transfer *transfer) |
1079 | { | |
6cdeb002 | 1080 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
ff1ba3da CG |
1081 | unsigned long transfer_timeout; |
1082 | unsigned long timeout; | |
b5f3294f | 1083 | |
6cdeb002 UKK |
1084 | spi_imx->tx_buf = transfer->tx_buf; |
1085 | spi_imx->rx_buf = transfer->rx_buf; | |
1086 | spi_imx->count = transfer->len; | |
1087 | spi_imx->txfifo = 0; | |
b5f3294f | 1088 | |
aa0fe826 | 1089 | reinit_completion(&spi_imx->xfer_done); |
b5f3294f | 1090 | |
6cdeb002 | 1091 | spi_imx_push(spi_imx); |
b5f3294f | 1092 | |
edd501bb | 1093 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); |
b5f3294f | 1094 | |
ff1ba3da CG |
1095 | transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); |
1096 | ||
1097 | timeout = wait_for_completion_timeout(&spi_imx->xfer_done, | |
1098 | transfer_timeout); | |
1099 | if (!timeout) { | |
1100 | dev_err(&spi->dev, "I/O Error in PIO\n"); | |
1101 | spi_imx->devtype_data->reset(spi_imx); | |
1102 | return -ETIMEDOUT; | |
1103 | } | |
b5f3294f SH |
1104 | |
1105 | return transfer->len; | |
1106 | } | |
1107 | ||
f62caccd RG |
1108 | static int spi_imx_transfer(struct spi_device *spi, |
1109 | struct spi_transfer *transfer) | |
1110 | { | |
f62caccd RG |
1111 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
1112 | ||
c008a800 | 1113 | if (spi_imx->usedma) |
99f1cf1c | 1114 | return spi_imx_dma_transfer(spi_imx, transfer); |
c008a800 SH |
1115 | else |
1116 | return spi_imx_pio_transfer(spi, transfer); | |
f62caccd RG |
1117 | } |
1118 | ||
6cdeb002 | 1119 | static int spi_imx_setup(struct spi_device *spi) |
b5f3294f | 1120 | { |
f4d4ecfe | 1121 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
b5f3294f SH |
1122 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
1123 | ||
b36581df AS |
1124 | if (gpio_is_valid(spi->cs_gpio)) |
1125 | gpio_direction_output(spi->cs_gpio, | |
1126 | spi->mode & SPI_CS_HIGH ? 0 : 1); | |
6c23e5d4 | 1127 | |
6cdeb002 | 1128 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
b5f3294f SH |
1129 | |
1130 | return 0; | |
1131 | } | |
1132 | ||
6cdeb002 | 1133 | static void spi_imx_cleanup(struct spi_device *spi) |
b5f3294f SH |
1134 | { |
1135 | } | |
1136 | ||
9e556dcc HS |
1137 | static int |
1138 | spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) | |
1139 | { | |
1140 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1141 | int ret; | |
1142 | ||
1143 | ret = clk_enable(spi_imx->clk_per); | |
1144 | if (ret) | |
1145 | return ret; | |
1146 | ||
1147 | ret = clk_enable(spi_imx->clk_ipg); | |
1148 | if (ret) { | |
1149 | clk_disable(spi_imx->clk_per); | |
1150 | return ret; | |
1151 | } | |
1152 | ||
1153 | return 0; | |
1154 | } | |
1155 | ||
1156 | static int | |
1157 | spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) | |
1158 | { | |
1159 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1160 | ||
1161 | clk_disable(spi_imx->clk_ipg); | |
1162 | clk_disable(spi_imx->clk_per); | |
1163 | return 0; | |
1164 | } | |
1165 | ||
fd4a319b | 1166 | static int spi_imx_probe(struct platform_device *pdev) |
b5f3294f | 1167 | { |
22a85e4c SG |
1168 | struct device_node *np = pdev->dev.of_node; |
1169 | const struct of_device_id *of_id = | |
1170 | of_match_device(spi_imx_dt_ids, &pdev->dev); | |
1171 | struct spi_imx_master *mxc_platform_info = | |
1172 | dev_get_platdata(&pdev->dev); | |
b5f3294f | 1173 | struct spi_master *master; |
6cdeb002 | 1174 | struct spi_imx_data *spi_imx; |
b5f3294f | 1175 | struct resource *res; |
b36581df | 1176 | int i, ret, irq; |
b5f3294f | 1177 | |
22a85e4c | 1178 | if (!np && !mxc_platform_info) { |
b5f3294f SH |
1179 | dev_err(&pdev->dev, "can't get the platform data\n"); |
1180 | return -EINVAL; | |
1181 | } | |
1182 | ||
b36581df | 1183 | master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data)); |
b5f3294f SH |
1184 | if (!master) |
1185 | return -ENOMEM; | |
1186 | ||
1187 | platform_set_drvdata(pdev, master); | |
1188 | ||
24778be2 | 1189 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); |
b36581df | 1190 | master->bus_num = np ? -1 : pdev->id; |
b5f3294f | 1191 | |
6cdeb002 | 1192 | spi_imx = spi_master_get_devdata(master); |
94c69f76 | 1193 | spi_imx->bitbang.master = master; |
6aa800ca | 1194 | spi_imx->dev = &pdev->dev; |
b5f3294f | 1195 | |
4686d1c3 AB |
1196 | spi_imx->devtype_data = of_id ? of_id->data : |
1197 | (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; | |
1198 | ||
b36581df AS |
1199 | if (mxc_platform_info) { |
1200 | master->num_chipselect = mxc_platform_info->num_chipselect; | |
1201 | master->cs_gpios = devm_kzalloc(&master->dev, | |
1202 | sizeof(int) * master->num_chipselect, GFP_KERNEL); | |
1203 | if (!master->cs_gpios) | |
1204 | return -ENOMEM; | |
4cc122ac | 1205 | |
b36581df AS |
1206 | for (i = 0; i < master->num_chipselect; i++) |
1207 | master->cs_gpios[i] = mxc_platform_info->chipselect[i]; | |
1208 | } | |
b5f3294f | 1209 | |
6cdeb002 UKK |
1210 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
1211 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; | |
1212 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; | |
1213 | spi_imx->bitbang.master->setup = spi_imx_setup; | |
1214 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; | |
9e556dcc HS |
1215 | spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; |
1216 | spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; | |
4686d1c3 | 1217 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
15ca9215 | 1218 | if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx)) |
4686d1c3 | 1219 | spi_imx->bitbang.master->mode_bits |= SPI_LOOP; |
b5f3294f | 1220 | |
6cdeb002 | 1221 | init_completion(&spi_imx->xfer_done); |
b5f3294f SH |
1222 | |
1223 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
130b82c0 FE |
1224 | spi_imx->base = devm_ioremap_resource(&pdev->dev, res); |
1225 | if (IS_ERR(spi_imx->base)) { | |
1226 | ret = PTR_ERR(spi_imx->base); | |
1227 | goto out_master_put; | |
b5f3294f | 1228 | } |
f12ae171 | 1229 | spi_imx->base_phys = res->start; |
b5f3294f | 1230 | |
4b5d6aad FE |
1231 | irq = platform_get_irq(pdev, 0); |
1232 | if (irq < 0) { | |
1233 | ret = irq; | |
130b82c0 | 1234 | goto out_master_put; |
b5f3294f SH |
1235 | } |
1236 | ||
4b5d6aad | 1237 | ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, |
8fc39b51 | 1238 | dev_name(&pdev->dev), spi_imx); |
b5f3294f | 1239 | if (ret) { |
4b5d6aad | 1240 | dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); |
130b82c0 | 1241 | goto out_master_put; |
b5f3294f SH |
1242 | } |
1243 | ||
aa29d840 SH |
1244 | spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1245 | if (IS_ERR(spi_imx->clk_ipg)) { | |
1246 | ret = PTR_ERR(spi_imx->clk_ipg); | |
130b82c0 | 1247 | goto out_master_put; |
b5f3294f SH |
1248 | } |
1249 | ||
aa29d840 SH |
1250 | spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); |
1251 | if (IS_ERR(spi_imx->clk_per)) { | |
1252 | ret = PTR_ERR(spi_imx->clk_per); | |
130b82c0 | 1253 | goto out_master_put; |
aa29d840 SH |
1254 | } |
1255 | ||
83174626 FE |
1256 | ret = clk_prepare_enable(spi_imx->clk_per); |
1257 | if (ret) | |
1258 | goto out_master_put; | |
1259 | ||
1260 | ret = clk_prepare_enable(spi_imx->clk_ipg); | |
1261 | if (ret) | |
1262 | goto out_put_per; | |
aa29d840 SH |
1263 | |
1264 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); | |
f62caccd | 1265 | /* |
2dd33f9c MK |
1266 | * Only validated on i.mx35 and i.mx6 now, can remove the constraint |
1267 | * if validated on other chips. | |
f62caccd | 1268 | */ |
2dd33f9c | 1269 | if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx)) { |
f12ae171 | 1270 | ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); |
bf9af08c AB |
1271 | if (ret == -EPROBE_DEFER) |
1272 | goto out_clk_put; | |
1273 | ||
3760047a AB |
1274 | if (ret < 0) |
1275 | dev_err(&pdev->dev, "dma setup error %d, use pio\n", | |
1276 | ret); | |
1277 | } | |
b5f3294f | 1278 | |
edd501bb | 1279 | spi_imx->devtype_data->reset(spi_imx); |
ce1807b2 | 1280 | |
edd501bb | 1281 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
b5f3294f | 1282 | |
22a85e4c | 1283 | master->dev.of_node = pdev->dev.of_node; |
6cdeb002 | 1284 | ret = spi_bitbang_start(&spi_imx->bitbang); |
b5f3294f SH |
1285 | if (ret) { |
1286 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); | |
1287 | goto out_clk_put; | |
1288 | } | |
1289 | ||
f13d4e18 MV |
1290 | if (!master->cs_gpios) { |
1291 | dev_err(&pdev->dev, "No CS GPIOs available\n"); | |
446576f9 | 1292 | ret = -EINVAL; |
f13d4e18 MV |
1293 | goto out_clk_put; |
1294 | } | |
1295 | ||
b36581df AS |
1296 | for (i = 0; i < master->num_chipselect; i++) { |
1297 | if (!gpio_is_valid(master->cs_gpios[i])) | |
1298 | continue; | |
1299 | ||
1300 | ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i], | |
1301 | DRIVER_NAME); | |
1302 | if (ret) { | |
1303 | dev_err(&pdev->dev, "Can't get CS GPIO %i\n", | |
1304 | master->cs_gpios[i]); | |
1305 | goto out_clk_put; | |
1306 | } | |
1307 | } | |
1308 | ||
b5f3294f SH |
1309 | dev_info(&pdev->dev, "probed\n"); |
1310 | ||
9e556dcc HS |
1311 | clk_disable(spi_imx->clk_ipg); |
1312 | clk_disable(spi_imx->clk_per); | |
b5f3294f SH |
1313 | return ret; |
1314 | ||
1315 | out_clk_put: | |
aa29d840 | 1316 | clk_disable_unprepare(spi_imx->clk_ipg); |
83174626 FE |
1317 | out_put_per: |
1318 | clk_disable_unprepare(spi_imx->clk_per); | |
130b82c0 | 1319 | out_master_put: |
b5f3294f | 1320 | spi_master_put(master); |
130b82c0 | 1321 | |
b5f3294f SH |
1322 | return ret; |
1323 | } | |
1324 | ||
fd4a319b | 1325 | static int spi_imx_remove(struct platform_device *pdev) |
b5f3294f SH |
1326 | { |
1327 | struct spi_master *master = platform_get_drvdata(pdev); | |
6cdeb002 | 1328 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
b5f3294f | 1329 | |
6cdeb002 | 1330 | spi_bitbang_stop(&spi_imx->bitbang); |
b5f3294f | 1331 | |
6cdeb002 | 1332 | writel(0, spi_imx->base + MXC_CSPICTRL); |
fd40dccb PDM |
1333 | clk_unprepare(spi_imx->clk_ipg); |
1334 | clk_unprepare(spi_imx->clk_per); | |
f62caccd | 1335 | spi_imx_sdma_exit(spi_imx); |
b5f3294f SH |
1336 | spi_master_put(master); |
1337 | ||
b5f3294f SH |
1338 | return 0; |
1339 | } | |
1340 | ||
6cdeb002 | 1341 | static struct platform_driver spi_imx_driver = { |
b5f3294f SH |
1342 | .driver = { |
1343 | .name = DRIVER_NAME, | |
22a85e4c | 1344 | .of_match_table = spi_imx_dt_ids, |
b5f3294f | 1345 | }, |
f4ba6315 | 1346 | .id_table = spi_imx_devtype, |
6cdeb002 | 1347 | .probe = spi_imx_probe, |
fd4a319b | 1348 | .remove = spi_imx_remove, |
b5f3294f | 1349 | }; |
940ab889 | 1350 | module_platform_driver(spi_imx_driver); |
b5f3294f SH |
1351 | |
1352 | MODULE_DESCRIPTION("SPI Master Controller driver"); | |
1353 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
1354 | MODULE_LICENSE("GPL"); | |
3133fba3 | 1355 | MODULE_ALIAS("platform:" DRIVER_NAME); |