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6e27388f AG |
1 | /* |
2 | * MPC512x PSC in SPI mode driver. | |
3 | * | |
4 | * Copyright (C) 2007,2008 Freescale Semiconductor Inc. | |
5 | * Original port from 52xx driver: | |
6 | * Hongjun Chen <hong-jun.chen@freescale.com> | |
7 | * | |
8 | * Fork of mpc52xx_psc_spi.c: | |
9 | * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
6e27388f AG |
19 | #include <linux/errno.h> |
20 | #include <linux/interrupt.h> | |
22ae782f | 21 | #include <linux/of_address.h> |
5af50730 | 22 | #include <linux/of_irq.h> |
6e27388f | 23 | #include <linux/of_platform.h> |
6e27388f AG |
24 | #include <linux/completion.h> |
25 | #include <linux/io.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/spi/spi.h> | |
29 | #include <linux/fsl_devices.h> | |
86e98743 | 30 | #include <linux/gpio.h> |
6e27388f AG |
31 | #include <asm/mpc52xx_psc.h> |
32 | ||
8bf96098 UKK |
33 | enum { |
34 | TYPE_MPC5121, | |
35 | TYPE_MPC5125, | |
36 | }; | |
37 | ||
38 | /* | |
39 | * This macro abstracts the differences in the PSC register layout between | |
40 | * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc). | |
41 | */ | |
42 | #define psc_addr(mps, regname) ({ \ | |
43 | void *__ret; \ | |
44 | switch(mps->type) { \ | |
45 | case TYPE_MPC5121: { \ | |
46 | struct mpc52xx_psc __iomem *psc = mps->psc; \ | |
47 | __ret = &psc->regname; \ | |
48 | }; \ | |
49 | break; \ | |
50 | case TYPE_MPC5125: { \ | |
51 | struct mpc5125_psc __iomem *psc = mps->psc; \ | |
52 | __ret = &psc->regname; \ | |
53 | }; \ | |
54 | break; \ | |
55 | } \ | |
56 | __ret; }) | |
57 | ||
6e27388f AG |
58 | struct mpc512x_psc_spi { |
59 | void (*cs_control)(struct spi_device *spi, bool on); | |
6e27388f AG |
60 | |
61 | /* driver internal data */ | |
8bf96098 UKK |
62 | int type; |
63 | void __iomem *psc; | |
6e27388f AG |
64 | struct mpc512x_psc_fifo __iomem *fifo; |
65 | unsigned int irq; | |
66 | u8 bits_per_word; | |
a81a5094 | 67 | struct clk *clk_mclk; |
dff148ad | 68 | struct clk *clk_ipg; |
a81a5094 | 69 | u32 mclk_rate; |
6e27388f | 70 | |
c36e93a0 | 71 | struct completion txisrdone; |
6e27388f AG |
72 | }; |
73 | ||
74 | /* controller state */ | |
75 | struct mpc512x_psc_spi_cs { | |
76 | int bits_per_word; | |
77 | int speed_hz; | |
78 | }; | |
79 | ||
80 | /* set clock freq, clock ramp, bits per work | |
81 | * if t is NULL then reset the values to the default values | |
82 | */ | |
83 | static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi, | |
84 | struct spi_transfer *t) | |
85 | { | |
86 | struct mpc512x_psc_spi_cs *cs = spi->controller_state; | |
87 | ||
88 | cs->speed_hz = (t && t->speed_hz) | |
89 | ? t->speed_hz : spi->max_speed_hz; | |
90 | cs->bits_per_word = (t && t->bits_per_word) | |
91 | ? t->bits_per_word : spi->bits_per_word; | |
92 | cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static void mpc512x_psc_spi_activate_cs(struct spi_device *spi) | |
97 | { | |
98 | struct mpc512x_psc_spi_cs *cs = spi->controller_state; | |
99 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); | |
6e27388f AG |
100 | u32 sicr; |
101 | u32 ccr; | |
a81a5094 | 102 | int speed; |
6e27388f AG |
103 | u16 bclkdiv; |
104 | ||
8bf96098 | 105 | sicr = in_be32(psc_addr(mps, sicr)); |
6e27388f AG |
106 | |
107 | /* Set clock phase and polarity */ | |
108 | if (spi->mode & SPI_CPHA) | |
109 | sicr |= 0x00001000; | |
110 | else | |
111 | sicr &= ~0x00001000; | |
112 | ||
113 | if (spi->mode & SPI_CPOL) | |
114 | sicr |= 0x00002000; | |
115 | else | |
116 | sicr &= ~0x00002000; | |
117 | ||
118 | if (spi->mode & SPI_LSB_FIRST) | |
119 | sicr |= 0x10000000; | |
120 | else | |
121 | sicr &= ~0x10000000; | |
8bf96098 | 122 | out_be32(psc_addr(mps, sicr), sicr); |
6e27388f | 123 | |
8bf96098 | 124 | ccr = in_be32(psc_addr(mps, ccr)); |
6e27388f | 125 | ccr &= 0xFF000000; |
a81a5094 GS |
126 | speed = cs->speed_hz; |
127 | if (!speed) | |
128 | speed = 1000000; /* default 1MHz */ | |
129 | bclkdiv = (mps->mclk_rate / speed) - 1; | |
6e27388f AG |
130 | |
131 | ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); | |
8bf96098 | 132 | out_be32(psc_addr(mps, ccr), ccr); |
6e27388f AG |
133 | mps->bits_per_word = cs->bits_per_word; |
134 | ||
86e98743 | 135 | if (mps->cs_control && gpio_is_valid(spi->cs_gpio)) |
6e27388f AG |
136 | mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0); |
137 | } | |
138 | ||
139 | static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi) | |
140 | { | |
141 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); | |
142 | ||
86e98743 | 143 | if (mps->cs_control && gpio_is_valid(spi->cs_gpio)) |
6e27388f AG |
144 | mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1); |
145 | ||
146 | } | |
147 | ||
148 | /* extract and scale size field in txsz or rxsz */ | |
149 | #define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2); | |
150 | ||
151 | #define EOFBYTE 1 | |
152 | ||
153 | static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi, | |
154 | struct spi_transfer *t) | |
155 | { | |
156 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); | |
6e27388f | 157 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; |
c36e93a0 | 158 | size_t tx_len = t->len; |
5df24ea6 | 159 | size_t rx_len = t->len; |
6e27388f AG |
160 | u8 *tx_buf = (u8 *)t->tx_buf; |
161 | u8 *rx_buf = (u8 *)t->rx_buf; | |
162 | ||
163 | if (!tx_buf && !rx_buf && t->len) | |
164 | return -EINVAL; | |
165 | ||
5df24ea6 | 166 | while (rx_len || tx_len) { |
c36e93a0 | 167 | size_t txcount; |
6e27388f AG |
168 | u8 data; |
169 | size_t fifosz; | |
c36e93a0 | 170 | size_t rxcount; |
5df24ea6 | 171 | int rxtries; |
6e27388f AG |
172 | |
173 | /* | |
5df24ea6 GS |
174 | * send the TX bytes in as large a chunk as possible |
175 | * but neither exceed the TX nor the RX FIFOs | |
6e27388f AG |
176 | */ |
177 | fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz)); | |
c36e93a0 | 178 | txcount = min(fifosz, tx_len); |
5df24ea6 GS |
179 | fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz)); |
180 | fifosz -= in_be32(&fifo->rxcnt) + 1; | |
181 | txcount = min(fifosz, txcount); | |
182 | if (txcount) { | |
183 | ||
184 | /* fill the TX FIFO */ | |
185 | while (txcount-- > 0) { | |
186 | data = tx_buf ? *tx_buf++ : 0; | |
187 | if (tx_len == EOFBYTE && t->cs_change) | |
188 | setbits32(&fifo->txcmd, | |
189 | MPC512x_PSC_FIFO_EOF); | |
190 | out_8(&fifo->txdata_8, data); | |
191 | tx_len--; | |
192 | } | |
6e27388f | 193 | |
5df24ea6 | 194 | /* have the ISR trigger when the TX FIFO is empty */ |
16735d02 | 195 | reinit_completion(&mps->txisrdone); |
5df24ea6 GS |
196 | out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); |
197 | out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY); | |
198 | wait_for_completion(&mps->txisrdone); | |
6e27388f AG |
199 | } |
200 | ||
5df24ea6 GS |
201 | /* |
202 | * consume as much RX data as the FIFO holds, while we | |
203 | * iterate over the transfer's TX data length | |
204 | * | |
205 | * only insist in draining all the remaining RX bytes | |
206 | * when the TX bytes were exhausted (that's at the very | |
207 | * end of this transfer, not when still iterating over | |
208 | * the transfer's chunks) | |
209 | */ | |
210 | rxtries = 50; | |
211 | do { | |
212 | ||
213 | /* | |
214 | * grab whatever was in the FIFO when we started | |
215 | * looking, don't bother fetching what was added to | |
216 | * the FIFO while we read from it -- we'll return | |
217 | * here eventually and prefer sending out remaining | |
218 | * TX data | |
219 | */ | |
220 | fifosz = in_be32(&fifo->rxcnt); | |
221 | rxcount = min(fifosz, rx_len); | |
222 | while (rxcount-- > 0) { | |
223 | data = in_8(&fifo->rxdata_8); | |
224 | if (rx_buf) | |
225 | *rx_buf++ = data; | |
226 | rx_len--; | |
227 | } | |
6e27388f | 228 | |
5df24ea6 GS |
229 | /* |
230 | * come back later if there still is TX data to send, | |
231 | * bail out of the RX drain loop if all of the TX data | |
232 | * was sent and all of the RX data was received (i.e. | |
233 | * when the transmission has completed) | |
234 | */ | |
235 | if (tx_len) | |
236 | break; | |
237 | if (!rx_len) | |
238 | break; | |
239 | ||
240 | /* | |
241 | * TX data transmission has completed while RX data | |
242 | * is still pending -- that's a transient situation | |
243 | * which depends on wire speed and specific | |
244 | * hardware implementation details (buffering) yet | |
245 | * should resolve very quickly | |
246 | * | |
247 | * just yield for a moment to not hog the CPU for | |
248 | * too long when running SPI at low speed | |
249 | * | |
250 | * the timeout range is rather arbitrary and tries | |
251 | * to balance throughput against system load; the | |
252 | * chosen values result in a minimal timeout of 50 | |
253 | * times 10us and thus work at speeds as low as | |
254 | * some 20kbps, while the maximum timeout at the | |
255 | * transfer's end could be 5ms _if_ nothing else | |
256 | * ticks in the system _and_ RX data still wasn't | |
257 | * received, which only occurs in situations that | |
258 | * are exceptional; removing the unpredictability | |
259 | * of the timeout either decreases throughput | |
260 | * (longer timeouts), or puts more load on the | |
261 | * system (fixed short timeouts) or requires the | |
262 | * use of a timeout API instead of a counter and an | |
263 | * unknown inner delay | |
264 | */ | |
265 | usleep_range(10, 100); | |
266 | ||
267 | } while (--rxtries > 0); | |
268 | if (!tx_len && rx_len && !rxtries) { | |
269 | /* | |
270 | * not enough RX bytes even after several retries | |
271 | * and the resulting rather long timeout? | |
272 | */ | |
273 | rxcount = in_be32(&fifo->rxcnt); | |
274 | dev_warn(&spi->dev, | |
275 | "short xfer, missing %zd RX bytes, FIFO level %zd\n", | |
276 | rx_len, rxcount); | |
6e27388f AG |
277 | } |
278 | ||
5df24ea6 GS |
279 | /* |
280 | * drain and drop RX data which "should not be there" in | |
281 | * the first place, for undisturbed transmission this turns | |
282 | * into a NOP (except for the FIFO level fetch) | |
283 | */ | |
284 | if (!tx_len && !rx_len) { | |
285 | while (in_be32(&fifo->rxcnt)) | |
286 | in_8(&fifo->rxdata_8); | |
6e27388f | 287 | } |
5df24ea6 | 288 | |
6e27388f | 289 | } |
6e27388f AG |
290 | return 0; |
291 | } | |
292 | ||
85085898 GS |
293 | static int mpc512x_psc_spi_msg_xfer(struct spi_master *master, |
294 | struct spi_message *m) | |
6e27388f | 295 | { |
85085898 GS |
296 | struct spi_device *spi; |
297 | unsigned cs_change; | |
298 | int status; | |
299 | struct spi_transfer *t; | |
300 | ||
301 | spi = m->spi; | |
302 | cs_change = 1; | |
303 | status = 0; | |
304 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
305 | if (t->bits_per_word || t->speed_hz) { | |
306 | status = mpc512x_psc_spi_transfer_setup(spi, t); | |
307 | if (status < 0) | |
6e27388f | 308 | break; |
85085898 | 309 | } |
6e27388f | 310 | |
85085898 GS |
311 | if (cs_change) |
312 | mpc512x_psc_spi_activate_cs(spi); | |
313 | cs_change = t->cs_change; | |
6e27388f | 314 | |
85085898 GS |
315 | status = mpc512x_psc_spi_transfer_rxtx(spi, t); |
316 | if (status) | |
317 | break; | |
318 | m->actual_length += t->len; | |
6e27388f | 319 | |
85085898 GS |
320 | if (t->delay_usecs) |
321 | udelay(t->delay_usecs); | |
6e27388f | 322 | |
85085898 | 323 | if (cs_change) |
6e27388f | 324 | mpc512x_psc_spi_deactivate_cs(spi); |
85085898 | 325 | } |
6e27388f | 326 | |
85085898 | 327 | m->status = status; |
0a6d3879 AL |
328 | if (m->complete) |
329 | m->complete(m->context); | |
6e27388f | 330 | |
85085898 GS |
331 | if (status || !cs_change) |
332 | mpc512x_psc_spi_deactivate_cs(spi); | |
333 | ||
334 | mpc512x_psc_spi_transfer_setup(spi, NULL); | |
335 | ||
336 | spi_finalize_current_message(master); | |
337 | return status; | |
338 | } | |
339 | ||
340 | static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master) | |
341 | { | |
342 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); | |
85085898 GS |
343 | |
344 | dev_dbg(&master->dev, "%s()\n", __func__); | |
345 | ||
346 | /* Zero MR2 */ | |
8bf96098 UKK |
347 | in_8(psc_addr(mps, mr2)); |
348 | out_8(psc_addr(mps, mr2), 0x0); | |
85085898 GS |
349 | |
350 | /* enable transmitter/receiver */ | |
8bf96098 | 351 | out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); |
85085898 GS |
352 | |
353 | return 0; | |
354 | } | |
355 | ||
356 | static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master) | |
357 | { | |
358 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); | |
85085898 GS |
359 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; |
360 | ||
361 | dev_dbg(&master->dev, "%s()\n", __func__); | |
362 | ||
363 | /* disable transmitter/receiver and fifo interrupt */ | |
8bf96098 | 364 | out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); |
85085898 GS |
365 | out_be32(&fifo->tximr, 0); |
366 | ||
367 | return 0; | |
6e27388f AG |
368 | } |
369 | ||
370 | static int mpc512x_psc_spi_setup(struct spi_device *spi) | |
371 | { | |
6e27388f | 372 | struct mpc512x_psc_spi_cs *cs = spi->controller_state; |
86e98743 | 373 | int ret; |
6e27388f AG |
374 | |
375 | if (spi->bits_per_word % 8) | |
376 | return -EINVAL; | |
377 | ||
378 | if (!cs) { | |
379 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
380 | if (!cs) | |
381 | return -ENOMEM; | |
86e98743 AG |
382 | |
383 | if (gpio_is_valid(spi->cs_gpio)) { | |
384 | ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); | |
385 | if (ret) { | |
386 | dev_err(&spi->dev, "can't get CS gpio: %d\n", | |
387 | ret); | |
388 | kfree(cs); | |
389 | return ret; | |
390 | } | |
391 | gpio_direction_output(spi->cs_gpio, | |
392 | spi->mode & SPI_CS_HIGH ? 0 : 1); | |
393 | } | |
394 | ||
6e27388f AG |
395 | spi->controller_state = cs; |
396 | } | |
397 | ||
398 | cs->bits_per_word = spi->bits_per_word; | |
399 | cs->speed_hz = spi->max_speed_hz; | |
400 | ||
6e27388f AG |
401 | return 0; |
402 | } | |
403 | ||
404 | static void mpc512x_psc_spi_cleanup(struct spi_device *spi) | |
405 | { | |
86e98743 AG |
406 | if (gpio_is_valid(spi->cs_gpio)) |
407 | gpio_free(spi->cs_gpio); | |
6e27388f AG |
408 | kfree(spi->controller_state); |
409 | } | |
410 | ||
411 | static int mpc512x_psc_spi_port_config(struct spi_master *master, | |
412 | struct mpc512x_psc_spi *mps) | |
413 | { | |
6e27388f | 414 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; |
6e27388f AG |
415 | u32 sicr; |
416 | u32 ccr; | |
a81a5094 | 417 | int speed; |
6e27388f AG |
418 | u16 bclkdiv; |
419 | ||
6e27388f | 420 | /* Reset the PSC into a known state */ |
8bf96098 UKK |
421 | out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX); |
422 | out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX); | |
423 | out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); | |
6e27388f AG |
424 | |
425 | /* Disable psc interrupts all useful interrupts are in fifo */ | |
8bf96098 | 426 | out_be16(psc_addr(mps, isr_imr.imr), 0); |
6e27388f AG |
427 | |
428 | /* Disable fifo interrupts, will be enabled later */ | |
429 | out_be32(&fifo->tximr, 0); | |
430 | out_be32(&fifo->rximr, 0); | |
431 | ||
432 | /* Setup fifo slice address and size */ | |
433 | /*out_be32(&fifo->txsz, 0x0fe00004);*/ | |
434 | /*out_be32(&fifo->rxsz, 0x0ff00004);*/ | |
435 | ||
436 | sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */ | |
437 | 0x00800000 | /* GenClk = 1 -- internal clk */ | |
438 | 0x00008000 | /* SPI = 1 */ | |
439 | 0x00004000 | /* MSTR = 1 -- SPI master */ | |
440 | 0x00000800; /* UseEOF = 1 -- SS low until EOF */ | |
441 | ||
8bf96098 | 442 | out_be32(psc_addr(mps, sicr), sicr); |
6e27388f | 443 | |
8bf96098 | 444 | ccr = in_be32(psc_addr(mps, ccr)); |
6e27388f | 445 | ccr &= 0xFF000000; |
a81a5094 GS |
446 | speed = 1000000; /* default 1MHz */ |
447 | bclkdiv = (mps->mclk_rate / speed) - 1; | |
6e27388f | 448 | ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); |
8bf96098 | 449 | out_be32(psc_addr(mps, ccr), ccr); |
6e27388f AG |
450 | |
451 | /* Set 2ms DTL delay */ | |
8bf96098 UKK |
452 | out_8(psc_addr(mps, ctur), 0x00); |
453 | out_8(psc_addr(mps, ctlr), 0x82); | |
6e27388f AG |
454 | |
455 | /* we don't use the alarms */ | |
456 | out_be32(&fifo->rxalarm, 0xfff); | |
457 | out_be32(&fifo->txalarm, 0); | |
458 | ||
459 | /* Enable FIFO slices for Rx/Tx */ | |
460 | out_be32(&fifo->rxcmd, | |
461 | MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA); | |
462 | out_be32(&fifo->txcmd, | |
463 | MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA); | |
464 | ||
465 | mps->bits_per_word = 8; | |
466 | ||
a81a5094 | 467 | return 0; |
6e27388f AG |
468 | } |
469 | ||
470 | static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id) | |
471 | { | |
472 | struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id; | |
473 | struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; | |
474 | ||
85085898 | 475 | /* clear interrupt and wake up the rx/tx routine */ |
6e27388f AG |
476 | if (in_be32(&fifo->txisr) & |
477 | in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) { | |
478 | out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); | |
479 | out_be32(&fifo->tximr, 0); | |
c36e93a0 | 480 | complete(&mps->txisrdone); |
6e27388f AG |
481 | return IRQ_HANDLED; |
482 | } | |
483 | return IRQ_NONE; | |
484 | } | |
485 | ||
86e98743 AG |
486 | static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff) |
487 | { | |
488 | gpio_set_value(spi->cs_gpio, onoff); | |
489 | } | |
490 | ||
fd4a319b | 491 | static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr, |
3d8c8697 | 492 | u32 size, unsigned int irq) |
6e27388f | 493 | { |
8074cf06 | 494 | struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); |
6e27388f AG |
495 | struct mpc512x_psc_spi *mps; |
496 | struct spi_master *master; | |
497 | int ret; | |
498 | void *tempp; | |
a81a5094 | 499 | struct clk *clk; |
6e27388f AG |
500 | |
501 | master = spi_alloc_master(dev, sizeof *mps); | |
502 | if (master == NULL) | |
503 | return -ENOMEM; | |
504 | ||
505 | dev_set_drvdata(dev, master); | |
506 | mps = spi_master_get_devdata(master); | |
8bf96098 | 507 | mps->type = (int)of_device_get_match_data(dev); |
6e27388f AG |
508 | mps->irq = irq; |
509 | ||
510 | if (pdata == NULL) { | |
86e98743 | 511 | mps->cs_control = mpc512x_spi_cs_control; |
6e27388f AG |
512 | } else { |
513 | mps->cs_control = pdata->cs_control; | |
6e27388f AG |
514 | master->bus_num = pdata->bus_num; |
515 | master->num_chipselect = pdata->max_chipselect; | |
516 | } | |
517 | ||
c88dd349 | 518 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; |
6e27388f | 519 | master->setup = mpc512x_psc_spi_setup; |
85085898 GS |
520 | master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw; |
521 | master->transfer_one_message = mpc512x_psc_spi_msg_xfer; | |
522 | master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw; | |
6e27388f | 523 | master->cleanup = mpc512x_psc_spi_cleanup; |
12b15e83 | 524 | master->dev.of_node = dev->of_node; |
6e27388f | 525 | |
e1d0cd47 | 526 | tempp = devm_ioremap(dev, regaddr, size); |
6e27388f AG |
527 | if (!tempp) { |
528 | dev_err(dev, "could not ioremap I/O port range\n"); | |
529 | ret = -EFAULT; | |
530 | goto free_master; | |
531 | } | |
532 | mps->psc = tempp; | |
533 | mps->fifo = | |
534 | (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc)); | |
e1d0cd47 JH |
535 | ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED, |
536 | "mpc512x-psc-spi", mps); | |
6e27388f AG |
537 | if (ret) |
538 | goto free_master; | |
85085898 | 539 | init_completion(&mps->txisrdone); |
6e27388f | 540 | |
dff148ad | 541 | clk = devm_clk_get(dev, "mclk"); |
eadf69cf WY |
542 | if (IS_ERR(clk)) { |
543 | ret = PTR_ERR(clk); | |
e1d0cd47 | 544 | goto free_master; |
eadf69cf | 545 | } |
a81a5094 GS |
546 | ret = clk_prepare_enable(clk); |
547 | if (ret) | |
e1d0cd47 | 548 | goto free_master; |
a81a5094 GS |
549 | mps->clk_mclk = clk; |
550 | mps->mclk_rate = clk_get_rate(clk); | |
551 | ||
dff148ad GS |
552 | clk = devm_clk_get(dev, "ipg"); |
553 | if (IS_ERR(clk)) { | |
554 | ret = PTR_ERR(clk); | |
555 | goto free_mclk_clock; | |
556 | } | |
557 | ret = clk_prepare_enable(clk); | |
558 | if (ret) | |
559 | goto free_mclk_clock; | |
560 | mps->clk_ipg = clk; | |
561 | ||
6e27388f AG |
562 | ret = mpc512x_psc_spi_port_config(master, mps); |
563 | if (ret < 0) | |
dff148ad | 564 | goto free_ipg_clock; |
6e27388f | 565 | |
eaa24297 | 566 | ret = devm_spi_register_master(dev, master); |
6e27388f | 567 | if (ret < 0) |
dff148ad | 568 | goto free_ipg_clock; |
6e27388f AG |
569 | |
570 | return ret; | |
571 | ||
dff148ad GS |
572 | free_ipg_clock: |
573 | clk_disable_unprepare(mps->clk_ipg); | |
574 | free_mclk_clock: | |
a81a5094 | 575 | clk_disable_unprepare(mps->clk_mclk); |
6e27388f | 576 | free_master: |
6e27388f AG |
577 | spi_master_put(master); |
578 | ||
579 | return ret; | |
580 | } | |
581 | ||
fd4a319b | 582 | static int mpc512x_psc_spi_do_remove(struct device *dev) |
6e27388f | 583 | { |
a4469a42 | 584 | struct spi_master *master = dev_get_drvdata(dev); |
6e27388f AG |
585 | struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); |
586 | ||
a81a5094 | 587 | clk_disable_unprepare(mps->clk_mclk); |
dff148ad | 588 | clk_disable_unprepare(mps->clk_ipg); |
6e27388f AG |
589 | |
590 | return 0; | |
591 | } | |
592 | ||
fd4a319b | 593 | static int mpc512x_psc_spi_of_probe(struct platform_device *op) |
6e27388f AG |
594 | { |
595 | const u32 *regaddr_p; | |
596 | u64 regaddr64, size64; | |
6e27388f | 597 | |
ef7f2e83 | 598 | regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL); |
6e27388f AG |
599 | if (!regaddr_p) { |
600 | dev_err(&op->dev, "Invalid PSC address\n"); | |
601 | return -EINVAL; | |
602 | } | |
ef7f2e83 | 603 | regaddr64 = of_translate_address(op->dev.of_node, regaddr_p); |
6e27388f | 604 | |
6e27388f | 605 | return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64, |
3d8c8697 | 606 | irq_of_parse_and_map(op->dev.of_node, 0)); |
6e27388f AG |
607 | } |
608 | ||
fd4a319b | 609 | static int mpc512x_psc_spi_of_remove(struct platform_device *op) |
6e27388f AG |
610 | { |
611 | return mpc512x_psc_spi_do_remove(&op->dev); | |
612 | } | |
613 | ||
09355402 | 614 | static const struct of_device_id mpc512x_psc_spi_of_match[] = { |
8bf96098 UKK |
615 | { .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 }, |
616 | { .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 }, | |
6e27388f AG |
617 | {}, |
618 | }; | |
619 | ||
620 | MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match); | |
621 | ||
18d306d1 | 622 | static struct platform_driver mpc512x_psc_spi_of_driver = { |
6e27388f | 623 | .probe = mpc512x_psc_spi_of_probe, |
fd4a319b | 624 | .remove = mpc512x_psc_spi_of_remove, |
6e27388f AG |
625 | .driver = { |
626 | .name = "mpc512x-psc-spi", | |
ef7f2e83 | 627 | .of_match_table = mpc512x_psc_spi_of_match, |
6e27388f AG |
628 | }, |
629 | }; | |
940ab889 | 630 | module_platform_driver(mpc512x_psc_spi_of_driver); |
6e27388f AG |
631 | |
632 | MODULE_AUTHOR("John Rigby"); | |
633 | MODULE_DESCRIPTION("MPC512x PSC SPI Driver"); | |
634 | MODULE_LICENSE("GPL"); |