[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-mpc52xx-psc.c

/*
 * MPC52xx PSC in SPI mode driver.
 *
 * Maintainer: Dragos Carp
 *
 * Copyright (C) 2006 TOPTICA Photonics AG.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/workqueue.h>
#include <linux/completion.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/fsl_devices.h>
#include <linux/slab.h>

#include <asm/mpc52xx.h>
#include <asm/mpc52xx_psc.h>

#define MCLK 20000000 /* PSC port MClk in hz */

struct mpc52xx_psc_spi {
	/* fsl_spi_platform data */
	void (*cs_control)(struct spi_device *spi, bool on);
	u32 sysclk;

	/* driver internal data */
	struct mpc52xx_psc __iomem *psc;
	struct mpc52xx_psc_fifo __iomem *fifo;
	unsigned int irq;
	u8 bits_per_word;
	u8 busy;

	struct workqueue_struct *workqueue;
	struct work_struct work;

	struct list_head queue;
	spinlock_t lock;

	struct completion done;
};

/* controller state */
struct mpc52xx_psc_spi_cs {
	int bits_per_word;
	int speed_hz;
};

/* set clock freq, clock ramp, bits per work
 * if t is NULL then reset the values to the default values
 */
static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
		struct spi_transfer *t)
{
	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;

	cs->speed_hz = (t && t->speed_hz)
			? t->speed_hz : spi->max_speed_hz;
	cs->bits_per_word = (t && t->bits_per_word)
			? t->bits_per_word : spi->bits_per_word;
	cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
	return 0;
}

static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
{
	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	struct mpc52xx_psc __iomem *psc = mps->psc;
	u32 sicr;
	u16 ccr;

	sicr = in_be32(&psc->sicr);

	/* Set clock phase and polarity */
	if (spi->mode & SPI_CPHA)
		sicr |= 0x00001000;
	else
		sicr &= ~0x00001000;
	if (spi->mode & SPI_CPOL)
		sicr |= 0x00002000;
	else
		sicr &= ~0x00002000;

	if (spi->mode & SPI_LSB_FIRST)
		sicr |= 0x10000000;
	else
		sicr &= ~0x10000000;
	out_be32(&psc->sicr, sicr);

	/* Set clock frequency and bits per word
	 * Because psc->ccr is defined as 16bit register instead of 32bit
	 * just set the lower byte of BitClkDiv
	 */
	ccr = in_be16((u16 __iomem *)&psc->ccr);
	ccr &= 0xFF00;
	if (cs->speed_hz)
		ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
	else /* by default SPI Clk 1MHz */
		ccr |= (MCLK / 1000000 - 1) & 0xFF;
	out_be16((u16 __iomem *)&psc->ccr, ccr);
	mps->bits_per_word = cs->bits_per_word;

	if (mps->cs_control)
		mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
}

static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
{
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);

	if (mps->cs_control)
		mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
}

#define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
/* wake up when 80% fifo full */
#define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)

static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
						struct spi_transfer *t)
{
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	struct mpc52xx_psc __iomem *psc = mps->psc;
	struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
	unsigned rb = 0;	/* number of bytes receieved */
	unsigned sb = 0;	/* number of bytes sent */
	unsigned char *rx_buf = (unsigned char *)t->rx_buf;
	unsigned char *tx_buf = (unsigned char *)t->tx_buf;
	unsigned rfalarm;
	unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
	unsigned recv_at_once;
	int last_block = 0;

	if (!t->tx_buf && !t->rx_buf && t->len)
		return -EINVAL;

	/* enable transmiter/receiver */
	out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
	while (rb < t->len) {
		if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
			rfalarm = MPC52xx_PSC_RFALARM;
			last_block = 0;
		} else {
			send_at_once = t->len - sb;
			rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
			last_block = 1;
		}

		dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
		for (; send_at_once; sb++, send_at_once--) {
			/* set EOF flag before the last word is sent */
			if (send_at_once == 1 && last_block)
				out_8(&psc->ircr2, 0x01);

			if (tx_buf)
				out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
			else
				out_8(&psc->mpc52xx_psc_buffer_8, 0);
		}


		/* enable interrupts and wait for wake up
		 * if just one byte is expected the Rx FIFO genererates no
		 * FFULL interrupt, so activate the RxRDY interrupt
		 */
		out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
		if (t->len - rb == 1) {
			out_8(&psc->mode, 0);
		} else {
			out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
			out_be16(&fifo->rfalarm, rfalarm);
		}
		out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
		wait_for_completion(&mps->done);
		recv_at_once = in_be16(&fifo->rfnum);
		dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);

		send_at_once = recv_at_once;
		if (rx_buf) {
			for (; recv_at_once; rb++, recv_at_once--)
				rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
		} else {
			for (; recv_at_once; rb++, recv_at_once--)
				in_8(&psc->mpc52xx_psc_buffer_8);
		}
	}
	/* disable transmiter/receiver */
	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);

	return 0;
}

static void mpc52xx_psc_spi_work(struct work_struct *work)
{
	struct mpc52xx_psc_spi *mps =
		container_of(work, struct mpc52xx_psc_spi, work);

	spin_lock_irq(&mps->lock);
	mps->busy = 1;
	while (!list_empty(&mps->queue)) {
		struct spi_message *m;
		struct spi_device *spi;
		struct spi_transfer *t = NULL;
		unsigned cs_change;
		int status;

		m = container_of(mps->queue.next, struct spi_message, queue);
		list_del_init(&m->queue);
		spin_unlock_irq(&mps->lock);

		spi = m->spi;
		cs_change = 1;
		status = 0;
		list_for_each_entry (t, &m->transfers, transfer_list) {
			if (t->bits_per_word || t->speed_hz) {
				status = mpc52xx_psc_spi_transfer_setup(spi, t);
				if (status < 0)
					break;
			}

			if (cs_change)
				mpc52xx_psc_spi_activate_cs(spi);
			cs_change = t->cs_change;

			status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
			if (status)
				break;
			m->actual_length += t->len;

			if (t->delay_usecs)
				udelay(t->delay_usecs);

			if (cs_change)
				mpc52xx_psc_spi_deactivate_cs(spi);
		}

		m->status = status;
		m->complete(m->context);

		if (status || !cs_change)
			mpc52xx_psc_spi_deactivate_cs(spi);

		mpc52xx_psc_spi_transfer_setup(spi, NULL);

		spin_lock_irq(&mps->lock);
	}
	mps->busy = 0;
	spin_unlock_irq(&mps->lock);
}

static int mpc52xx_psc_spi_setup(struct spi_device *spi)
{
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
	unsigned long flags;

	if (spi->bits_per_word%8)
		return -EINVAL;

	if (!cs) {
		cs = kzalloc(sizeof *cs, GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}

	cs->bits_per_word = spi->bits_per_word;
	cs->speed_hz = spi->max_speed_hz;

	spin_lock_irqsave(&mps->lock, flags);
	if (!mps->busy)
		mpc52xx_psc_spi_deactivate_cs(spi);
	spin_unlock_irqrestore(&mps->lock, flags);

	return 0;
}

static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
		struct spi_message *m)
{
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	unsigned long flags;

	m->actual_length = 0;
	m->status = -EINPROGRESS;

	spin_lock_irqsave(&mps->lock, flags);
	list_add_tail(&m->queue, &mps->queue);
	queue_work(mps->workqueue, &mps->work);
	spin_unlock_irqrestore(&mps->lock, flags);

	return 0;
}

static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}

static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
{
	struct mpc52xx_psc __iomem *psc = mps->psc;
	struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
	u32 mclken_div;
	int ret;

	/* default sysclk is 512MHz */
	mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
	ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
	if (ret)
		return ret;

	/* Reset the PSC into a known state */
	out_8(&psc->command, MPC52xx_PSC_RST_RX);
	out_8(&psc->command, MPC52xx_PSC_RST_TX);
	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);

	/* Disable interrupts, interrupts are based on alarm level */
	out_be16(&psc->mpc52xx_psc_imr, 0);
	out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
	out_8(&fifo->rfcntl, 0);
	out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);

	/* Configure 8bit codec mode as a SPI master and use EOF flags */
	/* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
	out_be32(&psc->sicr, 0x0180C800);
	out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */

	/* Set 2ms DTL delay */
	out_8(&psc->ctur, 0x00);
	out_8(&psc->ctlr, 0x84);

	mps->bits_per_word = 8;

	return 0;
}

static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
{
	struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
	struct mpc52xx_psc __iomem *psc = mps->psc;

	/* disable interrupt and wake up the work queue */
	if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
		out_be16(&psc->mpc52xx_psc_imr, 0);
		complete(&mps->done);
		return IRQ_HANDLED;
	}
	return IRQ_NONE;
}

/* bus_num is used only for the case dev->platform_data == NULL */
static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
				u32 size, unsigned int irq, s16 bus_num)
{
	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
	struct mpc52xx_psc_spi *mps;
	struct spi_master *master;
	int ret;

	master = spi_alloc_master(dev, sizeof *mps);
	if (master == NULL)
		return -ENOMEM;

	dev_set_drvdata(dev, master);
	mps = spi_master_get_devdata(master);

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;

	mps->irq = irq;
	if (pdata == NULL) {
		dev_warn(dev,
			 "probe called without platform data, no cs_control function will be called\n");
		mps->cs_control = NULL;
		mps->sysclk = 0;
		master->bus_num = bus_num;
		master->num_chipselect = 255;
	} else {
		mps->cs_control = pdata->cs_control;
		mps->sysclk = pdata->sysclk;
		master->bus_num = pdata->bus_num;
		master->num_chipselect = pdata->max_chipselect;
	}
	master->setup = mpc52xx_psc_spi_setup;
	master->transfer = mpc52xx_psc_spi_transfer;
	master->cleanup = mpc52xx_psc_spi_cleanup;
	master->dev.of_node = dev->of_node;

	mps->psc = ioremap(regaddr, size);
	if (!mps->psc) {
		dev_err(dev, "could not ioremap I/O port range\n");
		ret = -EFAULT;
		goto free_master;
	}
	/* On the 5200, fifo regs are immediately ajacent to the psc regs */
	mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);

	ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
				mps);
	if (ret)
		goto free_master;

	ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
	if (ret < 0) {
		dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
		goto free_irq;
	}

	spin_lock_init(&mps->lock);
	init_completion(&mps->done);
	INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
	INIT_LIST_HEAD(&mps->queue);

	mps->workqueue = create_singlethread_workqueue(
		dev_name(master->dev.parent));
	if (mps->workqueue == NULL) {
		ret = -EBUSY;
		goto free_irq;
	}

	ret = spi_register_master(master);
	if (ret < 0)
		goto unreg_master;

	return ret;

unreg_master:
	destroy_workqueue(mps->workqueue);
free_irq:
	free_irq(mps->irq, mps);
free_master:
	if (mps->psc)
		iounmap(mps->psc);
	spi_master_put(master);

	return ret;
}

static int mpc52xx_psc_spi_of_probe(struct platform_device *op)
{
	const u32 *regaddr_p;
	u64 regaddr64, size64;
	s16 id = -1;

	regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
	if (!regaddr_p) {
		dev_err(&op->dev, "Invalid PSC address\n");
		return -EINVAL;
	}
	regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);

	/* get PSC id (1..6, used by port_config) */
	if (op->dev.platform_data == NULL) {
		const u32 *psc_nump;

		psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
		if (!psc_nump || *psc_nump > 5) {
			dev_err(&op->dev, "Invalid cell-index property\n");
			return -EINVAL;
		}
		id = *psc_nump + 1;
	}

	return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
				irq_of_parse_and_map(op->dev.of_node, 0), id);
}

static int mpc52xx_psc_spi_of_remove(struct platform_device *op)
{
	struct spi_master *master = spi_master_get(platform_get_drvdata(op));
	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);

	flush_workqueue(mps->workqueue);
	destroy_workqueue(mps->workqueue);
	spi_unregister_master(master);
	free_irq(mps->irq, mps);
	if (mps->psc)
		iounmap(mps->psc);
	spi_master_put(master);

	return 0;
}

static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
	{ .compatible = "fsl,mpc5200-psc-spi", },
	{ .compatible = "mpc5200-psc-spi", }, /* old */
	{}
};

MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);

static struct platform_driver mpc52xx_psc_spi_of_driver = {
	.probe = mpc52xx_psc_spi_of_probe,
	.remove = mpc52xx_psc_spi_of_remove,
	.driver = {
		.name = "mpc52xx-psc-spi",
		.owner = THIS_MODULE,
		.of_match_table = mpc52xx_psc_spi_of_match,
	},
};
module_platform_driver(mpc52xx_psc_spi_of_driver);

MODULE_AUTHOR("Dragos Carp");
MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
00b8fd23	1	/*
57cc0979	2	* MPC52xx PSC in SPI mode driver.
00b8fd23 DC	3	*
	4	* Maintainer: Dragos Carp
	5	*
	6	* Copyright (C) 2006 TOPTICA Photonics AG.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/module.h>
73902842	15	#include <linux/types.h>
00b8fd23 DC	16	#include <linux/errno.h>
00b8fd23 DC	17	#include <linux/interrupt.h>
22ae782f	18	#include <linux/of_address.h>
76ef7dd0	19	#include <linux/of_platform.h>
00b8fd23 DC	20	#include <linux/workqueue.h>
	21	#include <linux/completion.h>
	22	#include <linux/io.h>
	23	#include <linux/delay.h>
	24	#include <linux/spi/spi.h>
	25	#include <linux/fsl_devices.h>
5a0e3ad6	26	#include <linux/slab.h>
00b8fd23 DC	27
	28	#include <asm/mpc52xx.h>
	29	#include <asm/mpc52xx_psc.h>
	30
	31	#define MCLK 20000000 /* PSC port MClk in hz */
	32
	33	struct mpc52xx_psc_spi {
	34	/* fsl_spi_platform data */
73902842	35	void (cs_control)(struct spi_device spi, bool on);
00b8fd23 DC	36	u32 sysclk;
	37
	38	/* driver internal data */
	39	struct mpc52xx_psc __iomem *psc;
4874cc1b	40	struct mpc52xx_psc_fifo __iomem *fifo;
00b8fd23 DC	41	unsigned int irq;
	42	u8 bits_per_word;
	43	u8 busy;
	44
	45	struct workqueue_struct *workqueue;
	46	struct work_struct work;
	47
	48	struct list_head queue;
	49	spinlock_t lock;
	50
	51	struct completion done;
	52	};
	53
	54	/* controller state */
	55	struct mpc52xx_psc_spi_cs {
	56	int bits_per_word;
	57	int speed_hz;
	58	};
	59
	60	/* set clock freq, clock ramp, bits per work
	61	* if t is NULL then reset the values to the default values
	62	*/
	63	static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
	64	struct spi_transfer *t)
	65	{
	66	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
	67
	68	cs->speed_hz = (t && t->speed_hz)
	69	? t->speed_hz : spi->max_speed_hz;
	70	cs->bits_per_word = (t && t->bits_per_word)
	71	? t->bits_per_word : spi->bits_per_word;
	72	cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
	73	return 0;
	74	}
	75
	76	static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
	77	{
	78	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
	79	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	80	struct mpc52xx_psc __iomem *psc = mps->psc;
	81	u32 sicr;
	82	u16 ccr;
	83
	84	sicr = in_be32(&psc->sicr);
	85
	86	/* Set clock phase and polarity */
	87	if (spi->mode & SPI_CPHA)
	88	sicr \|= 0x00001000;
	89	else
	90	sicr &= ~0x00001000;
	91	if (spi->mode & SPI_CPOL)
	92	sicr \|= 0x00002000;
	93	else
	94	sicr &= ~0x00002000;
	95
	96	if (spi->mode & SPI_LSB_FIRST)
	97	sicr \|= 0x10000000;
	98	else
	99	sicr &= ~0x10000000;
	100	out_be32(&psc->sicr, sicr);
	101
	102	/* Set clock frequency and bits per word
	103	* Because psc->ccr is defined as 16bit register instead of 32bit
	104	* just set the lower byte of BitClkDiv
105	*/
a897ea13	106	ccr = in_be16((u16 __iomem *)&psc->ccr);
00b8fd23 DC	107	ccr &= 0xFF00;
	108	if (cs->speed_hz)
	109	ccr \|= (MCLK / cs->speed_hz - 1) & 0xFF;
	110	else /* by default SPI Clk 1MHz */
	111	ccr \|= (MCLK / 1000000 - 1) & 0xFF;
a897ea13	112	out_be16((u16 __iomem *)&psc->ccr, ccr);
00b8fd23 DC	113	mps->bits_per_word = cs->bits_per_word;
00b8fd23 DC	114
73902842 AV	115	if (mps->cs_control)
73902842 AV	116	mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
00b8fd23 DC	117	}
	118
	119	static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
	120	{
	121	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	122
73902842 AV	123	if (mps->cs_control)
73902842 AV	124	mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
00b8fd23 DC	125	}
	126
	127	#define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
	128	/* wake up when 80% fifo full */
	129	#define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
	130
	131	static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
	132	struct spi_transfer *t)
	133	{
	134	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
	135	struct mpc52xx_psc __iomem *psc = mps->psc;
4874cc1b	136	struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
00b8fd23 DC	137	unsigned rb = 0; /* number of bytes receieved */
	138	unsigned sb = 0; /* number of bytes sent */
	139	unsigned char rx_buf = (unsigned char )t->rx_buf;
	140	unsigned char tx_buf = (unsigned char )t->tx_buf;
	141	unsigned rfalarm;
	142	unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
	143	unsigned recv_at_once;
b7d271df	144	int last_block = 0;
00b8fd23 DC	145
	146	if (!t->tx_buf && !t->rx_buf && t->len)
	147	return -EINVAL;
	148
	149	/* enable transmiter/receiver */
	150	out_8(&psc->command, MPC52xx_PSC_TX_ENABLE \| MPC52xx_PSC_RX_ENABLE);
	151	while (rb < t->len) {
	152	if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
	153	rfalarm = MPC52xx_PSC_RFALARM;
b7d271df	154	last_block = 0;
00b8fd23 DC	155	} else {
	156	send_at_once = t->len - sb;
	157	rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
b7d271df	158	last_block = 1;
00b8fd23 DC	159	}
	160
	161	dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
9a7867e1 LF	162	for (; send_at_once; sb++, send_at_once--) {
9a7867e1 LF	163	/* set EOF flag before the last word is sent */
b7d271df	164	if (send_at_once == 1 && last_block)
9a7867e1 LF	165	out_8(&psc->ircr2, 0x01);
	166
	167	if (tx_buf)
00b8fd23	168	out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
9a7867e1	169	else
00b8fd23	170	out_8(&psc->mpc52xx_psc_buffer_8, 0);
00b8fd23 DC	171	}
	172
	173
3a4fa0a2	174	/* enable interrupts and wait for wake up
00b8fd23 DC	175	* if just one byte is expected the Rx FIFO genererates no
	176	* FFULL interrupt, so activate the RxRDY interrupt
	177	*/
	178	out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
	179	if (t->len - rb == 1) {
	180	out_8(&psc->mode, 0);
	181	} else {
	182	out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
4874cc1b	183	out_be16(&fifo->rfalarm, rfalarm);
00b8fd23 DC	184	}
	185	out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
	186	wait_for_completion(&mps->done);
4874cc1b	187	recv_at_once = in_be16(&fifo->rfnum);
00b8fd23 DC	188	dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
	189
	190	send_at_once = recv_at_once;
	191	if (rx_buf) {
	192	for (; recv_at_once; rb++, recv_at_once--)
	193	rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
	194	} else {
	195	for (; recv_at_once; rb++, recv_at_once--)
	196	in_8(&psc->mpc52xx_psc_buffer_8);
	197	}
	198	}
	199	/* disable transmiter/receiver */
	200	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE \| MPC52xx_PSC_RX_DISABLE);
	201
	202	return 0;
	203	}
	204
	205	static void mpc52xx_psc_spi_work(struct work_struct *work)
	206	{
	207	struct mpc52xx_psc_spi *mps =
	208	container_of(work, struct mpc52xx_psc_spi, work);
	209
	210	spin_lock_irq(&mps->lock);
	211	mps->busy = 1;
	212	while (!list_empty(&mps->queue)) {
	213	struct spi_message *m;
	214	struct spi_device *spi;
	215	struct spi_transfer *t = NULL;
	216	unsigned cs_change;
	217	int status;
	218
	219	m = container_of(mps->queue.next, struct spi_message, queue);
	220	list_del_init(&m->queue);
	221	spin_unlock_irq(&mps->lock);
	222
	223	spi = m->spi;
	224	cs_change = 1;
	225	status = 0;
	226	list_for_each_entry (t, &m->transfers, transfer_list) {
	227	if (t->bits_per_word \|\| t->speed_hz) {
	228	status = mpc52xx_psc_spi_transfer_setup(spi, t);
	229	if (status < 0)
	230	break;
	231	}
	232
	233	if (cs_change)
	234	mpc52xx_psc_spi_activate_cs(spi);
	235	cs_change = t->cs_change;
	236
	237	status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
	238	if (status)
	239	break;
	240	m->actual_length += t->len;
	241
	242	if (t->delay_usecs)
	243	udelay(t->delay_usecs);
	244
	245	if (cs_change)
	246	mpc52xx_psc_spi_deactivate_cs(spi);
	247	}
	248
	249	m->status = status;
	250	m->complete(m->context);
	251
252	if (status \|\| !cs_change)
253	mpc52xx_psc_spi_deactivate_cs(spi);
254
255	mpc52xx_psc_spi_transfer_setup(spi, NULL);
256
257	spin_lock_irq(&mps->lock);
258	}
259	mps->busy = 0;
260	spin_unlock_irq(&mps->lock);
261	}
262
263	static int mpc52xx_psc_spi_setup(struct spi_device *spi)
264	{
265	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
266	struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
267	unsigned long flags;
268
269	if (spi->bits_per_word%8)
270	return -EINVAL;
271
272	if (!cs) {
273	cs = kzalloc(sizeof *cs, GFP_KERNEL);
274	if (!cs)
275	return -ENOMEM;
276	spi->controller_state = cs;
277	}
278
279	cs->bits_per_word = spi->bits_per_word;
280	cs->speed_hz = spi->max_speed_hz;
281
282	spin_lock_irqsave(&mps->lock, flags);
283	if (!mps->busy)
284	mpc52xx_psc_spi_deactivate_cs(spi);
285	spin_unlock_irqrestore(&mps->lock, flags);
286
287	return 0;
288	}
289
290	static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
291	struct spi_message *m)
292	{
293	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
294	unsigned long flags;
295
296	m->actual_length = 0;
297	m->status = -EINPROGRESS;
298
299	spin_lock_irqsave(&mps->lock, flags);
300	list_add_tail(&m->queue, &mps->queue);
301	queue_work(mps->workqueue, &mps->work);
302	spin_unlock_irqrestore(&mps->lock, flags);
303
304	return 0;
305	}
306
307	static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
308	{
309	kfree(spi->controller_state);
310	}
311
312	static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
313	{
00b8fd23	314	struct mpc52xx_psc __iomem *psc = mps->psc;
4874cc1b	315	struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
00b8fd23	316	u32 mclken_div;
f856cf01	317	int ret;
00b8fd23	318
00b8fd23	319	/* default sysclk is 512MHz */
4fb4c558	320	mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
f856cf01 WS	321	ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
	322	if (ret)
	323	return ret;
00b8fd23 DC	324
	325	/* Reset the PSC into a known state */
	326	out_8(&psc->command, MPC52xx_PSC_RST_RX);
	327	out_8(&psc->command, MPC52xx_PSC_RST_TX);
	328	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE \| MPC52xx_PSC_RX_DISABLE);
	329
	330	/* Disable interrupts, interrupts are based on alarm level */
	331	out_be16(&psc->mpc52xx_psc_imr, 0);
	332	out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
4874cc1b	333	out_8(&fifo->rfcntl, 0);
00b8fd23 DC	334	out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
	335
	336	/* Configure 8bit codec mode as a SPI master and use EOF flags */
	337	/* SICR_SIM_CODEC8\|SICR_GENCLK\|SICR_SPI\|SICR_MSTR\|SICR_USEEOF */
	338	out_be32(&psc->sicr, 0x0180C800);
a897ea13	339	out_be16((u16 __iomem )&psc->ccr, 0x070F); / default SPI Clk 1MHz */
00b8fd23 DC	340
	341	/* Set 2ms DTL delay */
	342	out_8(&psc->ctur, 0x00);
	343	out_8(&psc->ctlr, 0x84);
	344
	345	mps->bits_per_word = 8;
	346
f856cf01	347	return 0;
00b8fd23 DC	348	}
	349
	350	static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
	351	{
	352	struct mpc52xx_psc_spi mps = (struct mpc52xx_psc_spi )dev_id;
	353	struct mpc52xx_psc __iomem *psc = mps->psc;
	354
	355	/* disable interrupt and wake up the work queue */
	356	if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
	357	out_be16(&psc->mpc52xx_psc_imr, 0);
	358	complete(&mps->done);
	359	return IRQ_HANDLED;
	360	}
	361	return IRQ_NONE;
	362	}
	363
	364	/* bus_num is used only for the case dev->platform_data == NULL */
fd4a319b	365	static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
00b8fd23 DC	366	u32 size, unsigned int irq, s16 bus_num)
00b8fd23 DC	367	{
8074cf06	368	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
00b8fd23 DC	369	struct mpc52xx_psc_spi *mps;
	370	struct spi_master *master;
	371	int ret;
	372
00b8fd23 DC	373	master = spi_alloc_master(dev, sizeof *mps);
	374	if (master == NULL)
	375	return -ENOMEM;
	376
	377	dev_set_drvdata(dev, master);
	378	mps = spi_master_get_devdata(master);
	379
e7db06b5 DB	380	/* the spi->mode bits understood by this driver: */
	381	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \| SPI_LSB_FIRST;
	382
00b8fd23 DC	383	mps->irq = irq;
00b8fd23 DC	384	if (pdata == NULL) {
f6bd03a7 JN	385	dev_warn(dev,
f6bd03a7 JN	386	"probe called without platform data, no cs_control function will be called\n");
73902842	387	mps->cs_control = NULL;
00b8fd23 DC	388	mps->sysclk = 0;
	389	master->bus_num = bus_num;
	390	master->num_chipselect = 255;
	391	} else {
73902842	392	mps->cs_control = pdata->cs_control;
00b8fd23 DC	393	mps->sysclk = pdata->sysclk;
	394	master->bus_num = pdata->bus_num;
	395	master->num_chipselect = pdata->max_chipselect;
	396	}
	397	master->setup = mpc52xx_psc_spi_setup;
	398	master->transfer = mpc52xx_psc_spi_transfer;
	399	master->cleanup = mpc52xx_psc_spi_cleanup;
12b15e83	400	master->dev.of_node = dev->of_node;
00b8fd23 DC	401
	402	mps->psc = ioremap(regaddr, size);
	403	if (!mps->psc) {
	404	dev_err(dev, "could not ioremap I/O port range\n");
	405	ret = -EFAULT;
	406	goto free_master;
	407	}
4874cc1b GL	408	/* On the 5200, fifo regs are immediately ajacent to the psc regs */
4874cc1b GL	409	mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
00b8fd23 DC	410
	411	ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
	412	mps);
	413	if (ret)
	414	goto free_master;
	415
	416	ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
f856cf01 WS	417	if (ret < 0) {
f856cf01 WS	418	dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
00b8fd23	419	goto free_irq;
f856cf01	420	}
00b8fd23 DC	421
	422	spin_lock_init(&mps->lock);
	423	init_completion(&mps->done);
	424	INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
	425	INIT_LIST_HEAD(&mps->queue);
	426
	427	mps->workqueue = create_singlethread_workqueue(
6c7377ab	428	dev_name(master->dev.parent));
00b8fd23 DC	429	if (mps->workqueue == NULL) {
	430	ret = -EBUSY;
	431	goto free_irq;
	432	}
	433
	434	ret = spi_register_master(master);
	435	if (ret < 0)
	436	goto unreg_master;
	437
	438	return ret;
	439
	440	unreg_master:
	441	destroy_workqueue(mps->workqueue);
	442	free_irq:
	443	free_irq(mps->irq, mps);
	444	free_master:
	445	if (mps->psc)
	446	iounmap(mps->psc);
	447	spi_master_put(master);
	448
	449	return ret;
	450	}
	451
fd4a319b	452	static int mpc52xx_psc_spi_of_probe(struct platform_device *op)
00b8fd23 DC	453	{
	454	const u32 *regaddr_p;
	455	u64 regaddr64, size64;
	456	s16 id = -1;
	457
61c7a080	458	regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
00b8fd23	459	if (!regaddr_p) {
5cc17d7e	460	dev_err(&op->dev, "Invalid PSC address\n");
00b8fd23 DC	461	return -EINVAL;
00b8fd23 DC	462	}
61c7a080	463	regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
00b8fd23	464
8888735f	465	/* get PSC id (1..6, used by port_config) */
00b8fd23	466	if (op->dev.platform_data == NULL) {
8888735f	467	const u32 *psc_nump;
00b8fd23	468
61c7a080	469	psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
8888735f	470	if (!psc_nump \|\| *psc_nump > 5) {
5cc17d7e	471	dev_err(&op->dev, "Invalid cell-index property\n");
8888735f	472	return -EINVAL;
00b8fd23	473	}
8888735f	474	id = *psc_nump + 1;
00b8fd23 DC	475	}
00b8fd23 DC	476
12b15e83	477	return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
61c7a080	478	irq_of_parse_and_map(op->dev.of_node, 0), id);
00b8fd23 DC	479	}
00b8fd23 DC	480
fd4a319b	481	static int mpc52xx_psc_spi_of_remove(struct platform_device *op)
00b8fd23	482	{
24b5a82c	483	struct spi_master *master = spi_master_get(platform_get_drvdata(op));
5aa68b85 WS	484	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
	485
	486	flush_workqueue(mps->workqueue);
	487	destroy_workqueue(mps->workqueue);
	488	spi_unregister_master(master);
	489	free_irq(mps->irq, mps);
	490	if (mps->psc)
	491	iounmap(mps->psc);
c8c87c65	492	spi_master_put(master);
5aa68b85 WS	493
5aa68b85 WS	494	return 0;
00b8fd23 DC	495	}
00b8fd23 DC	496
631e61b7	497	static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
66ffbe49 GL	498	{ .compatible = "fsl,mpc5200-psc-spi", },
	499	{ .compatible = "mpc5200-psc-spi", }, /* old */
	500	{}
00b8fd23 DC	501	};
	502
	503	MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
	504
18d306d1	505	static struct platform_driver mpc52xx_psc_spi_of_driver = {
00b8fd23	506	.probe = mpc52xx_psc_spi_of_probe,
fd4a319b	507	.remove = mpc52xx_psc_spi_of_remove,
00b8fd23 DC	508	.driver = {
	509	.name = "mpc52xx-psc-spi",
	510	.owner = THIS_MODULE,
4018294b	511	.of_match_table = mpc52xx_psc_spi_of_match,
00b8fd23 DC	512	},
00b8fd23 DC	513	};
940ab889	514	module_platform_driver(mpc52xx_psc_spi_of_driver);
00b8fd23	515
00b8fd23 DC	516	MODULE_AUTHOR("Dragos Carp");
	517	MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
	518	MODULE_LICENSE("GPL");