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[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-mt65xx.c
CommitLineData
a568231f
LL		 1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Leilk Liu <leilk.liu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/device.h>
17#include <linux/err.h>
18#include <linux/interrupt.h>
dd69a0a6 19#include <linux/io.h>
a568231f
LL		 20#include <linux/ioport.h>
21#include <linux/module.h>
22#include <linux/of.h>
37457607 23#include <linux/of_gpio.h>
a568231f
LL		 24#include <linux/platform_device.h>
25#include <linux/platform_data/spi-mt65xx.h>
26#include <linux/pm_runtime.h>
27#include <linux/spi/spi.h>
28
29#define SPI_CFG0_REG 0x0000
30#define SPI_CFG1_REG 0x0004
31#define SPI_TX_SRC_REG 0x0008
32#define SPI_RX_DST_REG 0x000c
33#define SPI_TX_DATA_REG 0x0010
34#define SPI_RX_DATA_REG 0x0014
35#define SPI_CMD_REG 0x0018
36#define SPI_STATUS0_REG 0x001c
37#define SPI_PAD_SEL_REG 0x0024
38
39#define SPI_CFG0_SCK_HIGH_OFFSET 0
40#define SPI_CFG0_SCK_LOW_OFFSET 8
41#define SPI_CFG0_CS_HOLD_OFFSET 16
42#define SPI_CFG0_CS_SETUP_OFFSET 24
43
44#define SPI_CFG1_CS_IDLE_OFFSET 0
45#define SPI_CFG1_PACKET_LOOP_OFFSET 8
46#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
47#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
48
49#define SPI_CFG1_CS_IDLE_MASK 0xff
50#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
51#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
52
a71d6ea6
LL		 53#define SPI_CMD_ACT BIT(0)
54#define SPI_CMD_RESUME BIT(1)
a568231f
LL		 55#define SPI_CMD_RST BIT(2)
56#define SPI_CMD_PAUSE_EN BIT(4)
57#define SPI_CMD_DEASSERT BIT(5)
58#define SPI_CMD_CPHA BIT(8)
59#define SPI_CMD_CPOL BIT(9)
60#define SPI_CMD_RX_DMA BIT(10)
61#define SPI_CMD_TX_DMA BIT(11)
62#define SPI_CMD_TXMSBF BIT(12)
63#define SPI_CMD_RXMSBF BIT(13)
64#define SPI_CMD_RX_ENDIAN BIT(14)
65#define SPI_CMD_TX_ENDIAN BIT(15)
66#define SPI_CMD_FINISH_IE BIT(16)
67#define SPI_CMD_PAUSE_IE BIT(17)
68
a568231f
LL		 69#define MT8173_SPI_MAX_PAD_SEL 3
70
50f8fec2
LL		 71#define MTK_SPI_PAUSE_INT_STATUS 0x2
72
a568231f
LL		 73#define MTK_SPI_IDLE 0
74#define MTK_SPI_PAUSED 1
75
1ce24864 76#define MTK_SPI_MAX_FIFO_SIZE 32U
a568231f
LL		 77#define MTK_SPI_PACKET_SIZE 1024
78
79struct mtk_spi_compatible {
af57937e
LL		 80 bool need_pad_sel;
81 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
82 bool must_tx;
a568231f
LL		 83};
84
85struct mtk_spi {
86 void __iomem *base;
87 u32 state;
37457607
LL		 88 int pad_num;
89 u32 *pad_sel;
adcbcfea 90 struct clk *parent_clk, *sel_clk, *spi_clk;
a568231f
LL		 91 struct spi_transfer *cur_transfer;
92 u32 xfer_len;
93 struct scatterlist *tx_sgl, *rx_sgl;
94 u32 tx_sgl_len, rx_sgl_len;
95 const struct mtk_spi_compatible *dev_comp;
96};
97
4eaf6f73 98static const struct mtk_spi_compatible mtk_common_compat;
a568231f 99static const struct mtk_spi_compatible mt8173_compat = {
af57937e
LL		 100 .need_pad_sel = true,
101 .must_tx = true,
a568231f
LL		 102};
103
104/*
105 * A piece of default chip info unless the platform
106 * supplies it.
107 */
108static const struct mtk_chip_config mtk_default_chip_info = {
109 .rx_mlsb = 1,
110 .tx_mlsb = 1,
a568231f
LL		 111};
112
113static const struct of_device_id mtk_spi_of_match[] = {
15bcdefd
LL		 114 { .compatible = "mediatek,mt2701-spi",
115 .data = (void *)&mtk_common_compat,
116 },
4eaf6f73
LL		 117 { .compatible = "mediatek,mt6589-spi",
118 .data = (void *)&mtk_common_compat,
119 },
120 { .compatible = "mediatek,mt8135-spi",
121 .data = (void *)&mtk_common_compat,
122 },
123 { .compatible = "mediatek,mt8173-spi",
124 .data = (void *)&mt8173_compat,
125 },
a568231f
LL		 126 {}
127};
128MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
129
130static void mtk_spi_reset(struct mtk_spi *mdata)
131{
132 u32 reg_val;
133
134 /* set the software reset bit in SPI_CMD_REG. */
135 reg_val = readl(mdata->base + SPI_CMD_REG);
136 reg_val |= SPI_CMD_RST;
137 writel(reg_val, mdata->base + SPI_CMD_REG);
138
139 reg_val = readl(mdata->base + SPI_CMD_REG);
140 reg_val &= ~SPI_CMD_RST;
141 writel(reg_val, mdata->base + SPI_CMD_REG);
142}
143
79b5d3f2
LL		 144static int mtk_spi_prepare_message(struct spi_master *master,
145 struct spi_message *msg)
a568231f 146{
79b5d3f2 147 u16 cpha, cpol;
a568231f 148 u32 reg_val;
79b5d3f2 149 struct spi_device *spi = msg->spi;
58a984c7 150 struct mtk_chip_config *chip_config = spi->controller_data;
79b5d3f2
LL		 151 struct mtk_spi *mdata = spi_master_get_devdata(master);
152
153 cpha = spi->mode & SPI_CPHA ? 1 : 0;
154 cpol = spi->mode & SPI_CPOL ? 1 : 0;
155
79b5d3f2
LL		 156 reg_val = readl(mdata->base + SPI_CMD_REG);
157 if (cpha)
158 reg_val |= SPI_CMD_CPHA;
159 else
160 reg_val &= ~SPI_CMD_CPHA;
161 if (cpol)
162 reg_val |= SPI_CMD_CPOL;
163 else
164 reg_val &= ~SPI_CMD_CPOL;
a568231f
LL		 165
166 /* set the mlsbx and mlsbtx */
a71d6ea6
LL		 167 if (chip_config->tx_mlsb)
168 reg_val |= SPI_CMD_TXMSBF;
169 else
170 reg_val &= ~SPI_CMD_TXMSBF;
171 if (chip_config->rx_mlsb)
172 reg_val |= SPI_CMD_RXMSBF;
173 else
174 reg_val &= ~SPI_CMD_RXMSBF;
a568231f
LL		 175
176 /* set the tx/rx endian */
44f636da
LL		 177#ifdef __LITTLE_ENDIAN
178 reg_val &= ~SPI_CMD_TX_ENDIAN;
179 reg_val &= ~SPI_CMD_RX_ENDIAN;
180#else
181 reg_val |= SPI_CMD_TX_ENDIAN;
182 reg_val |= SPI_CMD_RX_ENDIAN;
183#endif
a568231f
LL		 184
185 /* set finish and pause interrupt always enable */
15293324 186 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
a568231f
LL		 187
188 /* disable dma mode */
189 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
190
191 /* disable deassert mode */
192 reg_val &= ~SPI_CMD_DEASSERT;
193
194 writel(reg_val, mdata->base + SPI_CMD_REG);
195
196 /* pad select */
197 if (mdata->dev_comp->need_pad_sel)
37457607
LL		 198 writel(mdata->pad_sel[spi->chip_select],
199 mdata->base + SPI_PAD_SEL_REG);
a568231f
LL		 200
201 return 0;
202}
203
204static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
205{
206 u32 reg_val;
207 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
208
209 reg_val = readl(mdata->base + SPI_CMD_REG);
6583d203 210 if (!enable) {
a568231f 211 reg_val |= SPI_CMD_PAUSE_EN;
6583d203
LL		 212 writel(reg_val, mdata->base + SPI_CMD_REG);
213 } else {
a568231f 214 reg_val &= ~SPI_CMD_PAUSE_EN;
6583d203
LL		 215 writel(reg_val, mdata->base + SPI_CMD_REG);
216 mdata->state = MTK_SPI_IDLE;
217 mtk_spi_reset(mdata);
218 }
a568231f
LL		 219}
220
221static void mtk_spi_prepare_transfer(struct spi_master *master,
222 struct spi_transfer *xfer)
223{
2ce0acf5 224 u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
a568231f
LL		 225 struct mtk_spi *mdata = spi_master_get_devdata(master);
226
227 spi_clk_hz = clk_get_rate(mdata->spi_clk);
228 if (xfer->speed_hz < spi_clk_hz / 2)
229 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
230 else
231 div = 1;
232
2ce0acf5
LL		 233 sck_time = (div + 1) / 2;
234 cs_time = sck_time * 2;
a568231f 235
2ce0acf5
LL		 236 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
237 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
238 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
239 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
a568231f
LL		 240 writel(reg_val, mdata->base + SPI_CFG0_REG);
241
242 reg_val = readl(mdata->base + SPI_CFG1_REG);
243 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
2ce0acf5 244 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
a568231f
LL		 245 writel(reg_val, mdata->base + SPI_CFG1_REG);
246}
247
248static void mtk_spi_setup_packet(struct spi_master *master)
249{
250 u32 packet_size, packet_loop, reg_val;
251 struct mtk_spi *mdata = spi_master_get_devdata(master);
252
50f8fec2 253 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
a568231f
LL		 254 packet_loop = mdata->xfer_len / packet_size;
255
256 reg_val = readl(mdata->base + SPI_CFG1_REG);
50f8fec2 257 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
a568231f
LL		 258 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
259 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
260 writel(reg_val, mdata->base + SPI_CFG1_REG);
261}
262
263static void mtk_spi_enable_transfer(struct spi_master *master)
264{
50f8fec2 265 u32 cmd;
a568231f
LL		 266 struct mtk_spi *mdata = spi_master_get_devdata(master);
267
268 cmd = readl(mdata->base + SPI_CMD_REG);
269 if (mdata->state == MTK_SPI_IDLE)
a71d6ea6 270 cmd |= SPI_CMD_ACT;
a568231f 271 else
a71d6ea6 272 cmd |= SPI_CMD_RESUME;
a568231f
LL		 273 writel(cmd, mdata->base + SPI_CMD_REG);
274}
275
50f8fec2 276static int mtk_spi_get_mult_delta(u32 xfer_len)
a568231f 277{
50f8fec2 278 u32 mult_delta;
a568231f
LL		 279
280 if (xfer_len > MTK_SPI_PACKET_SIZE)
281 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
282 else
283 mult_delta = 0;
284
285 return mult_delta;
286}
287
288static void mtk_spi_update_mdata_len(struct spi_master *master)
289{
290 int mult_delta;
291 struct mtk_spi *mdata = spi_master_get_devdata(master);
292
293 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
294 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
295 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
296 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
297 mdata->rx_sgl_len = mult_delta;
298 mdata->tx_sgl_len -= mdata->xfer_len;
299 } else {
300 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
301 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
302 mdata->tx_sgl_len = mult_delta;
303 mdata->rx_sgl_len -= mdata->xfer_len;
304 }
305 } else if (mdata->tx_sgl_len) {
306 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
307 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
308 mdata->tx_sgl_len = mult_delta;
309 } else if (mdata->rx_sgl_len) {
310 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
311 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
312 mdata->rx_sgl_len = mult_delta;
313 }
314}
315
316static void mtk_spi_setup_dma_addr(struct spi_master *master,
317 struct spi_transfer *xfer)
318{
319 struct mtk_spi *mdata = spi_master_get_devdata(master);
320
321 if (mdata->tx_sgl)
39ba928f 322 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
a568231f 323 if (mdata->rx_sgl)
39ba928f 324 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
a568231f
LL		 325}
326
327static int mtk_spi_fifo_transfer(struct spi_master *master,
328 struct spi_device *spi,
329 struct spi_transfer *xfer)
330{
de327e49
NB		 331 int cnt, remainder;
332 u32 reg_val;
a568231f
LL		 333 struct mtk_spi *mdata = spi_master_get_devdata(master);
334
335 mdata->cur_transfer = xfer;
1ce24864 336 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
a568231f
LL		 337 mtk_spi_prepare_transfer(master, xfer);
338 mtk_spi_setup_packet(master);
339
de327e49 340 cnt = xfer->len / 4;
44f636da 341 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
a568231f 342
de327e49
NB		 343 remainder = xfer->len % 4;
344 if (remainder > 0) {
345 reg_val = 0;
346 memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
347 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
348 }
349
a568231f
LL		 350 mtk_spi_enable_transfer(master);
351
352 return 1;
353}
354
355static int mtk_spi_dma_transfer(struct spi_master *master,
356 struct spi_device *spi,
357 struct spi_transfer *xfer)
358{
359 int cmd;
360 struct mtk_spi *mdata = spi_master_get_devdata(master);
361
362 mdata->tx_sgl = NULL;
363 mdata->rx_sgl = NULL;
364 mdata->tx_sgl_len = 0;
365 mdata->rx_sgl_len = 0;
366 mdata->cur_transfer = xfer;
367
368 mtk_spi_prepare_transfer(master, xfer);
369
370 cmd = readl(mdata->base + SPI_CMD_REG);
371 if (xfer->tx_buf)
372 cmd |= SPI_CMD_TX_DMA;
373 if (xfer->rx_buf)
374 cmd |= SPI_CMD_RX_DMA;
375 writel(cmd, mdata->base + SPI_CMD_REG);
376
377 if (xfer->tx_buf)
378 mdata->tx_sgl = xfer->tx_sg.sgl;
379 if (xfer->rx_buf)
380 mdata->rx_sgl = xfer->rx_sg.sgl;
381
382 if (mdata->tx_sgl) {
383 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
384 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
385 }
386 if (mdata->rx_sgl) {
387 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
388 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
389 }
390
391 mtk_spi_update_mdata_len(master);
392 mtk_spi_setup_packet(master);
393 mtk_spi_setup_dma_addr(master, xfer);
394 mtk_spi_enable_transfer(master);
395
396 return 1;
397}
398
399static int mtk_spi_transfer_one(struct spi_master *master,
400 struct spi_device *spi,
401 struct spi_transfer *xfer)
402{
403 if (master->can_dma(master, spi, xfer))
404 return mtk_spi_dma_transfer(master, spi, xfer);
405 else
406 return mtk_spi_fifo_transfer(master, spi, xfer);
407}
408
409static bool mtk_spi_can_dma(struct spi_master *master,
410 struct spi_device *spi,
411 struct spi_transfer *xfer)
412{
1ce24864
DK		 413 /* Buffers for DMA transactions must be 4-byte aligned */
414 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
415 (unsigned long)xfer->tx_buf % 4 == 0 &&
416 (unsigned long)xfer->rx_buf % 4 == 0);
a568231f
LL		 417}
418
58a984c7
LL		 419static int mtk_spi_setup(struct spi_device *spi)
420{
421 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
422
423 if (!spi->controller_data)
424 spi->controller_data = (void *)&mtk_default_chip_info;
425
98c8dccf 426 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
37457607
LL		 427 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
428
58a984c7
LL		 429 return 0;
430}
431
a568231f
LL		 432static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
433{
de327e49 434 u32 cmd, reg_val, cnt, remainder;
a568231f
LL		 435 struct spi_master *master = dev_id;
436 struct mtk_spi *mdata = spi_master_get_devdata(master);
437 struct spi_transfer *trans = mdata->cur_transfer;
438
439 reg_val = readl(mdata->base + SPI_STATUS0_REG);
50f8fec2 440 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
a568231f
LL		 441 mdata->state = MTK_SPI_PAUSED;
442 else
443 mdata->state = MTK_SPI_IDLE;
444
445 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
a568231f 446 if (trans->rx_buf) {
de327e49 447 cnt = mdata->xfer_len / 4;
44f636da
LL		 448 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
449 trans->rx_buf, cnt);
de327e49
NB		 450 remainder = mdata->xfer_len % 4;
451 if (remainder > 0) {
452 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
453 memcpy(trans->rx_buf + (cnt * 4),
454 &reg_val, remainder);
455 }
a568231f 456 }
1ce24864
DK		 457
458 trans->len -= mdata->xfer_len;
459 if (!trans->len) {
460 spi_finalize_current_transfer(master);
461 return IRQ_HANDLED;
462 }
463
464 if (trans->tx_buf)
465 trans->tx_buf += mdata->xfer_len;
466 if (trans->rx_buf)
467 trans->rx_buf += mdata->xfer_len;
468
469 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, trans->len);
470 mtk_spi_setup_packet(master);
471
472 cnt = trans->len / 4;
473 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, trans->tx_buf, cnt);
474
475 remainder = trans->len % 4;
476 if (remainder > 0) {
477 reg_val = 0;
478 memcpy(&reg_val, trans->tx_buf + (cnt * 4), remainder);
479 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
480 }
481
482 mtk_spi_enable_transfer(master);
483
a568231f
LL		 484 return IRQ_HANDLED;
485 }
486
487 if (mdata->tx_sgl)
488 trans->tx_dma += mdata->xfer_len;
489 if (mdata->rx_sgl)
490 trans->rx_dma += mdata->xfer_len;
491
492 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
493 mdata->tx_sgl = sg_next(mdata->tx_sgl);
494 if (mdata->tx_sgl) {
495 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
496 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
497 }
498 }
499 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
500 mdata->rx_sgl = sg_next(mdata->rx_sgl);
501 if (mdata->rx_sgl) {
502 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
503 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
504 }
505 }
506
507 if (!mdata->tx_sgl && !mdata->rx_sgl) {
508 /* spi disable dma */
509 cmd = readl(mdata->base + SPI_CMD_REG);
510 cmd &= ~SPI_CMD_TX_DMA;
511 cmd &= ~SPI_CMD_RX_DMA;
512 writel(cmd, mdata->base + SPI_CMD_REG);
513
514 spi_finalize_current_transfer(master);
515 return IRQ_HANDLED;
516 }
517
518 mtk_spi_update_mdata_len(master);
519 mtk_spi_setup_packet(master);
520 mtk_spi_setup_dma_addr(master, trans);
521 mtk_spi_enable_transfer(master);
522
523 return IRQ_HANDLED;
524}
525
526static int mtk_spi_probe(struct platform_device *pdev)
527{
528 struct spi_master *master;
529 struct mtk_spi *mdata;
530 const struct of_device_id *of_id;
531 struct resource *res;
37457607 532 int i, irq, ret;
a568231f
LL		 533
534 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
535 if (!master) {
536 dev_err(&pdev->dev, "failed to alloc spi master\n");
537 return -ENOMEM;
538 }
539
540 master->auto_runtime_pm = true;
541 master->dev.of_node = pdev->dev.of_node;
542 master->mode_bits = SPI_CPOL | SPI_CPHA;
543
544 master->set_cs = mtk_spi_set_cs;
a568231f
LL		 545 master->prepare_message = mtk_spi_prepare_message;
546 master->transfer_one = mtk_spi_transfer_one;
547 master->can_dma = mtk_spi_can_dma;
58a984c7 548 master->setup = mtk_spi_setup;
a568231f
LL		 549
550 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
551 if (!of_id) {
552 dev_err(&pdev->dev, "failed to probe of_node\n");
553 ret = -EINVAL;
554 goto err_put_master;
555 }
556
557 mdata = spi_master_get_devdata(master);
558 mdata->dev_comp = of_id->data;
559 if (mdata->dev_comp->must_tx)
560 master->flags = SPI_MASTER_MUST_TX;
561
562 if (mdata->dev_comp->need_pad_sel) {
37457607
LL		 563 mdata->pad_num = of_property_count_u32_elems(
564 pdev->dev.of_node,
565 "mediatek,pad-select");
566 if (mdata->pad_num < 0) {
567 dev_err(&pdev->dev,
568 "No 'mediatek,pad-select' property\n");
569 ret = -EINVAL;
a568231f
LL		 570 goto err_put_master;
571 }
572
37457607
LL		 573 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
574 sizeof(u32), GFP_KERNEL);
575 if (!mdata->pad_sel) {
576 ret = -ENOMEM;
a568231f
LL		 577 goto err_put_master;
578 }
37457607
LL		 579
580 for (i = 0; i < mdata->pad_num; i++) {
581 of_property_read_u32_index(pdev->dev.of_node,
582 "mediatek,pad-select",
583 i, &mdata->pad_sel[i]);
584 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
585 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
586 i, mdata->pad_sel[i]);
587 ret = -EINVAL;
588 goto err_put_master;
589 }
590 }
a568231f
LL		 591 }
592
593 platform_set_drvdata(pdev, master);
594
595 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
596 if (!res) {
597 ret = -ENODEV;
598 dev_err(&pdev->dev, "failed to determine base address\n");
599 goto err_put_master;
600 }
601
602 mdata->base = devm_ioremap_resource(&pdev->dev, res);
603 if (IS_ERR(mdata->base)) {
604 ret = PTR_ERR(mdata->base);
605 goto err_put_master;
606 }
607
608 irq = platform_get_irq(pdev, 0);
609 if (irq < 0) {
610 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
611 ret = irq;
612 goto err_put_master;
613 }
614
615 if (!pdev->dev.dma_mask)
616 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
617
618 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
619 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
620 if (ret) {
621 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
622 goto err_put_master;
623 }
624
a568231f
LL		 625 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
626 if (IS_ERR(mdata->parent_clk)) {
627 ret = PTR_ERR(mdata->parent_clk);
628 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
629 goto err_put_master;
630 }
631
adcbcfea
LL		 632 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
633 if (IS_ERR(mdata->sel_clk)) {
e26d15f7 634 ret = PTR_ERR(mdata->sel_clk);
adcbcfea 635 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
a568231f
LL		 636 goto err_put_master;
637 }
638
adcbcfea
LL		 639 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
640 if (IS_ERR(mdata->spi_clk)) {
e26d15f7 641 ret = PTR_ERR(mdata->spi_clk);
adcbcfea 642 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
a568231f
LL		 643 goto err_put_master;
644 }
645
646 ret = clk_prepare_enable(mdata->spi_clk);
647 if (ret < 0) {
648 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
649 goto err_put_master;
650 }
651
adcbcfea 652 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
a568231f
LL		 653 if (ret < 0) {
654 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
e38da37f
LL		 655 clk_disable_unprepare(mdata->spi_clk);
656 goto err_put_master;
a568231f
LL		 657 }
658
659 clk_disable_unprepare(mdata->spi_clk);
660
661 pm_runtime_enable(&pdev->dev);
662
663 ret = devm_spi_register_master(&pdev->dev, master);
664 if (ret) {
665 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
e38da37f 666 goto err_disable_runtime_pm;
a568231f
LL		 667 }
668
37457607
LL		 669 if (mdata->dev_comp->need_pad_sel) {
670 if (mdata->pad_num != master->num_chipselect) {
671 dev_err(&pdev->dev,
672 "pad_num does not match num_chipselect(%d != %d)\n",
673 mdata->pad_num, master->num_chipselect);
674 ret = -EINVAL;
e38da37f 675 goto err_disable_runtime_pm;
37457607
LL		 676 }
677
98c8dccf
NB		 678 if (!master->cs_gpios && master->num_chipselect > 1) {
679 dev_err(&pdev->dev,
680 "cs_gpios not specified and num_chipselect > 1\n");
681 ret = -EINVAL;
e38da37f 682 goto err_disable_runtime_pm;
98c8dccf
NB		 683 }
684
685 if (master->cs_gpios) {
686 for (i = 0; i < master->num_chipselect; i++) {
687 ret = devm_gpio_request(&pdev->dev,
688 master->cs_gpios[i],
689 dev_name(&pdev->dev));
690 if (ret) {
691 dev_err(&pdev->dev,
692 "can't get CS GPIO %i\n", i);
e38da37f 693 goto err_disable_runtime_pm;
98c8dccf 694 }
37457607
LL		 695 }
696 }
697 }
698
a568231f
LL		 699 return 0;
700
e38da37f
LL		 701err_disable_runtime_pm:
702 pm_runtime_disable(&pdev->dev);
a568231f
LL		 703err_put_master:
704 spi_master_put(master);
705
706 return ret;
707}
708
709static int mtk_spi_remove(struct platform_device *pdev)
710{
711 struct spi_master *master = platform_get_drvdata(pdev);
712 struct mtk_spi *mdata = spi_master_get_devdata(master);
713
714 pm_runtime_disable(&pdev->dev);
715
716 mtk_spi_reset(mdata);
a568231f
LL		 717
718 return 0;
719}
720
721#ifdef CONFIG_PM_SLEEP
722static int mtk_spi_suspend(struct device *dev)
723{
724 int ret;
725 struct spi_master *master = dev_get_drvdata(dev);
726 struct mtk_spi *mdata = spi_master_get_devdata(master);
727
728 ret = spi_master_suspend(master);
729 if (ret)
730 return ret;
731
732 if (!pm_runtime_suspended(dev))
733 clk_disable_unprepare(mdata->spi_clk);
734
735 return ret;
736}
737
738static int mtk_spi_resume(struct device *dev)
739{
740 int ret;
741 struct spi_master *master = dev_get_drvdata(dev);
742 struct mtk_spi *mdata = spi_master_get_devdata(master);
743
744 if (!pm_runtime_suspended(dev)) {
745 ret = clk_prepare_enable(mdata->spi_clk);
13da5a0b
LL		 746 if (ret < 0) {
747 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
a568231f 748 return ret;
13da5a0b 749 }
a568231f
LL		 750 }
751
752 ret = spi_master_resume(master);
753 if (ret < 0)
754 clk_disable_unprepare(mdata->spi_clk);
755
756 return ret;
757}
758#endif /* CONFIG_PM_SLEEP */
759
760#ifdef CONFIG_PM
761static int mtk_spi_runtime_suspend(struct device *dev)
762{
763 struct spi_master *master = dev_get_drvdata(dev);
764 struct mtk_spi *mdata = spi_master_get_devdata(master);
765
766 clk_disable_unprepare(mdata->spi_clk);
767
768 return 0;
769}
770
771static int mtk_spi_runtime_resume(struct device *dev)
772{
773 struct spi_master *master = dev_get_drvdata(dev);
774 struct mtk_spi *mdata = spi_master_get_devdata(master);
13da5a0b
LL		 775 int ret;
776
777 ret = clk_prepare_enable(mdata->spi_clk);
778 if (ret < 0) {
779 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
780 return ret;
781 }
a568231f 782
13da5a0b 783 return 0;
a568231f
LL		 784}
785#endif /* CONFIG_PM */
786
787static const struct dev_pm_ops mtk_spi_pm = {
788 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
789 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
790 mtk_spi_runtime_resume, NULL)
791};
792
4299aaaa 793static struct platform_driver mtk_spi_driver = {
a568231f
LL		 794 .driver = {
795 .name = "mtk-spi",
796 .pm = &mtk_spi_pm,
797 .of_match_table = mtk_spi_of_match,
798 },
799 .probe = mtk_spi_probe,
800 .remove = mtk_spi_remove,
801};
802
803module_platform_driver(mtk_spi_driver);
804
805MODULE_DESCRIPTION("MTK SPI Controller driver");
806MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
807MODULE_LICENSE("GPL v2");
e4001885 808MODULE_ALIAS("platform:mtk-spi");
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