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spi: mediatek: handle controller_data in mtk_spi_setup
[mirror_ubuntu-hirsute-kernel.git] / drivers / spi / spi-mt65xx.c
CommitLineData
a568231f
LL		 1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Leilk Liu <leilk.liu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/device.h>
17#include <linux/err.h>
18#include <linux/interrupt.h>
dd69a0a6 19#include <linux/io.h>
a568231f
LL		 20#include <linux/ioport.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/platform_data/spi-mt65xx.h>
25#include <linux/pm_runtime.h>
26#include <linux/spi/spi.h>
27
28#define SPI_CFG0_REG 0x0000
29#define SPI_CFG1_REG 0x0004
30#define SPI_TX_SRC_REG 0x0008
31#define SPI_RX_DST_REG 0x000c
32#define SPI_TX_DATA_REG 0x0010
33#define SPI_RX_DATA_REG 0x0014
34#define SPI_CMD_REG 0x0018
35#define SPI_STATUS0_REG 0x001c
36#define SPI_PAD_SEL_REG 0x0024
37
38#define SPI_CFG0_SCK_HIGH_OFFSET 0
39#define SPI_CFG0_SCK_LOW_OFFSET 8
40#define SPI_CFG0_CS_HOLD_OFFSET 16
41#define SPI_CFG0_CS_SETUP_OFFSET 24
42
43#define SPI_CFG1_CS_IDLE_OFFSET 0
44#define SPI_CFG1_PACKET_LOOP_OFFSET 8
45#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
46#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
47
48#define SPI_CFG1_CS_IDLE_MASK 0xff
49#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
50#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
51
a71d6ea6
LL		 52#define SPI_CMD_ACT BIT(0)
53#define SPI_CMD_RESUME BIT(1)
a568231f
LL		 54#define SPI_CMD_RST BIT(2)
55#define SPI_CMD_PAUSE_EN BIT(4)
56#define SPI_CMD_DEASSERT BIT(5)
57#define SPI_CMD_CPHA BIT(8)
58#define SPI_CMD_CPOL BIT(9)
59#define SPI_CMD_RX_DMA BIT(10)
60#define SPI_CMD_TX_DMA BIT(11)
61#define SPI_CMD_TXMSBF BIT(12)
62#define SPI_CMD_RXMSBF BIT(13)
63#define SPI_CMD_RX_ENDIAN BIT(14)
64#define SPI_CMD_TX_ENDIAN BIT(15)
65#define SPI_CMD_FINISH_IE BIT(16)
66#define SPI_CMD_PAUSE_IE BIT(17)
67
a568231f
LL		 68#define MT8173_SPI_MAX_PAD_SEL 3
69
50f8fec2
LL		 70#define MTK_SPI_PAUSE_INT_STATUS 0x2
71
a568231f
LL		 72#define MTK_SPI_IDLE 0
73#define MTK_SPI_PAUSED 1
74
75#define MTK_SPI_MAX_FIFO_SIZE 32
76#define MTK_SPI_PACKET_SIZE 1024
77
78struct mtk_spi_compatible {
af57937e
LL		 79 bool need_pad_sel;
80 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
81 bool must_tx;
a568231f
LL		 82};
83
84struct mtk_spi {
85 void __iomem *base;
86 u32 state;
87 u32 pad_sel;
adcbcfea 88 struct clk *parent_clk, *sel_clk, *spi_clk;
a568231f
LL		 89 struct spi_transfer *cur_transfer;
90 u32 xfer_len;
91 struct scatterlist *tx_sgl, *rx_sgl;
92 u32 tx_sgl_len, rx_sgl_len;
93 const struct mtk_spi_compatible *dev_comp;
94};
95
af57937e
LL		 96static const struct mtk_spi_compatible mt6589_compat;
97static const struct mtk_spi_compatible mt8135_compat;
a568231f 98static const struct mtk_spi_compatible mt8173_compat = {
af57937e
LL		 99 .need_pad_sel = true,
100 .must_tx = true,
a568231f
LL		 101};
102
103/*
104 * A piece of default chip info unless the platform
105 * supplies it.
106 */
107static const struct mtk_chip_config mtk_default_chip_info = {
108 .rx_mlsb = 1,
109 .tx_mlsb = 1,
a568231f
LL		 110};
111
112static const struct of_device_id mtk_spi_of_match[] = {
113 { .compatible = "mediatek,mt6589-spi", .data = (void *)&mt6589_compat },
114 { .compatible = "mediatek,mt8135-spi", .data = (void *)&mt8135_compat },
115 { .compatible = "mediatek,mt8173-spi", .data = (void *)&mt8173_compat },
116 {}
117};
118MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
119
120static void mtk_spi_reset(struct mtk_spi *mdata)
121{
122 u32 reg_val;
123
124 /* set the software reset bit in SPI_CMD_REG. */
125 reg_val = readl(mdata->base + SPI_CMD_REG);
126 reg_val |= SPI_CMD_RST;
127 writel(reg_val, mdata->base + SPI_CMD_REG);
128
129 reg_val = readl(mdata->base + SPI_CMD_REG);
130 reg_val &= ~SPI_CMD_RST;
131 writel(reg_val, mdata->base + SPI_CMD_REG);
132}
133
79b5d3f2
LL		 134static int mtk_spi_prepare_message(struct spi_master *master,
135 struct spi_message *msg)
a568231f 136{
79b5d3f2 137 u16 cpha, cpol;
a568231f 138 u32 reg_val;
79b5d3f2 139 struct spi_device *spi = msg->spi;
58a984c7 140 struct mtk_chip_config *chip_config = spi->controller_data;
79b5d3f2
LL		 141 struct mtk_spi *mdata = spi_master_get_devdata(master);
142
143 cpha = spi->mode & SPI_CPHA ? 1 : 0;
144 cpol = spi->mode & SPI_CPOL ? 1 : 0;
145
79b5d3f2
LL		 146 reg_val = readl(mdata->base + SPI_CMD_REG);
147 if (cpha)
148 reg_val |= SPI_CMD_CPHA;
149 else
150 reg_val &= ~SPI_CMD_CPHA;
151 if (cpol)
152 reg_val |= SPI_CMD_CPOL;
153 else
154 reg_val &= ~SPI_CMD_CPOL;
155 writel(reg_val, mdata->base + SPI_CMD_REG);
a568231f
LL		 156
157 reg_val = readl(mdata->base + SPI_CMD_REG);
158
159 /* set the mlsbx and mlsbtx */
a71d6ea6
LL		 160 if (chip_config->tx_mlsb)
161 reg_val |= SPI_CMD_TXMSBF;
162 else
163 reg_val &= ~SPI_CMD_TXMSBF;
164 if (chip_config->rx_mlsb)
165 reg_val |= SPI_CMD_RXMSBF;
166 else
167 reg_val &= ~SPI_CMD_RXMSBF;
a568231f
LL		 168
169 /* set the tx/rx endian */
44f636da
LL		 170#ifdef __LITTLE_ENDIAN
171 reg_val &= ~SPI_CMD_TX_ENDIAN;
172 reg_val &= ~SPI_CMD_RX_ENDIAN;
173#else
174 reg_val |= SPI_CMD_TX_ENDIAN;
175 reg_val |= SPI_CMD_RX_ENDIAN;
176#endif
a568231f
LL		 177
178 /* set finish and pause interrupt always enable */
15293324 179 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
a568231f
LL		 180
181 /* disable dma mode */
182 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
183
184 /* disable deassert mode */
185 reg_val &= ~SPI_CMD_DEASSERT;
186
187 writel(reg_val, mdata->base + SPI_CMD_REG);
188
189 /* pad select */
190 if (mdata->dev_comp->need_pad_sel)
191 writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG);
a568231f
LL		 192
193 return 0;
194}
195
196static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
197{
198 u32 reg_val;
199 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
200
201 reg_val = readl(mdata->base + SPI_CMD_REG);
6583d203 202 if (!enable) {
a568231f 203 reg_val |= SPI_CMD_PAUSE_EN;
6583d203
LL		 204 writel(reg_val, mdata->base + SPI_CMD_REG);
205 } else {
a568231f 206 reg_val &= ~SPI_CMD_PAUSE_EN;
6583d203
LL		 207 writel(reg_val, mdata->base + SPI_CMD_REG);
208 mdata->state = MTK_SPI_IDLE;
209 mtk_spi_reset(mdata);
210 }
a568231f
LL		 211}
212
213static void mtk_spi_prepare_transfer(struct spi_master *master,
214 struct spi_transfer *xfer)
215{
2ce0acf5 216 u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
a568231f
LL		 217 struct mtk_spi *mdata = spi_master_get_devdata(master);
218
219 spi_clk_hz = clk_get_rate(mdata->spi_clk);
220 if (xfer->speed_hz < spi_clk_hz / 2)
221 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
222 else
223 div = 1;
224
2ce0acf5
LL		 225 sck_time = (div + 1) / 2;
226 cs_time = sck_time * 2;
a568231f 227
2ce0acf5
LL		 228 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
229 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
230 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
231 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
a568231f
LL		 232 writel(reg_val, mdata->base + SPI_CFG0_REG);
233
234 reg_val = readl(mdata->base + SPI_CFG1_REG);
235 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
2ce0acf5 236 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
a568231f
LL		 237 writel(reg_val, mdata->base + SPI_CFG1_REG);
238}
239
240static void mtk_spi_setup_packet(struct spi_master *master)
241{
242 u32 packet_size, packet_loop, reg_val;
243 struct mtk_spi *mdata = spi_master_get_devdata(master);
244
50f8fec2 245 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
a568231f
LL		 246 packet_loop = mdata->xfer_len / packet_size;
247
248 reg_val = readl(mdata->base + SPI_CFG1_REG);
50f8fec2 249 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
a568231f
LL		 250 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
251 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
252 writel(reg_val, mdata->base + SPI_CFG1_REG);
253}
254
255static void mtk_spi_enable_transfer(struct spi_master *master)
256{
50f8fec2 257 u32 cmd;
a568231f
LL		 258 struct mtk_spi *mdata = spi_master_get_devdata(master);
259
260 cmd = readl(mdata->base + SPI_CMD_REG);
261 if (mdata->state == MTK_SPI_IDLE)
a71d6ea6 262 cmd |= SPI_CMD_ACT;
a568231f 263 else
a71d6ea6 264 cmd |= SPI_CMD_RESUME;
a568231f
LL		 265 writel(cmd, mdata->base + SPI_CMD_REG);
266}
267
50f8fec2 268static int mtk_spi_get_mult_delta(u32 xfer_len)
a568231f 269{
50f8fec2 270 u32 mult_delta;
a568231f
LL		 271
272 if (xfer_len > MTK_SPI_PACKET_SIZE)
273 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
274 else
275 mult_delta = 0;
276
277 return mult_delta;
278}
279
280static void mtk_spi_update_mdata_len(struct spi_master *master)
281{
282 int mult_delta;
283 struct mtk_spi *mdata = spi_master_get_devdata(master);
284
285 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
286 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
287 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
288 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
289 mdata->rx_sgl_len = mult_delta;
290 mdata->tx_sgl_len -= mdata->xfer_len;
291 } else {
292 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
293 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
294 mdata->tx_sgl_len = mult_delta;
295 mdata->rx_sgl_len -= mdata->xfer_len;
296 }
297 } else if (mdata->tx_sgl_len) {
298 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
299 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
300 mdata->tx_sgl_len = mult_delta;
301 } else if (mdata->rx_sgl_len) {
302 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
303 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
304 mdata->rx_sgl_len = mult_delta;
305 }
306}
307
308static void mtk_spi_setup_dma_addr(struct spi_master *master,
309 struct spi_transfer *xfer)
310{
311 struct mtk_spi *mdata = spi_master_get_devdata(master);
312
313 if (mdata->tx_sgl)
39ba928f 314 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
a568231f 315 if (mdata->rx_sgl)
39ba928f 316 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
a568231f
LL		 317}
318
319static int mtk_spi_fifo_transfer(struct spi_master *master,
320 struct spi_device *spi,
321 struct spi_transfer *xfer)
322{
44f636da 323 int cnt;
a568231f
LL		 324 struct mtk_spi *mdata = spi_master_get_devdata(master);
325
326 mdata->cur_transfer = xfer;
327 mdata->xfer_len = xfer->len;
328 mtk_spi_prepare_transfer(master, xfer);
329 mtk_spi_setup_packet(master);
330
331 if (xfer->len % 4)
332 cnt = xfer->len / 4 + 1;
333 else
334 cnt = xfer->len / 4;
44f636da 335 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
a568231f
LL		 336
337 mtk_spi_enable_transfer(master);
338
339 return 1;
340}
341
342static int mtk_spi_dma_transfer(struct spi_master *master,
343 struct spi_device *spi,
344 struct spi_transfer *xfer)
345{
346 int cmd;
347 struct mtk_spi *mdata = spi_master_get_devdata(master);
348
349 mdata->tx_sgl = NULL;
350 mdata->rx_sgl = NULL;
351 mdata->tx_sgl_len = 0;
352 mdata->rx_sgl_len = 0;
353 mdata->cur_transfer = xfer;
354
355 mtk_spi_prepare_transfer(master, xfer);
356
357 cmd = readl(mdata->base + SPI_CMD_REG);
358 if (xfer->tx_buf)
359 cmd |= SPI_CMD_TX_DMA;
360 if (xfer->rx_buf)
361 cmd |= SPI_CMD_RX_DMA;
362 writel(cmd, mdata->base + SPI_CMD_REG);
363
364 if (xfer->tx_buf)
365 mdata->tx_sgl = xfer->tx_sg.sgl;
366 if (xfer->rx_buf)
367 mdata->rx_sgl = xfer->rx_sg.sgl;
368
369 if (mdata->tx_sgl) {
370 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
371 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
372 }
373 if (mdata->rx_sgl) {
374 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
375 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
376 }
377
378 mtk_spi_update_mdata_len(master);
379 mtk_spi_setup_packet(master);
380 mtk_spi_setup_dma_addr(master, xfer);
381 mtk_spi_enable_transfer(master);
382
383 return 1;
384}
385
386static int mtk_spi_transfer_one(struct spi_master *master,
387 struct spi_device *spi,
388 struct spi_transfer *xfer)
389{
390 if (master->can_dma(master, spi, xfer))
391 return mtk_spi_dma_transfer(master, spi, xfer);
392 else
393 return mtk_spi_fifo_transfer(master, spi, xfer);
394}
395
396static bool mtk_spi_can_dma(struct spi_master *master,
397 struct spi_device *spi,
398 struct spi_transfer *xfer)
399{
400 return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
401}
402
58a984c7
LL		 403static int mtk_spi_setup(struct spi_device *spi)
404{
405 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
406
407 if (!spi->controller_data)
408 spi->controller_data = (void *)&mtk_default_chip_info;
409
410 return 0;
411}
412
a568231f
LL		 413static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
414{
44f636da 415 u32 cmd, reg_val, cnt;
a568231f
LL		 416 struct spi_master *master = dev_id;
417 struct mtk_spi *mdata = spi_master_get_devdata(master);
418 struct spi_transfer *trans = mdata->cur_transfer;
419
420 reg_val = readl(mdata->base + SPI_STATUS0_REG);
50f8fec2 421 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
a568231f
LL		 422 mdata->state = MTK_SPI_PAUSED;
423 else
424 mdata->state = MTK_SPI_IDLE;
425
426 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
a568231f 427 if (trans->rx_buf) {
44f636da
LL		 428 if (mdata->xfer_len % 4)
429 cnt = mdata->xfer_len / 4 + 1;
430 else
431 cnt = mdata->xfer_len / 4;
432 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
433 trans->rx_buf, cnt);
a568231f
LL		 434 }
435 spi_finalize_current_transfer(master);
436 return IRQ_HANDLED;
437 }
438
439 if (mdata->tx_sgl)
440 trans->tx_dma += mdata->xfer_len;
441 if (mdata->rx_sgl)
442 trans->rx_dma += mdata->xfer_len;
443
444 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
445 mdata->tx_sgl = sg_next(mdata->tx_sgl);
446 if (mdata->tx_sgl) {
447 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
448 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
449 }
450 }
451 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
452 mdata->rx_sgl = sg_next(mdata->rx_sgl);
453 if (mdata->rx_sgl) {
454 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
455 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
456 }
457 }
458
459 if (!mdata->tx_sgl && !mdata->rx_sgl) {
460 /* spi disable dma */
461 cmd = readl(mdata->base + SPI_CMD_REG);
462 cmd &= ~SPI_CMD_TX_DMA;
463 cmd &= ~SPI_CMD_RX_DMA;
464 writel(cmd, mdata->base + SPI_CMD_REG);
465
466 spi_finalize_current_transfer(master);
467 return IRQ_HANDLED;
468 }
469
470 mtk_spi_update_mdata_len(master);
471 mtk_spi_setup_packet(master);
472 mtk_spi_setup_dma_addr(master, trans);
473 mtk_spi_enable_transfer(master);
474
475 return IRQ_HANDLED;
476}
477
478static int mtk_spi_probe(struct platform_device *pdev)
479{
480 struct spi_master *master;
481 struct mtk_spi *mdata;
482 const struct of_device_id *of_id;
483 struct resource *res;
50f8fec2 484 int irq, ret;
a568231f
LL		 485
486 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
487 if (!master) {
488 dev_err(&pdev->dev, "failed to alloc spi master\n");
489 return -ENOMEM;
490 }
491
492 master->auto_runtime_pm = true;
493 master->dev.of_node = pdev->dev.of_node;
494 master->mode_bits = SPI_CPOL | SPI_CPHA;
495
496 master->set_cs = mtk_spi_set_cs;
a568231f
LL		 497 master->prepare_message = mtk_spi_prepare_message;
498 master->transfer_one = mtk_spi_transfer_one;
499 master->can_dma = mtk_spi_can_dma;
58a984c7 500 master->setup = mtk_spi_setup;
a568231f
LL		 501
502 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
503 if (!of_id) {
504 dev_err(&pdev->dev, "failed to probe of_node\n");
505 ret = -EINVAL;
506 goto err_put_master;
507 }
508
509 mdata = spi_master_get_devdata(master);
510 mdata->dev_comp = of_id->data;
511 if (mdata->dev_comp->must_tx)
512 master->flags = SPI_MASTER_MUST_TX;
513
514 if (mdata->dev_comp->need_pad_sel) {
515 ret = of_property_read_u32(pdev->dev.of_node,
516 "mediatek,pad-select",
517 &mdata->pad_sel);
518 if (ret) {
519 dev_err(&pdev->dev, "failed to read pad select: %d\n",
520 ret);
521 goto err_put_master;
522 }
523
524 if (mdata->pad_sel > MT8173_SPI_MAX_PAD_SEL) {
525 dev_err(&pdev->dev, "wrong pad-select: %u\n",
526 mdata->pad_sel);
527 ret = -EINVAL;
528 goto err_put_master;
529 }
530 }
531
532 platform_set_drvdata(pdev, master);
533
534 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
535 if (!res) {
536 ret = -ENODEV;
537 dev_err(&pdev->dev, "failed to determine base address\n");
538 goto err_put_master;
539 }
540
541 mdata->base = devm_ioremap_resource(&pdev->dev, res);
542 if (IS_ERR(mdata->base)) {
543 ret = PTR_ERR(mdata->base);
544 goto err_put_master;
545 }
546
547 irq = platform_get_irq(pdev, 0);
548 if (irq < 0) {
549 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
550 ret = irq;
551 goto err_put_master;
552 }
553
554 if (!pdev->dev.dma_mask)
555 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
556
557 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
558 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
559 if (ret) {
560 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
561 goto err_put_master;
562 }
563
a568231f
LL		 564 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
565 if (IS_ERR(mdata->parent_clk)) {
566 ret = PTR_ERR(mdata->parent_clk);
567 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
568 goto err_put_master;
569 }
570
adcbcfea
LL		 571 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
572 if (IS_ERR(mdata->sel_clk)) {
e26d15f7 573 ret = PTR_ERR(mdata->sel_clk);
adcbcfea 574 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
a568231f
LL		 575 goto err_put_master;
576 }
577
adcbcfea
LL		 578 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
579 if (IS_ERR(mdata->spi_clk)) {
e26d15f7 580 ret = PTR_ERR(mdata->spi_clk);
adcbcfea 581 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
a568231f
LL		 582 goto err_put_master;
583 }
584
585 ret = clk_prepare_enable(mdata->spi_clk);
586 if (ret < 0) {
587 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
588 goto err_put_master;
589 }
590
adcbcfea 591 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
a568231f
LL		 592 if (ret < 0) {
593 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
594 goto err_disable_clk;
595 }
596
597 clk_disable_unprepare(mdata->spi_clk);
598
599 pm_runtime_enable(&pdev->dev);
600
601 ret = devm_spi_register_master(&pdev->dev, master);
602 if (ret) {
603 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
604 goto err_put_master;
605 }
606
607 return 0;
608
609err_disable_clk:
610 clk_disable_unprepare(mdata->spi_clk);
611err_put_master:
612 spi_master_put(master);
613
614 return ret;
615}
616
617static int mtk_spi_remove(struct platform_device *pdev)
618{
619 struct spi_master *master = platform_get_drvdata(pdev);
620 struct mtk_spi *mdata = spi_master_get_devdata(master);
621
622 pm_runtime_disable(&pdev->dev);
623
624 mtk_spi_reset(mdata);
a568231f
LL		 625 spi_master_put(master);
626
627 return 0;
628}
629
630#ifdef CONFIG_PM_SLEEP
631static int mtk_spi_suspend(struct device *dev)
632{
633 int ret;
634 struct spi_master *master = dev_get_drvdata(dev);
635 struct mtk_spi *mdata = spi_master_get_devdata(master);
636
637 ret = spi_master_suspend(master);
638 if (ret)
639 return ret;
640
641 if (!pm_runtime_suspended(dev))
642 clk_disable_unprepare(mdata->spi_clk);
643
644 return ret;
645}
646
647static int mtk_spi_resume(struct device *dev)
648{
649 int ret;
650 struct spi_master *master = dev_get_drvdata(dev);
651 struct mtk_spi *mdata = spi_master_get_devdata(master);
652
653 if (!pm_runtime_suspended(dev)) {
654 ret = clk_prepare_enable(mdata->spi_clk);
13da5a0b
LL		 655 if (ret < 0) {
656 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
a568231f 657 return ret;
13da5a0b 658 }
a568231f
LL		 659 }
660
661 ret = spi_master_resume(master);
662 if (ret < 0)
663 clk_disable_unprepare(mdata->spi_clk);
664
665 return ret;
666}
667#endif /* CONFIG_PM_SLEEP */
668
669#ifdef CONFIG_PM
670static int mtk_spi_runtime_suspend(struct device *dev)
671{
672 struct spi_master *master = dev_get_drvdata(dev);
673 struct mtk_spi *mdata = spi_master_get_devdata(master);
674
675 clk_disable_unprepare(mdata->spi_clk);
676
677 return 0;
678}
679
680static int mtk_spi_runtime_resume(struct device *dev)
681{
682 struct spi_master *master = dev_get_drvdata(dev);
683 struct mtk_spi *mdata = spi_master_get_devdata(master);
13da5a0b
LL		 684 int ret;
685
686 ret = clk_prepare_enable(mdata->spi_clk);
687 if (ret < 0) {
688 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
689 return ret;
690 }
a568231f 691
13da5a0b 692 return 0;
a568231f
LL		 693}
694#endif /* CONFIG_PM */
695
696static const struct dev_pm_ops mtk_spi_pm = {
697 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
698 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
699 mtk_spi_runtime_resume, NULL)
700};
701
4299aaaa 702static struct platform_driver mtk_spi_driver = {
a568231f
LL		 703 .driver = {
704 .name = "mtk-spi",
705 .pm = &mtk_spi_pm,
706 .of_match_table = mtk_spi_of_match,
707 },
708 .probe = mtk_spi_probe,
709 .remove = mtk_spi_remove,
710};
711
712module_platform_driver(mtk_spi_driver);
713
714MODULE_DESCRIPTION("MTK SPI Controller driver");
715MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
716MODULE_LICENSE("GPL v2");
e4001885 717MODULE_ALIAS("platform:mtk-spi");
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