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[mirror_ubuntu-hirsute-kernel.git] / drivers / spi / spi-mt65xx.c
CommitLineData
a568231f
LL		 1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Leilk Liu <leilk.liu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/device.h>
17#include <linux/err.h>
18#include <linux/interrupt.h>
dd69a0a6 19#include <linux/io.h>
a568231f
LL		 20#include <linux/ioport.h>
21#include <linux/module.h>
22#include <linux/of.h>
37457607 23#include <linux/of_gpio.h>
a568231f
LL		 24#include <linux/platform_device.h>
25#include <linux/platform_data/spi-mt65xx.h>
26#include <linux/pm_runtime.h>
27#include <linux/spi/spi.h>
28
29#define SPI_CFG0_REG 0x0000
30#define SPI_CFG1_REG 0x0004
31#define SPI_TX_SRC_REG 0x0008
32#define SPI_RX_DST_REG 0x000c
33#define SPI_TX_DATA_REG 0x0010
34#define SPI_RX_DATA_REG 0x0014
35#define SPI_CMD_REG 0x0018
36#define SPI_STATUS0_REG 0x001c
37#define SPI_PAD_SEL_REG 0x0024
38
39#define SPI_CFG0_SCK_HIGH_OFFSET 0
40#define SPI_CFG0_SCK_LOW_OFFSET 8
41#define SPI_CFG0_CS_HOLD_OFFSET 16
42#define SPI_CFG0_CS_SETUP_OFFSET 24
43
44#define SPI_CFG1_CS_IDLE_OFFSET 0
45#define SPI_CFG1_PACKET_LOOP_OFFSET 8
46#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
47#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
48
49#define SPI_CFG1_CS_IDLE_MASK 0xff
50#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
51#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
52
a71d6ea6
LL		 53#define SPI_CMD_ACT BIT(0)
54#define SPI_CMD_RESUME BIT(1)
a568231f
LL		 55#define SPI_CMD_RST BIT(2)
56#define SPI_CMD_PAUSE_EN BIT(4)
57#define SPI_CMD_DEASSERT BIT(5)
58#define SPI_CMD_CPHA BIT(8)
59#define SPI_CMD_CPOL BIT(9)
60#define SPI_CMD_RX_DMA BIT(10)
61#define SPI_CMD_TX_DMA BIT(11)
62#define SPI_CMD_TXMSBF BIT(12)
63#define SPI_CMD_RXMSBF BIT(13)
64#define SPI_CMD_RX_ENDIAN BIT(14)
65#define SPI_CMD_TX_ENDIAN BIT(15)
66#define SPI_CMD_FINISH_IE BIT(16)
67#define SPI_CMD_PAUSE_IE BIT(17)
68
a568231f
LL		 69#define MT8173_SPI_MAX_PAD_SEL 3
70
50f8fec2
LL		 71#define MTK_SPI_PAUSE_INT_STATUS 0x2
72
a568231f
LL		 73#define MTK_SPI_IDLE 0
74#define MTK_SPI_PAUSED 1
75
76#define MTK_SPI_MAX_FIFO_SIZE 32
77#define MTK_SPI_PACKET_SIZE 1024
78
79struct mtk_spi_compatible {
af57937e
LL		 80 bool need_pad_sel;
81 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
82 bool must_tx;
a568231f
LL		 83};
84
85struct mtk_spi {
86 void __iomem *base;
87 u32 state;
37457607
LL		 88 int pad_num;
89 u32 *pad_sel;
adcbcfea 90 struct clk *parent_clk, *sel_clk, *spi_clk;
a568231f
LL		 91 struct spi_transfer *cur_transfer;
92 u32 xfer_len;
93 struct scatterlist *tx_sgl, *rx_sgl;
94 u32 tx_sgl_len, rx_sgl_len;
95 const struct mtk_spi_compatible *dev_comp;
96};
97
af57937e
LL		 98static const struct mtk_spi_compatible mt6589_compat;
99static const struct mtk_spi_compatible mt8135_compat;
a568231f 100static const struct mtk_spi_compatible mt8173_compat = {
af57937e
LL		 101 .need_pad_sel = true,
102 .must_tx = true,
a568231f
LL		 103};
104
105/*
106 * A piece of default chip info unless the platform
107 * supplies it.
108 */
109static const struct mtk_chip_config mtk_default_chip_info = {
110 .rx_mlsb = 1,
111 .tx_mlsb = 1,
a568231f
LL		 112};
113
114static const struct of_device_id mtk_spi_of_match[] = {
115 { .compatible = "mediatek,mt6589-spi", .data = (void *)&mt6589_compat },
116 { .compatible = "mediatek,mt8135-spi", .data = (void *)&mt8135_compat },
117 { .compatible = "mediatek,mt8173-spi", .data = (void *)&mt8173_compat },
118 {}
119};
120MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
121
122static void mtk_spi_reset(struct mtk_spi *mdata)
123{
124 u32 reg_val;
125
126 /* set the software reset bit in SPI_CMD_REG. */
127 reg_val = readl(mdata->base + SPI_CMD_REG);
128 reg_val |= SPI_CMD_RST;
129 writel(reg_val, mdata->base + SPI_CMD_REG);
130
131 reg_val = readl(mdata->base + SPI_CMD_REG);
132 reg_val &= ~SPI_CMD_RST;
133 writel(reg_val, mdata->base + SPI_CMD_REG);
134}
135
79b5d3f2
LL		 136static int mtk_spi_prepare_message(struct spi_master *master,
137 struct spi_message *msg)
a568231f 138{
79b5d3f2 139 u16 cpha, cpol;
a568231f 140 u32 reg_val;
79b5d3f2 141 struct spi_device *spi = msg->spi;
58a984c7 142 struct mtk_chip_config *chip_config = spi->controller_data;
79b5d3f2
LL		 143 struct mtk_spi *mdata = spi_master_get_devdata(master);
144
145 cpha = spi->mode & SPI_CPHA ? 1 : 0;
146 cpol = spi->mode & SPI_CPOL ? 1 : 0;
147
79b5d3f2
LL		 148 reg_val = readl(mdata->base + SPI_CMD_REG);
149 if (cpha)
150 reg_val |= SPI_CMD_CPHA;
151 else
152 reg_val &= ~SPI_CMD_CPHA;
153 if (cpol)
154 reg_val |= SPI_CMD_CPOL;
155 else
156 reg_val &= ~SPI_CMD_CPOL;
157 writel(reg_val, mdata->base + SPI_CMD_REG);
a568231f
LL		 158
159 reg_val = readl(mdata->base + SPI_CMD_REG);
160
161 /* set the mlsbx and mlsbtx */
a71d6ea6
LL		 162 if (chip_config->tx_mlsb)
163 reg_val |= SPI_CMD_TXMSBF;
164 else
165 reg_val &= ~SPI_CMD_TXMSBF;
166 if (chip_config->rx_mlsb)
167 reg_val |= SPI_CMD_RXMSBF;
168 else
169 reg_val &= ~SPI_CMD_RXMSBF;
a568231f
LL		 170
171 /* set the tx/rx endian */
44f636da
LL		 172#ifdef __LITTLE_ENDIAN
173 reg_val &= ~SPI_CMD_TX_ENDIAN;
174 reg_val &= ~SPI_CMD_RX_ENDIAN;
175#else
176 reg_val |= SPI_CMD_TX_ENDIAN;
177 reg_val |= SPI_CMD_RX_ENDIAN;
178#endif
a568231f
LL		 179
180 /* set finish and pause interrupt always enable */
15293324 181 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
a568231f
LL		 182
183 /* disable dma mode */
184 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
185
186 /* disable deassert mode */
187 reg_val &= ~SPI_CMD_DEASSERT;
188
189 writel(reg_val, mdata->base + SPI_CMD_REG);
190
191 /* pad select */
192 if (mdata->dev_comp->need_pad_sel)
37457607
LL		 193 writel(mdata->pad_sel[spi->chip_select],
194 mdata->base + SPI_PAD_SEL_REG);
a568231f
LL		 195
196 return 0;
197}
198
199static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
200{
201 u32 reg_val;
202 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
203
204 reg_val = readl(mdata->base + SPI_CMD_REG);
6583d203 205 if (!enable) {
a568231f 206 reg_val |= SPI_CMD_PAUSE_EN;
6583d203
LL		 207 writel(reg_val, mdata->base + SPI_CMD_REG);
208 } else {
a568231f 209 reg_val &= ~SPI_CMD_PAUSE_EN;
6583d203
LL		 210 writel(reg_val, mdata->base + SPI_CMD_REG);
211 mdata->state = MTK_SPI_IDLE;
212 mtk_spi_reset(mdata);
213 }
a568231f
LL		 214}
215
216static void mtk_spi_prepare_transfer(struct spi_master *master,
217 struct spi_transfer *xfer)
218{
2ce0acf5 219 u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
a568231f
LL		 220 struct mtk_spi *mdata = spi_master_get_devdata(master);
221
222 spi_clk_hz = clk_get_rate(mdata->spi_clk);
223 if (xfer->speed_hz < spi_clk_hz / 2)
224 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
225 else
226 div = 1;
227
2ce0acf5
LL		 228 sck_time = (div + 1) / 2;
229 cs_time = sck_time * 2;
a568231f 230
2ce0acf5
LL		 231 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
232 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
233 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
234 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
a568231f
LL		 235 writel(reg_val, mdata->base + SPI_CFG0_REG);
236
237 reg_val = readl(mdata->base + SPI_CFG1_REG);
238 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
2ce0acf5 239 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
a568231f
LL		 240 writel(reg_val, mdata->base + SPI_CFG1_REG);
241}
242
243static void mtk_spi_setup_packet(struct spi_master *master)
244{
245 u32 packet_size, packet_loop, reg_val;
246 struct mtk_spi *mdata = spi_master_get_devdata(master);
247
50f8fec2 248 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
a568231f
LL		 249 packet_loop = mdata->xfer_len / packet_size;
250
251 reg_val = readl(mdata->base + SPI_CFG1_REG);
50f8fec2 252 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
a568231f
LL		 253 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
254 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
255 writel(reg_val, mdata->base + SPI_CFG1_REG);
256}
257
258static void mtk_spi_enable_transfer(struct spi_master *master)
259{
50f8fec2 260 u32 cmd;
a568231f
LL		 261 struct mtk_spi *mdata = spi_master_get_devdata(master);
262
263 cmd = readl(mdata->base + SPI_CMD_REG);
264 if (mdata->state == MTK_SPI_IDLE)
a71d6ea6 265 cmd |= SPI_CMD_ACT;
a568231f 266 else
a71d6ea6 267 cmd |= SPI_CMD_RESUME;
a568231f
LL		 268 writel(cmd, mdata->base + SPI_CMD_REG);
269}
270
50f8fec2 271static int mtk_spi_get_mult_delta(u32 xfer_len)
a568231f 272{
50f8fec2 273 u32 mult_delta;
a568231f
LL		 274
275 if (xfer_len > MTK_SPI_PACKET_SIZE)
276 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
277 else
278 mult_delta = 0;
279
280 return mult_delta;
281}
282
283static void mtk_spi_update_mdata_len(struct spi_master *master)
284{
285 int mult_delta;
286 struct mtk_spi *mdata = spi_master_get_devdata(master);
287
288 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
289 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
290 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
291 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
292 mdata->rx_sgl_len = mult_delta;
293 mdata->tx_sgl_len -= mdata->xfer_len;
294 } else {
295 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
296 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
297 mdata->tx_sgl_len = mult_delta;
298 mdata->rx_sgl_len -= mdata->xfer_len;
299 }
300 } else if (mdata->tx_sgl_len) {
301 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
302 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
303 mdata->tx_sgl_len = mult_delta;
304 } else if (mdata->rx_sgl_len) {
305 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
306 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
307 mdata->rx_sgl_len = mult_delta;
308 }
309}
310
311static void mtk_spi_setup_dma_addr(struct spi_master *master,
312 struct spi_transfer *xfer)
313{
314 struct mtk_spi *mdata = spi_master_get_devdata(master);
315
316 if (mdata->tx_sgl)
39ba928f 317 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
a568231f 318 if (mdata->rx_sgl)
39ba928f 319 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
a568231f
LL		 320}
321
322static int mtk_spi_fifo_transfer(struct spi_master *master,
323 struct spi_device *spi,
324 struct spi_transfer *xfer)
325{
de327e49
NB		 326 int cnt, remainder;
327 u32 reg_val;
a568231f
LL		 328 struct mtk_spi *mdata = spi_master_get_devdata(master);
329
330 mdata->cur_transfer = xfer;
331 mdata->xfer_len = xfer->len;
332 mtk_spi_prepare_transfer(master, xfer);
333 mtk_spi_setup_packet(master);
334
de327e49 335 cnt = xfer->len / 4;
44f636da 336 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
a568231f 337
de327e49
NB		 338 remainder = xfer->len % 4;
339 if (remainder > 0) {
340 reg_val = 0;
341 memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
342 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
343 }
344
a568231f
LL		 345 mtk_spi_enable_transfer(master);
346
347 return 1;
348}
349
350static int mtk_spi_dma_transfer(struct spi_master *master,
351 struct spi_device *spi,
352 struct spi_transfer *xfer)
353{
354 int cmd;
355 struct mtk_spi *mdata = spi_master_get_devdata(master);
356
357 mdata->tx_sgl = NULL;
358 mdata->rx_sgl = NULL;
359 mdata->tx_sgl_len = 0;
360 mdata->rx_sgl_len = 0;
361 mdata->cur_transfer = xfer;
362
363 mtk_spi_prepare_transfer(master, xfer);
364
365 cmd = readl(mdata->base + SPI_CMD_REG);
366 if (xfer->tx_buf)
367 cmd |= SPI_CMD_TX_DMA;
368 if (xfer->rx_buf)
369 cmd |= SPI_CMD_RX_DMA;
370 writel(cmd, mdata->base + SPI_CMD_REG);
371
372 if (xfer->tx_buf)
373 mdata->tx_sgl = xfer->tx_sg.sgl;
374 if (xfer->rx_buf)
375 mdata->rx_sgl = xfer->rx_sg.sgl;
376
377 if (mdata->tx_sgl) {
378 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
379 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
380 }
381 if (mdata->rx_sgl) {
382 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
383 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
384 }
385
386 mtk_spi_update_mdata_len(master);
387 mtk_spi_setup_packet(master);
388 mtk_spi_setup_dma_addr(master, xfer);
389 mtk_spi_enable_transfer(master);
390
391 return 1;
392}
393
394static int mtk_spi_transfer_one(struct spi_master *master,
395 struct spi_device *spi,
396 struct spi_transfer *xfer)
397{
398 if (master->can_dma(master, spi, xfer))
399 return mtk_spi_dma_transfer(master, spi, xfer);
400 else
401 return mtk_spi_fifo_transfer(master, spi, xfer);
402}
403
404static bool mtk_spi_can_dma(struct spi_master *master,
405 struct spi_device *spi,
406 struct spi_transfer *xfer)
407{
408 return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
409}
410
58a984c7
LL		 411static int mtk_spi_setup(struct spi_device *spi)
412{
413 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
414
415 if (!spi->controller_data)
416 spi->controller_data = (void *)&mtk_default_chip_info;
417
98c8dccf 418 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
37457607
LL		 419 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
420
58a984c7
LL		 421 return 0;
422}
423
a568231f
LL		 424static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
425{
de327e49 426 u32 cmd, reg_val, cnt, remainder;
a568231f
LL		 427 struct spi_master *master = dev_id;
428 struct mtk_spi *mdata = spi_master_get_devdata(master);
429 struct spi_transfer *trans = mdata->cur_transfer;
430
431 reg_val = readl(mdata->base + SPI_STATUS0_REG);
50f8fec2 432 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
a568231f
LL		 433 mdata->state = MTK_SPI_PAUSED;
434 else
435 mdata->state = MTK_SPI_IDLE;
436
437 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
a568231f 438 if (trans->rx_buf) {
de327e49 439 cnt = mdata->xfer_len / 4;
44f636da
LL		 440 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
441 trans->rx_buf, cnt);
de327e49
NB		 442 remainder = mdata->xfer_len % 4;
443 if (remainder > 0) {
444 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
445 memcpy(trans->rx_buf + (cnt * 4),
446 &reg_val, remainder);
447 }
a568231f
LL		 448 }
449 spi_finalize_current_transfer(master);
450 return IRQ_HANDLED;
451 }
452
453 if (mdata->tx_sgl)
454 trans->tx_dma += mdata->xfer_len;
455 if (mdata->rx_sgl)
456 trans->rx_dma += mdata->xfer_len;
457
458 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
459 mdata->tx_sgl = sg_next(mdata->tx_sgl);
460 if (mdata->tx_sgl) {
461 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
462 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
463 }
464 }
465 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
466 mdata->rx_sgl = sg_next(mdata->rx_sgl);
467 if (mdata->rx_sgl) {
468 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
469 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
470 }
471 }
472
473 if (!mdata->tx_sgl && !mdata->rx_sgl) {
474 /* spi disable dma */
475 cmd = readl(mdata->base + SPI_CMD_REG);
476 cmd &= ~SPI_CMD_TX_DMA;
477 cmd &= ~SPI_CMD_RX_DMA;
478 writel(cmd, mdata->base + SPI_CMD_REG);
479
480 spi_finalize_current_transfer(master);
481 return IRQ_HANDLED;
482 }
483
484 mtk_spi_update_mdata_len(master);
485 mtk_spi_setup_packet(master);
486 mtk_spi_setup_dma_addr(master, trans);
487 mtk_spi_enable_transfer(master);
488
489 return IRQ_HANDLED;
490}
491
492static int mtk_spi_probe(struct platform_device *pdev)
493{
494 struct spi_master *master;
495 struct mtk_spi *mdata;
496 const struct of_device_id *of_id;
497 struct resource *res;
37457607 498 int i, irq, ret;
a568231f
LL		 499
500 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
501 if (!master) {
502 dev_err(&pdev->dev, "failed to alloc spi master\n");
503 return -ENOMEM;
504 }
505
506 master->auto_runtime_pm = true;
507 master->dev.of_node = pdev->dev.of_node;
508 master->mode_bits = SPI_CPOL | SPI_CPHA;
509
510 master->set_cs = mtk_spi_set_cs;
a568231f
LL		 511 master->prepare_message = mtk_spi_prepare_message;
512 master->transfer_one = mtk_spi_transfer_one;
513 master->can_dma = mtk_spi_can_dma;
58a984c7 514 master->setup = mtk_spi_setup;
a568231f
LL		 515
516 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
517 if (!of_id) {
518 dev_err(&pdev->dev, "failed to probe of_node\n");
519 ret = -EINVAL;
520 goto err_put_master;
521 }
522
523 mdata = spi_master_get_devdata(master);
524 mdata->dev_comp = of_id->data;
525 if (mdata->dev_comp->must_tx)
526 master->flags = SPI_MASTER_MUST_TX;
527
528 if (mdata->dev_comp->need_pad_sel) {
37457607
LL		 529 mdata->pad_num = of_property_count_u32_elems(
530 pdev->dev.of_node,
531 "mediatek,pad-select");
532 if (mdata->pad_num < 0) {
533 dev_err(&pdev->dev,
534 "No 'mediatek,pad-select' property\n");
535 ret = -EINVAL;
a568231f
LL		 536 goto err_put_master;
537 }
538
37457607
LL		 539 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
540 sizeof(u32), GFP_KERNEL);
541 if (!mdata->pad_sel) {
542 ret = -ENOMEM;
a568231f
LL		 543 goto err_put_master;
544 }
37457607
LL		 545
546 for (i = 0; i < mdata->pad_num; i++) {
547 of_property_read_u32_index(pdev->dev.of_node,
548 "mediatek,pad-select",
549 i, &mdata->pad_sel[i]);
550 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
551 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
552 i, mdata->pad_sel[i]);
553 ret = -EINVAL;
554 goto err_put_master;
555 }
556 }
a568231f
LL		 557 }
558
559 platform_set_drvdata(pdev, master);
560
561 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
562 if (!res) {
563 ret = -ENODEV;
564 dev_err(&pdev->dev, "failed to determine base address\n");
565 goto err_put_master;
566 }
567
568 mdata->base = devm_ioremap_resource(&pdev->dev, res);
569 if (IS_ERR(mdata->base)) {
570 ret = PTR_ERR(mdata->base);
571 goto err_put_master;
572 }
573
574 irq = platform_get_irq(pdev, 0);
575 if (irq < 0) {
576 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
577 ret = irq;
578 goto err_put_master;
579 }
580
581 if (!pdev->dev.dma_mask)
582 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
583
584 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
585 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
586 if (ret) {
587 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
588 goto err_put_master;
589 }
590
a568231f
LL		 591 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
592 if (IS_ERR(mdata->parent_clk)) {
593 ret = PTR_ERR(mdata->parent_clk);
594 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
595 goto err_put_master;
596 }
597
adcbcfea
LL		 598 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
599 if (IS_ERR(mdata->sel_clk)) {
e26d15f7 600 ret = PTR_ERR(mdata->sel_clk);
adcbcfea 601 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
a568231f
LL		 602 goto err_put_master;
603 }
604
adcbcfea
LL		 605 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
606 if (IS_ERR(mdata->spi_clk)) {
e26d15f7 607 ret = PTR_ERR(mdata->spi_clk);
adcbcfea 608 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
a568231f
LL		 609 goto err_put_master;
610 }
611
612 ret = clk_prepare_enable(mdata->spi_clk);
613 if (ret < 0) {
614 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
615 goto err_put_master;
616 }
617
adcbcfea 618 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
a568231f
LL		 619 if (ret < 0) {
620 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
621 goto err_disable_clk;
622 }
623
624 clk_disable_unprepare(mdata->spi_clk);
625
626 pm_runtime_enable(&pdev->dev);
627
628 ret = devm_spi_register_master(&pdev->dev, master);
629 if (ret) {
630 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
631 goto err_put_master;
632 }
633
37457607
LL		 634 if (mdata->dev_comp->need_pad_sel) {
635 if (mdata->pad_num != master->num_chipselect) {
636 dev_err(&pdev->dev,
637 "pad_num does not match num_chipselect(%d != %d)\n",
638 mdata->pad_num, master->num_chipselect);
639 ret = -EINVAL;
640 goto err_put_master;
641 }
642
98c8dccf
NB		 643 if (!master->cs_gpios && master->num_chipselect > 1) {
644 dev_err(&pdev->dev,
645 "cs_gpios not specified and num_chipselect > 1\n");
646 ret = -EINVAL;
647 goto err_put_master;
648 }
649
650 if (master->cs_gpios) {
651 for (i = 0; i < master->num_chipselect; i++) {
652 ret = devm_gpio_request(&pdev->dev,
653 master->cs_gpios[i],
654 dev_name(&pdev->dev));
655 if (ret) {
656 dev_err(&pdev->dev,
657 "can't get CS GPIO %i\n", i);
658 goto err_put_master;
659 }
37457607
LL		 660 }
661 }
662 }
663
a568231f
LL		 664 return 0;
665
666err_disable_clk:
667 clk_disable_unprepare(mdata->spi_clk);
668err_put_master:
669 spi_master_put(master);
670
671 return ret;
672}
673
674static int mtk_spi_remove(struct platform_device *pdev)
675{
676 struct spi_master *master = platform_get_drvdata(pdev);
677 struct mtk_spi *mdata = spi_master_get_devdata(master);
678
679 pm_runtime_disable(&pdev->dev);
680
681 mtk_spi_reset(mdata);
a568231f
LL		 682 spi_master_put(master);
683
684 return 0;
685}
686
687#ifdef CONFIG_PM_SLEEP
688static int mtk_spi_suspend(struct device *dev)
689{
690 int ret;
691 struct spi_master *master = dev_get_drvdata(dev);
692 struct mtk_spi *mdata = spi_master_get_devdata(master);
693
694 ret = spi_master_suspend(master);
695 if (ret)
696 return ret;
697
698 if (!pm_runtime_suspended(dev))
699 clk_disable_unprepare(mdata->spi_clk);
700
701 return ret;
702}
703
704static int mtk_spi_resume(struct device *dev)
705{
706 int ret;
707 struct spi_master *master = dev_get_drvdata(dev);
708 struct mtk_spi *mdata = spi_master_get_devdata(master);
709
710 if (!pm_runtime_suspended(dev)) {
711 ret = clk_prepare_enable(mdata->spi_clk);
13da5a0b
LL		 712 if (ret < 0) {
713 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
a568231f 714 return ret;
13da5a0b 715 }
a568231f
LL		 716 }
717
718 ret = spi_master_resume(master);
719 if (ret < 0)
720 clk_disable_unprepare(mdata->spi_clk);
721
722 return ret;
723}
724#endif /* CONFIG_PM_SLEEP */
725
726#ifdef CONFIG_PM
727static int mtk_spi_runtime_suspend(struct device *dev)
728{
729 struct spi_master *master = dev_get_drvdata(dev);
730 struct mtk_spi *mdata = spi_master_get_devdata(master);
731
732 clk_disable_unprepare(mdata->spi_clk);
733
734 return 0;
735}
736
737static int mtk_spi_runtime_resume(struct device *dev)
738{
739 struct spi_master *master = dev_get_drvdata(dev);
740 struct mtk_spi *mdata = spi_master_get_devdata(master);
13da5a0b
LL		 741 int ret;
742
743 ret = clk_prepare_enable(mdata->spi_clk);
744 if (ret < 0) {
745 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
746 return ret;
747 }
a568231f 748
13da5a0b 749 return 0;
a568231f
LL		 750}
751#endif /* CONFIG_PM */
752
753static const struct dev_pm_ops mtk_spi_pm = {
754 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
755 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
756 mtk_spi_runtime_resume, NULL)
757};
758
4299aaaa 759static struct platform_driver mtk_spi_driver = {
a568231f
LL		 760 .driver = {
761 .name = "mtk-spi",
762 .pm = &mtk_spi_pm,
763 .of_match_table = mtk_spi_of_match,
764 },
765 .probe = mtk_spi_probe,
766 .remove = mtk_spi_remove,
767};
768
769module_platform_driver(mtk_spi_driver);
770
771MODULE_DESCRIPTION("MTK SPI Controller driver");
772MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
773MODULE_LICENSE("GPL v2");
e4001885 774MODULE_ALIAS("platform:mtk-spi");
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