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spi: mediatek: fix wrong error return value on probe
[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-mt65xx.c
CommitLineData
a568231f
LL		 1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Leilk Liu <leilk.liu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/device.h>
17#include <linux/err.h>
18#include <linux/interrupt.h>
dd69a0a6 19#include <linux/io.h>
a568231f
LL		 20#include <linux/ioport.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/platform_data/spi-mt65xx.h>
25#include <linux/pm_runtime.h>
26#include <linux/spi/spi.h>
27
28#define SPI_CFG0_REG 0x0000
29#define SPI_CFG1_REG 0x0004
30#define SPI_TX_SRC_REG 0x0008
31#define SPI_RX_DST_REG 0x000c
32#define SPI_TX_DATA_REG 0x0010
33#define SPI_RX_DATA_REG 0x0014
34#define SPI_CMD_REG 0x0018
35#define SPI_STATUS0_REG 0x001c
36#define SPI_PAD_SEL_REG 0x0024
37
38#define SPI_CFG0_SCK_HIGH_OFFSET 0
39#define SPI_CFG0_SCK_LOW_OFFSET 8
40#define SPI_CFG0_CS_HOLD_OFFSET 16
41#define SPI_CFG0_CS_SETUP_OFFSET 24
42
43#define SPI_CFG1_CS_IDLE_OFFSET 0
44#define SPI_CFG1_PACKET_LOOP_OFFSET 8
45#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
46#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
47
48#define SPI_CFG1_CS_IDLE_MASK 0xff
49#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
50#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
51
a71d6ea6
LL		 52#define SPI_CMD_ACT BIT(0)
53#define SPI_CMD_RESUME BIT(1)
a568231f
LL		 54#define SPI_CMD_RST BIT(2)
55#define SPI_CMD_PAUSE_EN BIT(4)
56#define SPI_CMD_DEASSERT BIT(5)
57#define SPI_CMD_CPHA BIT(8)
58#define SPI_CMD_CPOL BIT(9)
59#define SPI_CMD_RX_DMA BIT(10)
60#define SPI_CMD_TX_DMA BIT(11)
61#define SPI_CMD_TXMSBF BIT(12)
62#define SPI_CMD_RXMSBF BIT(13)
63#define SPI_CMD_RX_ENDIAN BIT(14)
64#define SPI_CMD_TX_ENDIAN BIT(15)
65#define SPI_CMD_FINISH_IE BIT(16)
66#define SPI_CMD_PAUSE_IE BIT(17)
67
a568231f
LL		 68#define MT8173_SPI_MAX_PAD_SEL 3
69
50f8fec2
LL		 70#define MTK_SPI_PAUSE_INT_STATUS 0x2
71
a568231f
LL		 72#define MTK_SPI_IDLE 0
73#define MTK_SPI_PAUSED 1
74
75#define MTK_SPI_MAX_FIFO_SIZE 32
76#define MTK_SPI_PACKET_SIZE 1024
77
78struct mtk_spi_compatible {
af57937e
LL		 79 bool need_pad_sel;
80 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
81 bool must_tx;
a568231f
LL		 82};
83
84struct mtk_spi {
85 void __iomem *base;
86 u32 state;
87 u32 pad_sel;
adcbcfea 88 struct clk *parent_clk, *sel_clk, *spi_clk;
a568231f
LL		 89 struct spi_transfer *cur_transfer;
90 u32 xfer_len;
91 struct scatterlist *tx_sgl, *rx_sgl;
92 u32 tx_sgl_len, rx_sgl_len;
93 const struct mtk_spi_compatible *dev_comp;
94};
95
af57937e
LL		 96static const struct mtk_spi_compatible mt6589_compat;
97static const struct mtk_spi_compatible mt8135_compat;
a568231f 98static const struct mtk_spi_compatible mt8173_compat = {
af57937e
LL		 99 .need_pad_sel = true,
100 .must_tx = true,
a568231f
LL		 101};
102
103/*
104 * A piece of default chip info unless the platform
105 * supplies it.
106 */
107static const struct mtk_chip_config mtk_default_chip_info = {
108 .rx_mlsb = 1,
109 .tx_mlsb = 1,
a568231f
LL		 110};
111
112static const struct of_device_id mtk_spi_of_match[] = {
113 { .compatible = "mediatek,mt6589-spi", .data = (void *)&mt6589_compat },
114 { .compatible = "mediatek,mt8135-spi", .data = (void *)&mt8135_compat },
115 { .compatible = "mediatek,mt8173-spi", .data = (void *)&mt8173_compat },
116 {}
117};
118MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
119
120static void mtk_spi_reset(struct mtk_spi *mdata)
121{
122 u32 reg_val;
123
124 /* set the software reset bit in SPI_CMD_REG. */
125 reg_val = readl(mdata->base + SPI_CMD_REG);
126 reg_val |= SPI_CMD_RST;
127 writel(reg_val, mdata->base + SPI_CMD_REG);
128
129 reg_val = readl(mdata->base + SPI_CMD_REG);
130 reg_val &= ~SPI_CMD_RST;
131 writel(reg_val, mdata->base + SPI_CMD_REG);
132}
133
134static void mtk_spi_config(struct mtk_spi *mdata,
135 struct mtk_chip_config *chip_config)
136{
137 u32 reg_val;
138
139 reg_val = readl(mdata->base + SPI_CMD_REG);
140
141 /* set the mlsbx and mlsbtx */
a71d6ea6
LL		 142 if (chip_config->tx_mlsb)
143 reg_val |= SPI_CMD_TXMSBF;
144 else
145 reg_val &= ~SPI_CMD_TXMSBF;
146 if (chip_config->rx_mlsb)
147 reg_val |= SPI_CMD_RXMSBF;
148 else
149 reg_val &= ~SPI_CMD_RXMSBF;
a568231f
LL		 150
151 /* set the tx/rx endian */
44f636da
LL		 152#ifdef __LITTLE_ENDIAN
153 reg_val &= ~SPI_CMD_TX_ENDIAN;
154 reg_val &= ~SPI_CMD_RX_ENDIAN;
155#else
156 reg_val |= SPI_CMD_TX_ENDIAN;
157 reg_val |= SPI_CMD_RX_ENDIAN;
158#endif
a568231f
LL		 159
160 /* set finish and pause interrupt always enable */
15293324 161 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
a568231f
LL		 162
163 /* disable dma mode */
164 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
165
166 /* disable deassert mode */
167 reg_val &= ~SPI_CMD_DEASSERT;
168
169 writel(reg_val, mdata->base + SPI_CMD_REG);
170
171 /* pad select */
172 if (mdata->dev_comp->need_pad_sel)
173 writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG);
174}
175
176static int mtk_spi_prepare_hardware(struct spi_master *master)
177{
178 struct spi_transfer *trans;
179 struct mtk_spi *mdata = spi_master_get_devdata(master);
180 struct spi_message *msg = master->cur_msg;
a568231f
LL		 181
182 trans = list_first_entry(&msg->transfers, struct spi_transfer,
183 transfer_list);
50f8fec2 184 if (!trans->cs_change) {
a568231f
LL		 185 mdata->state = MTK_SPI_IDLE;
186 mtk_spi_reset(mdata);
187 }
188
a568231f
LL		 189 return 0;
190}
191
192static int mtk_spi_prepare_message(struct spi_master *master,
193 struct spi_message *msg)
194{
195 u32 reg_val;
196 u8 cpha, cpol;
197 struct mtk_chip_config *chip_config;
198 struct spi_device *spi = msg->spi;
199 struct mtk_spi *mdata = spi_master_get_devdata(master);
200
201 cpha = spi->mode & SPI_CPHA ? 1 : 0;
202 cpol = spi->mode & SPI_CPOL ? 1 : 0;
203
204 reg_val = readl(mdata->base + SPI_CMD_REG);
a71d6ea6
LL		 205 if (cpha)
206 reg_val |= SPI_CMD_CPHA;
207 else
208 reg_val &= ~SPI_CMD_CPHA;
209 if (cpol)
210 reg_val |= SPI_CMD_CPOL;
211 else
212 reg_val &= ~SPI_CMD_CPOL;
a568231f
LL		 213 writel(reg_val, mdata->base + SPI_CMD_REG);
214
215 chip_config = spi->controller_data;
216 if (!chip_config) {
217 chip_config = (void *)&mtk_default_chip_info;
218 spi->controller_data = chip_config;
219 }
220 mtk_spi_config(mdata, chip_config);
221
222 return 0;
223}
224
225static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
226{
227 u32 reg_val;
228 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
229
230 reg_val = readl(mdata->base + SPI_CMD_REG);
231 if (!enable)
232 reg_val |= SPI_CMD_PAUSE_EN;
233 else
234 reg_val &= ~SPI_CMD_PAUSE_EN;
235 writel(reg_val, mdata->base + SPI_CMD_REG);
236}
237
238static void mtk_spi_prepare_transfer(struct spi_master *master,
239 struct spi_transfer *xfer)
240{
2ce0acf5 241 u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
a568231f
LL		 242 struct mtk_spi *mdata = spi_master_get_devdata(master);
243
244 spi_clk_hz = clk_get_rate(mdata->spi_clk);
245 if (xfer->speed_hz < spi_clk_hz / 2)
246 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
247 else
248 div = 1;
249
2ce0acf5
LL		 250 sck_time = (div + 1) / 2;
251 cs_time = sck_time * 2;
a568231f 252
2ce0acf5
LL		 253 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
254 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
255 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
256 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
a568231f
LL		 257 writel(reg_val, mdata->base + SPI_CFG0_REG);
258
259 reg_val = readl(mdata->base + SPI_CFG1_REG);
260 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
2ce0acf5 261 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
a568231f
LL		 262 writel(reg_val, mdata->base + SPI_CFG1_REG);
263}
264
265static void mtk_spi_setup_packet(struct spi_master *master)
266{
267 u32 packet_size, packet_loop, reg_val;
268 struct mtk_spi *mdata = spi_master_get_devdata(master);
269
50f8fec2 270 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
a568231f
LL		 271 packet_loop = mdata->xfer_len / packet_size;
272
273 reg_val = readl(mdata->base + SPI_CFG1_REG);
50f8fec2 274 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
a568231f
LL		 275 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
276 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
277 writel(reg_val, mdata->base + SPI_CFG1_REG);
278}
279
280static void mtk_spi_enable_transfer(struct spi_master *master)
281{
50f8fec2 282 u32 cmd;
a568231f
LL		 283 struct mtk_spi *mdata = spi_master_get_devdata(master);
284
285 cmd = readl(mdata->base + SPI_CMD_REG);
286 if (mdata->state == MTK_SPI_IDLE)
a71d6ea6 287 cmd |= SPI_CMD_ACT;
a568231f 288 else
a71d6ea6 289 cmd |= SPI_CMD_RESUME;
a568231f
LL		 290 writel(cmd, mdata->base + SPI_CMD_REG);
291}
292
50f8fec2 293static int mtk_spi_get_mult_delta(u32 xfer_len)
a568231f 294{
50f8fec2 295 u32 mult_delta;
a568231f
LL		 296
297 if (xfer_len > MTK_SPI_PACKET_SIZE)
298 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
299 else
300 mult_delta = 0;
301
302 return mult_delta;
303}
304
305static void mtk_spi_update_mdata_len(struct spi_master *master)
306{
307 int mult_delta;
308 struct mtk_spi *mdata = spi_master_get_devdata(master);
309
310 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
311 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
312 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
313 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
314 mdata->rx_sgl_len = mult_delta;
315 mdata->tx_sgl_len -= mdata->xfer_len;
316 } else {
317 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
318 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
319 mdata->tx_sgl_len = mult_delta;
320 mdata->rx_sgl_len -= mdata->xfer_len;
321 }
322 } else if (mdata->tx_sgl_len) {
323 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
324 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
325 mdata->tx_sgl_len = mult_delta;
326 } else if (mdata->rx_sgl_len) {
327 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
328 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
329 mdata->rx_sgl_len = mult_delta;
330 }
331}
332
333static void mtk_spi_setup_dma_addr(struct spi_master *master,
334 struct spi_transfer *xfer)
335{
336 struct mtk_spi *mdata = spi_master_get_devdata(master);
337
338 if (mdata->tx_sgl)
39ba928f 339 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
a568231f 340 if (mdata->rx_sgl)
39ba928f 341 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
a568231f
LL		 342}
343
344static int mtk_spi_fifo_transfer(struct spi_master *master,
345 struct spi_device *spi,
346 struct spi_transfer *xfer)
347{
44f636da 348 int cnt;
a568231f
LL		 349 struct mtk_spi *mdata = spi_master_get_devdata(master);
350
351 mdata->cur_transfer = xfer;
352 mdata->xfer_len = xfer->len;
353 mtk_spi_prepare_transfer(master, xfer);
354 mtk_spi_setup_packet(master);
355
356 if (xfer->len % 4)
357 cnt = xfer->len / 4 + 1;
358 else
359 cnt = xfer->len / 4;
44f636da 360 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
a568231f
LL		 361
362 mtk_spi_enable_transfer(master);
363
364 return 1;
365}
366
367static int mtk_spi_dma_transfer(struct spi_master *master,
368 struct spi_device *spi,
369 struct spi_transfer *xfer)
370{
371 int cmd;
372 struct mtk_spi *mdata = spi_master_get_devdata(master);
373
374 mdata->tx_sgl = NULL;
375 mdata->rx_sgl = NULL;
376 mdata->tx_sgl_len = 0;
377 mdata->rx_sgl_len = 0;
378 mdata->cur_transfer = xfer;
379
380 mtk_spi_prepare_transfer(master, xfer);
381
382 cmd = readl(mdata->base + SPI_CMD_REG);
383 if (xfer->tx_buf)
384 cmd |= SPI_CMD_TX_DMA;
385 if (xfer->rx_buf)
386 cmd |= SPI_CMD_RX_DMA;
387 writel(cmd, mdata->base + SPI_CMD_REG);
388
389 if (xfer->tx_buf)
390 mdata->tx_sgl = xfer->tx_sg.sgl;
391 if (xfer->rx_buf)
392 mdata->rx_sgl = xfer->rx_sg.sgl;
393
394 if (mdata->tx_sgl) {
395 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
396 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
397 }
398 if (mdata->rx_sgl) {
399 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
400 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
401 }
402
403 mtk_spi_update_mdata_len(master);
404 mtk_spi_setup_packet(master);
405 mtk_spi_setup_dma_addr(master, xfer);
406 mtk_spi_enable_transfer(master);
407
408 return 1;
409}
410
411static int mtk_spi_transfer_one(struct spi_master *master,
412 struct spi_device *spi,
413 struct spi_transfer *xfer)
414{
415 if (master->can_dma(master, spi, xfer))
416 return mtk_spi_dma_transfer(master, spi, xfer);
417 else
418 return mtk_spi_fifo_transfer(master, spi, xfer);
419}
420
421static bool mtk_spi_can_dma(struct spi_master *master,
422 struct spi_device *spi,
423 struct spi_transfer *xfer)
424{
425 return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
426}
427
428static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
429{
44f636da 430 u32 cmd, reg_val, cnt;
a568231f
LL		 431 struct spi_master *master = dev_id;
432 struct mtk_spi *mdata = spi_master_get_devdata(master);
433 struct spi_transfer *trans = mdata->cur_transfer;
434
435 reg_val = readl(mdata->base + SPI_STATUS0_REG);
50f8fec2 436 if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
a568231f
LL		 437 mdata->state = MTK_SPI_PAUSED;
438 else
439 mdata->state = MTK_SPI_IDLE;
440
441 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
a568231f 442 if (trans->rx_buf) {
44f636da
LL		 443 if (mdata->xfer_len % 4)
444 cnt = mdata->xfer_len / 4 + 1;
445 else
446 cnt = mdata->xfer_len / 4;
447 ioread32_rep(mdata->base + SPI_RX_DATA_REG,
448 trans->rx_buf, cnt);
a568231f
LL		 449 }
450 spi_finalize_current_transfer(master);
451 return IRQ_HANDLED;
452 }
453
454 if (mdata->tx_sgl)
455 trans->tx_dma += mdata->xfer_len;
456 if (mdata->rx_sgl)
457 trans->rx_dma += mdata->xfer_len;
458
459 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
460 mdata->tx_sgl = sg_next(mdata->tx_sgl);
461 if (mdata->tx_sgl) {
462 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
463 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
464 }
465 }
466 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
467 mdata->rx_sgl = sg_next(mdata->rx_sgl);
468 if (mdata->rx_sgl) {
469 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
470 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
471 }
472 }
473
474 if (!mdata->tx_sgl && !mdata->rx_sgl) {
475 /* spi disable dma */
476 cmd = readl(mdata->base + SPI_CMD_REG);
477 cmd &= ~SPI_CMD_TX_DMA;
478 cmd &= ~SPI_CMD_RX_DMA;
479 writel(cmd, mdata->base + SPI_CMD_REG);
480
481 spi_finalize_current_transfer(master);
482 return IRQ_HANDLED;
483 }
484
485 mtk_spi_update_mdata_len(master);
486 mtk_spi_setup_packet(master);
487 mtk_spi_setup_dma_addr(master, trans);
488 mtk_spi_enable_transfer(master);
489
490 return IRQ_HANDLED;
491}
492
493static int mtk_spi_probe(struct platform_device *pdev)
494{
495 struct spi_master *master;
496 struct mtk_spi *mdata;
497 const struct of_device_id *of_id;
498 struct resource *res;
50f8fec2 499 int irq, ret;
a568231f
LL		 500
501 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
502 if (!master) {
503 dev_err(&pdev->dev, "failed to alloc spi master\n");
504 return -ENOMEM;
505 }
506
507 master->auto_runtime_pm = true;
508 master->dev.of_node = pdev->dev.of_node;
509 master->mode_bits = SPI_CPOL | SPI_CPHA;
510
511 master->set_cs = mtk_spi_set_cs;
512 master->prepare_transfer_hardware = mtk_spi_prepare_hardware;
a568231f
LL		 513 master->prepare_message = mtk_spi_prepare_message;
514 master->transfer_one = mtk_spi_transfer_one;
515 master->can_dma = mtk_spi_can_dma;
516
517 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
518 if (!of_id) {
519 dev_err(&pdev->dev, "failed to probe of_node\n");
520 ret = -EINVAL;
521 goto err_put_master;
522 }
523
524 mdata = spi_master_get_devdata(master);
525 mdata->dev_comp = of_id->data;
526 if (mdata->dev_comp->must_tx)
527 master->flags = SPI_MASTER_MUST_TX;
528
529 if (mdata->dev_comp->need_pad_sel) {
530 ret = of_property_read_u32(pdev->dev.of_node,
531 "mediatek,pad-select",
532 &mdata->pad_sel);
533 if (ret) {
534 dev_err(&pdev->dev, "failed to read pad select: %d\n",
535 ret);
536 goto err_put_master;
537 }
538
539 if (mdata->pad_sel > MT8173_SPI_MAX_PAD_SEL) {
540 dev_err(&pdev->dev, "wrong pad-select: %u\n",
541 mdata->pad_sel);
542 ret = -EINVAL;
543 goto err_put_master;
544 }
545 }
546
547 platform_set_drvdata(pdev, master);
548
549 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
550 if (!res) {
551 ret = -ENODEV;
552 dev_err(&pdev->dev, "failed to determine base address\n");
553 goto err_put_master;
554 }
555
556 mdata->base = devm_ioremap_resource(&pdev->dev, res);
557 if (IS_ERR(mdata->base)) {
558 ret = PTR_ERR(mdata->base);
559 goto err_put_master;
560 }
561
562 irq = platform_get_irq(pdev, 0);
563 if (irq < 0) {
564 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
565 ret = irq;
566 goto err_put_master;
567 }
568
569 if (!pdev->dev.dma_mask)
570 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
571
572 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
573 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
574 if (ret) {
575 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
576 goto err_put_master;
577 }
578
adcbcfea
LL		 579 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
580 if (IS_ERR(mdata->parent_clk)) {
581 ret = PTR_ERR(mdata->parent_clk);
582 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
583 goto err_put_master;
584 }
585
586 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
587 if (IS_ERR(mdata->sel_clk)) {
e26d15f7 588 ret = PTR_ERR(mdata->sel_clk);
adcbcfea 589 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
a568231f
LL		 590 goto err_put_master;
591 }
592
adcbcfea
LL		 593 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
594 if (IS_ERR(mdata->spi_clk)) {
e26d15f7 595 ret = PTR_ERR(mdata->spi_clk);
adcbcfea 596 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
a568231f
LL		 597 goto err_put_master;
598 }
599
600 ret = clk_prepare_enable(mdata->spi_clk);
601 if (ret < 0) {
602 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
603 goto err_put_master;
604 }
605
adcbcfea 606 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
a568231f
LL		 607 if (ret < 0) {
608 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
609 goto err_disable_clk;
610 }
611
612 clk_disable_unprepare(mdata->spi_clk);
613
614 pm_runtime_enable(&pdev->dev);
615
616 ret = devm_spi_register_master(&pdev->dev, master);
617 if (ret) {
618 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
619 goto err_put_master;
620 }
621
622 return 0;
623
624err_disable_clk:
625 clk_disable_unprepare(mdata->spi_clk);
626err_put_master:
627 spi_master_put(master);
628
629 return ret;
630}
631
632static int mtk_spi_remove(struct platform_device *pdev)
633{
634 struct spi_master *master = platform_get_drvdata(pdev);
635 struct mtk_spi *mdata = spi_master_get_devdata(master);
636
637 pm_runtime_disable(&pdev->dev);
638
639 mtk_spi_reset(mdata);
a568231f
LL		 640 spi_master_put(master);
641
642 return 0;
643}
644
645#ifdef CONFIG_PM_SLEEP
646static int mtk_spi_suspend(struct device *dev)
647{
648 int ret;
649 struct spi_master *master = dev_get_drvdata(dev);
650 struct mtk_spi *mdata = spi_master_get_devdata(master);
651
652 ret = spi_master_suspend(master);
653 if (ret)
654 return ret;
655
656 if (!pm_runtime_suspended(dev))
657 clk_disable_unprepare(mdata->spi_clk);
658
659 return ret;
660}
661
662static int mtk_spi_resume(struct device *dev)
663{
664 int ret;
665 struct spi_master *master = dev_get_drvdata(dev);
666 struct mtk_spi *mdata = spi_master_get_devdata(master);
667
668 if (!pm_runtime_suspended(dev)) {
669 ret = clk_prepare_enable(mdata->spi_clk);
13da5a0b
LL		 670 if (ret < 0) {
671 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
a568231f 672 return ret;
13da5a0b 673 }
a568231f
LL		 674 }
675
676 ret = spi_master_resume(master);
677 if (ret < 0)
678 clk_disable_unprepare(mdata->spi_clk);
679
680 return ret;
681}
682#endif /* CONFIG_PM_SLEEP */
683
684#ifdef CONFIG_PM
685static int mtk_spi_runtime_suspend(struct device *dev)
686{
687 struct spi_master *master = dev_get_drvdata(dev);
688 struct mtk_spi *mdata = spi_master_get_devdata(master);
689
690 clk_disable_unprepare(mdata->spi_clk);
691
692 return 0;
693}
694
695static int mtk_spi_runtime_resume(struct device *dev)
696{
697 struct spi_master *master = dev_get_drvdata(dev);
698 struct mtk_spi *mdata = spi_master_get_devdata(master);
13da5a0b
LL		 699 int ret;
700
701 ret = clk_prepare_enable(mdata->spi_clk);
702 if (ret < 0) {
703 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
704 return ret;
705 }
a568231f 706
13da5a0b 707 return 0;
a568231f
LL		 708}
709#endif /* CONFIG_PM */
710
711static const struct dev_pm_ops mtk_spi_pm = {
712 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
713 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
714 mtk_spi_runtime_resume, NULL)
715};
716
4299aaaa 717static struct platform_driver mtk_spi_driver = {
a568231f
LL		 718 .driver = {
719 .name = "mtk-spi",
720 .pm = &mtk_spi_pm,
721 .of_match_table = mtk_spi_of_match,
722 },
723 .probe = mtk_spi_probe,
724 .remove = mtk_spi_remove,
725};
726
727module_platform_driver(mtk_spi_driver);
728
729MODULE_DESCRIPTION("MTK SPI Controller driver");
730MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
731MODULE_LICENSE("GPL v2");
e4001885 732MODULE_ALIAS("platform:mtk-spi");
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