[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-mt7621.c

// SPDX-License-Identifier: GPL-2.0
//
// spi-mt7621.c -- MediaTek MT7621 SPI controller driver
//
// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
//
// Some parts are based on spi-orion.c:
//   Author: Shadi Ammouri <shadi@marvell.com>
//   Copyright (C) 2007-2008 Marvell Ltd.

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/reset.h>
#include <linux/spi/spi.h>

#define DRIVER_NAME		"spi-mt7621"

/* in usec */
#define RALINK_SPI_WAIT_MAX_LOOP 2000

/* SPISTAT register bit field */
#define SPISTAT_BUSY		BIT(0)

#define MT7621_SPI_TRANS	0x00
#define SPITRANS_BUSY		BIT(16)

#define MT7621_SPI_OPCODE	0x04
#define MT7621_SPI_DATA0	0x08
#define MT7621_SPI_DATA4	0x18
#define SPI_CTL_TX_RX_CNT_MASK	0xff
#define SPI_CTL_START		BIT(8)

#define MT7621_SPI_MASTER	0x28
#define MASTER_MORE_BUFMODE	BIT(2)
#define MASTER_FULL_DUPLEX	BIT(10)
#define MASTER_RS_CLK_SEL	GENMASK(27, 16)
#define MASTER_RS_CLK_SEL_SHIFT	16
#define MASTER_RS_SLAVE_SEL	GENMASK(31, 29)

#define MT7621_SPI_MOREBUF	0x2c
#define MT7621_SPI_POLAR	0x38
#define MT7621_SPI_SPACE	0x3c

#define MT7621_CPHA		BIT(5)
#define MT7621_CPOL		BIT(4)
#define MT7621_LSB_FIRST	BIT(3)

struct mt7621_spi {
	struct spi_controller	*master;
	void __iomem		*base;
	unsigned int		sys_freq;
	unsigned int		speed;
	struct clk		*clk;
	int			pending_write;
};

static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
{
	return spi_controller_get_devdata(spi->master);
}

static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
{
	return ioread32(rs->base + reg);
}

static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
{
	iowrite32(val, rs->base + reg);
}

static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
{
	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	int cs = spi->chip_select;
	u32 polar = 0;
	u32 master;

	/*
	 * Select SPI device 7, enable "more buffer mode" and disable
	 * full-duplex (only half-duplex really works on this chip
	 * reliably)
	 */
	master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
	master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
	master &= ~MASTER_FULL_DUPLEX;
	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);

	rs->pending_write = 0;

	if (enable)
		polar = BIT(cs);
	mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
}

static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
{
	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	u32 rate;
	u32 reg;

	dev_dbg(&spi->dev, "speed:%u\n", speed);

	rate = DIV_ROUND_UP(rs->sys_freq, speed);
	dev_dbg(&spi->dev, "rate-1:%u\n", rate);

	if (rate > 4097)
		return -EINVAL;

	if (rate < 2)
		rate = 2;

	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
	reg &= ~MASTER_RS_CLK_SEL;
	reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
	rs->speed = speed;

	reg &= ~MT7621_LSB_FIRST;
	if (spi->mode & SPI_LSB_FIRST)
		reg |= MT7621_LSB_FIRST;

	/*
	 * This SPI controller seems to be tested on SPI flash only and some
	 * bits are swizzled under other SPI modes probably due to incorrect
	 * wiring inside the silicon. Only mode 0 works correctly.
	 */
	reg &= ~(MT7621_CPHA | MT7621_CPOL);

	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);

	return 0;
}

static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
{
	int i;

	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
		u32 status;

		status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
		if ((status & SPITRANS_BUSY) == 0)
			return 0;
		cpu_relax();
		udelay(1);
	}

	return -ETIMEDOUT;
}

static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
					int rx_len, u8 *buf)
{
	int tx_len;

	/*
	 * Combine with any pending write, and perform one or more half-duplex
	 * transactions reading 'len' bytes. Data to be written is already in
	 * MT7621_SPI_DATA.
	 */
	tx_len = rs->pending_write;
	rs->pending_write = 0;

	while (rx_len || tx_len) {
		int i;
		u32 val = (min(tx_len, 4) * 8) << 24;
		int rx = min(rx_len, 32);

		if (tx_len > 4)
			val |= (tx_len - 4) * 8;
		val |= (rx * 8) << 12;
		mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);

		tx_len = 0;

		val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
		val |= SPI_CTL_START;
		mt7621_spi_write(rs, MT7621_SPI_TRANS, val);

		mt7621_spi_wait_till_ready(rs);

		for (i = 0; i < rx; i++) {
			if ((i % 4) == 0)
				val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
			*buf++ = val & 0xff;
			val >>= 8;
		}

		rx_len -= i;
	}
}

static inline void mt7621_spi_flush(struct mt7621_spi *rs)
{
	mt7621_spi_read_half_duplex(rs, 0, NULL);
}

static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
					 int tx_len, const u8 *buf)
{
	int len = rs->pending_write;
	int val = 0;

	if (len & 3) {
		val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
		if (len < 4) {
			val <<= (4 - len) * 8;
			val = swab32(val);
		}
	}

	while (tx_len > 0) {
		if (len >= 36) {
			rs->pending_write = len;
			mt7621_spi_flush(rs);
			len = 0;
		}

		val |= *buf++ << (8 * (len & 3));
		len++;
		if ((len & 3) == 0) {
			if (len == 4)
				/* The byte-order of the opcode is weird! */
				val = swab32(val);
			mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
			val = 0;
		}
		tx_len -= 1;
	}

	if (len & 3) {
		if (len < 4) {
			val = swab32(val);
			val >>= (4 - len) * 8;
		}
		mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
	}

	rs->pending_write = len;
}

static int mt7621_spi_transfer_one_message(struct spi_controller *master,
					   struct spi_message *m)
{
	struct mt7621_spi *rs = spi_controller_get_devdata(master);
	struct spi_device *spi = m->spi;
	unsigned int speed = spi->max_speed_hz;
	struct spi_transfer *t = NULL;
	int status = 0;

	mt7621_spi_wait_till_ready(rs);

	list_for_each_entry(t, &m->transfers, transfer_list)
		if (t->speed_hz < speed)
			speed = t->speed_hz;

	if (mt7621_spi_prepare(spi, speed)) {
		status = -EIO;
		goto msg_done;
	}

	/* Assert CS */
	mt7621_spi_set_cs(spi, 1);

	m->actual_length = 0;
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if ((t->rx_buf) && (t->tx_buf)) {
			/*
			 * This controller will shift some extra data out
			 * of spi_opcode if (mosi_bit_cnt > 0) &&
			 * (cmd_bit_cnt == 0). So the claimed full-duplex
			 * support is broken since we have no way to read
			 * the MISO value during that bit.
			 */
			status = -EIO;
			goto msg_done;
		} else if (t->rx_buf) {
			mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
		} else if (t->tx_buf) {
			mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
		}
		m->actual_length += t->len;
	}

	/* Flush data and deassert CS */
	mt7621_spi_flush(rs);
	mt7621_spi_set_cs(spi, 0);

msg_done:
	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

static int mt7621_spi_setup(struct spi_device *spi)
{
	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);

	if ((spi->max_speed_hz == 0) ||
	    (spi->max_speed_hz > (rs->sys_freq / 2)))
		spi->max_speed_hz = rs->sys_freq / 2;

	if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
		dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
			spi->max_speed_hz);
		return -EINVAL;
	}

	return 0;
}

static const struct of_device_id mt7621_spi_match[] = {
	{ .compatible = "ralink,mt7621-spi" },
	{},
};
MODULE_DEVICE_TABLE(of, mt7621_spi_match);

static int mt7621_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct spi_controller *master;
	struct mt7621_spi *rs;
	void __iomem *base;
	int status = 0;
	struct clk *clk;
	int ret;

	match = of_match_device(mt7621_spi_match, &pdev->dev);
	if (!match)
		return -EINVAL;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
			status);
		return PTR_ERR(clk);
	}

	status = clk_prepare_enable(clk);
	if (status)
		return status;

	master = devm_spi_alloc_master(&pdev->dev, sizeof(*rs));
	if (!master) {
		dev_info(&pdev->dev, "master allocation failed\n");
		clk_disable_unprepare(clk);
		return -ENOMEM;
	}

	master->mode_bits = SPI_LSB_FIRST;
	master->flags = SPI_CONTROLLER_HALF_DUPLEX;
	master->setup = mt7621_spi_setup;
	master->transfer_one_message = mt7621_spi_transfer_one_message;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->dev.of_node = pdev->dev.of_node;
	master->num_chipselect = 2;

	dev_set_drvdata(&pdev->dev, master);

	rs = spi_controller_get_devdata(master);
	rs->base = base;
	rs->clk = clk;
	rs->master = master;
	rs->sys_freq = clk_get_rate(rs->clk);
	rs->pending_write = 0;
	dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);

	ret = device_reset(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "SPI reset failed!\n");
		clk_disable_unprepare(clk);
		return ret;
	}

	ret = spi_register_controller(master);
	if (ret)
		clk_disable_unprepare(clk);

	return ret;
}

static int mt7621_spi_remove(struct platform_device *pdev)
{
	struct spi_controller *master;
	struct mt7621_spi *rs;

	master = dev_get_drvdata(&pdev->dev);
	rs = spi_controller_get_devdata(master);

	spi_unregister_controller(master);
	clk_disable_unprepare(rs->clk);

	return 0;
}

MODULE_ALIAS("platform:" DRIVER_NAME);

static struct platform_driver mt7621_spi_driver = {
	.driver = {
		.name = DRIVER_NAME,
		.of_match_table = mt7621_spi_match,
	},
	.probe = mt7621_spi_probe,
	.remove = mt7621_spi_remove,
};

module_platform_driver(mt7621_spi_driver);

MODULE_DESCRIPTION("MT7621 SPI driver");
MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
MODULE_LICENSE("GPL");
Commit	Line	Data
9ad67a12	1	// SPDX-License-Identifier: GPL-2.0
cbd66c62 SR	2	//
	3	// spi-mt7621.c -- MediaTek MT7621 SPI controller driver
	4	//
	5	// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
	6	// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
	7	// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
	8	//
	9	// Some parts are based on spi-orion.c:
	10	// Author: Shadi Ammouri <shadi@marvell.com>
	11	// Copyright (C) 2007-2008 Marvell Ltd.
1ab7f2a4	12
1ab7f2a4	13	#include <linux/clk.h>
1ab7f2a4 JC	14	#include <linux/delay.h>
1ab7f2a4 JC	15	#include <linux/io.h>
dab7ed43 SR	16	#include <linux/module.h>
dab7ed43 SR	17	#include <linux/of_device.h>
1ab7f2a4 JC	18	#include <linux/reset.h>
1ab7f2a4 JC	19	#include <linux/spi/spi.h>
1ab7f2a4	20
718a4917 SR	21	#define DRIVER_NAME "spi-mt7621"
718a4917 SR	22
1ab7f2a4	23	/* in usec */
718a4917	24	#define RALINK_SPI_WAIT_MAX_LOOP 2000
1ab7f2a4 JC	25
1ab7f2a4 JC	26	/* SPISTAT register bit field */
718a4917	27	#define SPISTAT_BUSY BIT(0)
1ab7f2a4 JC	28
	29	#define MT7621_SPI_TRANS 0x00
	30	#define SPITRANS_BUSY BIT(16)
	31
	32	#define MT7621_SPI_OPCODE 0x04
	33	#define MT7621_SPI_DATA0 0x08
	34	#define MT7621_SPI_DATA4 0x18
	35	#define SPI_CTL_TX_RX_CNT_MASK 0xff
	36	#define SPI_CTL_START BIT(8)
	37
1ab7f2a4	38	#define MT7621_SPI_MASTER 0x28
5220dd4f SR	39	#define MASTER_MORE_BUFMODE BIT(2)
	40	#define MASTER_FULL_DUPLEX BIT(10)
	41	#define MASTER_RS_CLK_SEL GENMASK(27, 16)
	42	#define MASTER_RS_CLK_SEL_SHIFT 16
	43	#define MASTER_RS_SLAVE_SEL GENMASK(31, 29)
	44
1ab7f2a4	45	#define MT7621_SPI_MOREBUF 0x2c
376a6220	46	#define MT7621_SPI_POLAR 0x38
1ab7f2a4 JC	47	#define MT7621_SPI_SPACE 0x3c
	48
	49	#define MT7621_CPHA BIT(5)
	50	#define MT7621_CPOL BIT(4)
	51	#define MT7621_LSB_FIRST BIT(3)
	52
1ab7f2a4	53	struct mt7621_spi {
cbd66c62	54	struct spi_controller *master;
1ab7f2a4 JC	55	void __iomem *base;
	56	unsigned int sys_freq;
	57	unsigned int speed;
	58	struct clk *clk;
bf732c6b	59	int pending_write;
1ab7f2a4 JC	60	};
	61
	62	static inline struct mt7621_spi spidev_to_mt7621_spi(struct spi_device spi)
	63	{
cbd66c62	64	return spi_controller_get_devdata(spi->master);
1ab7f2a4 JC	65	}
	66
	67	static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
	68	{
	69	return ioread32(rs->base + reg);
	70	}
	71
	72	static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
	73	{
	74	iowrite32(val, rs->base + reg);
	75	}
	76
cbd66c62	77	static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
1ab7f2a4	78	{
cbd66c62 SR	79	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	80	int cs = spi->chip_select;
	81	u32 polar = 0;
	82	u32 master;
1ab7f2a4	83
5220dd4f SR	84	/*
	85	* Select SPI device 7, enable "more buffer mode" and disable
	86	* full-duplex (only half-duplex really works on this chip
	87	* reliably)
	88	*/
cbd66c62	89	master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
5220dd4f SR	90	master \|= MASTER_RS_SLAVE_SEL \| MASTER_MORE_BUFMODE;
5220dd4f SR	91	master &= ~MASTER_FULL_DUPLEX;
1ab7f2a4	92	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
1ab7f2a4	93
cbd66c62	94	rs->pending_write = 0;
1ab7f2a4	95
1ab7f2a4 JC	96	if (enable)
	97	polar = BIT(cs);
	98	mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
	99	}
	100
	101	static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
	102	{
	103	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	104	u32 rate;
	105	u32 reg;
	106
	107	dev_dbg(&spi->dev, "speed:%u\n", speed);
	108
	109	rate = DIV_ROUND_UP(rs->sys_freq, speed);
	110	dev_dbg(&spi->dev, "rate-1:%u\n", rate);
	111
	112	if (rate > 4097)
	113	return -EINVAL;
	114
	115	if (rate < 2)
	116	rate = 2;
	117
	118	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
5220dd4f SR	119	reg &= ~MASTER_RS_CLK_SEL;
5220dd4f SR	120	reg \|= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
1ab7f2a4 JC	121	rs->speed = speed;
	122
	123	reg &= ~MT7621_LSB_FIRST;
	124	if (spi->mode & SPI_LSB_FIRST)
	125	reg \|= MT7621_LSB_FIRST;
	126
feec667e SR	127	/*
	128	* This SPI controller seems to be tested on SPI flash only and some
	129	* bits are swizzled under other SPI modes probably due to incorrect
	130	* wiring inside the silicon. Only mode 0 works correctly.
354ea2ee	131	*/
1ab7f2a4	132	reg &= ~(MT7621_CPHA \| MT7621_CPOL);
354ea2ee	133
1ab7f2a4 JC	134	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
	135
	136	return 0;
	137	}
	138
a83834c1	139	static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
1ab7f2a4	140	{
1ab7f2a4 JC	141	int i;
	142
	143	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
	144	u32 status;
	145
	146	status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
9c562d84	147	if ((status & SPITRANS_BUSY) == 0)
1ab7f2a4	148	return 0;
1ab7f2a4 JC	149	cpu_relax();
	150	udelay(1);
	151	}
	152
	153	return -ETIMEDOUT;
	154	}
	155
bf732c6b N	156	static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
bf732c6b N	157	int rx_len, u8 *buf)
1ab7f2a4	158	{
cbd66c62 SR	159	int tx_len;
cbd66c62 SR	160
feec667e SR	161	/*
	162	* Combine with any pending write, and perform one or more half-duplex
	163	* transactions reading 'len' bytes. Data to be written is already in
	164	* MT7621_SPI_DATA.
bf732c6b	165	*/
cbd66c62	166	tx_len = rs->pending_write;
bf732c6b	167	rs->pending_write = 0;
1ab7f2a4	168
bf732c6b N	169	while (rx_len \|\| tx_len) {
	170	int i;
	171	u32 val = (min(tx_len, 4) * 8) << 24;
	172	int rx = min(rx_len, 32);
1ab7f2a4	173
bf732c6b N	174	if (tx_len > 4)
	175	val \|= (tx_len - 4) * 8;
	176	val \|= (rx * 8) << 12;
	177	mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
1ab7f2a4	178
bf732c6b	179	tx_len = 0;
1ab7f2a4	180
bf732c6b N	181	val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
	182	val \|= SPI_CTL_START;
	183	mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
1ab7f2a4	184
bf732c6b	185	mt7621_spi_wait_till_ready(rs);
1ab7f2a4	186
bf732c6b N	187	for (i = 0; i < rx; i++) {
	188	if ((i % 4) == 0)
	189	val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
	190	*buf++ = val & 0xff;
	191	val >>= 8;
	192	}
718a4917	193
bf732c6b	194	rx_len -= i;
1ab7f2a4	195	}
bf732c6b	196	}
1ab7f2a4	197
bf732c6b N	198	static inline void mt7621_spi_flush(struct mt7621_spi *rs)
	199	{
	200	mt7621_spi_read_half_duplex(rs, 0, NULL);
	201	}
1ab7f2a4	202
bf732c6b N	203	static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
	204	int tx_len, const u8 *buf)
	205	{
bf732c6b	206	int len = rs->pending_write;
cbd66c62	207	int val = 0;
bf732c6b N	208
	209	if (len & 3) {
	210	val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
	211	if (len < 4) {
	212	val <<= (4 - len) * 8;
	213	val = swab32(val);
	214	}
1ab7f2a4	215	}
1ab7f2a4	216
bf732c6b N	217	while (tx_len > 0) {
	218	if (len >= 36) {
	219	rs->pending_write = len;
	220	mt7621_spi_flush(rs);
	221	len = 0;
	222	}
1ab7f2a4	223
bf732c6b N	224	val \|= buf++ << (8 (len & 3));
	225	len++;
	226	if ((len & 3) == 0) {
	227	if (len == 4)
	228	/* The byte-order of the opcode is weird! */
	229	val = swab32(val);
	230	mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
	231	val = 0;
	232	}
	233	tx_len -= 1;
	234	}
cbd66c62	235
bf732c6b N	236	if (len & 3) {
	237	if (len < 4) {
	238	val = swab32(val);
	239	val >>= (4 - len) * 8;
	240	}
	241	mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
	242	}
cbd66c62	243
bf732c6b N	244	rs->pending_write = len;
bf732c6b N	245	}
1ab7f2a4	246
cbd66c62	247	static int mt7621_spi_transfer_one_message(struct spi_controller *master,
bf732c6b N	248	struct spi_message *m)
bf732c6b N	249	{
cbd66c62	250	struct mt7621_spi *rs = spi_controller_get_devdata(master);
bf732c6b N	251	struct spi_device *spi = m->spi;
	252	unsigned int speed = spi->max_speed_hz;
	253	struct spi_transfer *t = NULL;
	254	int status = 0;
1ab7f2a4	255
a83834c1	256	mt7621_spi_wait_till_ready(rs);
1ab7f2a4	257
bf732c6b N	258	list_for_each_entry(t, &m->transfers, transfer_list)
	259	if (t->speed_hz < speed)
	260	speed = t->speed_hz;
1ab7f2a4	261
bf732c6b N	262	if (mt7621_spi_prepare(spi, speed)) {
	263	status = -EIO;
	264	goto msg_done;
	265	}
1ab7f2a4	266
cbd66c62	267	/* Assert CS */
bf732c6b	268	mt7621_spi_set_cs(spi, 1);
cbd66c62	269
bf732c6b	270	m->actual_length = 0;
1ab7f2a4	271	list_for_each_entry(t, &m->transfers, transfer_list) {
108d9dd5	272	if ((t->rx_buf) && (t->tx_buf)) {
cbd66c62 SR	273	/*
cbd66c62 SR	274	* This controller will shift some extra data out
108d9dd5 CG	275	* of spi_opcode if (mosi_bit_cnt > 0) &&
	276	* (cmd_bit_cnt == 0). So the claimed full-duplex
	277	* support is broken since we have no way to read
	278	* the MISO value during that bit.
	279	*/
	280	status = -EIO;
	281	goto msg_done;
	282	} else if (t->rx_buf) {
bf732c6b	283	mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
108d9dd5	284	} else if (t->tx_buf) {
bf732c6b	285	mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
108d9dd5	286	}
bf732c6b	287	m->actual_length += t->len;
1ab7f2a4 JC	288	}
1ab7f2a4 JC	289
cbd66c62 SR	290	/* Flush data and deassert CS */
cbd66c62 SR	291	mt7621_spi_flush(rs);
bf732c6b	292	mt7621_spi_set_cs(spi, 0);
718a4917	293
1ab7f2a4 JC	294	msg_done:
	295	m->status = status;
	296	spi_finalize_current_message(master);
	297
	298	return 0;
	299	}
	300
1ab7f2a4 JC	301	static int mt7621_spi_setup(struct spi_device *spi)
	302	{
	303	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	304
	305	if ((spi->max_speed_hz == 0) \|\|
cbd66c62	306	(spi->max_speed_hz > (rs->sys_freq / 2)))
18f0e249	307	spi->max_speed_hz = rs->sys_freq / 2;
1ab7f2a4 JC	308
	309	if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
	310	dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
	311	spi->max_speed_hz);
	312	return -EINVAL;
	313	}
	314
	315	return 0;
	316	}
	317
	318	static const struct of_device_id mt7621_spi_match[] = {
	319	{ .compatible = "ralink,mt7621-spi" },
	320	{},
	321	};
	322	MODULE_DEVICE_TABLE(of, mt7621_spi_match);
	323
1ab7f2a4 JC	324	static int mt7621_spi_probe(struct platform_device *pdev)
	325	{
	326	const struct of_device_id *match;
cbd66c62	327	struct spi_controller *master;
1ab7f2a4	328	struct mt7621_spi *rs;
1ab7f2a4	329	void __iomem *base;
1ab7f2a4 JC	330	int status = 0;
1ab7f2a4 JC	331	struct clk *clk;
46c33787	332	int ret;
1ab7f2a4 JC	333
	334	match = of_match_device(mt7621_spi_match, &pdev->dev);
	335	if (!match)
	336	return -EINVAL;
1ab7f2a4	337
f88771ca	338	base = devm_platform_ioremap_resource(pdev, 0);
1ab7f2a4 JC	339	if (IS_ERR(base))
	340	return PTR_ERR(base);
	341
	342	clk = devm_clk_get(&pdev->dev, NULL);
	343	if (IS_ERR(clk)) {
	344	dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
	345	status);
	346	return PTR_ERR(clk);
	347	}
	348
	349	status = clk_prepare_enable(clk);
	350	if (status)
	351	return status;
	352
46b5c4fb	353	master = devm_spi_alloc_master(&pdev->dev, sizeof(*rs));
5ccbce3a	354	if (!master) {
1ab7f2a4	355	dev_info(&pdev->dev, "master allocation failed\n");
702b15cb	356	clk_disable_unprepare(clk);
1ab7f2a4 JC	357	return -ENOMEM;
	358	}
	359
354ea2ee	360	master->mode_bits = SPI_LSB_FIRST;
cbd66c62	361	master->flags = SPI_CONTROLLER_HALF_DUPLEX;
1ab7f2a4 JC	362	master->setup = mt7621_spi_setup;
	363	master->transfer_one_message = mt7621_spi_transfer_one_message;
	364	master->bits_per_word_mask = SPI_BPW_MASK(8);
	365	master->dev.of_node = pdev->dev.of_node;
	366	master->num_chipselect = 2;
1ab7f2a4 JC	367
	368	dev_set_drvdata(&pdev->dev, master);
	369
cbd66c62	370	rs = spi_controller_get_devdata(master);
1ab7f2a4 JC	371	rs->base = base;
	372	rs->clk = clk;
	373	rs->master = master;
	374	rs->sys_freq = clk_get_rate(rs->clk);
bf732c6b	375	rs->pending_write = 0;
1ab7f2a4	376	dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
1ab7f2a4	377
46c33787 SR	378	ret = device_reset(&pdev->dev);
	379	if (ret) {
	380	dev_err(&pdev->dev, "SPI reset failed!\n");
702b15cb	381	clk_disable_unprepare(clk);
46c33787 SR	382	return ret;
46c33787 SR	383	}
1ab7f2a4	384
46b5c4fb	385	ret = spi_register_controller(master);
24f70334 LW	386	if (ret)
	387	clk_disable_unprepare(clk);
	388
	389	return ret;
1ab7f2a4 JC	390	}
	391
	392	static int mt7621_spi_remove(struct platform_device *pdev)
	393	{
cbd66c62	394	struct spi_controller *master;
1ab7f2a4 JC	395	struct mt7621_spi *rs;
	396
	397	master = dev_get_drvdata(&pdev->dev);
cbd66c62	398	rs = spi_controller_get_devdata(master);
1ab7f2a4	399
46b5c4fb	400	spi_unregister_controller(master);
cbd66c62	401	clk_disable_unprepare(rs->clk);
1ab7f2a4 JC	402
	403	return 0;
	404	}
	405
	406	MODULE_ALIAS("platform:" DRIVER_NAME);
	407
	408	static struct platform_driver mt7621_spi_driver = {
	409	.driver = {
	410	.name = DRIVER_NAME,
1ab7f2a4 JC	411	.of_match_table = mt7621_spi_match,
	412	},
	413	.probe = mt7621_spi_probe,
	414	.remove = mt7621_spi_remove,
	415	};
	416
	417	module_platform_driver(mt7621_spi_driver);
	418
	419	MODULE_DESCRIPTION("MT7621 SPI driver");
	420	MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
	421	MODULE_LICENSE("GPL");