[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-mxs.c

/*
 * Freescale MXS SPI master driver
 *
 * Copyright 2012 DENX Software Engineering, GmbH.
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * Rework and transition to new API by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on previous attempt by:
 * Fabio Estevam <fabio.estevam@freescale.com>
 *
 * Based on code from U-Boot bootloader by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on spi-stmp.c, which is:
 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/module.h>
#include <linux/stmp_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/mxs-spi.h>

#define DRIVER_NAME		"mxs-spi"

/* Use 10S timeout for very long transfers, it should suffice. */
#define SSP_TIMEOUT		10000

#define SG_MAXLEN		0xff00

/*
 * Flags for txrx functions.  More efficient that using an argument register for
 * each one.
 */
#define TXRX_WRITE		(1<<0)	/* This is a write */
#define TXRX_DEASSERT_CS	(1<<1)	/* De-assert CS at end of txrx */

struct mxs_spi {
	struct mxs_ssp		ssp;
	struct completion	c;
	unsigned int		sck;	/* Rate requested (vs actual) */
};

static int mxs_spi_setup_transfer(struct spi_device *dev,
				  const struct spi_transfer *t)
{
	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	struct mxs_ssp *ssp = &spi->ssp;
	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);

	if (hz == 0) {
		dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
		return -EINVAL;
	}

	if (hz != spi->sck) {
		mxs_ssp_set_clk_rate(ssp, hz);
		/*
		 * Save requested rate, hz, rather than the actual rate,
		 * ssp->clk_rate.  Otherwise we would set the rate every transfer
		 * when the actual rate is not quite the same as requested rate.
		 */
		spi->sck = hz;
		/*
		 * Perhaps we should return an error if the actual clock is
		 * nowhere close to what was requested?
		 */
	}

	writel(BM_SSP_CTRL0_LOCK_CS,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
	       BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
	       ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
	       ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	       ssp->base + HW_SSP_CTRL1(ssp));

	writel(0x0, ssp->base + HW_SSP_CMD0);
	writel(0x0, ssp->base + HW_SSP_CMD1);

	return 0;
}

static u32 mxs_spi_cs_to_reg(unsigned cs)
{
	u32 select = 0;

	/*
	 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	 *
	 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
	 * the datasheet for further details. In SPI mode, they are used to
	 * toggle the chip-select lines (nCS pins).
	 */
	if (cs & 1)
		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
	if (cs & 2)
		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;

	return select;
}

static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
{
	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
	struct mxs_ssp *ssp = &spi->ssp;
	u32 reg;

	do {
		reg = readl_relaxed(ssp->base + offset);

		if (!set)
			reg = ~reg;

		reg &= mask;

		if (reg == mask)
			return 0;
	} while (time_before(jiffies, timeout));

	return -ETIMEDOUT;
}

static void mxs_ssp_dma_irq_callback(void *param)
{
	struct mxs_spi *spi = param;

	complete(&spi->c);
}

static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
{
	struct mxs_ssp *ssp = dev_id;

	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
		__func__, __LINE__,
		readl(ssp->base + HW_SSP_CTRL1(ssp)),
		readl(ssp->base + HW_SSP_STATUS(ssp)));
	return IRQ_HANDLED;
}

static int mxs_spi_txrx_dma(struct mxs_spi *spi,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;
	struct dma_async_tx_descriptor *desc = NULL;
	const bool vmalloced_buf = is_vmalloc_addr(buf);
	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	const int sgs = DIV_ROUND_UP(len, desc_len);
	int sg_count;
	int min, ret;
	u32 ctrl0;
	struct page *vm_page;
	struct {
		u32			pio[4];
		struct scatterlist	sg;
	} *dma_xfer;

	if (!len)
		return -EINVAL;

	dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
	if (!dma_xfer)
		return -ENOMEM;

	reinit_completion(&spi->c);

	/* Chip select was already programmed into CTRL0 */
	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
		 BM_SSP_CTRL0_READ);
	ctrl0 |= BM_SSP_CTRL0_DATA_XFER;

	if (!(flags & TXRX_WRITE))
		ctrl0 |= BM_SSP_CTRL0_READ;

	/* Queue the DMA data transfer. */
	for (sg_count = 0; sg_count < sgs; sg_count++) {
		/* Prepare the transfer descriptor. */
		min = min(len, desc_len);

		/*
		 * De-assert CS on last segment if flag is set (i.e., no more
		 * transfers will follow)
		 */
		if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
			ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;

		if (ssp->devid == IMX23_SSP) {
			ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
			ctrl0 |= min;
		}

		dma_xfer[sg_count].pio[0] = ctrl0;
		dma_xfer[sg_count].pio[3] = min;

		if (vmalloced_buf) {
			vm_page = vmalloc_to_page(buf);
			if (!vm_page) {
				ret = -ENOMEM;
				goto err_vmalloc;
			}

			sg_init_table(&dma_xfer[sg_count].sg, 1);
			sg_set_page(&dma_xfer[sg_count].sg, vm_page,
				    min, offset_in_page(buf));
		} else {
			sg_init_one(&dma_xfer[sg_count].sg, buf, min);
		}

		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);

		len -= min;
		buf += min;

		/* Queue the PIO register write transfer. */
		desc = dmaengine_prep_slave_sg(ssp->dmach,
				(struct scatterlist *)dma_xfer[sg_count].pio,
				(ssp->devid == IMX23_SSP) ? 1 : 4,
				DMA_TRANS_NONE,
				sg_count ? DMA_PREP_INTERRUPT : 0);
		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get PIO reg. write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}

		desc = dmaengine_prep_slave_sg(ssp->dmach,
				&dma_xfer[sg_count].sg, 1,
				(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get DMA data write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}
	}

	/*
	 * The last descriptor must have this callback,
	 * to finish the DMA transaction.
	 */
	desc->callback = mxs_ssp_dma_irq_callback;
	desc->callback_param = spi;

	/* Start the transfer. */
	dmaengine_submit(desc);
	dma_async_issue_pending(ssp->dmach);

	if (!wait_for_completion_timeout(&spi->c,
					 msecs_to_jiffies(SSP_TIMEOUT))) {
		dev_err(ssp->dev, "DMA transfer timeout\n");
		ret = -ETIMEDOUT;
		dmaengine_terminate_all(ssp->dmach);
		goto err_vmalloc;
	}

	ret = 0;

err_vmalloc:
	while (--sg_count >= 0) {
err_mapped:
		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	}

	kfree(dma_xfer);

	return ret;
}

static int mxs_spi_txrx_pio(struct mxs_spi *spi,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;

	writel(BM_SSP_CTRL0_IGNORE_CRC,
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);

	while (len--) {
		if (len == 0 && (flags & TXRX_DEASSERT_CS))
			writel(BM_SSP_CTRL0_IGNORE_CRC,
			       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (ssp->devid == IMX23_SSP) {
			writel(BM_SSP_CTRL0_XFER_COUNT,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
			writel(1,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
		} else {
			writel(1, ssp->base + HW_SSP_XFER_SIZE);
		}

		if (flags & TXRX_WRITE)
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
		else
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		writel(BM_SSP_CTRL0_RUN,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
			return -ETIMEDOUT;

		if (flags & TXRX_WRITE)
			writel(*buf, ssp->base + HW_SSP_DATA(ssp));

		writel(BM_SSP_CTRL0_DATA_XFER,
			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (!(flags & TXRX_WRITE)) {
			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
						BM_SSP_STATUS_FIFO_EMPTY, 0))
				return -ETIMEDOUT;

			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
		}

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
			return -ETIMEDOUT;

		buf++;
	}

	if (len <= 0)
		return 0;

	return -ETIMEDOUT;
}

static int mxs_spi_transfer_one(struct spi_master *master,
				struct spi_message *m)
{
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	struct spi_transfer *t;
	unsigned int flag;
	int status = 0;

	/* Program CS register bits here, it will be used for all transfers. */
	writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	writel(mxs_spi_cs_to_reg(m->spi->chip_select),
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

	list_for_each_entry(t, &m->transfers, transfer_list) {

		status = mxs_spi_setup_transfer(m->spi, t);
		if (status)
			break;

		/* De-assert on last transfer, inverted by cs_change flag */
		flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
		       TXRX_DEASSERT_CS : 0;

		/*
		 * Small blocks can be transfered via PIO.
		 * Measured by empiric means:
		 *
		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
		 *
		 * DMA only: 2.164808 seconds, 473.0KB/s
		 * Combined: 1.676276 seconds, 610.9KB/s
		 */
		if (t->len < 32) {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_CLR);

			if (t->tx_buf)
				status = mxs_spi_txrx_pio(spi,
						(void *)t->tx_buf,
						t->len, flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_pio(spi,
						t->rx_buf, t->len,
						flag);
		} else {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_SET);

			if (t->tx_buf)
				status = mxs_spi_txrx_dma(spi,
						(void *)t->tx_buf, t->len,
						flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_dma(spi,
						t->rx_buf, t->len,
						flag);
		}

		if (status) {
			stmp_reset_block(ssp->base);
			break;
		}

		m->actual_length += t->len;
	}

	m->status = status;
	spi_finalize_current_message(master);

	return status;
}

static const struct of_device_id mxs_spi_dt_ids[] = {
	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);

static int mxs_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_spi_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;
	struct resource *iores;
	struct clk *clk;
	void __iomem *base;
	int devid, clk_freq;
	int ret = 0, irq_err;

	/*
	 * Default clock speed for the SPI core. 160MHz seems to
	 * work reasonably well with most SPI flashes, so use this
	 * as a default. Override with "clock-frequency" DT prop.
	 */
	const int clk_freq_default = 160000000;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq_err = platform_get_irq(pdev, 0);
	if (irq_err < 0)
		return irq_err;

	base = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	devid = (enum mxs_ssp_id) of_id->data;
	ret = of_property_read_u32(np, "clock-frequency",
				   &clk_freq);
	if (ret)
		clk_freq = clk_freq_default;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (!master)
		return -ENOMEM;

	master->transfer_one_message = mxs_spi_transfer_one;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->num_chipselect = 3;
	master->dev.of_node = np;
	master->flags = SPI_MASTER_HALF_DUPLEX;

	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;
	ssp->dev = &pdev->dev;
	ssp->clk = clk;
	ssp->base = base;
	ssp->devid = devid;

	init_completion(&spi->c);

	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
			       dev_name(&pdev->dev), ssp);
	if (ret)
		goto out_master_free;

	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
	if (!ssp->dmach) {
		dev_err(ssp->dev, "Failed to request DMA\n");
		ret = -ENODEV;
		goto out_master_free;
	}

	ret = clk_prepare_enable(ssp->clk);
	if (ret)
		goto out_dma_release;

	clk_set_rate(ssp->clk, clk_freq);

	ret = stmp_reset_block(ssp->base);
	if (ret)
		goto out_disable_clk;

	platform_set_drvdata(pdev, master);

	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret) {
		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
		goto out_disable_clk;
	}

	return 0;

out_disable_clk:
	clk_disable_unprepare(ssp->clk);
out_dma_release:
	dma_release_channel(ssp->dmach);
out_master_free:
	spi_master_put(master);
	return ret;
}

static int mxs_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;

	master = platform_get_drvdata(pdev);
	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;

	clk_disable_unprepare(ssp->clk);
	dma_release_channel(ssp->dmach);

	return 0;
}

static struct platform_driver mxs_spi_driver = {
	.probe	= mxs_spi_probe,
	.remove	= mxs_spi_remove,
	.driver	= {
		.name	= DRIVER_NAME,
		.of_match_table = mxs_spi_dt_ids,
	},
};

module_platform_driver(mxs_spi_driver);

MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_DESCRIPTION("MXS SPI master driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mxs-spi");
Commit	Line	Data
646781d3 MV	1	/*
	2	* Freescale MXS SPI master driver
	3	*
	4	* Copyright 2012 DENX Software Engineering, GmbH.
	5	* Copyright 2012 Freescale Semiconductor, Inc.
	6	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
	7	*
	8	* Rework and transition to new API by:
	9	* Marek Vasut <marex@denx.de>
	10	*
	11	* Based on previous attempt by:
	12	* Fabio Estevam <fabio.estevam@freescale.com>
	13	*
	14	* Based on code from U-Boot bootloader by:
	15	* Marek Vasut <marex@denx.de>
	16	*
	17	* Based on spi-stmp.c, which is:
	18	* Author: Dmitry Pervushin <dimka@embeddedalley.com>
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License as published by
	22	* the Free Software Foundation; either version 2 of the License, or
	23	* (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*/
	30
	31	#include <linux/kernel.h>
646781d3 MV	32	#include <linux/ioport.h>
	33	#include <linux/of.h>
	34	#include <linux/of_device.h>
	35	#include <linux/of_gpio.h>
	36	#include <linux/platform_device.h>
	37	#include <linux/delay.h>
	38	#include <linux/interrupt.h>
	39	#include <linux/dma-mapping.h>
	40	#include <linux/dmaengine.h>
	41	#include <linux/highmem.h>
	42	#include <linux/clk.h>
	43	#include <linux/err.h>
	44	#include <linux/completion.h>
	45	#include <linux/gpio.h>
	46	#include <linux/regulator/consumer.h>
	47	#include <linux/module.h>
646781d3 MV	48	#include <linux/stmp_device.h>
	49	#include <linux/spi/spi.h>
	50	#include <linux/spi/mxs-spi.h>
	51
	52	#define DRIVER_NAME "mxs-spi"
	53
010b4818 MV	54	/* Use 10S timeout for very long transfers, it should suffice. */
010b4818 MV	55	#define SSP_TIMEOUT 10000
646781d3	56
474afc04 MV	57	#define SG_MAXLEN 0xff00
474afc04 MV	58
28cad125 TP	59	/*
	60	* Flags for txrx functions. More efficient that using an argument register for
	61	* each one.
	62	*/
	63	#define TXRX_WRITE (1<<0) /* This is a write */
	64	#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
	65
646781d3 MV	66	struct mxs_spi {
646781d3 MV	67	struct mxs_ssp ssp;
474afc04	68	struct completion c;
a560943e	69	unsigned int sck; /* Rate requested (vs actual) */
646781d3 MV	70	};
	71
	72	static int mxs_spi_setup_transfer(struct spi_device *dev,
aa9e0c6f	73	const struct spi_transfer *t)
646781d3 MV	74	{
	75	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	76	struct mxs_ssp *ssp = &spi->ssp;
aa9e0c6f	77	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
646781d3	78
646781d3	79	if (hz == 0) {
aa9e0c6f	80	dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
646781d3 MV	81	return -EINVAL;
	82	}
	83
a560943e TP	84	if (hz != spi->sck) {
	85	mxs_ssp_set_clk_rate(ssp, hz);
	86	/*
	87	* Save requested rate, hz, rather than the actual rate,
a44619c3	88	* ssp->clk_rate. Otherwise we would set the rate every transfer
a560943e TP	89	* when the actual rate is not quite the same as requested rate.
	90	*/
	91	spi->sck = hz;
	92	/*
	93	* Perhaps we should return an error if the actual clock is
	94	* nowhere close to what was requested?
	95	*/
	96	}
646781d3	97
58f46e41 TP	98	writel(BM_SSP_CTRL0_LOCK_CS,
58f46e41 TP	99	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	100
646781d3 MV	101	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) \|
aa9e0c6f TP	102	BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) \|
	103	((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) \|
	104	((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	105	ssp->base + HW_SSP_CTRL1(ssp));
646781d3 MV	106
	107	writel(0x0, ssp->base + HW_SSP_CMD0);
	108	writel(0x0, ssp->base + HW_SSP_CMD1);
	109
	110	return 0;
	111	}
	112
42e182f8	113	static u32 mxs_spi_cs_to_reg(unsigned cs)
646781d3	114	{
42e182f8	115	u32 select = 0;
646781d3 MV	116
	117	/*
	118	* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	119	*
	120	* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	121	* in HW_SSP_CTRL0 register do have multiple usage, please refer to
	122	* the datasheet for further details. In SPI mode, they are used to
	123	* toggle the chip-select lines (nCS pins).
	124	*/
	125	if (cs & 1)
	126	select \|= BM_SSP_CTRL0_WAIT_FOR_CMD;
	127	if (cs & 2)
	128	select \|= BM_SSP_CTRL0_WAIT_FOR_IRQ;
	129
	130	return select;
	131	}
	132
646781d3 MV	133	static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
646781d3 MV	134	{
f13639dc	135	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
646781d3	136	struct mxs_ssp *ssp = &spi->ssp;
42e182f8	137	u32 reg;
646781d3	138
f13639dc	139	do {
646781d3 MV	140	reg = readl_relaxed(ssp->base + offset);
646781d3 MV	141
f13639dc MV	142	if (!set)
f13639dc MV	143	reg = ~reg;
646781d3	144
f13639dc	145	reg &= mask;
646781d3	146
f13639dc MV	147	if (reg == mask)
	148	return 0;
	149	} while (time_before(jiffies, timeout));
646781d3	150
f13639dc	151	return -ETIMEDOUT;
646781d3 MV	152	}
646781d3 MV	153
474afc04 MV	154	static void mxs_ssp_dma_irq_callback(void *param)
	155	{
	156	struct mxs_spi *spi = param;
a7fa3219	157
474afc04 MV	158	complete(&spi->c);
	159	}
	160
	161	static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
	162	{
	163	struct mxs_ssp *ssp = dev_id;
a7fa3219	164
474afc04 MV	165	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
	166	__func__, __LINE__,
	167	readl(ssp->base + HW_SSP_CTRL1(ssp)),
	168	readl(ssp->base + HW_SSP_STATUS(ssp)));
	169	return IRQ_HANDLED;
	170	}
	171
0b782f70	172	static int mxs_spi_txrx_dma(struct mxs_spi *spi,
474afc04	173	unsigned char *buf, int len,
28cad125	174	unsigned int flags)
474afc04 MV	175	{
474afc04 MV	176	struct mxs_ssp *ssp = &spi->ssp;
010b4818 MV	177	struct dma_async_tx_descriptor *desc = NULL;
	178	const bool vmalloced_buf = is_vmalloc_addr(buf);
	179	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	180	const int sgs = DIV_ROUND_UP(len, desc_len);
474afc04	181	int sg_count;
010b4818	182	int min, ret;
42e182f8	183	u32 ctrl0;
010b4818	184	struct page *vm_page;
010b4818	185	struct {
42e182f8	186	u32 pio[4];
010b4818 MV	187	struct scatterlist sg;
	188	} *dma_xfer;
	189
	190	if (!len)
474afc04	191	return -EINVAL;
010b4818	192
a7fa3219	193	dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
010b4818 MV	194	if (!dma_xfer)
010b4818 MV	195	return -ENOMEM;
474afc04	196
16735d02	197	reinit_completion(&spi->c);
474afc04	198
0b782f70	199	/* Chip select was already programmed into CTRL0 */
010b4818	200	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
df23286e TP	201	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT \| BM_SSP_CTRL0_IGNORE_CRC \|
df23286e TP	202	BM_SSP_CTRL0_READ);
0b782f70	203	ctrl0 \|= BM_SSP_CTRL0_DATA_XFER;
010b4818	204
28cad125	205	if (!(flags & TXRX_WRITE))
010b4818	206	ctrl0 \|= BM_SSP_CTRL0_READ;
474afc04 MV	207
474afc04 MV	208	/* Queue the DMA data transfer. */
010b4818	209	for (sg_count = 0; sg_count < sgs; sg_count++) {
28cad125	210	/* Prepare the transfer descriptor. */
010b4818 MV	211	min = min(len, desc_len);
010b4818 MV	212
28cad125 TP	213	/*
	214	* De-assert CS on last segment if flag is set (i.e., no more
	215	* transfers will follow)
	216	*/
	217	if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
010b4818 MV	218	ctrl0 \|= BM_SSP_CTRL0_IGNORE_CRC;
010b4818 MV	219
ba486a2a JL	220	if (ssp->devid == IMX23_SSP) {
ba486a2a JL	221	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818	222	ctrl0 \|= min;
ba486a2a	223	}
010b4818 MV	224
	225	dma_xfer[sg_count].pio[0] = ctrl0;
	226	dma_xfer[sg_count].pio[3] = min;
	227
	228	if (vmalloced_buf) {
	229	vm_page = vmalloc_to_page(buf);
	230	if (!vm_page) {
	231	ret = -ENOMEM;
	232	goto err_vmalloc;
	233	}
9e8987ac CK	234
	235	sg_init_table(&dma_xfer[sg_count].sg, 1);
	236	sg_set_page(&dma_xfer[sg_count].sg, vm_page,
	237	min, offset_in_page(buf));
010b4818	238	} else {
9e8987ac	239	sg_init_one(&dma_xfer[sg_count].sg, buf, min);
010b4818 MV	240	}
010b4818 MV	241
010b4818	242	ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	243	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
010b4818 MV	244
	245	len -= min;
	246	buf += min;
	247
	248	/* Queue the PIO register write transfer. */
	249	desc = dmaengine_prep_slave_sg(ssp->dmach,
	250	(struct scatterlist *)dma_xfer[sg_count].pio,
	251	(ssp->devid == IMX23_SSP) ? 1 : 4,
	252	DMA_TRANS_NONE,
	253	sg_count ? DMA_PREP_INTERRUPT : 0);
	254	if (!desc) {
	255	dev_err(ssp->dev,
	256	"Failed to get PIO reg. write descriptor.\n");
	257	ret = -EINVAL;
	258	goto err_mapped;
	259	}
	260
	261	desc = dmaengine_prep_slave_sg(ssp->dmach,
	262	&dma_xfer[sg_count].sg, 1,
28cad125	263	(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
010b4818 MV	264	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	265
	266	if (!desc) {
	267	dev_err(ssp->dev,
	268	"Failed to get DMA data write descriptor.\n");
	269	ret = -EINVAL;
	270	goto err_mapped;
	271	}
474afc04 MV	272	}
	273
	274	/*
	275	* The last descriptor must have this callback,
	276	* to finish the DMA transaction.
	277	*/
	278	desc->callback = mxs_ssp_dma_irq_callback;
	279	desc->callback_param = spi;
	280
	281	/* Start the transfer. */
	282	dmaengine_submit(desc);
	283	dma_async_issue_pending(ssp->dmach);
	284
f2234691 NMG	285	if (!wait_for_completion_timeout(&spi->c,
f2234691 NMG	286	msecs_to_jiffies(SSP_TIMEOUT))) {
474afc04 MV	287	dev_err(ssp->dev, "DMA transfer timeout\n");
474afc04 MV	288	ret = -ETIMEDOUT;
44968466	289	dmaengine_terminate_all(ssp->dmach);
010b4818	290	goto err_vmalloc;
474afc04 MV	291	}
	292
	293	ret = 0;
	294
010b4818 MV	295	err_vmalloc:
	296	while (--sg_count >= 0) {
	297	err_mapped:
	298	dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	299	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
474afc04 MV	300	}
474afc04 MV	301
010b4818 MV	302	kfree(dma_xfer);
010b4818 MV	303
474afc04 MV	304	return ret;
	305	}
	306
0b782f70	307	static int mxs_spi_txrx_pio(struct mxs_spi *spi,
646781d3	308	unsigned char *buf, int len,
28cad125	309	unsigned int flags)
646781d3 MV	310	{
	311	struct mxs_ssp *ssp = &spi->ssp;
	312
75e73fa2 TP	313	writel(BM_SSP_CTRL0_IGNORE_CRC,
75e73fa2 TP	314	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
646781d3 MV	315
646781d3 MV	316	while (len--) {
28cad125	317	if (len == 0 && (flags & TXRX_DEASSERT_CS))
f5bc7384 TP	318	writel(BM_SSP_CTRL0_IGNORE_CRC,
f5bc7384 TP	319	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	320
	321	if (ssp->devid == IMX23_SSP) {
	322	writel(BM_SSP_CTRL0_XFER_COUNT,
	323	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	324	writel(1,
	325	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	326	} else {
	327	writel(1, ssp->base + HW_SSP_XFER_SIZE);
	328	}
	329
28cad125	330	if (flags & TXRX_WRITE)
646781d3 MV	331	writel(BM_SSP_CTRL0_READ,
	332	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	333	else
	334	writel(BM_SSP_CTRL0_READ,
	335	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	336
	337	writel(BM_SSP_CTRL0_RUN,
	338	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	339
	340	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
	341	return -ETIMEDOUT;
	342
28cad125	343	if (flags & TXRX_WRITE)
646781d3 MV	344	writel(*buf, ssp->base + HW_SSP_DATA(ssp));
	345
	346	writel(BM_SSP_CTRL0_DATA_XFER,
	347	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	348
28cad125	349	if (!(flags & TXRX_WRITE)) {
646781d3 MV	350	if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
	351	BM_SSP_STATUS_FIFO_EMPTY, 0))
	352	return -ETIMEDOUT;
	353
	354	*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
	355	}
	356
	357	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
	358	return -ETIMEDOUT;
	359
	360	buf++;
	361	}
	362
	363	if (len <= 0)
	364	return 0;
	365
	366	return -ETIMEDOUT;
	367	}
	368
	369	static int mxs_spi_transfer_one(struct spi_master *master,
	370	struct spi_message *m)
	371	{
	372	struct mxs_spi *spi = spi_master_get_devdata(master);
	373	struct mxs_ssp *ssp = &spi->ssp;
9a7da6cc	374	struct spi_transfer *t;
28cad125	375	unsigned int flag;
646781d3	376	int status = 0;
646781d3	377
0b782f70 TP	378	/* Program CS register bits here, it will be used for all transfers. */
	379	writel(BM_SSP_CTRL0_WAIT_FOR_CMD \| BM_SSP_CTRL0_WAIT_FOR_IRQ,
	380	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	381	writel(mxs_spi_cs_to_reg(m->spi->chip_select),
	382	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3	383
9a7da6cc	384	list_for_each_entry(t, &m->transfers, transfer_list) {
646781d3 MV	385
	386	status = mxs_spi_setup_transfer(m->spi, t);
	387	if (status)
	388	break;
	389
28cad125 TP	390	/* De-assert on last transfer, inverted by cs_change flag */
	391	flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
	392	TXRX_DEASSERT_CS : 0;
646781d3	393
474afc04 MV	394	/*
	395	* Small blocks can be transfered via PIO.
	396	* Measured by empiric means:
	397	*
	398	* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
	399	*
	400	* DMA only: 2.164808 seconds, 473.0KB/s
	401	* Combined: 1.676276 seconds, 610.9KB/s
	402	*/
727c10e3	403	if (t->len < 32) {
474afc04 MV	404	writel(BM_SSP_CTRL1_DMA_ENABLE,
	405	ssp->base + HW_SSP_CTRL1(ssp) +
	406	STMP_OFFSET_REG_CLR);
	407
	408	if (t->tx_buf)
0b782f70	409	status = mxs_spi_txrx_pio(spi,
474afc04	410	(void *)t->tx_buf,
28cad125	411	t->len, flag \| TXRX_WRITE);
474afc04	412	if (t->rx_buf)
0b782f70	413	status = mxs_spi_txrx_pio(spi,
474afc04	414	t->rx_buf, t->len,
28cad125	415	flag);
474afc04 MV	416	} else {
	417	writel(BM_SSP_CTRL1_DMA_ENABLE,
	418	ssp->base + HW_SSP_CTRL1(ssp) +
	419	STMP_OFFSET_REG_SET);
	420
	421	if (t->tx_buf)
0b782f70	422	status = mxs_spi_txrx_dma(spi,
474afc04	423	(void *)t->tx_buf, t->len,
28cad125	424	flag \| TXRX_WRITE);
474afc04	425	if (t->rx_buf)
0b782f70	426	status = mxs_spi_txrx_dma(spi,
474afc04	427	t->rx_buf, t->len,
28cad125	428	flag);
474afc04	429	}
646781d3	430
c895db0f MV	431	if (status) {
c895db0f MV	432	stmp_reset_block(ssp->base);
646781d3	433	break;
c895db0f	434	}
646781d3	435
204e706f	436	m->actual_length += t->len;
646781d3 MV	437	}
646781d3 MV	438
d856f1eb	439	m->status = status;
646781d3 MV	440	spi_finalize_current_message(master);
	441
	442	return status;
	443	}
	444
	445	static const struct of_device_id mxs_spi_dt_ids[] = {
	446	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	447	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	448	{ /* sentinel */ }
	449	};
	450	MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
	451
fd4a319b	452	static int mxs_spi_probe(struct platform_device *pdev)
646781d3 MV	453	{
	454	const struct of_device_id *of_id =
	455	of_match_device(mxs_spi_dt_ids, &pdev->dev);
	456	struct device_node *np = pdev->dev.of_node;
	457	struct spi_master *master;
	458	struct mxs_spi *spi;
	459	struct mxs_ssp *ssp;
26aafa77	460	struct resource *iores;
646781d3 MV	461	struct clk *clk;
646781d3 MV	462	void __iomem *base;
26aafa77 SG	463	int devid, clk_freq;
26aafa77 SG	464	int ret = 0, irq_err;
646781d3	465
e64d07a2 MV	466	/*
	467	* Default clock speed for the SPI core. 160MHz seems to
	468	* work reasonably well with most SPI flashes, so use this
	469	* as a default. Override with "clock-frequency" DT prop.
	470	*/
	471	const int clk_freq_default = 160000000;
	472
646781d3	473	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474afc04	474	irq_err = platform_get_irq(pdev, 0);
796305a2	475	if (irq_err < 0)
cdd1945b	476	return irq_err;
646781d3	477
b0ee5605 TR	478	base = devm_ioremap_resource(&pdev->dev, iores);
	479	if (IS_ERR(base))
	480	return PTR_ERR(base);
646781d3	481
646781d3 MV	482	clk = devm_clk_get(&pdev->dev, NULL);
	483	if (IS_ERR(clk))
	484	return PTR_ERR(clk);
	485
26aafa77 SG	486	devid = (enum mxs_ssp_id) of_id->data;
	487	ret = of_property_read_u32(np, "clock-frequency",
	488	&clk_freq);
	489	if (ret)
e64d07a2	490	clk_freq = clk_freq_default;
646781d3 MV	491
	492	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	493	if (!master)
	494	return -ENOMEM;
	495
	496	master->transfer_one_message = mxs_spi_transfer_one;
24778be2	497	master->bits_per_word_mask = SPI_BPW_MASK(8);
646781d3 MV	498	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	499	master->num_chipselect = 3;
	500	master->dev.of_node = np;
	501	master->flags = SPI_MASTER_HALF_DUPLEX;
	502
	503	spi = spi_master_get_devdata(master);
	504	ssp = &spi->ssp;
	505	ssp->dev = &pdev->dev;
	506	ssp->clk = clk;
	507	ssp->base = base;
	508	ssp->devid = devid;
474afc04	509
41682e03 MV	510	init_completion(&spi->c);
41682e03 MV	511
474afc04	512	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
617100c2	513	dev_name(&pdev->dev), ssp);
474afc04 MV	514	if (ret)
	515	goto out_master_free;
	516
26aafa77	517	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
474afc04 MV	518	if (!ssp->dmach) {
474afc04 MV	519	dev_err(ssp->dev, "Failed to request DMA\n");
58ad60bb	520	ret = -ENODEV;
474afc04 MV	521	goto out_master_free;
474afc04 MV	522	}
646781d3	523
9c4a39af FE	524	ret = clk_prepare_enable(ssp->clk);
	525	if (ret)
	526	goto out_dma_release;
	527
e64d07a2	528	clk_set_rate(ssp->clk, clk_freq);
646781d3	529
8498bce9 FE	530	ret = stmp_reset_block(ssp->base);
	531	if (ret)
	532	goto out_disable_clk;
646781d3 MV	533
	534	platform_set_drvdata(pdev, master);
	535
33e195ac	536	ret = devm_spi_register_master(&pdev->dev, master);
646781d3 MV	537	if (ret) {
646781d3 MV	538	dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
9c4a39af	539	goto out_disable_clk;
646781d3 MV	540	}
	541
	542	return 0;
	543
9c4a39af	544	out_disable_clk:
646781d3	545	clk_disable_unprepare(ssp->clk);
9c4a39af	546	out_dma_release:
e11933f6	547	dma_release_channel(ssp->dmach);
474afc04	548	out_master_free:
646781d3 MV	549	spi_master_put(master);
	550	return ret;
	551	}
	552
fd4a319b	553	static int mxs_spi_remove(struct platform_device *pdev)
646781d3 MV	554	{
	555	struct spi_master *master;
	556	struct mxs_spi *spi;
	557	struct mxs_ssp *ssp;
	558
e322ce93	559	master = platform_get_drvdata(pdev);
646781d3 MV	560	spi = spi_master_get_devdata(master);
	561	ssp = &spi->ssp;
	562
646781d3	563	clk_disable_unprepare(ssp->clk);
e11933f6	564	dma_release_channel(ssp->dmach);
646781d3 MV	565
	566	return 0;
	567	}
	568
	569	static struct platform_driver mxs_spi_driver = {
	570	.probe = mxs_spi_probe,
fd4a319b	571	.remove = mxs_spi_remove,
646781d3 MV	572	.driver = {
646781d3 MV	573	.name = DRIVER_NAME,
646781d3 MV	574	.of_match_table = mxs_spi_dt_ids,
	575	},
	576	};
	577
	578	module_platform_driver(mxs_spi_driver);
	579
	580	MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
	581	MODULE_DESCRIPTION("MXS SPI master driver");
	582	MODULE_LICENSE("GPL");
	583	MODULE_ALIAS("platform:mxs-spi");