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646781d3 MV |
1 | /* |
2 | * Freescale MXS SPI master driver | |
3 | * | |
4 | * Copyright 2012 DENX Software Engineering, GmbH. | |
5 | * Copyright 2012 Freescale Semiconductor, Inc. | |
6 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | |
7 | * | |
8 | * Rework and transition to new API by: | |
9 | * Marek Vasut <marex@denx.de> | |
10 | * | |
11 | * Based on previous attempt by: | |
12 | * Fabio Estevam <fabio.estevam@freescale.com> | |
13 | * | |
14 | * Based on code from U-Boot bootloader by: | |
15 | * Marek Vasut <marex@denx.de> | |
16 | * | |
17 | * Based on spi-stmp.c, which is: | |
18 | * Author: Dmitry Pervushin <dimka@embeddedalley.com> | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/of.h> | |
35 | #include <linux/of_device.h> | |
36 | #include <linux/of_gpio.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/dmaengine.h> | |
42 | #include <linux/highmem.h> | |
43 | #include <linux/clk.h> | |
44 | #include <linux/err.h> | |
45 | #include <linux/completion.h> | |
46 | #include <linux/gpio.h> | |
47 | #include <linux/regulator/consumer.h> | |
48 | #include <linux/module.h> | |
646781d3 MV |
49 | #include <linux/pinctrl/consumer.h> |
50 | #include <linux/stmp_device.h> | |
51 | #include <linux/spi/spi.h> | |
52 | #include <linux/spi/mxs-spi.h> | |
53 | ||
54 | #define DRIVER_NAME "mxs-spi" | |
55 | ||
010b4818 MV |
56 | /* Use 10S timeout for very long transfers, it should suffice. */ |
57 | #define SSP_TIMEOUT 10000 | |
646781d3 | 58 | |
474afc04 MV |
59 | #define SG_MAXLEN 0xff00 |
60 | ||
646781d3 MV |
61 | struct mxs_spi { |
62 | struct mxs_ssp ssp; | |
474afc04 | 63 | struct completion c; |
646781d3 MV |
64 | }; |
65 | ||
66 | static int mxs_spi_setup_transfer(struct spi_device *dev, | |
67 | struct spi_transfer *t) | |
68 | { | |
69 | struct mxs_spi *spi = spi_master_get_devdata(dev->master); | |
70 | struct mxs_ssp *ssp = &spi->ssp; | |
71 | uint8_t bits_per_word; | |
72 | uint32_t hz = 0; | |
73 | ||
74 | bits_per_word = dev->bits_per_word; | |
75 | if (t && t->bits_per_word) | |
76 | bits_per_word = t->bits_per_word; | |
77 | ||
78 | if (bits_per_word != 8) { | |
79 | dev_err(&dev->dev, "%s, unsupported bits_per_word=%d\n", | |
80 | __func__, bits_per_word); | |
81 | return -EINVAL; | |
82 | } | |
83 | ||
84 | hz = dev->max_speed_hz; | |
85 | if (t && t->speed_hz) | |
86 | hz = min(hz, t->speed_hz); | |
87 | if (hz == 0) { | |
88 | dev_err(&dev->dev, "Cannot continue with zero clock\n"); | |
89 | return -EINVAL; | |
90 | } | |
91 | ||
92 | mxs_ssp_set_clk_rate(ssp, hz); | |
93 | ||
94 | writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | | |
95 | BF_SSP_CTRL1_WORD_LENGTH | |
96 | (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) | | |
97 | ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) | | |
98 | ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0), | |
99 | ssp->base + HW_SSP_CTRL1(ssp)); | |
100 | ||
101 | writel(0x0, ssp->base + HW_SSP_CMD0); | |
102 | writel(0x0, ssp->base + HW_SSP_CMD1); | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
107 | static int mxs_spi_setup(struct spi_device *dev) | |
108 | { | |
109 | int err = 0; | |
110 | ||
111 | if (!dev->bits_per_word) | |
112 | dev->bits_per_word = 8; | |
113 | ||
114 | if (dev->mode & ~(SPI_CPOL | SPI_CPHA)) | |
115 | return -EINVAL; | |
116 | ||
117 | err = mxs_spi_setup_transfer(dev, NULL); | |
118 | if (err) { | |
119 | dev_err(&dev->dev, | |
120 | "Failed to setup transfer, error = %d\n", err); | |
121 | } | |
122 | ||
123 | return err; | |
124 | } | |
125 | ||
126 | static uint32_t mxs_spi_cs_to_reg(unsigned cs) | |
127 | { | |
128 | uint32_t select = 0; | |
129 | ||
130 | /* | |
131 | * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0 | |
132 | * | |
133 | * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ | |
134 | * in HW_SSP_CTRL0 register do have multiple usage, please refer to | |
135 | * the datasheet for further details. In SPI mode, they are used to | |
136 | * toggle the chip-select lines (nCS pins). | |
137 | */ | |
138 | if (cs & 1) | |
139 | select |= BM_SSP_CTRL0_WAIT_FOR_CMD; | |
140 | if (cs & 2) | |
141 | select |= BM_SSP_CTRL0_WAIT_FOR_IRQ; | |
142 | ||
143 | return select; | |
144 | } | |
145 | ||
146 | static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs) | |
147 | { | |
148 | const uint32_t mask = | |
149 | BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ; | |
150 | uint32_t select; | |
151 | struct mxs_ssp *ssp = &spi->ssp; | |
152 | ||
153 | writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
154 | select = mxs_spi_cs_to_reg(cs); | |
155 | writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
156 | } | |
157 | ||
158 | static inline void mxs_spi_enable(struct mxs_spi *spi) | |
159 | { | |
160 | struct mxs_ssp *ssp = &spi->ssp; | |
161 | ||
162 | writel(BM_SSP_CTRL0_LOCK_CS, | |
163 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
164 | writel(BM_SSP_CTRL0_IGNORE_CRC, | |
165 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
166 | } | |
167 | ||
168 | static inline void mxs_spi_disable(struct mxs_spi *spi) | |
169 | { | |
170 | struct mxs_ssp *ssp = &spi->ssp; | |
171 | ||
172 | writel(BM_SSP_CTRL0_LOCK_CS, | |
173 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
174 | writel(BM_SSP_CTRL0_IGNORE_CRC, | |
175 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
176 | } | |
177 | ||
178 | static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set) | |
179 | { | |
180 | unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT); | |
181 | struct mxs_ssp *ssp = &spi->ssp; | |
182 | uint32_t reg; | |
183 | ||
184 | while (1) { | |
185 | reg = readl_relaxed(ssp->base + offset); | |
186 | ||
187 | if (set && ((reg & mask) == mask)) | |
188 | break; | |
189 | ||
190 | if (!set && ((~reg & mask) == mask)) | |
191 | break; | |
192 | ||
193 | udelay(1); | |
194 | ||
195 | if (time_after(jiffies, timeout)) | |
196 | return -ETIMEDOUT; | |
197 | } | |
198 | return 0; | |
199 | } | |
200 | ||
474afc04 MV |
201 | static void mxs_ssp_dma_irq_callback(void *param) |
202 | { | |
203 | struct mxs_spi *spi = param; | |
204 | complete(&spi->c); | |
205 | } | |
206 | ||
207 | static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id) | |
208 | { | |
209 | struct mxs_ssp *ssp = dev_id; | |
210 | dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n", | |
211 | __func__, __LINE__, | |
212 | readl(ssp->base + HW_SSP_CTRL1(ssp)), | |
213 | readl(ssp->base + HW_SSP_STATUS(ssp))); | |
214 | return IRQ_HANDLED; | |
215 | } | |
216 | ||
217 | static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs, | |
218 | unsigned char *buf, int len, | |
219 | int *first, int *last, int write) | |
220 | { | |
221 | struct mxs_ssp *ssp = &spi->ssp; | |
010b4818 MV |
222 | struct dma_async_tx_descriptor *desc = NULL; |
223 | const bool vmalloced_buf = is_vmalloc_addr(buf); | |
224 | const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN; | |
225 | const int sgs = DIV_ROUND_UP(len, desc_len); | |
474afc04 | 226 | int sg_count; |
010b4818 MV |
227 | int min, ret; |
228 | uint32_t ctrl0; | |
229 | struct page *vm_page; | |
230 | void *sg_buf; | |
231 | struct { | |
232 | uint32_t pio[4]; | |
233 | struct scatterlist sg; | |
234 | } *dma_xfer; | |
235 | ||
236 | if (!len) | |
474afc04 | 237 | return -EINVAL; |
010b4818 MV |
238 | |
239 | dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL); | |
240 | if (!dma_xfer) | |
241 | return -ENOMEM; | |
474afc04 | 242 | |
41682e03 | 243 | INIT_COMPLETION(spi->c); |
474afc04 | 244 | |
010b4818 MV |
245 | ctrl0 = readl(ssp->base + HW_SSP_CTRL0); |
246 | ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs); | |
247 | ||
474afc04 | 248 | if (*first) |
010b4818 | 249 | ctrl0 |= BM_SSP_CTRL0_LOCK_CS; |
474afc04 | 250 | if (!write) |
010b4818 | 251 | ctrl0 |= BM_SSP_CTRL0_READ; |
474afc04 MV |
252 | |
253 | /* Queue the DMA data transfer. */ | |
010b4818 MV |
254 | for (sg_count = 0; sg_count < sgs; sg_count++) { |
255 | min = min(len, desc_len); | |
256 | ||
257 | /* Prepare the transfer descriptor. */ | |
258 | if ((sg_count + 1 == sgs) && *last) | |
259 | ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC; | |
260 | ||
261 | if (ssp->devid == IMX23_SSP) | |
262 | ctrl0 |= min; | |
263 | ||
264 | dma_xfer[sg_count].pio[0] = ctrl0; | |
265 | dma_xfer[sg_count].pio[3] = min; | |
266 | ||
267 | if (vmalloced_buf) { | |
268 | vm_page = vmalloc_to_page(buf); | |
269 | if (!vm_page) { | |
270 | ret = -ENOMEM; | |
271 | goto err_vmalloc; | |
272 | } | |
273 | sg_buf = page_address(vm_page) + | |
274 | ((size_t)buf & ~PAGE_MASK); | |
275 | } else { | |
276 | sg_buf = buf; | |
277 | } | |
278 | ||
279 | sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min); | |
280 | ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, | |
281 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
282 | ||
283 | len -= min; | |
284 | buf += min; | |
285 | ||
286 | /* Queue the PIO register write transfer. */ | |
287 | desc = dmaengine_prep_slave_sg(ssp->dmach, | |
288 | (struct scatterlist *)dma_xfer[sg_count].pio, | |
289 | (ssp->devid == IMX23_SSP) ? 1 : 4, | |
290 | DMA_TRANS_NONE, | |
291 | sg_count ? DMA_PREP_INTERRUPT : 0); | |
292 | if (!desc) { | |
293 | dev_err(ssp->dev, | |
294 | "Failed to get PIO reg. write descriptor.\n"); | |
295 | ret = -EINVAL; | |
296 | goto err_mapped; | |
297 | } | |
298 | ||
299 | desc = dmaengine_prep_slave_sg(ssp->dmach, | |
300 | &dma_xfer[sg_count].sg, 1, | |
301 | write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
302 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
303 | ||
304 | if (!desc) { | |
305 | dev_err(ssp->dev, | |
306 | "Failed to get DMA data write descriptor.\n"); | |
307 | ret = -EINVAL; | |
308 | goto err_mapped; | |
309 | } | |
474afc04 MV |
310 | } |
311 | ||
312 | /* | |
313 | * The last descriptor must have this callback, | |
314 | * to finish the DMA transaction. | |
315 | */ | |
316 | desc->callback = mxs_ssp_dma_irq_callback; | |
317 | desc->callback_param = spi; | |
318 | ||
319 | /* Start the transfer. */ | |
320 | dmaengine_submit(desc); | |
321 | dma_async_issue_pending(ssp->dmach); | |
322 | ||
323 | ret = wait_for_completion_timeout(&spi->c, | |
324 | msecs_to_jiffies(SSP_TIMEOUT)); | |
474afc04 MV |
325 | if (!ret) { |
326 | dev_err(ssp->dev, "DMA transfer timeout\n"); | |
327 | ret = -ETIMEDOUT; | |
010b4818 | 328 | goto err_vmalloc; |
474afc04 MV |
329 | } |
330 | ||
331 | ret = 0; | |
332 | ||
010b4818 MV |
333 | err_vmalloc: |
334 | while (--sg_count >= 0) { | |
335 | err_mapped: | |
336 | dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, | |
474afc04 MV |
337 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
338 | } | |
339 | ||
010b4818 MV |
340 | kfree(dma_xfer); |
341 | ||
474afc04 MV |
342 | return ret; |
343 | } | |
344 | ||
646781d3 MV |
345 | static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs, |
346 | unsigned char *buf, int len, | |
347 | int *first, int *last, int write) | |
348 | { | |
349 | struct mxs_ssp *ssp = &spi->ssp; | |
350 | ||
351 | if (*first) | |
352 | mxs_spi_enable(spi); | |
353 | ||
354 | mxs_spi_set_cs(spi, cs); | |
355 | ||
356 | while (len--) { | |
357 | if (*last && len == 0) | |
358 | mxs_spi_disable(spi); | |
359 | ||
360 | if (ssp->devid == IMX23_SSP) { | |
361 | writel(BM_SSP_CTRL0_XFER_COUNT, | |
362 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
363 | writel(1, | |
364 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
365 | } else { | |
366 | writel(1, ssp->base + HW_SSP_XFER_SIZE); | |
367 | } | |
368 | ||
369 | if (write) | |
370 | writel(BM_SSP_CTRL0_READ, | |
371 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
372 | else | |
373 | writel(BM_SSP_CTRL0_READ, | |
374 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
375 | ||
376 | writel(BM_SSP_CTRL0_RUN, | |
377 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
378 | ||
379 | if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1)) | |
380 | return -ETIMEDOUT; | |
381 | ||
382 | if (write) | |
383 | writel(*buf, ssp->base + HW_SSP_DATA(ssp)); | |
384 | ||
385 | writel(BM_SSP_CTRL0_DATA_XFER, | |
386 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
387 | ||
388 | if (!write) { | |
389 | if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp), | |
390 | BM_SSP_STATUS_FIFO_EMPTY, 0)) | |
391 | return -ETIMEDOUT; | |
392 | ||
393 | *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff); | |
394 | } | |
395 | ||
396 | if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0)) | |
397 | return -ETIMEDOUT; | |
398 | ||
399 | buf++; | |
400 | } | |
401 | ||
402 | if (len <= 0) | |
403 | return 0; | |
404 | ||
405 | return -ETIMEDOUT; | |
406 | } | |
407 | ||
408 | static int mxs_spi_transfer_one(struct spi_master *master, | |
409 | struct spi_message *m) | |
410 | { | |
411 | struct mxs_spi *spi = spi_master_get_devdata(master); | |
412 | struct mxs_ssp *ssp = &spi->ssp; | |
413 | int first, last; | |
414 | struct spi_transfer *t, *tmp_t; | |
415 | int status = 0; | |
416 | int cs; | |
417 | ||
418 | first = last = 0; | |
419 | ||
420 | cs = m->spi->chip_select; | |
421 | ||
422 | list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) { | |
423 | ||
424 | status = mxs_spi_setup_transfer(m->spi, t); | |
425 | if (status) | |
426 | break; | |
427 | ||
428 | if (&t->transfer_list == m->transfers.next) | |
429 | first = 1; | |
430 | if (&t->transfer_list == m->transfers.prev) | |
431 | last = 1; | |
474afc04 | 432 | if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) { |
646781d3 MV |
433 | dev_err(ssp->dev, |
434 | "Cannot send and receive simultaneously\n"); | |
435 | status = -EINVAL; | |
436 | break; | |
437 | } | |
438 | ||
474afc04 MV |
439 | /* |
440 | * Small blocks can be transfered via PIO. | |
441 | * Measured by empiric means: | |
442 | * | |
443 | * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1 | |
444 | * | |
445 | * DMA only: 2.164808 seconds, 473.0KB/s | |
446 | * Combined: 1.676276 seconds, 610.9KB/s | |
447 | */ | |
448 | if (t->len <= 256) { | |
449 | writel(BM_SSP_CTRL1_DMA_ENABLE, | |
450 | ssp->base + HW_SSP_CTRL1(ssp) + | |
451 | STMP_OFFSET_REG_CLR); | |
452 | ||
453 | if (t->tx_buf) | |
454 | status = mxs_spi_txrx_pio(spi, cs, | |
455 | (void *)t->tx_buf, | |
456 | t->len, &first, &last, 1); | |
457 | if (t->rx_buf) | |
458 | status = mxs_spi_txrx_pio(spi, cs, | |
459 | t->rx_buf, t->len, | |
460 | &first, &last, 0); | |
461 | } else { | |
462 | writel(BM_SSP_CTRL1_DMA_ENABLE, | |
463 | ssp->base + HW_SSP_CTRL1(ssp) + | |
464 | STMP_OFFSET_REG_SET); | |
465 | ||
466 | if (t->tx_buf) | |
467 | status = mxs_spi_txrx_dma(spi, cs, | |
468 | (void *)t->tx_buf, t->len, | |
469 | &first, &last, 1); | |
470 | if (t->rx_buf) | |
471 | status = mxs_spi_txrx_dma(spi, cs, | |
472 | t->rx_buf, t->len, | |
473 | &first, &last, 0); | |
474 | } | |
646781d3 | 475 | |
c895db0f MV |
476 | if (status) { |
477 | stmp_reset_block(ssp->base); | |
646781d3 | 478 | break; |
c895db0f | 479 | } |
646781d3 | 480 | |
204e706f | 481 | m->actual_length += t->len; |
646781d3 MV |
482 | first = last = 0; |
483 | } | |
484 | ||
485 | m->status = 0; | |
486 | spi_finalize_current_message(master); | |
487 | ||
488 | return status; | |
489 | } | |
490 | ||
474afc04 MV |
491 | static bool mxs_ssp_dma_filter(struct dma_chan *chan, void *param) |
492 | { | |
493 | struct mxs_ssp *ssp = param; | |
494 | ||
495 | if (!mxs_dma_is_apbh(chan)) | |
496 | return false; | |
497 | ||
498 | if (chan->chan_id != ssp->dma_channel) | |
499 | return false; | |
500 | ||
501 | chan->private = &ssp->dma_data; | |
502 | ||
503 | return true; | |
504 | } | |
505 | ||
646781d3 MV |
506 | static const struct of_device_id mxs_spi_dt_ids[] = { |
507 | { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, }, | |
508 | { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, }, | |
509 | { /* sentinel */ } | |
510 | }; | |
511 | MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids); | |
512 | ||
513 | static int __devinit mxs_spi_probe(struct platform_device *pdev) | |
514 | { | |
515 | const struct of_device_id *of_id = | |
516 | of_match_device(mxs_spi_dt_ids, &pdev->dev); | |
517 | struct device_node *np = pdev->dev.of_node; | |
518 | struct spi_master *master; | |
519 | struct mxs_spi *spi; | |
520 | struct mxs_ssp *ssp; | |
474afc04 | 521 | struct resource *iores, *dmares; |
646781d3 MV |
522 | struct pinctrl *pinctrl; |
523 | struct clk *clk; | |
524 | void __iomem *base; | |
474afc04 MV |
525 | int devid, dma_channel; |
526 | int ret = 0, irq_err, irq_dma; | |
527 | dma_cap_mask_t mask; | |
646781d3 MV |
528 | |
529 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
474afc04 MV |
530 | irq_err = platform_get_irq(pdev, 0); |
531 | irq_dma = platform_get_irq(pdev, 1); | |
532 | if (!iores || irq_err < 0 || irq_dma < 0) | |
646781d3 MV |
533 | return -EINVAL; |
534 | ||
535 | base = devm_request_and_ioremap(&pdev->dev, iores); | |
536 | if (!base) | |
537 | return -EADDRNOTAVAIL; | |
538 | ||
539 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | |
540 | if (IS_ERR(pinctrl)) | |
541 | return PTR_ERR(pinctrl); | |
542 | ||
543 | clk = devm_clk_get(&pdev->dev, NULL); | |
544 | if (IS_ERR(clk)) | |
545 | return PTR_ERR(clk); | |
546 | ||
474afc04 | 547 | if (np) { |
646781d3 | 548 | devid = (enum mxs_ssp_id) of_id->data; |
474afc04 MV |
549 | /* |
550 | * TODO: This is a temporary solution and should be changed | |
551 | * to use generic DMA binding later when the helpers get in. | |
552 | */ | |
553 | ret = of_property_read_u32(np, "fsl,ssp-dma-channel", | |
554 | &dma_channel); | |
555 | if (ret) { | |
556 | dev_err(&pdev->dev, | |
557 | "Failed to get DMA channel\n"); | |
558 | return -EINVAL; | |
559 | } | |
560 | } else { | |
561 | dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
562 | if (!dmares) | |
563 | return -EINVAL; | |
646781d3 | 564 | devid = pdev->id_entry->driver_data; |
474afc04 MV |
565 | dma_channel = dmares->start; |
566 | } | |
646781d3 MV |
567 | |
568 | master = spi_alloc_master(&pdev->dev, sizeof(*spi)); | |
569 | if (!master) | |
570 | return -ENOMEM; | |
571 | ||
572 | master->transfer_one_message = mxs_spi_transfer_one; | |
573 | master->setup = mxs_spi_setup; | |
574 | master->mode_bits = SPI_CPOL | SPI_CPHA; | |
575 | master->num_chipselect = 3; | |
576 | master->dev.of_node = np; | |
577 | master->flags = SPI_MASTER_HALF_DUPLEX; | |
578 | ||
579 | spi = spi_master_get_devdata(master); | |
580 | ssp = &spi->ssp; | |
581 | ssp->dev = &pdev->dev; | |
582 | ssp->clk = clk; | |
583 | ssp->base = base; | |
584 | ssp->devid = devid; | |
474afc04 MV |
585 | ssp->dma_channel = dma_channel; |
586 | ||
41682e03 MV |
587 | init_completion(&spi->c); |
588 | ||
474afc04 MV |
589 | ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0, |
590 | DRIVER_NAME, ssp); | |
591 | if (ret) | |
592 | goto out_master_free; | |
593 | ||
594 | dma_cap_zero(mask); | |
595 | dma_cap_set(DMA_SLAVE, mask); | |
596 | ssp->dma_data.chan_irq = irq_dma; | |
597 | ssp->dmach = dma_request_channel(mask, mxs_ssp_dma_filter, ssp); | |
598 | if (!ssp->dmach) { | |
599 | dev_err(ssp->dev, "Failed to request DMA\n"); | |
600 | goto out_master_free; | |
601 | } | |
646781d3 | 602 | |
474afc04 MV |
603 | /* |
604 | * Crank up the clock to 120MHz, this will be further divided onto a | |
605 | * proper speed. | |
606 | */ | |
646781d3 | 607 | clk_prepare_enable(ssp->clk); |
474afc04 | 608 | clk_set_rate(ssp->clk, 120 * 1000 * 1000); |
646781d3 MV |
609 | ssp->clk_rate = clk_get_rate(ssp->clk) / 1000; |
610 | ||
611 | stmp_reset_block(ssp->base); | |
612 | ||
613 | platform_set_drvdata(pdev, master); | |
614 | ||
615 | ret = spi_register_master(master); | |
616 | if (ret) { | |
617 | dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret); | |
474afc04 | 618 | goto out_free_dma; |
646781d3 MV |
619 | } |
620 | ||
621 | return 0; | |
622 | ||
474afc04 | 623 | out_free_dma: |
474afc04 | 624 | dma_release_channel(ssp->dmach); |
646781d3 | 625 | clk_disable_unprepare(ssp->clk); |
474afc04 | 626 | out_master_free: |
646781d3 MV |
627 | spi_master_put(master); |
628 | return ret; | |
629 | } | |
630 | ||
631 | static int __devexit mxs_spi_remove(struct platform_device *pdev) | |
632 | { | |
633 | struct spi_master *master; | |
634 | struct mxs_spi *spi; | |
635 | struct mxs_ssp *ssp; | |
636 | ||
7d520d28 | 637 | master = spi_master_get(platform_get_drvdata(pdev)); |
646781d3 MV |
638 | spi = spi_master_get_devdata(master); |
639 | ssp = &spi->ssp; | |
640 | ||
641 | spi_unregister_master(master); | |
642 | ||
474afc04 MV |
643 | dma_release_channel(ssp->dmach); |
644 | ||
646781d3 MV |
645 | clk_disable_unprepare(ssp->clk); |
646 | ||
647 | spi_master_put(master); | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
652 | static struct platform_driver mxs_spi_driver = { | |
653 | .probe = mxs_spi_probe, | |
654 | .remove = __devexit_p(mxs_spi_remove), | |
655 | .driver = { | |
656 | .name = DRIVER_NAME, | |
657 | .owner = THIS_MODULE, | |
658 | .of_match_table = mxs_spi_dt_ids, | |
659 | }, | |
660 | }; | |
661 | ||
662 | module_platform_driver(mxs_spi_driver); | |
663 | ||
664 | MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); | |
665 | MODULE_DESCRIPTION("MXS SPI master driver"); | |
666 | MODULE_LICENSE("GPL"); | |
667 | MODULE_ALIAS("platform:mxs-spi"); |