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646781d3 MV |
1 | /* |
2 | * Freescale MXS SPI master driver | |
3 | * | |
4 | * Copyright 2012 DENX Software Engineering, GmbH. | |
5 | * Copyright 2012 Freescale Semiconductor, Inc. | |
6 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | |
7 | * | |
8 | * Rework and transition to new API by: | |
9 | * Marek Vasut <marex@denx.de> | |
10 | * | |
11 | * Based on previous attempt by: | |
12 | * Fabio Estevam <fabio.estevam@freescale.com> | |
13 | * | |
14 | * Based on code from U-Boot bootloader by: | |
15 | * Marek Vasut <marex@denx.de> | |
16 | * | |
17 | * Based on spi-stmp.c, which is: | |
18 | * Author: Dmitry Pervushin <dimka@embeddedalley.com> | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/of.h> | |
35 | #include <linux/of_device.h> | |
36 | #include <linux/of_gpio.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/dmaengine.h> | |
42 | #include <linux/highmem.h> | |
43 | #include <linux/clk.h> | |
44 | #include <linux/err.h> | |
45 | #include <linux/completion.h> | |
46 | #include <linux/gpio.h> | |
47 | #include <linux/regulator/consumer.h> | |
48 | #include <linux/module.h> | |
646781d3 MV |
49 | #include <linux/pinctrl/consumer.h> |
50 | #include <linux/stmp_device.h> | |
51 | #include <linux/spi/spi.h> | |
52 | #include <linux/spi/mxs-spi.h> | |
53 | ||
54 | #define DRIVER_NAME "mxs-spi" | |
55 | ||
56 | #define SSP_TIMEOUT 1000 /* 1000 ms */ | |
57 | ||
58 | struct mxs_spi { | |
59 | struct mxs_ssp ssp; | |
60 | }; | |
61 | ||
62 | static int mxs_spi_setup_transfer(struct spi_device *dev, | |
63 | struct spi_transfer *t) | |
64 | { | |
65 | struct mxs_spi *spi = spi_master_get_devdata(dev->master); | |
66 | struct mxs_ssp *ssp = &spi->ssp; | |
67 | uint8_t bits_per_word; | |
68 | uint32_t hz = 0; | |
69 | ||
70 | bits_per_word = dev->bits_per_word; | |
71 | if (t && t->bits_per_word) | |
72 | bits_per_word = t->bits_per_word; | |
73 | ||
74 | if (bits_per_word != 8) { | |
75 | dev_err(&dev->dev, "%s, unsupported bits_per_word=%d\n", | |
76 | __func__, bits_per_word); | |
77 | return -EINVAL; | |
78 | } | |
79 | ||
80 | hz = dev->max_speed_hz; | |
81 | if (t && t->speed_hz) | |
82 | hz = min(hz, t->speed_hz); | |
83 | if (hz == 0) { | |
84 | dev_err(&dev->dev, "Cannot continue with zero clock\n"); | |
85 | return -EINVAL; | |
86 | } | |
87 | ||
88 | mxs_ssp_set_clk_rate(ssp, hz); | |
89 | ||
90 | writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | | |
91 | BF_SSP_CTRL1_WORD_LENGTH | |
92 | (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) | | |
93 | ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) | | |
94 | ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0), | |
95 | ssp->base + HW_SSP_CTRL1(ssp)); | |
96 | ||
97 | writel(0x0, ssp->base + HW_SSP_CMD0); | |
98 | writel(0x0, ssp->base + HW_SSP_CMD1); | |
99 | ||
100 | return 0; | |
101 | } | |
102 | ||
103 | static int mxs_spi_setup(struct spi_device *dev) | |
104 | { | |
105 | int err = 0; | |
106 | ||
107 | if (!dev->bits_per_word) | |
108 | dev->bits_per_word = 8; | |
109 | ||
110 | if (dev->mode & ~(SPI_CPOL | SPI_CPHA)) | |
111 | return -EINVAL; | |
112 | ||
113 | err = mxs_spi_setup_transfer(dev, NULL); | |
114 | if (err) { | |
115 | dev_err(&dev->dev, | |
116 | "Failed to setup transfer, error = %d\n", err); | |
117 | } | |
118 | ||
119 | return err; | |
120 | } | |
121 | ||
122 | static uint32_t mxs_spi_cs_to_reg(unsigned cs) | |
123 | { | |
124 | uint32_t select = 0; | |
125 | ||
126 | /* | |
127 | * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0 | |
128 | * | |
129 | * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ | |
130 | * in HW_SSP_CTRL0 register do have multiple usage, please refer to | |
131 | * the datasheet for further details. In SPI mode, they are used to | |
132 | * toggle the chip-select lines (nCS pins). | |
133 | */ | |
134 | if (cs & 1) | |
135 | select |= BM_SSP_CTRL0_WAIT_FOR_CMD; | |
136 | if (cs & 2) | |
137 | select |= BM_SSP_CTRL0_WAIT_FOR_IRQ; | |
138 | ||
139 | return select; | |
140 | } | |
141 | ||
142 | static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs) | |
143 | { | |
144 | const uint32_t mask = | |
145 | BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ; | |
146 | uint32_t select; | |
147 | struct mxs_ssp *ssp = &spi->ssp; | |
148 | ||
149 | writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
150 | select = mxs_spi_cs_to_reg(cs); | |
151 | writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
152 | } | |
153 | ||
154 | static inline void mxs_spi_enable(struct mxs_spi *spi) | |
155 | { | |
156 | struct mxs_ssp *ssp = &spi->ssp; | |
157 | ||
158 | writel(BM_SSP_CTRL0_LOCK_CS, | |
159 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
160 | writel(BM_SSP_CTRL0_IGNORE_CRC, | |
161 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
162 | } | |
163 | ||
164 | static inline void mxs_spi_disable(struct mxs_spi *spi) | |
165 | { | |
166 | struct mxs_ssp *ssp = &spi->ssp; | |
167 | ||
168 | writel(BM_SSP_CTRL0_LOCK_CS, | |
169 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
170 | writel(BM_SSP_CTRL0_IGNORE_CRC, | |
171 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
172 | } | |
173 | ||
174 | static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set) | |
175 | { | |
176 | unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT); | |
177 | struct mxs_ssp *ssp = &spi->ssp; | |
178 | uint32_t reg; | |
179 | ||
180 | while (1) { | |
181 | reg = readl_relaxed(ssp->base + offset); | |
182 | ||
183 | if (set && ((reg & mask) == mask)) | |
184 | break; | |
185 | ||
186 | if (!set && ((~reg & mask) == mask)) | |
187 | break; | |
188 | ||
189 | udelay(1); | |
190 | ||
191 | if (time_after(jiffies, timeout)) | |
192 | return -ETIMEDOUT; | |
193 | } | |
194 | return 0; | |
195 | } | |
196 | ||
197 | static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs, | |
198 | unsigned char *buf, int len, | |
199 | int *first, int *last, int write) | |
200 | { | |
201 | struct mxs_ssp *ssp = &spi->ssp; | |
202 | ||
203 | if (*first) | |
204 | mxs_spi_enable(spi); | |
205 | ||
206 | mxs_spi_set_cs(spi, cs); | |
207 | ||
208 | while (len--) { | |
209 | if (*last && len == 0) | |
210 | mxs_spi_disable(spi); | |
211 | ||
212 | if (ssp->devid == IMX23_SSP) { | |
213 | writel(BM_SSP_CTRL0_XFER_COUNT, | |
214 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
215 | writel(1, | |
216 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
217 | } else { | |
218 | writel(1, ssp->base + HW_SSP_XFER_SIZE); | |
219 | } | |
220 | ||
221 | if (write) | |
222 | writel(BM_SSP_CTRL0_READ, | |
223 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
224 | else | |
225 | writel(BM_SSP_CTRL0_READ, | |
226 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
227 | ||
228 | writel(BM_SSP_CTRL0_RUN, | |
229 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
230 | ||
231 | if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1)) | |
232 | return -ETIMEDOUT; | |
233 | ||
234 | if (write) | |
235 | writel(*buf, ssp->base + HW_SSP_DATA(ssp)); | |
236 | ||
237 | writel(BM_SSP_CTRL0_DATA_XFER, | |
238 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
239 | ||
240 | if (!write) { | |
241 | if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp), | |
242 | BM_SSP_STATUS_FIFO_EMPTY, 0)) | |
243 | return -ETIMEDOUT; | |
244 | ||
245 | *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff); | |
246 | } | |
247 | ||
248 | if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0)) | |
249 | return -ETIMEDOUT; | |
250 | ||
251 | buf++; | |
252 | } | |
253 | ||
254 | if (len <= 0) | |
255 | return 0; | |
256 | ||
257 | return -ETIMEDOUT; | |
258 | } | |
259 | ||
260 | static int mxs_spi_transfer_one(struct spi_master *master, | |
261 | struct spi_message *m) | |
262 | { | |
263 | struct mxs_spi *spi = spi_master_get_devdata(master); | |
264 | struct mxs_ssp *ssp = &spi->ssp; | |
265 | int first, last; | |
266 | struct spi_transfer *t, *tmp_t; | |
267 | int status = 0; | |
268 | int cs; | |
269 | ||
270 | first = last = 0; | |
271 | ||
272 | cs = m->spi->chip_select; | |
273 | ||
274 | list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) { | |
275 | ||
276 | status = mxs_spi_setup_transfer(m->spi, t); | |
277 | if (status) | |
278 | break; | |
279 | ||
280 | if (&t->transfer_list == m->transfers.next) | |
281 | first = 1; | |
282 | if (&t->transfer_list == m->transfers.prev) | |
283 | last = 1; | |
284 | if (t->rx_buf && t->tx_buf) { | |
285 | dev_err(ssp->dev, | |
286 | "Cannot send and receive simultaneously\n"); | |
287 | status = -EINVAL; | |
288 | break; | |
289 | } | |
290 | ||
291 | if (t->tx_buf) | |
292 | status = mxs_spi_txrx_pio(spi, cs, (void *)t->tx_buf, | |
293 | t->len, &first, &last, 1); | |
294 | if (t->rx_buf) | |
295 | status = mxs_spi_txrx_pio(spi, cs, t->rx_buf, | |
296 | t->len, &first, &last, 0); | |
297 | ||
298 | m->actual_length += t->len; | |
299 | if (status) | |
300 | break; | |
301 | ||
302 | first = last = 0; | |
303 | } | |
304 | ||
305 | m->status = 0; | |
306 | spi_finalize_current_message(master); | |
307 | ||
308 | return status; | |
309 | } | |
310 | ||
311 | static const struct of_device_id mxs_spi_dt_ids[] = { | |
312 | { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, }, | |
313 | { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, }, | |
314 | { /* sentinel */ } | |
315 | }; | |
316 | MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids); | |
317 | ||
318 | static int __devinit mxs_spi_probe(struct platform_device *pdev) | |
319 | { | |
320 | const struct of_device_id *of_id = | |
321 | of_match_device(mxs_spi_dt_ids, &pdev->dev); | |
322 | struct device_node *np = pdev->dev.of_node; | |
323 | struct spi_master *master; | |
324 | struct mxs_spi *spi; | |
325 | struct mxs_ssp *ssp; | |
326 | struct resource *iores; | |
327 | struct pinctrl *pinctrl; | |
328 | struct clk *clk; | |
329 | void __iomem *base; | |
330 | int devid; | |
331 | int ret = 0; | |
332 | ||
333 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
334 | if (!iores) | |
335 | return -EINVAL; | |
336 | ||
337 | base = devm_request_and_ioremap(&pdev->dev, iores); | |
338 | if (!base) | |
339 | return -EADDRNOTAVAIL; | |
340 | ||
341 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | |
342 | if (IS_ERR(pinctrl)) | |
343 | return PTR_ERR(pinctrl); | |
344 | ||
345 | clk = devm_clk_get(&pdev->dev, NULL); | |
346 | if (IS_ERR(clk)) | |
347 | return PTR_ERR(clk); | |
348 | ||
349 | if (np) | |
350 | devid = (enum mxs_ssp_id) of_id->data; | |
351 | else | |
352 | devid = pdev->id_entry->driver_data; | |
353 | ||
354 | master = spi_alloc_master(&pdev->dev, sizeof(*spi)); | |
355 | if (!master) | |
356 | return -ENOMEM; | |
357 | ||
358 | master->transfer_one_message = mxs_spi_transfer_one; | |
359 | master->setup = mxs_spi_setup; | |
360 | master->mode_bits = SPI_CPOL | SPI_CPHA; | |
361 | master->num_chipselect = 3; | |
362 | master->dev.of_node = np; | |
363 | master->flags = SPI_MASTER_HALF_DUPLEX; | |
364 | ||
365 | spi = spi_master_get_devdata(master); | |
366 | ssp = &spi->ssp; | |
367 | ssp->dev = &pdev->dev; | |
368 | ssp->clk = clk; | |
369 | ssp->base = base; | |
370 | ssp->devid = devid; | |
371 | ||
372 | clk_prepare_enable(ssp->clk); | |
373 | ssp->clk_rate = clk_get_rate(ssp->clk) / 1000; | |
374 | ||
375 | stmp_reset_block(ssp->base); | |
376 | ||
377 | platform_set_drvdata(pdev, master); | |
378 | ||
379 | ret = spi_register_master(master); | |
380 | if (ret) { | |
381 | dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret); | |
382 | goto out_master_free; | |
383 | } | |
384 | ||
385 | return 0; | |
386 | ||
387 | out_master_free: | |
388 | platform_set_drvdata(pdev, NULL); | |
389 | clk_disable_unprepare(ssp->clk); | |
390 | spi_master_put(master); | |
391 | return ret; | |
392 | } | |
393 | ||
394 | static int __devexit mxs_spi_remove(struct platform_device *pdev) | |
395 | { | |
396 | struct spi_master *master; | |
397 | struct mxs_spi *spi; | |
398 | struct mxs_ssp *ssp; | |
399 | ||
400 | master = platform_get_drvdata(pdev); | |
401 | spi = spi_master_get_devdata(master); | |
402 | ssp = &spi->ssp; | |
403 | ||
404 | spi_unregister_master(master); | |
405 | ||
406 | platform_set_drvdata(pdev, NULL); | |
407 | ||
408 | clk_disable_unprepare(ssp->clk); | |
409 | ||
410 | spi_master_put(master); | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | static struct platform_driver mxs_spi_driver = { | |
416 | .probe = mxs_spi_probe, | |
417 | .remove = __devexit_p(mxs_spi_remove), | |
418 | .driver = { | |
419 | .name = DRIVER_NAME, | |
420 | .owner = THIS_MODULE, | |
421 | .of_match_table = mxs_spi_dt_ids, | |
422 | }, | |
423 | }; | |
424 | ||
425 | module_platform_driver(mxs_spi_driver); | |
426 | ||
427 | MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); | |
428 | MODULE_DESCRIPTION("MXS SPI master driver"); | |
429 | MODULE_LICENSE("GPL"); | |
430 | MODULE_ALIAS("platform:mxs-spi"); |