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646781d3 MV |
1 | /* |
2 | * Freescale MXS SPI master driver | |
3 | * | |
4 | * Copyright 2012 DENX Software Engineering, GmbH. | |
5 | * Copyright 2012 Freescale Semiconductor, Inc. | |
6 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | |
7 | * | |
8 | * Rework and transition to new API by: | |
9 | * Marek Vasut <marex@denx.de> | |
10 | * | |
11 | * Based on previous attempt by: | |
12 | * Fabio Estevam <fabio.estevam@freescale.com> | |
13 | * | |
14 | * Based on code from U-Boot bootloader by: | |
15 | * Marek Vasut <marex@denx.de> | |
16 | * | |
17 | * Based on spi-stmp.c, which is: | |
18 | * Author: Dmitry Pervushin <dimka@embeddedalley.com> | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/of.h> | |
35 | #include <linux/of_device.h> | |
36 | #include <linux/of_gpio.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/dmaengine.h> | |
42 | #include <linux/highmem.h> | |
43 | #include <linux/clk.h> | |
44 | #include <linux/err.h> | |
45 | #include <linux/completion.h> | |
46 | #include <linux/gpio.h> | |
47 | #include <linux/regulator/consumer.h> | |
48 | #include <linux/module.h> | |
646781d3 MV |
49 | #include <linux/pinctrl/consumer.h> |
50 | #include <linux/stmp_device.h> | |
51 | #include <linux/spi/spi.h> | |
52 | #include <linux/spi/mxs-spi.h> | |
53 | ||
54 | #define DRIVER_NAME "mxs-spi" | |
55 | ||
56 | #define SSP_TIMEOUT 1000 /* 1000 ms */ | |
57 | ||
474afc04 MV |
58 | #define SG_NUM 4 |
59 | #define SG_MAXLEN 0xff00 | |
60 | ||
646781d3 MV |
61 | struct mxs_spi { |
62 | struct mxs_ssp ssp; | |
474afc04 | 63 | struct completion c; |
646781d3 MV |
64 | }; |
65 | ||
66 | static int mxs_spi_setup_transfer(struct spi_device *dev, | |
67 | struct spi_transfer *t) | |
68 | { | |
69 | struct mxs_spi *spi = spi_master_get_devdata(dev->master); | |
70 | struct mxs_ssp *ssp = &spi->ssp; | |
71 | uint8_t bits_per_word; | |
72 | uint32_t hz = 0; | |
73 | ||
74 | bits_per_word = dev->bits_per_word; | |
75 | if (t && t->bits_per_word) | |
76 | bits_per_word = t->bits_per_word; | |
77 | ||
78 | if (bits_per_word != 8) { | |
79 | dev_err(&dev->dev, "%s, unsupported bits_per_word=%d\n", | |
80 | __func__, bits_per_word); | |
81 | return -EINVAL; | |
82 | } | |
83 | ||
84 | hz = dev->max_speed_hz; | |
85 | if (t && t->speed_hz) | |
86 | hz = min(hz, t->speed_hz); | |
87 | if (hz == 0) { | |
88 | dev_err(&dev->dev, "Cannot continue with zero clock\n"); | |
89 | return -EINVAL; | |
90 | } | |
91 | ||
92 | mxs_ssp_set_clk_rate(ssp, hz); | |
93 | ||
94 | writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | | |
95 | BF_SSP_CTRL1_WORD_LENGTH | |
96 | (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) | | |
97 | ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) | | |
98 | ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0), | |
99 | ssp->base + HW_SSP_CTRL1(ssp)); | |
100 | ||
101 | writel(0x0, ssp->base + HW_SSP_CMD0); | |
102 | writel(0x0, ssp->base + HW_SSP_CMD1); | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
107 | static int mxs_spi_setup(struct spi_device *dev) | |
108 | { | |
109 | int err = 0; | |
110 | ||
111 | if (!dev->bits_per_word) | |
112 | dev->bits_per_word = 8; | |
113 | ||
114 | if (dev->mode & ~(SPI_CPOL | SPI_CPHA)) | |
115 | return -EINVAL; | |
116 | ||
117 | err = mxs_spi_setup_transfer(dev, NULL); | |
118 | if (err) { | |
119 | dev_err(&dev->dev, | |
120 | "Failed to setup transfer, error = %d\n", err); | |
121 | } | |
122 | ||
123 | return err; | |
124 | } | |
125 | ||
126 | static uint32_t mxs_spi_cs_to_reg(unsigned cs) | |
127 | { | |
128 | uint32_t select = 0; | |
129 | ||
130 | /* | |
131 | * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0 | |
132 | * | |
133 | * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ | |
134 | * in HW_SSP_CTRL0 register do have multiple usage, please refer to | |
135 | * the datasheet for further details. In SPI mode, they are used to | |
136 | * toggle the chip-select lines (nCS pins). | |
137 | */ | |
138 | if (cs & 1) | |
139 | select |= BM_SSP_CTRL0_WAIT_FOR_CMD; | |
140 | if (cs & 2) | |
141 | select |= BM_SSP_CTRL0_WAIT_FOR_IRQ; | |
142 | ||
143 | return select; | |
144 | } | |
145 | ||
146 | static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs) | |
147 | { | |
148 | const uint32_t mask = | |
149 | BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ; | |
150 | uint32_t select; | |
151 | struct mxs_ssp *ssp = &spi->ssp; | |
152 | ||
153 | writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
154 | select = mxs_spi_cs_to_reg(cs); | |
155 | writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
156 | } | |
157 | ||
158 | static inline void mxs_spi_enable(struct mxs_spi *spi) | |
159 | { | |
160 | struct mxs_ssp *ssp = &spi->ssp; | |
161 | ||
162 | writel(BM_SSP_CTRL0_LOCK_CS, | |
163 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
164 | writel(BM_SSP_CTRL0_IGNORE_CRC, | |
165 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
166 | } | |
167 | ||
168 | static inline void mxs_spi_disable(struct mxs_spi *spi) | |
169 | { | |
170 | struct mxs_ssp *ssp = &spi->ssp; | |
171 | ||
172 | writel(BM_SSP_CTRL0_LOCK_CS, | |
173 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
174 | writel(BM_SSP_CTRL0_IGNORE_CRC, | |
175 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
176 | } | |
177 | ||
178 | static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set) | |
179 | { | |
180 | unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT); | |
181 | struct mxs_ssp *ssp = &spi->ssp; | |
182 | uint32_t reg; | |
183 | ||
184 | while (1) { | |
185 | reg = readl_relaxed(ssp->base + offset); | |
186 | ||
187 | if (set && ((reg & mask) == mask)) | |
188 | break; | |
189 | ||
190 | if (!set && ((~reg & mask) == mask)) | |
191 | break; | |
192 | ||
193 | udelay(1); | |
194 | ||
195 | if (time_after(jiffies, timeout)) | |
196 | return -ETIMEDOUT; | |
197 | } | |
198 | return 0; | |
199 | } | |
200 | ||
474afc04 MV |
201 | static void mxs_ssp_dma_irq_callback(void *param) |
202 | { | |
203 | struct mxs_spi *spi = param; | |
204 | complete(&spi->c); | |
205 | } | |
206 | ||
207 | static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id) | |
208 | { | |
209 | struct mxs_ssp *ssp = dev_id; | |
210 | dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n", | |
211 | __func__, __LINE__, | |
212 | readl(ssp->base + HW_SSP_CTRL1(ssp)), | |
213 | readl(ssp->base + HW_SSP_STATUS(ssp))); | |
214 | return IRQ_HANDLED; | |
215 | } | |
216 | ||
217 | static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs, | |
218 | unsigned char *buf, int len, | |
219 | int *first, int *last, int write) | |
220 | { | |
221 | struct mxs_ssp *ssp = &spi->ssp; | |
222 | struct dma_async_tx_descriptor *desc; | |
223 | struct scatterlist sg[SG_NUM]; | |
224 | int sg_count; | |
225 | uint32_t pio = BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs); | |
226 | int ret; | |
227 | ||
228 | if (len > SG_NUM * SG_MAXLEN) { | |
229 | dev_err(ssp->dev, "Data chunk too big for DMA\n"); | |
230 | return -EINVAL; | |
231 | } | |
232 | ||
41682e03 | 233 | INIT_COMPLETION(spi->c); |
474afc04 MV |
234 | |
235 | if (*first) | |
236 | pio |= BM_SSP_CTRL0_LOCK_CS; | |
237 | if (*last) | |
238 | pio |= BM_SSP_CTRL0_IGNORE_CRC; | |
239 | if (!write) | |
240 | pio |= BM_SSP_CTRL0_READ; | |
241 | ||
242 | if (ssp->devid == IMX23_SSP) | |
243 | pio |= len; | |
244 | else | |
245 | writel(len, ssp->base + HW_SSP_XFER_SIZE); | |
246 | ||
247 | /* Queue the PIO register write transfer. */ | |
248 | desc = dmaengine_prep_slave_sg(ssp->dmach, | |
249 | (struct scatterlist *)&pio, | |
250 | 1, DMA_TRANS_NONE, 0); | |
251 | if (!desc) { | |
252 | dev_err(ssp->dev, | |
253 | "Failed to get PIO reg. write descriptor.\n"); | |
254 | return -EINVAL; | |
255 | } | |
256 | ||
257 | /* Queue the DMA data transfer. */ | |
258 | sg_init_table(sg, (len / SG_MAXLEN) + 1); | |
259 | sg_count = 0; | |
260 | while (len) { | |
261 | sg_set_buf(&sg[sg_count++], buf, min(len, SG_MAXLEN)); | |
262 | len -= min(len, SG_MAXLEN); | |
263 | buf += min(len, SG_MAXLEN); | |
264 | } | |
265 | dma_map_sg(ssp->dev, sg, sg_count, | |
266 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
267 | ||
268 | desc = dmaengine_prep_slave_sg(ssp->dmach, sg, sg_count, | |
269 | write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
270 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
271 | ||
272 | if (!desc) { | |
273 | dev_err(ssp->dev, | |
274 | "Failed to get DMA data write descriptor.\n"); | |
275 | ret = -EINVAL; | |
276 | goto err; | |
277 | } | |
278 | ||
279 | /* | |
280 | * The last descriptor must have this callback, | |
281 | * to finish the DMA transaction. | |
282 | */ | |
283 | desc->callback = mxs_ssp_dma_irq_callback; | |
284 | desc->callback_param = spi; | |
285 | ||
286 | /* Start the transfer. */ | |
287 | dmaengine_submit(desc); | |
288 | dma_async_issue_pending(ssp->dmach); | |
289 | ||
290 | ret = wait_for_completion_timeout(&spi->c, | |
291 | msecs_to_jiffies(SSP_TIMEOUT)); | |
292 | ||
293 | if (!ret) { | |
294 | dev_err(ssp->dev, "DMA transfer timeout\n"); | |
295 | ret = -ETIMEDOUT; | |
296 | goto err; | |
297 | } | |
298 | ||
299 | ret = 0; | |
300 | ||
301 | err: | |
302 | for (--sg_count; sg_count >= 0; sg_count--) { | |
303 | dma_unmap_sg(ssp->dev, &sg[sg_count], 1, | |
304 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
305 | } | |
306 | ||
307 | return ret; | |
308 | } | |
309 | ||
646781d3 MV |
310 | static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs, |
311 | unsigned char *buf, int len, | |
312 | int *first, int *last, int write) | |
313 | { | |
314 | struct mxs_ssp *ssp = &spi->ssp; | |
315 | ||
316 | if (*first) | |
317 | mxs_spi_enable(spi); | |
318 | ||
319 | mxs_spi_set_cs(spi, cs); | |
320 | ||
321 | while (len--) { | |
322 | if (*last && len == 0) | |
323 | mxs_spi_disable(spi); | |
324 | ||
325 | if (ssp->devid == IMX23_SSP) { | |
326 | writel(BM_SSP_CTRL0_XFER_COUNT, | |
327 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
328 | writel(1, | |
329 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
330 | } else { | |
331 | writel(1, ssp->base + HW_SSP_XFER_SIZE); | |
332 | } | |
333 | ||
334 | if (write) | |
335 | writel(BM_SSP_CTRL0_READ, | |
336 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); | |
337 | else | |
338 | writel(BM_SSP_CTRL0_READ, | |
339 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
340 | ||
341 | writel(BM_SSP_CTRL0_RUN, | |
342 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
343 | ||
344 | if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1)) | |
345 | return -ETIMEDOUT; | |
346 | ||
347 | if (write) | |
348 | writel(*buf, ssp->base + HW_SSP_DATA(ssp)); | |
349 | ||
350 | writel(BM_SSP_CTRL0_DATA_XFER, | |
351 | ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); | |
352 | ||
353 | if (!write) { | |
354 | if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp), | |
355 | BM_SSP_STATUS_FIFO_EMPTY, 0)) | |
356 | return -ETIMEDOUT; | |
357 | ||
358 | *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff); | |
359 | } | |
360 | ||
361 | if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0)) | |
362 | return -ETIMEDOUT; | |
363 | ||
364 | buf++; | |
365 | } | |
366 | ||
367 | if (len <= 0) | |
368 | return 0; | |
369 | ||
370 | return -ETIMEDOUT; | |
371 | } | |
372 | ||
373 | static int mxs_spi_transfer_one(struct spi_master *master, | |
374 | struct spi_message *m) | |
375 | { | |
376 | struct mxs_spi *spi = spi_master_get_devdata(master); | |
377 | struct mxs_ssp *ssp = &spi->ssp; | |
378 | int first, last; | |
379 | struct spi_transfer *t, *tmp_t; | |
380 | int status = 0; | |
381 | int cs; | |
382 | ||
383 | first = last = 0; | |
384 | ||
385 | cs = m->spi->chip_select; | |
386 | ||
387 | list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) { | |
388 | ||
389 | status = mxs_spi_setup_transfer(m->spi, t); | |
390 | if (status) | |
391 | break; | |
392 | ||
393 | if (&t->transfer_list == m->transfers.next) | |
394 | first = 1; | |
395 | if (&t->transfer_list == m->transfers.prev) | |
396 | last = 1; | |
474afc04 | 397 | if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) { |
646781d3 MV |
398 | dev_err(ssp->dev, |
399 | "Cannot send and receive simultaneously\n"); | |
400 | status = -EINVAL; | |
401 | break; | |
402 | } | |
403 | ||
474afc04 MV |
404 | /* |
405 | * Small blocks can be transfered via PIO. | |
406 | * Measured by empiric means: | |
407 | * | |
408 | * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1 | |
409 | * | |
410 | * DMA only: 2.164808 seconds, 473.0KB/s | |
411 | * Combined: 1.676276 seconds, 610.9KB/s | |
412 | */ | |
413 | if (t->len <= 256) { | |
414 | writel(BM_SSP_CTRL1_DMA_ENABLE, | |
415 | ssp->base + HW_SSP_CTRL1(ssp) + | |
416 | STMP_OFFSET_REG_CLR); | |
417 | ||
418 | if (t->tx_buf) | |
419 | status = mxs_spi_txrx_pio(spi, cs, | |
420 | (void *)t->tx_buf, | |
421 | t->len, &first, &last, 1); | |
422 | if (t->rx_buf) | |
423 | status = mxs_spi_txrx_pio(spi, cs, | |
424 | t->rx_buf, t->len, | |
425 | &first, &last, 0); | |
426 | } else { | |
427 | writel(BM_SSP_CTRL1_DMA_ENABLE, | |
428 | ssp->base + HW_SSP_CTRL1(ssp) + | |
429 | STMP_OFFSET_REG_SET); | |
430 | ||
431 | if (t->tx_buf) | |
432 | status = mxs_spi_txrx_dma(spi, cs, | |
433 | (void *)t->tx_buf, t->len, | |
434 | &first, &last, 1); | |
435 | if (t->rx_buf) | |
436 | status = mxs_spi_txrx_dma(spi, cs, | |
437 | t->rx_buf, t->len, | |
438 | &first, &last, 0); | |
439 | } | |
646781d3 MV |
440 | |
441 | m->actual_length += t->len; | |
c895db0f MV |
442 | if (status) { |
443 | stmp_reset_block(ssp->base); | |
646781d3 | 444 | break; |
c895db0f | 445 | } |
646781d3 MV |
446 | |
447 | first = last = 0; | |
448 | } | |
449 | ||
450 | m->status = 0; | |
451 | spi_finalize_current_message(master); | |
452 | ||
453 | return status; | |
454 | } | |
455 | ||
474afc04 MV |
456 | static bool mxs_ssp_dma_filter(struct dma_chan *chan, void *param) |
457 | { | |
458 | struct mxs_ssp *ssp = param; | |
459 | ||
460 | if (!mxs_dma_is_apbh(chan)) | |
461 | return false; | |
462 | ||
463 | if (chan->chan_id != ssp->dma_channel) | |
464 | return false; | |
465 | ||
466 | chan->private = &ssp->dma_data; | |
467 | ||
468 | return true; | |
469 | } | |
470 | ||
646781d3 MV |
471 | static const struct of_device_id mxs_spi_dt_ids[] = { |
472 | { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, }, | |
473 | { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, }, | |
474 | { /* sentinel */ } | |
475 | }; | |
476 | MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids); | |
477 | ||
478 | static int __devinit mxs_spi_probe(struct platform_device *pdev) | |
479 | { | |
480 | const struct of_device_id *of_id = | |
481 | of_match_device(mxs_spi_dt_ids, &pdev->dev); | |
482 | struct device_node *np = pdev->dev.of_node; | |
483 | struct spi_master *master; | |
484 | struct mxs_spi *spi; | |
485 | struct mxs_ssp *ssp; | |
474afc04 | 486 | struct resource *iores, *dmares; |
646781d3 MV |
487 | struct pinctrl *pinctrl; |
488 | struct clk *clk; | |
489 | void __iomem *base; | |
474afc04 MV |
490 | int devid, dma_channel; |
491 | int ret = 0, irq_err, irq_dma; | |
492 | dma_cap_mask_t mask; | |
646781d3 MV |
493 | |
494 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
474afc04 MV |
495 | irq_err = platform_get_irq(pdev, 0); |
496 | irq_dma = platform_get_irq(pdev, 1); | |
497 | if (!iores || irq_err < 0 || irq_dma < 0) | |
646781d3 MV |
498 | return -EINVAL; |
499 | ||
500 | base = devm_request_and_ioremap(&pdev->dev, iores); | |
501 | if (!base) | |
502 | return -EADDRNOTAVAIL; | |
503 | ||
504 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | |
505 | if (IS_ERR(pinctrl)) | |
506 | return PTR_ERR(pinctrl); | |
507 | ||
508 | clk = devm_clk_get(&pdev->dev, NULL); | |
509 | if (IS_ERR(clk)) | |
510 | return PTR_ERR(clk); | |
511 | ||
474afc04 | 512 | if (np) { |
646781d3 | 513 | devid = (enum mxs_ssp_id) of_id->data; |
474afc04 MV |
514 | /* |
515 | * TODO: This is a temporary solution and should be changed | |
516 | * to use generic DMA binding later when the helpers get in. | |
517 | */ | |
518 | ret = of_property_read_u32(np, "fsl,ssp-dma-channel", | |
519 | &dma_channel); | |
520 | if (ret) { | |
521 | dev_err(&pdev->dev, | |
522 | "Failed to get DMA channel\n"); | |
523 | return -EINVAL; | |
524 | } | |
525 | } else { | |
526 | dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
527 | if (!dmares) | |
528 | return -EINVAL; | |
646781d3 | 529 | devid = pdev->id_entry->driver_data; |
474afc04 MV |
530 | dma_channel = dmares->start; |
531 | } | |
646781d3 MV |
532 | |
533 | master = spi_alloc_master(&pdev->dev, sizeof(*spi)); | |
534 | if (!master) | |
535 | return -ENOMEM; | |
536 | ||
537 | master->transfer_one_message = mxs_spi_transfer_one; | |
538 | master->setup = mxs_spi_setup; | |
539 | master->mode_bits = SPI_CPOL | SPI_CPHA; | |
540 | master->num_chipselect = 3; | |
541 | master->dev.of_node = np; | |
542 | master->flags = SPI_MASTER_HALF_DUPLEX; | |
543 | ||
544 | spi = spi_master_get_devdata(master); | |
545 | ssp = &spi->ssp; | |
546 | ssp->dev = &pdev->dev; | |
547 | ssp->clk = clk; | |
548 | ssp->base = base; | |
549 | ssp->devid = devid; | |
474afc04 MV |
550 | ssp->dma_channel = dma_channel; |
551 | ||
41682e03 MV |
552 | init_completion(&spi->c); |
553 | ||
474afc04 MV |
554 | ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0, |
555 | DRIVER_NAME, ssp); | |
556 | if (ret) | |
557 | goto out_master_free; | |
558 | ||
559 | dma_cap_zero(mask); | |
560 | dma_cap_set(DMA_SLAVE, mask); | |
561 | ssp->dma_data.chan_irq = irq_dma; | |
562 | ssp->dmach = dma_request_channel(mask, mxs_ssp_dma_filter, ssp); | |
563 | if (!ssp->dmach) { | |
564 | dev_err(ssp->dev, "Failed to request DMA\n"); | |
565 | goto out_master_free; | |
566 | } | |
646781d3 | 567 | |
474afc04 MV |
568 | /* |
569 | * Crank up the clock to 120MHz, this will be further divided onto a | |
570 | * proper speed. | |
571 | */ | |
646781d3 | 572 | clk_prepare_enable(ssp->clk); |
474afc04 | 573 | clk_set_rate(ssp->clk, 120 * 1000 * 1000); |
646781d3 MV |
574 | ssp->clk_rate = clk_get_rate(ssp->clk) / 1000; |
575 | ||
576 | stmp_reset_block(ssp->base); | |
577 | ||
578 | platform_set_drvdata(pdev, master); | |
579 | ||
580 | ret = spi_register_master(master); | |
581 | if (ret) { | |
582 | dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret); | |
474afc04 | 583 | goto out_free_dma; |
646781d3 MV |
584 | } |
585 | ||
586 | return 0; | |
587 | ||
474afc04 | 588 | out_free_dma: |
474afc04 | 589 | dma_release_channel(ssp->dmach); |
646781d3 | 590 | clk_disable_unprepare(ssp->clk); |
474afc04 | 591 | out_master_free: |
646781d3 MV |
592 | spi_master_put(master); |
593 | return ret; | |
594 | } | |
595 | ||
596 | static int __devexit mxs_spi_remove(struct platform_device *pdev) | |
597 | { | |
598 | struct spi_master *master; | |
599 | struct mxs_spi *spi; | |
600 | struct mxs_ssp *ssp; | |
601 | ||
7d520d28 | 602 | master = spi_master_get(platform_get_drvdata(pdev)); |
646781d3 MV |
603 | spi = spi_master_get_devdata(master); |
604 | ssp = &spi->ssp; | |
605 | ||
606 | spi_unregister_master(master); | |
607 | ||
474afc04 MV |
608 | dma_release_channel(ssp->dmach); |
609 | ||
646781d3 MV |
610 | clk_disable_unprepare(ssp->clk); |
611 | ||
612 | spi_master_put(master); | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | static struct platform_driver mxs_spi_driver = { | |
618 | .probe = mxs_spi_probe, | |
619 | .remove = __devexit_p(mxs_spi_remove), | |
620 | .driver = { | |
621 | .name = DRIVER_NAME, | |
622 | .owner = THIS_MODULE, | |
623 | .of_match_table = mxs_spi_dt_ids, | |
624 | }, | |
625 | }; | |
626 | ||
627 | module_platform_driver(mxs_spi_driver); | |
628 | ||
629 | MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); | |
630 | MODULE_DESCRIPTION("MXS SPI master driver"); | |
631 | MODULE_LICENSE("GPL"); | |
632 | MODULE_ALIAS("platform:mxs-spi"); |