[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-mxs.c

/*
 * Freescale MXS SPI master driver
 *
 * Copyright 2012 DENX Software Engineering, GmbH.
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * Rework and transition to new API by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on previous attempt by:
 * Fabio Estevam <fabio.estevam@freescale.com>
 *
 * Based on code from U-Boot bootloader by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on spi-stmp.c, which is:
 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/module.h>
#include <linux/stmp_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/mxs-spi.h>

#define DRIVER_NAME		"mxs-spi"

/* Use 10S timeout for very long transfers, it should suffice. */
#define SSP_TIMEOUT		10000

#define SG_MAXLEN		0xff00

/*
 * Flags for txrx functions.  More efficient that using an argument register for
 * each one.
 */
#define TXRX_WRITE		(1<<0)	/* This is a write */
#define TXRX_DEASSERT_CS	(1<<1)	/* De-assert CS at end of txrx */

struct mxs_spi {
	struct mxs_ssp		ssp;
	struct completion	c;
};

static int mxs_spi_setup_transfer(struct spi_device *dev,
				  const struct spi_transfer *t)
{
	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	struct mxs_ssp *ssp = &spi->ssp;
	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);

	if (hz == 0) {
		dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
		return -EINVAL;
	}

	mxs_ssp_set_clk_rate(ssp, hz);

	writel(BM_SSP_CTRL0_LOCK_CS,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
	       BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
	       ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
	       ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	       ssp->base + HW_SSP_CTRL1(ssp));

	writel(0x0, ssp->base + HW_SSP_CMD0);
	writel(0x0, ssp->base + HW_SSP_CMD1);

	return 0;
}

static int mxs_spi_setup(struct spi_device *dev)
{
	if (!dev->bits_per_word)
		dev->bits_per_word = 8;

	return 0;
}

static uint32_t mxs_spi_cs_to_reg(unsigned cs)
{
	uint32_t select = 0;

	/*
	 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	 *
	 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
	 * the datasheet for further details. In SPI mode, they are used to
	 * toggle the chip-select lines (nCS pins).
	 */
	if (cs & 1)
		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
	if (cs & 2)
		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;

	return select;
}

static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
{
	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
	struct mxs_ssp *ssp = &spi->ssp;
	uint32_t reg;

	do {
		reg = readl_relaxed(ssp->base + offset);

		if (!set)
			reg = ~reg;

		reg &= mask;

		if (reg == mask)
			return 0;
	} while (time_before(jiffies, timeout));

	return -ETIMEDOUT;
}

static void mxs_ssp_dma_irq_callback(void *param)
{
	struct mxs_spi *spi = param;
	complete(&spi->c);
}

static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
{
	struct mxs_ssp *ssp = dev_id;
	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
		__func__, __LINE__,
		readl(ssp->base + HW_SSP_CTRL1(ssp)),
		readl(ssp->base + HW_SSP_STATUS(ssp)));
	return IRQ_HANDLED;
}

static int mxs_spi_txrx_dma(struct mxs_spi *spi,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;
	struct dma_async_tx_descriptor *desc = NULL;
	const bool vmalloced_buf = is_vmalloc_addr(buf);
	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	const int sgs = DIV_ROUND_UP(len, desc_len);
	int sg_count;
	int min, ret;
	uint32_t ctrl0;
	struct page *vm_page;
	void *sg_buf;
	struct {
		uint32_t		pio[4];
		struct scatterlist	sg;
	} *dma_xfer;

	if (!len)
		return -EINVAL;

	dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
	if (!dma_xfer)
		return -ENOMEM;

	INIT_COMPLETION(spi->c);

	/* Chip select was already programmed into CTRL0 */
	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
		 BM_SSP_CTRL0_READ);
	ctrl0 |= BM_SSP_CTRL0_DATA_XFER;

	if (!(flags & TXRX_WRITE))
		ctrl0 |= BM_SSP_CTRL0_READ;

	/* Queue the DMA data transfer. */
	for (sg_count = 0; sg_count < sgs; sg_count++) {
		/* Prepare the transfer descriptor. */
		min = min(len, desc_len);

		/*
		 * De-assert CS on last segment if flag is set (i.e., no more
		 * transfers will follow)
		 */
		if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
			ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;

		if (ssp->devid == IMX23_SSP) {
			ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
			ctrl0 |= min;
		}

		dma_xfer[sg_count].pio[0] = ctrl0;
		dma_xfer[sg_count].pio[3] = min;

		if (vmalloced_buf) {
			vm_page = vmalloc_to_page(buf);
			if (!vm_page) {
				ret = -ENOMEM;
				goto err_vmalloc;
			}
			sg_buf = page_address(vm_page) +
				((size_t)buf & ~PAGE_MASK);
		} else {
			sg_buf = buf;
		}

		sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);

		len -= min;
		buf += min;

		/* Queue the PIO register write transfer. */
		desc = dmaengine_prep_slave_sg(ssp->dmach,
				(struct scatterlist *)dma_xfer[sg_count].pio,
				(ssp->devid == IMX23_SSP) ? 1 : 4,
				DMA_TRANS_NONE,
				sg_count ? DMA_PREP_INTERRUPT : 0);
		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get PIO reg. write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}

		desc = dmaengine_prep_slave_sg(ssp->dmach,
				&dma_xfer[sg_count].sg, 1,
				(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get DMA data write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}
	}

	/*
	 * The last descriptor must have this callback,
	 * to finish the DMA transaction.
	 */
	desc->callback = mxs_ssp_dma_irq_callback;
	desc->callback_param = spi;

	/* Start the transfer. */
	dmaengine_submit(desc);
	dma_async_issue_pending(ssp->dmach);

	ret = wait_for_completion_timeout(&spi->c,
				msecs_to_jiffies(SSP_TIMEOUT));
	if (!ret) {
		dev_err(ssp->dev, "DMA transfer timeout\n");
		ret = -ETIMEDOUT;
		dmaengine_terminate_all(ssp->dmach);
		goto err_vmalloc;
	}

	ret = 0;

err_vmalloc:
	while (--sg_count >= 0) {
err_mapped:
		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	}

	kfree(dma_xfer);

	return ret;
}

static int mxs_spi_txrx_pio(struct mxs_spi *spi,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;

	writel(BM_SSP_CTRL0_IGNORE_CRC,
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);

	while (len--) {
		if (len == 0 && (flags & TXRX_DEASSERT_CS))
			writel(BM_SSP_CTRL0_IGNORE_CRC,
			       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (ssp->devid == IMX23_SSP) {
			writel(BM_SSP_CTRL0_XFER_COUNT,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
			writel(1,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
		} else {
			writel(1, ssp->base + HW_SSP_XFER_SIZE);
		}

		if (flags & TXRX_WRITE)
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
		else
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		writel(BM_SSP_CTRL0_RUN,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
			return -ETIMEDOUT;

		if (flags & TXRX_WRITE)
			writel(*buf, ssp->base + HW_SSP_DATA(ssp));

		writel(BM_SSP_CTRL0_DATA_XFER,
			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (!(flags & TXRX_WRITE)) {
			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
						BM_SSP_STATUS_FIFO_EMPTY, 0))
				return -ETIMEDOUT;

			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
		}

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
			return -ETIMEDOUT;

		buf++;
	}

	if (len <= 0)
		return 0;

	return -ETIMEDOUT;
}

static int mxs_spi_transfer_one(struct spi_master *master,
				struct spi_message *m)
{
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	struct spi_transfer *t, *tmp_t;
	unsigned int flag;
	int status = 0;

	/* Program CS register bits here, it will be used for all transfers. */
	writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	writel(mxs_spi_cs_to_reg(m->spi->chip_select),
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {

		status = mxs_spi_setup_transfer(m->spi, t);
		if (status)
			break;

		/* De-assert on last transfer, inverted by cs_change flag */
		flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
		       TXRX_DEASSERT_CS : 0;

		/*
		 * Small blocks can be transfered via PIO.
		 * Measured by empiric means:
		 *
		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
		 *
		 * DMA only: 2.164808 seconds, 473.0KB/s
		 * Combined: 1.676276 seconds, 610.9KB/s
		 */
		if (t->len < 32) {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_CLR);

			if (t->tx_buf)
				status = mxs_spi_txrx_pio(spi,
						(void *)t->tx_buf,
						t->len, flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_pio(spi,
						t->rx_buf, t->len,
						flag);
		} else {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_SET);

			if (t->tx_buf)
				status = mxs_spi_txrx_dma(spi,
						(void *)t->tx_buf, t->len,
						flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_dma(spi,
						t->rx_buf, t->len,
						flag);
		}

		if (status) {
			stmp_reset_block(ssp->base);
			break;
		}

		m->actual_length += t->len;
	}

	m->status = status;
	spi_finalize_current_message(master);

	return status;
}

static const struct of_device_id mxs_spi_dt_ids[] = {
	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);

static int mxs_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_spi_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;
	struct resource *iores;
	struct clk *clk;
	void __iomem *base;
	int devid, clk_freq;
	int ret = 0, irq_err;

	/*
	 * Default clock speed for the SPI core. 160MHz seems to
	 * work reasonably well with most SPI flashes, so use this
	 * as a default. Override with "clock-frequency" DT prop.
	 */
	const int clk_freq_default = 160000000;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq_err = platform_get_irq(pdev, 0);
	if (irq_err < 0)
		return -EINVAL;

	base = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	devid = (enum mxs_ssp_id) of_id->data;
	ret = of_property_read_u32(np, "clock-frequency",
				   &clk_freq);
	if (ret)
		clk_freq = clk_freq_default;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (!master)
		return -ENOMEM;

	master->transfer_one_message = mxs_spi_transfer_one;
	master->setup = mxs_spi_setup;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->num_chipselect = 3;
	master->dev.of_node = np;
	master->flags = SPI_MASTER_HALF_DUPLEX;

	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;
	ssp->dev = &pdev->dev;
	ssp->clk = clk;
	ssp->base = base;
	ssp->devid = devid;

	init_completion(&spi->c);

	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
			       DRIVER_NAME, ssp);
	if (ret)
		goto out_master_free;

	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
	if (!ssp->dmach) {
		dev_err(ssp->dev, "Failed to request DMA\n");
		ret = -ENODEV;
		goto out_master_free;
	}

	ret = clk_prepare_enable(ssp->clk);
	if (ret)
		goto out_dma_release;

	clk_set_rate(ssp->clk, clk_freq);

	ret = stmp_reset_block(ssp->base);
	if (ret)
		goto out_disable_clk;

	platform_set_drvdata(pdev, master);

	ret = spi_register_master(master);
	if (ret) {
		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
		goto out_disable_clk;
	}

	return 0;

out_disable_clk:
	clk_disable_unprepare(ssp->clk);
out_dma_release:
	dma_release_channel(ssp->dmach);
out_master_free:
	spi_master_put(master);
	return ret;
}

static int mxs_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;

	master = spi_master_get(platform_get_drvdata(pdev));
	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;

	spi_unregister_master(master);
	clk_disable_unprepare(ssp->clk);
	dma_release_channel(ssp->dmach);
	spi_master_put(master);

	return 0;
}

static struct platform_driver mxs_spi_driver = {
	.probe	= mxs_spi_probe,
	.remove	= mxs_spi_remove,
	.driver	= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = mxs_spi_dt_ids,
	},
};

module_platform_driver(mxs_spi_driver);

MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_DESCRIPTION("MXS SPI master driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mxs-spi");
Commit	Line	Data
646781d3 MV	1	/*
	2	* Freescale MXS SPI master driver
	3	*
	4	* Copyright 2012 DENX Software Engineering, GmbH.
	5	* Copyright 2012 Freescale Semiconductor, Inc.
	6	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
	7	*
	8	* Rework and transition to new API by:
	9	* Marek Vasut <marex@denx.de>
	10	*
	11	* Based on previous attempt by:
	12	* Fabio Estevam <fabio.estevam@freescale.com>
	13	*
	14	* Based on code from U-Boot bootloader by:
	15	* Marek Vasut <marex@denx.de>
	16	*
	17	* Based on spi-stmp.c, which is:
	18	* Author: Dmitry Pervushin <dimka@embeddedalley.com>
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License as published by
	22	* the Free Software Foundation; either version 2 of the License, or
	23	* (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*/
	30
	31	#include <linux/kernel.h>
	32	#include <linux/init.h>
	33	#include <linux/ioport.h>
	34	#include <linux/of.h>
	35	#include <linux/of_device.h>
	36	#include <linux/of_gpio.h>
	37	#include <linux/platform_device.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
	40	#include <linux/dma-mapping.h>
	41	#include <linux/dmaengine.h>
	42	#include <linux/highmem.h>
	43	#include <linux/clk.h>
	44	#include <linux/err.h>
	45	#include <linux/completion.h>
	46	#include <linux/gpio.h>
	47	#include <linux/regulator/consumer.h>
	48	#include <linux/module.h>
646781d3 MV	49	#include <linux/stmp_device.h>
	50	#include <linux/spi/spi.h>
	51	#include <linux/spi/mxs-spi.h>
	52
	53	#define DRIVER_NAME "mxs-spi"
	54
010b4818 MV	55	/* Use 10S timeout for very long transfers, it should suffice. */
010b4818 MV	56	#define SSP_TIMEOUT 10000
646781d3	57
474afc04 MV	58	#define SG_MAXLEN 0xff00
474afc04 MV	59
28cad125 TP	60	/*
	61	* Flags for txrx functions. More efficient that using an argument register for
	62	* each one.
	63	*/
	64	#define TXRX_WRITE (1<<0) /* This is a write */
	65	#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
	66
646781d3 MV	67	struct mxs_spi {
646781d3 MV	68	struct mxs_ssp ssp;
474afc04	69	struct completion c;
646781d3 MV	70	};
	71
	72	static int mxs_spi_setup_transfer(struct spi_device *dev,
aa9e0c6f	73	const struct spi_transfer *t)
646781d3 MV	74	{
	75	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	76	struct mxs_ssp *ssp = &spi->ssp;
aa9e0c6f	77	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
646781d3	78
646781d3	79	if (hz == 0) {
aa9e0c6f	80	dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
646781d3 MV	81	return -EINVAL;
	82	}
	83
	84	mxs_ssp_set_clk_rate(ssp, hz);
	85
58f46e41 TP	86	writel(BM_SSP_CTRL0_LOCK_CS,
58f46e41 TP	87	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
aa9e0c6f	88
646781d3	89	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) \|
aa9e0c6f TP	90	BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) \|
	91	((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) \|
	92	((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	93	ssp->base + HW_SSP_CTRL1(ssp));
646781d3 MV	94
	95	writel(0x0, ssp->base + HW_SSP_CMD0);
	96	writel(0x0, ssp->base + HW_SSP_CMD1);
	97
	98	return 0;
	99	}
	100
	101	static int mxs_spi_setup(struct spi_device *dev)
	102	{
646781d3 MV	103	if (!dev->bits_per_word)
	104	dev->bits_per_word = 8;
	105
9c97e342	106	return 0;
646781d3 MV	107	}
	108
	109	static uint32_t mxs_spi_cs_to_reg(unsigned cs)
	110	{
	111	uint32_t select = 0;
	112
	113	/*
	114	* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	115	*
	116	* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	117	* in HW_SSP_CTRL0 register do have multiple usage, please refer to
	118	* the datasheet for further details. In SPI mode, they are used to
	119	* toggle the chip-select lines (nCS pins).
	120	*/
	121	if (cs & 1)
	122	select \|= BM_SSP_CTRL0_WAIT_FOR_CMD;
	123	if (cs & 2)
	124	select \|= BM_SSP_CTRL0_WAIT_FOR_IRQ;
	125
	126	return select;
	127	}
	128
646781d3 MV	129	static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
646781d3 MV	130	{
f13639dc	131	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
646781d3 MV	132	struct mxs_ssp *ssp = &spi->ssp;
	133	uint32_t reg;
	134
f13639dc	135	do {
646781d3 MV	136	reg = readl_relaxed(ssp->base + offset);
646781d3 MV	137
f13639dc MV	138	if (!set)
f13639dc MV	139	reg = ~reg;
646781d3	140
f13639dc	141	reg &= mask;
646781d3	142
f13639dc MV	143	if (reg == mask)
	144	return 0;
	145	} while (time_before(jiffies, timeout));
646781d3	146
f13639dc	147	return -ETIMEDOUT;
646781d3 MV	148	}
646781d3 MV	149
474afc04 MV	150	static void mxs_ssp_dma_irq_callback(void *param)
	151	{
	152	struct mxs_spi *spi = param;
	153	complete(&spi->c);
	154	}
	155
	156	static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
	157	{
	158	struct mxs_ssp *ssp = dev_id;
	159	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
	160	__func__, __LINE__,
	161	readl(ssp->base + HW_SSP_CTRL1(ssp)),
	162	readl(ssp->base + HW_SSP_STATUS(ssp)));
	163	return IRQ_HANDLED;
	164	}
	165
0b782f70	166	static int mxs_spi_txrx_dma(struct mxs_spi *spi,
474afc04	167	unsigned char *buf, int len,
28cad125	168	unsigned int flags)
474afc04 MV	169	{
474afc04 MV	170	struct mxs_ssp *ssp = &spi->ssp;
010b4818 MV	171	struct dma_async_tx_descriptor *desc = NULL;
	172	const bool vmalloced_buf = is_vmalloc_addr(buf);
	173	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	174	const int sgs = DIV_ROUND_UP(len, desc_len);
474afc04	175	int sg_count;
010b4818 MV	176	int min, ret;
	177	uint32_t ctrl0;
	178	struct page *vm_page;
	179	void *sg_buf;
	180	struct {
	181	uint32_t pio[4];
	182	struct scatterlist sg;
	183	} *dma_xfer;
	184
	185	if (!len)
474afc04	186	return -EINVAL;
010b4818 MV	187
	188	dma_xfer = kzalloc(sizeof(dma_xfer) sgs, GFP_KERNEL);
	189	if (!dma_xfer)
	190	return -ENOMEM;
474afc04	191
41682e03	192	INIT_COMPLETION(spi->c);
474afc04	193
0b782f70	194	/* Chip select was already programmed into CTRL0 */
010b4818	195	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
df23286e TP	196	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT \| BM_SSP_CTRL0_IGNORE_CRC \|
df23286e TP	197	BM_SSP_CTRL0_READ);
0b782f70	198	ctrl0 \|= BM_SSP_CTRL0_DATA_XFER;
010b4818	199
28cad125	200	if (!(flags & TXRX_WRITE))
010b4818	201	ctrl0 \|= BM_SSP_CTRL0_READ;
474afc04 MV	202
474afc04 MV	203	/* Queue the DMA data transfer. */
010b4818	204	for (sg_count = 0; sg_count < sgs; sg_count++) {
28cad125	205	/* Prepare the transfer descriptor. */
010b4818 MV	206	min = min(len, desc_len);
010b4818 MV	207
28cad125 TP	208	/*
	209	* De-assert CS on last segment if flag is set (i.e., no more
	210	* transfers will follow)
	211	*/
	212	if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
010b4818 MV	213	ctrl0 \|= BM_SSP_CTRL0_IGNORE_CRC;
010b4818 MV	214
ba486a2a JL	215	if (ssp->devid == IMX23_SSP) {
ba486a2a JL	216	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818	217	ctrl0 \|= min;
ba486a2a	218	}
010b4818 MV	219
	220	dma_xfer[sg_count].pio[0] = ctrl0;
	221	dma_xfer[sg_count].pio[3] = min;
	222
	223	if (vmalloced_buf) {
	224	vm_page = vmalloc_to_page(buf);
	225	if (!vm_page) {
	226	ret = -ENOMEM;
	227	goto err_vmalloc;
	228	}
	229	sg_buf = page_address(vm_page) +
	230	((size_t)buf & ~PAGE_MASK);
	231	} else {
	232	sg_buf = buf;
	233	}
	234
	235	sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
	236	ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	237	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
010b4818 MV	238
	239	len -= min;
	240	buf += min;
	241
	242	/* Queue the PIO register write transfer. */
	243	desc = dmaengine_prep_slave_sg(ssp->dmach,
	244	(struct scatterlist *)dma_xfer[sg_count].pio,
	245	(ssp->devid == IMX23_SSP) ? 1 : 4,
	246	DMA_TRANS_NONE,
	247	sg_count ? DMA_PREP_INTERRUPT : 0);
	248	if (!desc) {
	249	dev_err(ssp->dev,
	250	"Failed to get PIO reg. write descriptor.\n");
	251	ret = -EINVAL;
	252	goto err_mapped;
	253	}
	254
	255	desc = dmaengine_prep_slave_sg(ssp->dmach,
	256	&dma_xfer[sg_count].sg, 1,
28cad125	257	(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
010b4818 MV	258	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	259
	260	if (!desc) {
	261	dev_err(ssp->dev,
	262	"Failed to get DMA data write descriptor.\n");
	263	ret = -EINVAL;
	264	goto err_mapped;
	265	}
474afc04 MV	266	}
	267
	268	/*
	269	* The last descriptor must have this callback,
	270	* to finish the DMA transaction.
	271	*/
	272	desc->callback = mxs_ssp_dma_irq_callback;
	273	desc->callback_param = spi;
	274
	275	/* Start the transfer. */
	276	dmaengine_submit(desc);
	277	dma_async_issue_pending(ssp->dmach);
	278
	279	ret = wait_for_completion_timeout(&spi->c,
	280	msecs_to_jiffies(SSP_TIMEOUT));
474afc04 MV	281	if (!ret) {
	282	dev_err(ssp->dev, "DMA transfer timeout\n");
	283	ret = -ETIMEDOUT;
44968466	284	dmaengine_terminate_all(ssp->dmach);
010b4818	285	goto err_vmalloc;
474afc04 MV	286	}
	287
	288	ret = 0;
	289
010b4818 MV	290	err_vmalloc:
	291	while (--sg_count >= 0) {
	292	err_mapped:
	293	dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	294	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
474afc04 MV	295	}
474afc04 MV	296
010b4818 MV	297	kfree(dma_xfer);
010b4818 MV	298
474afc04 MV	299	return ret;
	300	}
	301
0b782f70	302	static int mxs_spi_txrx_pio(struct mxs_spi *spi,
646781d3	303	unsigned char *buf, int len,
28cad125	304	unsigned int flags)
646781d3 MV	305	{
	306	struct mxs_ssp *ssp = &spi->ssp;
	307
75e73fa2 TP	308	writel(BM_SSP_CTRL0_IGNORE_CRC,
75e73fa2 TP	309	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
646781d3	310
646781d3	311	while (len--) {
28cad125	312	if (len == 0 && (flags & TXRX_DEASSERT_CS))
f5bc7384 TP	313	writel(BM_SSP_CTRL0_IGNORE_CRC,
f5bc7384 TP	314	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	315
	316	if (ssp->devid == IMX23_SSP) {
	317	writel(BM_SSP_CTRL0_XFER_COUNT,
	318	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	319	writel(1,
	320	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	321	} else {
	322	writel(1, ssp->base + HW_SSP_XFER_SIZE);
	323	}
	324
28cad125	325	if (flags & TXRX_WRITE)
646781d3 MV	326	writel(BM_SSP_CTRL0_READ,
	327	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	328	else
	329	writel(BM_SSP_CTRL0_READ,
	330	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	331
	332	writel(BM_SSP_CTRL0_RUN,
	333	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	334
	335	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
	336	return -ETIMEDOUT;
	337
28cad125	338	if (flags & TXRX_WRITE)
646781d3 MV	339	writel(*buf, ssp->base + HW_SSP_DATA(ssp));
	340
	341	writel(BM_SSP_CTRL0_DATA_XFER,
	342	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	343
28cad125	344	if (!(flags & TXRX_WRITE)) {
646781d3 MV	345	if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
	346	BM_SSP_STATUS_FIFO_EMPTY, 0))
	347	return -ETIMEDOUT;
	348
	349	*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
	350	}
	351
	352	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
	353	return -ETIMEDOUT;
	354
	355	buf++;
	356	}
	357
	358	if (len <= 0)
	359	return 0;
	360
	361	return -ETIMEDOUT;
	362	}
	363
	364	static int mxs_spi_transfer_one(struct spi_master *master,
	365	struct spi_message *m)
	366	{
	367	struct mxs_spi *spi = spi_master_get_devdata(master);
	368	struct mxs_ssp *ssp = &spi->ssp;
646781d3	369	struct spi_transfer t, tmp_t;
28cad125	370	unsigned int flag;
646781d3	371	int status = 0;
646781d3	372
0b782f70 TP	373	/* Program CS register bits here, it will be used for all transfers. */
	374	writel(BM_SSP_CTRL0_WAIT_FOR_CMD \| BM_SSP_CTRL0_WAIT_FOR_IRQ,
	375	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	376	writel(mxs_spi_cs_to_reg(m->spi->chip_select),
	377	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	378
	379	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
	380
	381	status = mxs_spi_setup_transfer(m->spi, t);
	382	if (status)
	383	break;
	384
28cad125 TP	385	/* De-assert on last transfer, inverted by cs_change flag */
	386	flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
	387	TXRX_DEASSERT_CS : 0;
646781d3	388
474afc04 MV	389	/*
	390	* Small blocks can be transfered via PIO.
	391	* Measured by empiric means:
	392	*
	393	* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
	394	*
	395	* DMA only: 2.164808 seconds, 473.0KB/s
	396	* Combined: 1.676276 seconds, 610.9KB/s
	397	*/
727c10e3	398	if (t->len < 32) {
474afc04 MV	399	writel(BM_SSP_CTRL1_DMA_ENABLE,
	400	ssp->base + HW_SSP_CTRL1(ssp) +
	401	STMP_OFFSET_REG_CLR);
	402
	403	if (t->tx_buf)
0b782f70	404	status = mxs_spi_txrx_pio(spi,
474afc04	405	(void *)t->tx_buf,
28cad125	406	t->len, flag \| TXRX_WRITE);
474afc04	407	if (t->rx_buf)
0b782f70	408	status = mxs_spi_txrx_pio(spi,
474afc04	409	t->rx_buf, t->len,
28cad125	410	flag);
474afc04 MV	411	} else {
	412	writel(BM_SSP_CTRL1_DMA_ENABLE,
	413	ssp->base + HW_SSP_CTRL1(ssp) +
	414	STMP_OFFSET_REG_SET);
	415
	416	if (t->tx_buf)
0b782f70	417	status = mxs_spi_txrx_dma(spi,
474afc04	418	(void *)t->tx_buf, t->len,
28cad125	419	flag \| TXRX_WRITE);
474afc04	420	if (t->rx_buf)
0b782f70	421	status = mxs_spi_txrx_dma(spi,
474afc04	422	t->rx_buf, t->len,
28cad125	423	flag);
474afc04	424	}
646781d3	425
c895db0f MV	426	if (status) {
c895db0f MV	427	stmp_reset_block(ssp->base);
646781d3	428	break;
c895db0f	429	}
646781d3	430
204e706f	431	m->actual_length += t->len;
646781d3 MV	432	}
646781d3 MV	433
d856f1eb	434	m->status = status;
646781d3 MV	435	spi_finalize_current_message(master);
	436
	437	return status;
	438	}
	439
	440	static const struct of_device_id mxs_spi_dt_ids[] = {
	441	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	442	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	443	{ /* sentinel */ }
	444	};
	445	MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
	446
fd4a319b	447	static int mxs_spi_probe(struct platform_device *pdev)
646781d3 MV	448	{
	449	const struct of_device_id *of_id =
	450	of_match_device(mxs_spi_dt_ids, &pdev->dev);
	451	struct device_node *np = pdev->dev.of_node;
	452	struct spi_master *master;
	453	struct mxs_spi *spi;
	454	struct mxs_ssp *ssp;
26aafa77	455	struct resource *iores;
646781d3 MV	456	struct clk *clk;
646781d3 MV	457	void __iomem *base;
26aafa77 SG	458	int devid, clk_freq;
26aafa77 SG	459	int ret = 0, irq_err;
646781d3	460
e64d07a2 MV	461	/*
	462	* Default clock speed for the SPI core. 160MHz seems to
	463	* work reasonably well with most SPI flashes, so use this
	464	* as a default. Override with "clock-frequency" DT prop.
	465	*/
	466	const int clk_freq_default = 160000000;
	467
646781d3	468	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474afc04	469	irq_err = platform_get_irq(pdev, 0);
796305a2	470	if (irq_err < 0)
646781d3 MV	471	return -EINVAL;
646781d3 MV	472
b0ee5605 TR	473	base = devm_ioremap_resource(&pdev->dev, iores);
	474	if (IS_ERR(base))
	475	return PTR_ERR(base);
646781d3	476
646781d3 MV	477	clk = devm_clk_get(&pdev->dev, NULL);
	478	if (IS_ERR(clk))
	479	return PTR_ERR(clk);
	480
26aafa77 SG	481	devid = (enum mxs_ssp_id) of_id->data;
	482	ret = of_property_read_u32(np, "clock-frequency",
	483	&clk_freq);
	484	if (ret)
e64d07a2	485	clk_freq = clk_freq_default;
646781d3 MV	486
	487	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	488	if (!master)
	489	return -ENOMEM;
	490
	491	master->transfer_one_message = mxs_spi_transfer_one;
	492	master->setup = mxs_spi_setup;
24778be2	493	master->bits_per_word_mask = SPI_BPW_MASK(8);
646781d3 MV	494	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	495	master->num_chipselect = 3;
	496	master->dev.of_node = np;
	497	master->flags = SPI_MASTER_HALF_DUPLEX;
	498
	499	spi = spi_master_get_devdata(master);
	500	ssp = &spi->ssp;
	501	ssp->dev = &pdev->dev;
	502	ssp->clk = clk;
	503	ssp->base = base;
	504	ssp->devid = devid;
474afc04	505
41682e03 MV	506	init_completion(&spi->c);
41682e03 MV	507
474afc04 MV	508	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
	509	DRIVER_NAME, ssp);
	510	if (ret)
	511	goto out_master_free;
	512
26aafa77	513	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
474afc04 MV	514	if (!ssp->dmach) {
474afc04 MV	515	dev_err(ssp->dev, "Failed to request DMA\n");
58ad60bb	516	ret = -ENODEV;
474afc04 MV	517	goto out_master_free;
474afc04 MV	518	}
646781d3	519
9c4a39af FE	520	ret = clk_prepare_enable(ssp->clk);
	521	if (ret)
	522	goto out_dma_release;
	523
e64d07a2	524	clk_set_rate(ssp->clk, clk_freq);
646781d3	525
8498bce9 FE	526	ret = stmp_reset_block(ssp->base);
	527	if (ret)
	528	goto out_disable_clk;
646781d3 MV	529
	530	platform_set_drvdata(pdev, master);
	531
	532	ret = spi_register_master(master);
	533	if (ret) {
	534	dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
9c4a39af	535	goto out_disable_clk;
646781d3 MV	536	}
	537
	538	return 0;
	539
9c4a39af	540	out_disable_clk:
646781d3	541	clk_disable_unprepare(ssp->clk);
9c4a39af	542	out_dma_release:
e11933f6	543	dma_release_channel(ssp->dmach);
474afc04	544	out_master_free:
646781d3 MV	545	spi_master_put(master);
	546	return ret;
	547	}
	548
fd4a319b	549	static int mxs_spi_remove(struct platform_device *pdev)
646781d3 MV	550	{
	551	struct spi_master *master;
	552	struct mxs_spi *spi;
	553	struct mxs_ssp *ssp;
	554
7d520d28	555	master = spi_master_get(platform_get_drvdata(pdev));
646781d3 MV	556	spi = spi_master_get_devdata(master);
	557	ssp = &spi->ssp;
	558
	559	spi_unregister_master(master);
646781d3	560	clk_disable_unprepare(ssp->clk);
e11933f6	561	dma_release_channel(ssp->dmach);
646781d3 MV	562	spi_master_put(master);
	563
	564	return 0;
	565	}
	566
	567	static struct platform_driver mxs_spi_driver = {
	568	.probe = mxs_spi_probe,
fd4a319b	569	.remove = mxs_spi_remove,
646781d3 MV	570	.driver = {
	571	.name = DRIVER_NAME,
	572	.owner = THIS_MODULE,
	573	.of_match_table = mxs_spi_dt_ids,
	574	},
	575	};
	576
	577	module_platform_driver(mxs_spi_driver);
	578
	579	MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
	580	MODULE_DESCRIPTION("MXS SPI master driver");
	581	MODULE_LICENSE("GPL");
	582	MODULE_ALIAS("platform:mxs-spi");