[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-mxs.c

/*
 * Freescale MXS SPI master driver
 *
 * Copyright 2012 DENX Software Engineering, GmbH.
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * Rework and transition to new API by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on previous attempt by:
 * Fabio Estevam <fabio.estevam@freescale.com>
 *
 * Based on code from U-Boot bootloader by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on spi-stmp.c, which is:
 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/module.h>
#include <linux/stmp_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/mxs-spi.h>

#define DRIVER_NAME		"mxs-spi"

/* Use 10S timeout for very long transfers, it should suffice. */
#define SSP_TIMEOUT		10000

#define SG_MAXLEN		0xff00

struct mxs_spi {
	struct mxs_ssp		ssp;
	struct completion	c;
};

static int mxs_spi_setup_transfer(struct spi_device *dev,
				struct spi_transfer *t)
{
	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	struct mxs_ssp *ssp = &spi->ssp;
	uint8_t bits_per_word;
	uint32_t hz = 0;

	bits_per_word = dev->bits_per_word;
	if (t && t->bits_per_word)
		bits_per_word = t->bits_per_word;

	hz = dev->max_speed_hz;
	if (t && t->speed_hz)
		hz = min(hz, t->speed_hz);
	if (hz == 0) {
		dev_err(&dev->dev, "Cannot continue with zero clock\n");
		return -EINVAL;
	}

	mxs_ssp_set_clk_rate(ssp, hz);

	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
		     BF_SSP_CTRL1_WORD_LENGTH
		     (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
		     ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
		     ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
		     ssp->base + HW_SSP_CTRL1(ssp));

	writel(0x0, ssp->base + HW_SSP_CMD0);
	writel(0x0, ssp->base + HW_SSP_CMD1);

	return 0;
}

static int mxs_spi_setup(struct spi_device *dev)
{
	int err = 0;

	if (!dev->bits_per_word)
		dev->bits_per_word = 8;

	if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
		return -EINVAL;

	err = mxs_spi_setup_transfer(dev, NULL);
	if (err) {
		dev_err(&dev->dev,
			"Failed to setup transfer, error = %d\n", err);
	}

	return err;
}

static uint32_t mxs_spi_cs_to_reg(unsigned cs)
{
	uint32_t select = 0;

	/*
	 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	 *
	 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
	 * the datasheet for further details. In SPI mode, they are used to
	 * toggle the chip-select lines (nCS pins).
	 */
	if (cs & 1)
		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
	if (cs & 2)
		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;

	return select;
}

static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
{
	const uint32_t mask =
		BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ;
	uint32_t select;
	struct mxs_ssp *ssp = &spi->ssp;

	writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	select = mxs_spi_cs_to_reg(cs);
	writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
}

static inline void mxs_spi_enable(struct mxs_spi *spi)
{
	struct mxs_ssp *ssp = &spi->ssp;

	writel(BM_SSP_CTRL0_LOCK_CS,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	writel(BM_SSP_CTRL0_IGNORE_CRC,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
}

static inline void mxs_spi_disable(struct mxs_spi *spi)
{
	struct mxs_ssp *ssp = &spi->ssp;

	writel(BM_SSP_CTRL0_LOCK_CS,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	writel(BM_SSP_CTRL0_IGNORE_CRC,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
}

static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
{
	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
	struct mxs_ssp *ssp = &spi->ssp;
	uint32_t reg;

	do {
		reg = readl_relaxed(ssp->base + offset);

		if (!set)
			reg = ~reg;

		reg &= mask;

		if (reg == mask)
			return 0;
	} while (time_before(jiffies, timeout));

	return -ETIMEDOUT;
}

static void mxs_ssp_dma_irq_callback(void *param)
{
	struct mxs_spi *spi = param;
	complete(&spi->c);
}

static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
{
	struct mxs_ssp *ssp = dev_id;
	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
		__func__, __LINE__,
		readl(ssp->base + HW_SSP_CTRL1(ssp)),
		readl(ssp->base + HW_SSP_STATUS(ssp)));
	return IRQ_HANDLED;
}

static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
			    unsigned char *buf, int len,
			    int *first, int *last, int write)
{
	struct mxs_ssp *ssp = &spi->ssp;
	struct dma_async_tx_descriptor *desc = NULL;
	const bool vmalloced_buf = is_vmalloc_addr(buf);
	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	const int sgs = DIV_ROUND_UP(len, desc_len);
	int sg_count;
	int min, ret;
	uint32_t ctrl0;
	struct page *vm_page;
	void *sg_buf;
	struct {
		uint32_t		pio[4];
		struct scatterlist	sg;
	} *dma_xfer;

	if (!len)
		return -EINVAL;

	dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
	if (!dma_xfer)
		return -ENOMEM;

	INIT_COMPLETION(spi->c);

	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
	ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs);

	if (*first)
		ctrl0 |= BM_SSP_CTRL0_LOCK_CS;
	if (!write)
		ctrl0 |= BM_SSP_CTRL0_READ;

	/* Queue the DMA data transfer. */
	for (sg_count = 0; sg_count < sgs; sg_count++) {
		min = min(len, desc_len);

		/* Prepare the transfer descriptor. */
		if ((sg_count + 1 == sgs) && *last)
			ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;

		if (ssp->devid == IMX23_SSP) {
			ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
			ctrl0 |= min;
		}

		dma_xfer[sg_count].pio[0] = ctrl0;
		dma_xfer[sg_count].pio[3] = min;

		if (vmalloced_buf) {
			vm_page = vmalloc_to_page(buf);
			if (!vm_page) {
				ret = -ENOMEM;
				goto err_vmalloc;
			}
			sg_buf = page_address(vm_page) +
				((size_t)buf & ~PAGE_MASK);
		} else {
			sg_buf = buf;
		}

		sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);

		len -= min;
		buf += min;

		/* Queue the PIO register write transfer. */
		desc = dmaengine_prep_slave_sg(ssp->dmach,
				(struct scatterlist *)dma_xfer[sg_count].pio,
				(ssp->devid == IMX23_SSP) ? 1 : 4,
				DMA_TRANS_NONE,
				sg_count ? DMA_PREP_INTERRUPT : 0);
		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get PIO reg. write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}

		desc = dmaengine_prep_slave_sg(ssp->dmach,
				&dma_xfer[sg_count].sg, 1,
				write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get DMA data write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}
	}

	/*
	 * The last descriptor must have this callback,
	 * to finish the DMA transaction.
	 */
	desc->callback = mxs_ssp_dma_irq_callback;
	desc->callback_param = spi;

	/* Start the transfer. */
	dmaengine_submit(desc);
	dma_async_issue_pending(ssp->dmach);

	ret = wait_for_completion_timeout(&spi->c,
				msecs_to_jiffies(SSP_TIMEOUT));
	if (!ret) {
		dev_err(ssp->dev, "DMA transfer timeout\n");
		ret = -ETIMEDOUT;
		dmaengine_terminate_all(ssp->dmach);
		goto err_vmalloc;
	}

	ret = 0;

err_vmalloc:
	while (--sg_count >= 0) {
err_mapped:
		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	}

	kfree(dma_xfer);

	return ret;
}

static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
			    unsigned char *buf, int len,
			    int *first, int *last, int write)
{
	struct mxs_ssp *ssp = &spi->ssp;

	if (*first)
		mxs_spi_enable(spi);

	mxs_spi_set_cs(spi, cs);

	while (len--) {
		if (*last && len == 0)
			mxs_spi_disable(spi);

		if (ssp->devid == IMX23_SSP) {
			writel(BM_SSP_CTRL0_XFER_COUNT,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
			writel(1,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
		} else {
			writel(1, ssp->base + HW_SSP_XFER_SIZE);
		}

		if (write)
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
		else
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		writel(BM_SSP_CTRL0_RUN,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
			return -ETIMEDOUT;

		if (write)
			writel(*buf, ssp->base + HW_SSP_DATA(ssp));

		writel(BM_SSP_CTRL0_DATA_XFER,
			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (!write) {
			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
						BM_SSP_STATUS_FIFO_EMPTY, 0))
				return -ETIMEDOUT;

			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
		}

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
			return -ETIMEDOUT;

		buf++;
	}

	if (len <= 0)
		return 0;

	return -ETIMEDOUT;
}

static int mxs_spi_transfer_one(struct spi_master *master,
				struct spi_message *m)
{
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	int first, last;
	struct spi_transfer *t, *tmp_t;
	int status = 0;
	int cs;

	first = last = 0;

	cs = m->spi->chip_select;

	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {

		status = mxs_spi_setup_transfer(m->spi, t);
		if (status)
			break;

		if (&t->transfer_list == m->transfers.next)
			first = 1;
		if (&t->transfer_list == m->transfers.prev)
			last = 1;
		if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) {
			dev_err(ssp->dev,
				"Cannot send and receive simultaneously\n");
			status = -EINVAL;
			break;
		}

		/*
		 * Small blocks can be transfered via PIO.
		 * Measured by empiric means:
		 *
		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
		 *
		 * DMA only: 2.164808 seconds, 473.0KB/s
		 * Combined: 1.676276 seconds, 610.9KB/s
		 */
		if (t->len < 32) {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_CLR);

			if (t->tx_buf)
				status = mxs_spi_txrx_pio(spi, cs,
						(void *)t->tx_buf,
						t->len, &first, &last, 1);
			if (t->rx_buf)
				status = mxs_spi_txrx_pio(spi, cs,
						t->rx_buf, t->len,
						&first, &last, 0);
		} else {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_SET);

			if (t->tx_buf)
				status = mxs_spi_txrx_dma(spi, cs,
						(void *)t->tx_buf, t->len,
						&first, &last, 1);
			if (t->rx_buf)
				status = mxs_spi_txrx_dma(spi, cs,
						t->rx_buf, t->len,
						&first, &last, 0);
		}

		if (status) {
			stmp_reset_block(ssp->base);
			break;
		}

		m->actual_length += t->len;
		first = last = 0;
	}

	m->status = status;
	spi_finalize_current_message(master);

	return status;
}

static const struct of_device_id mxs_spi_dt_ids[] = {
	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);

static int mxs_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_spi_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;
	struct resource *iores;
	struct clk *clk;
	void __iomem *base;
	int devid, clk_freq;
	int ret = 0, irq_err;

	/*
	 * Default clock speed for the SPI core. 160MHz seems to
	 * work reasonably well with most SPI flashes, so use this
	 * as a default. Override with "clock-frequency" DT prop.
	 */
	const int clk_freq_default = 160000000;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq_err = platform_get_irq(pdev, 0);
	if (!iores || irq_err < 0)
		return -EINVAL;

	base = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	devid = (enum mxs_ssp_id) of_id->data;
	ret = of_property_read_u32(np, "clock-frequency",
				   &clk_freq);
	if (ret)
		clk_freq = clk_freq_default;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (!master)
		return -ENOMEM;

	master->transfer_one_message = mxs_spi_transfer_one;
	master->setup = mxs_spi_setup;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->num_chipselect = 3;
	master->dev.of_node = np;
	master->flags = SPI_MASTER_HALF_DUPLEX;

	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;
	ssp->dev = &pdev->dev;
	ssp->clk = clk;
	ssp->base = base;
	ssp->devid = devid;

	init_completion(&spi->c);

	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
			       DRIVER_NAME, ssp);
	if (ret)
		goto out_master_free;

	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
	if (!ssp->dmach) {
		dev_err(ssp->dev, "Failed to request DMA\n");
		ret = -ENODEV;
		goto out_master_free;
	}

	clk_prepare_enable(ssp->clk);
	clk_set_rate(ssp->clk, clk_freq);
	ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;

	stmp_reset_block(ssp->base);

	platform_set_drvdata(pdev, master);

	ret = spi_register_master(master);
	if (ret) {
		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
		goto out_free_dma;
	}

	return 0;

out_free_dma:
	dma_release_channel(ssp->dmach);
	clk_disable_unprepare(ssp->clk);
out_master_free:
	spi_master_put(master);
	return ret;
}

static int mxs_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;

	master = spi_master_get(platform_get_drvdata(pdev));
	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;

	spi_unregister_master(master);

	dma_release_channel(ssp->dmach);

	clk_disable_unprepare(ssp->clk);

	spi_master_put(master);

	return 0;
}

static struct platform_driver mxs_spi_driver = {
	.probe	= mxs_spi_probe,
	.remove	= mxs_spi_remove,
	.driver	= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = mxs_spi_dt_ids,
	},
};

module_platform_driver(mxs_spi_driver);

MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_DESCRIPTION("MXS SPI master driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mxs-spi");
Commit	Line	Data
646781d3 MV	1	/*
	2	* Freescale MXS SPI master driver
	3	*
	4	* Copyright 2012 DENX Software Engineering, GmbH.
	5	* Copyright 2012 Freescale Semiconductor, Inc.
	6	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
	7	*
	8	* Rework and transition to new API by:
	9	* Marek Vasut <marex@denx.de>
	10	*
	11	* Based on previous attempt by:
	12	* Fabio Estevam <fabio.estevam@freescale.com>
	13	*
	14	* Based on code from U-Boot bootloader by:
	15	* Marek Vasut <marex@denx.de>
	16	*
	17	* Based on spi-stmp.c, which is:
	18	* Author: Dmitry Pervushin <dimka@embeddedalley.com>
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License as published by
	22	* the Free Software Foundation; either version 2 of the License, or
	23	* (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*/
	30
	31	#include <linux/kernel.h>
	32	#include <linux/init.h>
	33	#include <linux/ioport.h>
	34	#include <linux/of.h>
	35	#include <linux/of_device.h>
	36	#include <linux/of_gpio.h>
	37	#include <linux/platform_device.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
	40	#include <linux/dma-mapping.h>
	41	#include <linux/dmaengine.h>
	42	#include <linux/highmem.h>
	43	#include <linux/clk.h>
	44	#include <linux/err.h>
	45	#include <linux/completion.h>
	46	#include <linux/gpio.h>
	47	#include <linux/regulator/consumer.h>
	48	#include <linux/module.h>
646781d3 MV	49	#include <linux/stmp_device.h>
	50	#include <linux/spi/spi.h>
	51	#include <linux/spi/mxs-spi.h>
	52
	53	#define DRIVER_NAME "mxs-spi"
	54
010b4818 MV	55	/* Use 10S timeout for very long transfers, it should suffice. */
010b4818 MV	56	#define SSP_TIMEOUT 10000
646781d3	57
474afc04 MV	58	#define SG_MAXLEN 0xff00
474afc04 MV	59
646781d3 MV	60	struct mxs_spi {
646781d3 MV	61	struct mxs_ssp ssp;
474afc04	62	struct completion c;
646781d3 MV	63	};
	64
	65	static int mxs_spi_setup_transfer(struct spi_device *dev,
	66	struct spi_transfer *t)
	67	{
	68	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	69	struct mxs_ssp *ssp = &spi->ssp;
	70	uint8_t bits_per_word;
	71	uint32_t hz = 0;
	72
	73	bits_per_word = dev->bits_per_word;
	74	if (t && t->bits_per_word)
	75	bits_per_word = t->bits_per_word;
	76
646781d3 MV	77	hz = dev->max_speed_hz;
	78	if (t && t->speed_hz)
	79	hz = min(hz, t->speed_hz);
	80	if (hz == 0) {
	81	dev_err(&dev->dev, "Cannot continue with zero clock\n");
	82	return -EINVAL;
	83	}
	84
	85	mxs_ssp_set_clk_rate(ssp, hz);
	86
	87	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) \|
	88	BF_SSP_CTRL1_WORD_LENGTH
	89	(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) \|
	90	((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) \|
	91	((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	92	ssp->base + HW_SSP_CTRL1(ssp));
	93
	94	writel(0x0, ssp->base + HW_SSP_CMD0);
	95	writel(0x0, ssp->base + HW_SSP_CMD1);
	96
	97	return 0;
	98	}
	99
	100	static int mxs_spi_setup(struct spi_device *dev)
	101	{
	102	int err = 0;
	103
	104	if (!dev->bits_per_word)
	105	dev->bits_per_word = 8;
	106
	107	if (dev->mode & ~(SPI_CPOL \| SPI_CPHA))
	108	return -EINVAL;
	109
	110	err = mxs_spi_setup_transfer(dev, NULL);
	111	if (err) {
	112	dev_err(&dev->dev,
	113	"Failed to setup transfer, error = %d\n", err);
	114	}
	115
	116	return err;
	117	}
	118
	119	static uint32_t mxs_spi_cs_to_reg(unsigned cs)
	120	{
	121	uint32_t select = 0;
	122
	123	/*
	124	* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	125	*
	126	* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	127	* in HW_SSP_CTRL0 register do have multiple usage, please refer to
	128	* the datasheet for further details. In SPI mode, they are used to
	129	* toggle the chip-select lines (nCS pins).
	130	*/
	131	if (cs & 1)
	132	select \|= BM_SSP_CTRL0_WAIT_FOR_CMD;
	133	if (cs & 2)
	134	select \|= BM_SSP_CTRL0_WAIT_FOR_IRQ;
	135
	136	return select;
	137	}
	138
	139	static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
	140	{
141	const uint32_t mask =
142	BM_SSP_CTRL0_WAIT_FOR_CMD \| BM_SSP_CTRL0_WAIT_FOR_IRQ;
143	uint32_t select;
144	struct mxs_ssp *ssp = &spi->ssp;
145
146	writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
147	select = mxs_spi_cs_to_reg(cs);
148	writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
149	}
150
151	static inline void mxs_spi_enable(struct mxs_spi *spi)
152	{
153	struct mxs_ssp *ssp = &spi->ssp;
154
155	writel(BM_SSP_CTRL0_LOCK_CS,
156	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
157	writel(BM_SSP_CTRL0_IGNORE_CRC,
158	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
159	}
160
161	static inline void mxs_spi_disable(struct mxs_spi *spi)
162	{
163	struct mxs_ssp *ssp = &spi->ssp;
164
165	writel(BM_SSP_CTRL0_LOCK_CS,
166	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
167	writel(BM_SSP_CTRL0_IGNORE_CRC,
168	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
169	}
170
171	static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
172	{
f13639dc	173	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
646781d3 MV	174	struct mxs_ssp *ssp = &spi->ssp;
	175	uint32_t reg;
	176
f13639dc	177	do {
646781d3 MV	178	reg = readl_relaxed(ssp->base + offset);
646781d3 MV	179
f13639dc MV	180	if (!set)
f13639dc MV	181	reg = ~reg;
646781d3	182
f13639dc	183	reg &= mask;
646781d3	184
f13639dc MV	185	if (reg == mask)
	186	return 0;
	187	} while (time_before(jiffies, timeout));
646781d3	188
f13639dc	189	return -ETIMEDOUT;
646781d3 MV	190	}
646781d3 MV	191
474afc04 MV	192	static void mxs_ssp_dma_irq_callback(void *param)
	193	{
	194	struct mxs_spi *spi = param;
	195	complete(&spi->c);
	196	}
	197
	198	static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
	199	{
	200	struct mxs_ssp *ssp = dev_id;
	201	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
	202	__func__, __LINE__,
	203	readl(ssp->base + HW_SSP_CTRL1(ssp)),
	204	readl(ssp->base + HW_SSP_STATUS(ssp)));
	205	return IRQ_HANDLED;
	206	}
	207
	208	static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
	209	unsigned char *buf, int len,
	210	int first, int last, int write)
	211	{
	212	struct mxs_ssp *ssp = &spi->ssp;
010b4818 MV	213	struct dma_async_tx_descriptor *desc = NULL;
	214	const bool vmalloced_buf = is_vmalloc_addr(buf);
	215	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	216	const int sgs = DIV_ROUND_UP(len, desc_len);
474afc04	217	int sg_count;
010b4818 MV	218	int min, ret;
	219	uint32_t ctrl0;
	220	struct page *vm_page;
	221	void *sg_buf;
	222	struct {
	223	uint32_t pio[4];
	224	struct scatterlist sg;
	225	} *dma_xfer;
	226
	227	if (!len)
474afc04	228	return -EINVAL;
010b4818 MV	229
	230	dma_xfer = kzalloc(sizeof(dma_xfer) sgs, GFP_KERNEL);
	231	if (!dma_xfer)
	232	return -ENOMEM;
474afc04	233
41682e03	234	INIT_COMPLETION(spi->c);
474afc04	235
010b4818	236	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
ba486a2a	237	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818 MV	238	ctrl0 \|= BM_SSP_CTRL0_DATA_XFER \| mxs_spi_cs_to_reg(cs);
010b4818 MV	239
474afc04	240	if (*first)
010b4818	241	ctrl0 \|= BM_SSP_CTRL0_LOCK_CS;
474afc04	242	if (!write)
010b4818	243	ctrl0 \|= BM_SSP_CTRL0_READ;
474afc04 MV	244
474afc04 MV	245	/* Queue the DMA data transfer. */
010b4818 MV	246	for (sg_count = 0; sg_count < sgs; sg_count++) {
	247	min = min(len, desc_len);
	248
	249	/* Prepare the transfer descriptor. */
	250	if ((sg_count + 1 == sgs) && *last)
	251	ctrl0 \|= BM_SSP_CTRL0_IGNORE_CRC;
	252
ba486a2a JL	253	if (ssp->devid == IMX23_SSP) {
ba486a2a JL	254	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818	255	ctrl0 \|= min;
ba486a2a	256	}
010b4818 MV	257
	258	dma_xfer[sg_count].pio[0] = ctrl0;
	259	dma_xfer[sg_count].pio[3] = min;
	260
	261	if (vmalloced_buf) {
	262	vm_page = vmalloc_to_page(buf);
	263	if (!vm_page) {
	264	ret = -ENOMEM;
	265	goto err_vmalloc;
	266	}
	267	sg_buf = page_address(vm_page) +
	268	((size_t)buf & ~PAGE_MASK);
	269	} else {
	270	sg_buf = buf;
	271	}
	272
	273	sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
	274	ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
	275	write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	276
	277	len -= min;
	278	buf += min;
	279
	280	/* Queue the PIO register write transfer. */
	281	desc = dmaengine_prep_slave_sg(ssp->dmach,
	282	(struct scatterlist *)dma_xfer[sg_count].pio,
	283	(ssp->devid == IMX23_SSP) ? 1 : 4,
	284	DMA_TRANS_NONE,
	285	sg_count ? DMA_PREP_INTERRUPT : 0);
	286	if (!desc) {
	287	dev_err(ssp->dev,
	288	"Failed to get PIO reg. write descriptor.\n");
	289	ret = -EINVAL;
	290	goto err_mapped;
	291	}
	292
	293	desc = dmaengine_prep_slave_sg(ssp->dmach,
	294	&dma_xfer[sg_count].sg, 1,
	295	write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
	296	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	297
	298	if (!desc) {
	299	dev_err(ssp->dev,
	300	"Failed to get DMA data write descriptor.\n");
	301	ret = -EINVAL;
	302	goto err_mapped;
	303	}
474afc04 MV	304	}
	305
	306	/*
	307	* The last descriptor must have this callback,
	308	* to finish the DMA transaction.
	309	*/
	310	desc->callback = mxs_ssp_dma_irq_callback;
	311	desc->callback_param = spi;
	312
	313	/* Start the transfer. */
	314	dmaengine_submit(desc);
	315	dma_async_issue_pending(ssp->dmach);
	316
	317	ret = wait_for_completion_timeout(&spi->c,
	318	msecs_to_jiffies(SSP_TIMEOUT));
474afc04 MV	319	if (!ret) {
	320	dev_err(ssp->dev, "DMA transfer timeout\n");
	321	ret = -ETIMEDOUT;
44968466	322	dmaengine_terminate_all(ssp->dmach);
010b4818	323	goto err_vmalloc;
474afc04 MV	324	}
	325
	326	ret = 0;
	327
010b4818 MV	328	err_vmalloc:
	329	while (--sg_count >= 0) {
	330	err_mapped:
	331	dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
474afc04 MV	332	write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	333	}
	334
010b4818 MV	335	kfree(dma_xfer);
010b4818 MV	336
474afc04 MV	337	return ret;
	338	}
	339
646781d3 MV	340	static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
	341	unsigned char *buf, int len,
	342	int first, int last, int write)
	343	{
	344	struct mxs_ssp *ssp = &spi->ssp;
	345
	346	if (*first)
	347	mxs_spi_enable(spi);
	348
	349	mxs_spi_set_cs(spi, cs);
	350
	351	while (len--) {
	352	if (*last && len == 0)
	353	mxs_spi_disable(spi);
	354
	355	if (ssp->devid == IMX23_SSP) {
	356	writel(BM_SSP_CTRL0_XFER_COUNT,
	357	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	358	writel(1,
	359	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	360	} else {
	361	writel(1, ssp->base + HW_SSP_XFER_SIZE);
	362	}
	363
	364	if (write)
	365	writel(BM_SSP_CTRL0_READ,
	366	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	367	else
	368	writel(BM_SSP_CTRL0_READ,
	369	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	370
	371	writel(BM_SSP_CTRL0_RUN,
	372	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	373
	374	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
	375	return -ETIMEDOUT;
	376
	377	if (write)
	378	writel(*buf, ssp->base + HW_SSP_DATA(ssp));
	379
	380	writel(BM_SSP_CTRL0_DATA_XFER,
	381	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	382
	383	if (!write) {
	384	if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
	385	BM_SSP_STATUS_FIFO_EMPTY, 0))
	386	return -ETIMEDOUT;
	387
	388	*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
	389	}
	390
	391	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
	392	return -ETIMEDOUT;
	393
	394	buf++;
	395	}
	396
	397	if (len <= 0)
	398	return 0;
	399
	400	return -ETIMEDOUT;
	401	}
	402
	403	static int mxs_spi_transfer_one(struct spi_master *master,
404	struct spi_message *m)
405	{
406	struct mxs_spi *spi = spi_master_get_devdata(master);
407	struct mxs_ssp *ssp = &spi->ssp;
408	int first, last;
409	struct spi_transfer t, tmp_t;
410	int status = 0;
411	int cs;
412
413	first = last = 0;
414
415	cs = m->spi->chip_select;
416
417	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
418
419	status = mxs_spi_setup_transfer(m->spi, t);
420	if (status)
421	break;
422
423	if (&t->transfer_list == m->transfers.next)
424	first = 1;
425	if (&t->transfer_list == m->transfers.prev)
426	last = 1;
474afc04	427	if ((t->rx_buf && t->tx_buf) \|\| (t->rx_dma && t->tx_dma)) {
646781d3 MV	428	dev_err(ssp->dev,
	429	"Cannot send and receive simultaneously\n");
	430	status = -EINVAL;
	431	break;
	432	}
	433
474afc04 MV	434	/*
	435	* Small blocks can be transfered via PIO.
	436	* Measured by empiric means:
	437	*
	438	* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
	439	*
	440	* DMA only: 2.164808 seconds, 473.0KB/s
	441	* Combined: 1.676276 seconds, 610.9KB/s
	442	*/
727c10e3	443	if (t->len < 32) {
474afc04 MV	444	writel(BM_SSP_CTRL1_DMA_ENABLE,
	445	ssp->base + HW_SSP_CTRL1(ssp) +
	446	STMP_OFFSET_REG_CLR);
	447
	448	if (t->tx_buf)
	449	status = mxs_spi_txrx_pio(spi, cs,
	450	(void *)t->tx_buf,
	451	t->len, &first, &last, 1);
	452	if (t->rx_buf)
	453	status = mxs_spi_txrx_pio(spi, cs,
	454	t->rx_buf, t->len,
	455	&first, &last, 0);
	456	} else {
	457	writel(BM_SSP_CTRL1_DMA_ENABLE,
	458	ssp->base + HW_SSP_CTRL1(ssp) +
	459	STMP_OFFSET_REG_SET);
	460
	461	if (t->tx_buf)
	462	status = mxs_spi_txrx_dma(spi, cs,
	463	(void *)t->tx_buf, t->len,
	464	&first, &last, 1);
	465	if (t->rx_buf)
	466	status = mxs_spi_txrx_dma(spi, cs,
	467	t->rx_buf, t->len,
	468	&first, &last, 0);
	469	}
646781d3	470
c895db0f MV	471	if (status) {
c895db0f MV	472	stmp_reset_block(ssp->base);
646781d3	473	break;
c895db0f	474	}
646781d3	475
204e706f	476	m->actual_length += t->len;
646781d3 MV	477	first = last = 0;
	478	}
	479
d856f1eb	480	m->status = status;
646781d3 MV	481	spi_finalize_current_message(master);
	482
	483	return status;
	484	}
	485
	486	static const struct of_device_id mxs_spi_dt_ids[] = {
	487	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	488	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	489	{ /* sentinel */ }
	490	};
	491	MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
	492
fd4a319b	493	static int mxs_spi_probe(struct platform_device *pdev)
646781d3 MV	494	{
	495	const struct of_device_id *of_id =
	496	of_match_device(mxs_spi_dt_ids, &pdev->dev);
	497	struct device_node *np = pdev->dev.of_node;
	498	struct spi_master *master;
	499	struct mxs_spi *spi;
	500	struct mxs_ssp *ssp;
26aafa77	501	struct resource *iores;
646781d3 MV	502	struct clk *clk;
646781d3 MV	503	void __iomem *base;
26aafa77 SG	504	int devid, clk_freq;
26aafa77 SG	505	int ret = 0, irq_err;
646781d3	506
e64d07a2 MV	507	/*
	508	* Default clock speed for the SPI core. 160MHz seems to
	509	* work reasonably well with most SPI flashes, so use this
	510	* as a default. Override with "clock-frequency" DT prop.
	511	*/
	512	const int clk_freq_default = 160000000;
	513
646781d3	514	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474afc04	515	irq_err = platform_get_irq(pdev, 0);
26aafa77	516	if (!iores \|\| irq_err < 0)
646781d3 MV	517	return -EINVAL;
646781d3 MV	518
b0ee5605 TR	519	base = devm_ioremap_resource(&pdev->dev, iores);
	520	if (IS_ERR(base))
	521	return PTR_ERR(base);
646781d3	522
646781d3 MV	523	clk = devm_clk_get(&pdev->dev, NULL);
	524	if (IS_ERR(clk))
	525	return PTR_ERR(clk);
	526
26aafa77 SG	527	devid = (enum mxs_ssp_id) of_id->data;
	528	ret = of_property_read_u32(np, "clock-frequency",
	529	&clk_freq);
	530	if (ret)
e64d07a2	531	clk_freq = clk_freq_default;
646781d3 MV	532
	533	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	534	if (!master)
	535	return -ENOMEM;
	536
	537	master->transfer_one_message = mxs_spi_transfer_one;
	538	master->setup = mxs_spi_setup;
24778be2	539	master->bits_per_word_mask = SPI_BPW_MASK(8);
646781d3 MV	540	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	541	master->num_chipselect = 3;
	542	master->dev.of_node = np;
	543	master->flags = SPI_MASTER_HALF_DUPLEX;
	544
	545	spi = spi_master_get_devdata(master);
	546	ssp = &spi->ssp;
	547	ssp->dev = &pdev->dev;
	548	ssp->clk = clk;
	549	ssp->base = base;
	550	ssp->devid = devid;
474afc04	551
41682e03 MV	552	init_completion(&spi->c);
41682e03 MV	553
474afc04 MV	554	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
	555	DRIVER_NAME, ssp);
	556	if (ret)
	557	goto out_master_free;
	558
26aafa77	559	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
474afc04 MV	560	if (!ssp->dmach) {
474afc04 MV	561	dev_err(ssp->dev, "Failed to request DMA\n");
58ad60bb	562	ret = -ENODEV;
474afc04 MV	563	goto out_master_free;
474afc04 MV	564	}
646781d3 MV	565
646781d3 MV	566	clk_prepare_enable(ssp->clk);
e64d07a2	567	clk_set_rate(ssp->clk, clk_freq);
646781d3 MV	568	ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
	569
	570	stmp_reset_block(ssp->base);
	571
	572	platform_set_drvdata(pdev, master);
	573
	574	ret = spi_register_master(master);
	575	if (ret) {
	576	dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
474afc04	577	goto out_free_dma;
646781d3 MV	578	}
	579
	580	return 0;
	581
474afc04	582	out_free_dma:
474afc04	583	dma_release_channel(ssp->dmach);
646781d3	584	clk_disable_unprepare(ssp->clk);
474afc04	585	out_master_free:
646781d3 MV	586	spi_master_put(master);
	587	return ret;
	588	}
	589
fd4a319b	590	static int mxs_spi_remove(struct platform_device *pdev)
646781d3 MV	591	{
	592	struct spi_master *master;
	593	struct mxs_spi *spi;
	594	struct mxs_ssp *ssp;
	595
7d520d28	596	master = spi_master_get(platform_get_drvdata(pdev));
646781d3 MV	597	spi = spi_master_get_devdata(master);
	598	ssp = &spi->ssp;
	599
	600	spi_unregister_master(master);
	601
474afc04 MV	602	dma_release_channel(ssp->dmach);
474afc04 MV	603
646781d3 MV	604	clk_disable_unprepare(ssp->clk);
	605
	606	spi_master_put(master);
	607
	608	return 0;
	609	}
	610
	611	static struct platform_driver mxs_spi_driver = {
	612	.probe = mxs_spi_probe,
fd4a319b	613	.remove = mxs_spi_remove,
646781d3 MV	614	.driver = {
	615	.name = DRIVER_NAME,
	616	.owner = THIS_MODULE,
	617	.of_match_table = mxs_spi_dt_ids,
	618	},
	619	};
	620
	621	module_platform_driver(mxs_spi_driver);
	622
	623	MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
	624	MODULE_DESCRIPTION("MXS SPI master driver");
	625	MODULE_LICENSE("GPL");
	626	MODULE_ALIAS("platform:mxs-spi");