[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-mxs.c

/*
 * Freescale MXS SPI master driver
 *
 * Copyright 2012 DENX Software Engineering, GmbH.
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * Rework and transition to new API by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on previous attempt by:
 * Fabio Estevam <fabio.estevam@freescale.com>
 *
 * Based on code from U-Boot bootloader by:
 * Marek Vasut <marex@denx.de>
 *
 * Based on spi-stmp.c, which is:
 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/module.h>
#include <linux/stmp_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/mxs-spi.h>

#define DRIVER_NAME		"mxs-spi"

/* Use 10S timeout for very long transfers, it should suffice. */
#define SSP_TIMEOUT		10000

#define SG_MAXLEN		0xff00

/*
 * Flags for txrx functions.  More efficient that using an argument register for
 * each one.
 */
#define TXRX_WRITE		(1<<0)	/* This is a write */
#define TXRX_DEASSERT_CS	(1<<1)	/* De-assert CS at end of txrx */

struct mxs_spi {
	struct mxs_ssp		ssp;
	struct completion	c;
};

static int mxs_spi_setup_transfer(struct spi_device *dev,
				struct spi_transfer *t)
{
	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	struct mxs_ssp *ssp = &spi->ssp;
	uint32_t hz = 0;

	hz = dev->max_speed_hz;
	if (t && t->speed_hz)
		hz = min(hz, t->speed_hz);
	if (hz == 0) {
		dev_err(&dev->dev, "Cannot continue with zero clock\n");
		return -EINVAL;
	}

	mxs_ssp_set_clk_rate(ssp, hz);

	writel(BM_SSP_CTRL0_LOCK_CS,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
		     BF_SSP_CTRL1_WORD_LENGTH
		     (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
		     ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
		     ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
		     ssp->base + HW_SSP_CTRL1(ssp));

	writel(0x0, ssp->base + HW_SSP_CMD0);
	writel(0x0, ssp->base + HW_SSP_CMD1);

	return 0;
}

static int mxs_spi_setup(struct spi_device *dev)
{
	int err = 0;

	if (!dev->bits_per_word)
		dev->bits_per_word = 8;

	if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
		return -EINVAL;

	err = mxs_spi_setup_transfer(dev, NULL);
	if (err) {
		dev_err(&dev->dev,
			"Failed to setup transfer, error = %d\n", err);
	}

	return err;
}

static uint32_t mxs_spi_cs_to_reg(unsigned cs)
{
	uint32_t select = 0;

	/*
	 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	 *
	 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
	 * the datasheet for further details. In SPI mode, they are used to
	 * toggle the chip-select lines (nCS pins).
	 */
	if (cs & 1)
		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
	if (cs & 2)
		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;

	return select;
}

static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
{
	const uint32_t mask =
		BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ;
	uint32_t select;
	struct mxs_ssp *ssp = &spi->ssp;

	writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	select = mxs_spi_cs_to_reg(cs);
	writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
}

static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
{
	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
	struct mxs_ssp *ssp = &spi->ssp;
	uint32_t reg;

	do {
		reg = readl_relaxed(ssp->base + offset);

		if (!set)
			reg = ~reg;

		reg &= mask;

		if (reg == mask)
			return 0;
	} while (time_before(jiffies, timeout));

	return -ETIMEDOUT;
}

static void mxs_ssp_dma_irq_callback(void *param)
{
	struct mxs_spi *spi = param;
	complete(&spi->c);
}

static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
{
	struct mxs_ssp *ssp = dev_id;
	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
		__func__, __LINE__,
		readl(ssp->base + HW_SSP_CTRL1(ssp)),
		readl(ssp->base + HW_SSP_STATUS(ssp)));
	return IRQ_HANDLED;
}

static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;
	struct dma_async_tx_descriptor *desc = NULL;
	const bool vmalloced_buf = is_vmalloc_addr(buf);
	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	const int sgs = DIV_ROUND_UP(len, desc_len);
	int sg_count;
	int min, ret;
	uint32_t ctrl0;
	struct page *vm_page;
	void *sg_buf;
	struct {
		uint32_t		pio[4];
		struct scatterlist	sg;
	} *dma_xfer;

	if (!len)
		return -EINVAL;

	dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
	if (!dma_xfer)
		return -ENOMEM;

	INIT_COMPLETION(spi->c);

	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
		 BM_SSP_CTRL0_READ);
	ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs);

	if (!(flags & TXRX_WRITE))
		ctrl0 |= BM_SSP_CTRL0_READ;

	/* Queue the DMA data transfer. */
	for (sg_count = 0; sg_count < sgs; sg_count++) {
		/* Prepare the transfer descriptor. */
		min = min(len, desc_len);

		/*
		 * De-assert CS on last segment if flag is set (i.e., no more
		 * transfers will follow)
		 */
		if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
			ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;

		if (ssp->devid == IMX23_SSP) {
			ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
			ctrl0 |= min;
		}

		dma_xfer[sg_count].pio[0] = ctrl0;
		dma_xfer[sg_count].pio[3] = min;

		if (vmalloced_buf) {
			vm_page = vmalloc_to_page(buf);
			if (!vm_page) {
				ret = -ENOMEM;
				goto err_vmalloc;
			}
			sg_buf = page_address(vm_page) +
				((size_t)buf & ~PAGE_MASK);
		} else {
			sg_buf = buf;
		}

		sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);

		len -= min;
		buf += min;

		/* Queue the PIO register write transfer. */
		desc = dmaengine_prep_slave_sg(ssp->dmach,
				(struct scatterlist *)dma_xfer[sg_count].pio,
				(ssp->devid == IMX23_SSP) ? 1 : 4,
				DMA_TRANS_NONE,
				sg_count ? DMA_PREP_INTERRUPT : 0);
		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get PIO reg. write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}

		desc = dmaengine_prep_slave_sg(ssp->dmach,
				&dma_xfer[sg_count].sg, 1,
				(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get DMA data write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}
	}

	/*
	 * The last descriptor must have this callback,
	 * to finish the DMA transaction.
	 */
	desc->callback = mxs_ssp_dma_irq_callback;
	desc->callback_param = spi;

	/* Start the transfer. */
	dmaengine_submit(desc);
	dma_async_issue_pending(ssp->dmach);

	ret = wait_for_completion_timeout(&spi->c,
				msecs_to_jiffies(SSP_TIMEOUT));
	if (!ret) {
		dev_err(ssp->dev, "DMA transfer timeout\n");
		ret = -ETIMEDOUT;
		dmaengine_terminate_all(ssp->dmach);
		goto err_vmalloc;
	}

	ret = 0;

err_vmalloc:
	while (--sg_count >= 0) {
err_mapped:
		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	}

	kfree(dma_xfer);

	return ret;
}

static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;

	writel(BM_SSP_CTRL0_IGNORE_CRC,
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);

	mxs_spi_set_cs(spi, cs);

	while (len--) {
		if (len == 0 && (flags & TXRX_DEASSERT_CS))
			writel(BM_SSP_CTRL0_IGNORE_CRC,
			       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (ssp->devid == IMX23_SSP) {
			writel(BM_SSP_CTRL0_XFER_COUNT,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
			writel(1,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
		} else {
			writel(1, ssp->base + HW_SSP_XFER_SIZE);
		}

		if (flags & TXRX_WRITE)
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
		else
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		writel(BM_SSP_CTRL0_RUN,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
			return -ETIMEDOUT;

		if (flags & TXRX_WRITE)
			writel(*buf, ssp->base + HW_SSP_DATA(ssp));

		writel(BM_SSP_CTRL0_DATA_XFER,
			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (!(flags & TXRX_WRITE)) {
			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
						BM_SSP_STATUS_FIFO_EMPTY, 0))
				return -ETIMEDOUT;

			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
		}

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
			return -ETIMEDOUT;

		buf++;
	}

	if (len <= 0)
		return 0;

	return -ETIMEDOUT;
}

static int mxs_spi_transfer_one(struct spi_master *master,
				struct spi_message *m)
{
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	struct spi_transfer *t, *tmp_t;
	unsigned int flag;
	int status = 0;
	int cs;

	cs = m->spi->chip_select;

	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {

		status = mxs_spi_setup_transfer(m->spi, t);
		if (status)
			break;

		/* De-assert on last transfer, inverted by cs_change flag */
		flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
		       TXRX_DEASSERT_CS : 0;
		if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) {
			dev_err(ssp->dev,
				"Cannot send and receive simultaneously\n");
			status = -EINVAL;
			break;
		}

		/*
		 * Small blocks can be transfered via PIO.
		 * Measured by empiric means:
		 *
		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
		 *
		 * DMA only: 2.164808 seconds, 473.0KB/s
		 * Combined: 1.676276 seconds, 610.9KB/s
		 */
		if (t->len < 32) {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_CLR);

			if (t->tx_buf)
				status = mxs_spi_txrx_pio(spi, cs,
						(void *)t->tx_buf,
						t->len, flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_pio(spi, cs,
						t->rx_buf, t->len,
						flag);
		} else {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_SET);

			if (t->tx_buf)
				status = mxs_spi_txrx_dma(spi, cs,
						(void *)t->tx_buf, t->len,
						flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_dma(spi, cs,
						t->rx_buf, t->len,
						flag);
		}

		if (status) {
			stmp_reset_block(ssp->base);
			break;
		}

		m->actual_length += t->len;
	}

	m->status = status;
	spi_finalize_current_message(master);

	return status;
}

static const struct of_device_id mxs_spi_dt_ids[] = {
	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);

static int mxs_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_spi_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;
	struct resource *iores;
	struct clk *clk;
	void __iomem *base;
	int devid, clk_freq;
	int ret = 0, irq_err;

	/*
	 * Default clock speed for the SPI core. 160MHz seems to
	 * work reasonably well with most SPI flashes, so use this
	 * as a default. Override with "clock-frequency" DT prop.
	 */
	const int clk_freq_default = 160000000;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq_err = platform_get_irq(pdev, 0);
	if (irq_err < 0)
		return -EINVAL;

	base = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	devid = (enum mxs_ssp_id) of_id->data;
	ret = of_property_read_u32(np, "clock-frequency",
				   &clk_freq);
	if (ret)
		clk_freq = clk_freq_default;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (!master)
		return -ENOMEM;

	master->transfer_one_message = mxs_spi_transfer_one;
	master->setup = mxs_spi_setup;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->num_chipselect = 3;
	master->dev.of_node = np;
	master->flags = SPI_MASTER_HALF_DUPLEX;

	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;
	ssp->dev = &pdev->dev;
	ssp->clk = clk;
	ssp->base = base;
	ssp->devid = devid;

	init_completion(&spi->c);

	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
			       DRIVER_NAME, ssp);
	if (ret)
		goto out_master_free;

	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
	if (!ssp->dmach) {
		dev_err(ssp->dev, "Failed to request DMA\n");
		ret = -ENODEV;
		goto out_master_free;
	}

	ret = clk_prepare_enable(ssp->clk);
	if (ret)
		goto out_dma_release;

	clk_set_rate(ssp->clk, clk_freq);
	ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;

	ret = stmp_reset_block(ssp->base);
	if (ret)
		goto out_disable_clk;

	platform_set_drvdata(pdev, master);

	ret = spi_register_master(master);
	if (ret) {
		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
		goto out_disable_clk;
	}

	return 0;

out_disable_clk:
	clk_disable_unprepare(ssp->clk);
out_dma_release:
	dma_release_channel(ssp->dmach);
out_master_free:
	spi_master_put(master);
	return ret;
}

static int mxs_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;

	master = spi_master_get(platform_get_drvdata(pdev));
	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;

	spi_unregister_master(master);
	clk_disable_unprepare(ssp->clk);
	dma_release_channel(ssp->dmach);
	spi_master_put(master);

	return 0;
}

static struct platform_driver mxs_spi_driver = {
	.probe	= mxs_spi_probe,
	.remove	= mxs_spi_remove,
	.driver	= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = mxs_spi_dt_ids,
	},
};

module_platform_driver(mxs_spi_driver);

MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_DESCRIPTION("MXS SPI master driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mxs-spi");
Commit	Line	Data
646781d3 MV	1	/*
	2	* Freescale MXS SPI master driver
	3	*
	4	* Copyright 2012 DENX Software Engineering, GmbH.
	5	* Copyright 2012 Freescale Semiconductor, Inc.
	6	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
	7	*
	8	* Rework and transition to new API by:
	9	* Marek Vasut <marex@denx.de>
	10	*
	11	* Based on previous attempt by:
	12	* Fabio Estevam <fabio.estevam@freescale.com>
	13	*
	14	* Based on code from U-Boot bootloader by:
	15	* Marek Vasut <marex@denx.de>
	16	*
	17	* Based on spi-stmp.c, which is:
	18	* Author: Dmitry Pervushin <dimka@embeddedalley.com>
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License as published by
	22	* the Free Software Foundation; either version 2 of the License, or
	23	* (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*/
	30
	31	#include <linux/kernel.h>
	32	#include <linux/init.h>
	33	#include <linux/ioport.h>
	34	#include <linux/of.h>
	35	#include <linux/of_device.h>
	36	#include <linux/of_gpio.h>
	37	#include <linux/platform_device.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
	40	#include <linux/dma-mapping.h>
	41	#include <linux/dmaengine.h>
	42	#include <linux/highmem.h>
	43	#include <linux/clk.h>
	44	#include <linux/err.h>
	45	#include <linux/completion.h>
	46	#include <linux/gpio.h>
	47	#include <linux/regulator/consumer.h>
	48	#include <linux/module.h>
646781d3 MV	49	#include <linux/stmp_device.h>
	50	#include <linux/spi/spi.h>
	51	#include <linux/spi/mxs-spi.h>
	52
	53	#define DRIVER_NAME "mxs-spi"
	54
010b4818 MV	55	/* Use 10S timeout for very long transfers, it should suffice. */
010b4818 MV	56	#define SSP_TIMEOUT 10000
646781d3	57
474afc04 MV	58	#define SG_MAXLEN 0xff00
474afc04 MV	59
28cad125 TP	60	/*
	61	* Flags for txrx functions. More efficient that using an argument register for
	62	* each one.
	63	*/
	64	#define TXRX_WRITE (1<<0) /* This is a write */
	65	#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
	66
646781d3 MV	67	struct mxs_spi {
646781d3 MV	68	struct mxs_ssp ssp;
474afc04	69	struct completion c;
646781d3 MV	70	};
	71
	72	static int mxs_spi_setup_transfer(struct spi_device *dev,
	73	struct spi_transfer *t)
	74	{
	75	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	76	struct mxs_ssp *ssp = &spi->ssp;
646781d3 MV	77	uint32_t hz = 0;
646781d3 MV	78
646781d3 MV	79	hz = dev->max_speed_hz;
	80	if (t && t->speed_hz)
	81	hz = min(hz, t->speed_hz);
	82	if (hz == 0) {
	83	dev_err(&dev->dev, "Cannot continue with zero clock\n");
	84	return -EINVAL;
	85	}
	86
	87	mxs_ssp_set_clk_rate(ssp, hz);
	88
58f46e41 TP	89	writel(BM_SSP_CTRL0_LOCK_CS,
58f46e41 TP	90	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	91	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) \|
	92	BF_SSP_CTRL1_WORD_LENGTH
	93	(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) \|
	94	((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) \|
	95	((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	96	ssp->base + HW_SSP_CTRL1(ssp));
	97
	98	writel(0x0, ssp->base + HW_SSP_CMD0);
	99	writel(0x0, ssp->base + HW_SSP_CMD1);
	100
	101	return 0;
	102	}
	103
	104	static int mxs_spi_setup(struct spi_device *dev)
	105	{
	106	int err = 0;
	107
	108	if (!dev->bits_per_word)
	109	dev->bits_per_word = 8;
	110
	111	if (dev->mode & ~(SPI_CPOL \| SPI_CPHA))
	112	return -EINVAL;
	113
	114	err = mxs_spi_setup_transfer(dev, NULL);
	115	if (err) {
	116	dev_err(&dev->dev,
	117	"Failed to setup transfer, error = %d\n", err);
	118	}
	119
	120	return err;
	121	}
	122
	123	static uint32_t mxs_spi_cs_to_reg(unsigned cs)
	124	{
	125	uint32_t select = 0;
	126
	127	/*
	128	* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	129	*
	130	* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	131	* in HW_SSP_CTRL0 register do have multiple usage, please refer to
	132	* the datasheet for further details. In SPI mode, they are used to
	133	* toggle the chip-select lines (nCS pins).
	134	*/
	135	if (cs & 1)
	136	select \|= BM_SSP_CTRL0_WAIT_FOR_CMD;
	137	if (cs & 2)
	138	select \|= BM_SSP_CTRL0_WAIT_FOR_IRQ;
	139
	140	return select;
	141	}
	142
	143	static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
	144	{
	145	const uint32_t mask =
	146	BM_SSP_CTRL0_WAIT_FOR_CMD \| BM_SSP_CTRL0_WAIT_FOR_IRQ;
	147	uint32_t select;
	148	struct mxs_ssp *ssp = &spi->ssp;
	149
	150	writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	151	select = mxs_spi_cs_to_reg(cs);
	152	writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	153	}
	154
646781d3 MV	155	static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
646781d3 MV	156	{
f13639dc	157	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
646781d3 MV	158	struct mxs_ssp *ssp = &spi->ssp;
	159	uint32_t reg;
	160
f13639dc	161	do {
646781d3 MV	162	reg = readl_relaxed(ssp->base + offset);
646781d3 MV	163
f13639dc MV	164	if (!set)
f13639dc MV	165	reg = ~reg;
646781d3	166
f13639dc	167	reg &= mask;
646781d3	168
f13639dc MV	169	if (reg == mask)
	170	return 0;
	171	} while (time_before(jiffies, timeout));
646781d3	172
f13639dc	173	return -ETIMEDOUT;
646781d3 MV	174	}
646781d3 MV	175
474afc04 MV	176	static void mxs_ssp_dma_irq_callback(void *param)
	177	{
	178	struct mxs_spi *spi = param;
	179	complete(&spi->c);
	180	}
	181
	182	static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
	183	{
	184	struct mxs_ssp *ssp = dev_id;
	185	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
	186	__func__, __LINE__,
	187	readl(ssp->base + HW_SSP_CTRL1(ssp)),
	188	readl(ssp->base + HW_SSP_STATUS(ssp)));
	189	return IRQ_HANDLED;
	190	}
	191
	192	static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
	193	unsigned char *buf, int len,
28cad125	194	unsigned int flags)
474afc04 MV	195	{
474afc04 MV	196	struct mxs_ssp *ssp = &spi->ssp;
010b4818 MV	197	struct dma_async_tx_descriptor *desc = NULL;
	198	const bool vmalloced_buf = is_vmalloc_addr(buf);
	199	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	200	const int sgs = DIV_ROUND_UP(len, desc_len);
474afc04	201	int sg_count;
010b4818 MV	202	int min, ret;
	203	uint32_t ctrl0;
	204	struct page *vm_page;
	205	void *sg_buf;
	206	struct {
	207	uint32_t pio[4];
	208	struct scatterlist sg;
	209	} *dma_xfer;
	210
	211	if (!len)
474afc04	212	return -EINVAL;
010b4818 MV	213
	214	dma_xfer = kzalloc(sizeof(dma_xfer) sgs, GFP_KERNEL);
	215	if (!dma_xfer)
	216	return -ENOMEM;
474afc04	217
41682e03	218	INIT_COMPLETION(spi->c);
474afc04	219
010b4818	220	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
df23286e TP	221	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT \| BM_SSP_CTRL0_IGNORE_CRC \|
df23286e TP	222	BM_SSP_CTRL0_READ);
010b4818 MV	223	ctrl0 \|= BM_SSP_CTRL0_DATA_XFER \| mxs_spi_cs_to_reg(cs);
010b4818 MV	224
28cad125	225	if (!(flags & TXRX_WRITE))
010b4818	226	ctrl0 \|= BM_SSP_CTRL0_READ;
474afc04 MV	227
474afc04 MV	228	/* Queue the DMA data transfer. */
010b4818	229	for (sg_count = 0; sg_count < sgs; sg_count++) {
28cad125	230	/* Prepare the transfer descriptor. */
010b4818 MV	231	min = min(len, desc_len);
010b4818 MV	232
28cad125 TP	233	/*
	234	* De-assert CS on last segment if flag is set (i.e., no more
	235	* transfers will follow)
	236	*/
	237	if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
010b4818 MV	238	ctrl0 \|= BM_SSP_CTRL0_IGNORE_CRC;
010b4818 MV	239
ba486a2a JL	240	if (ssp->devid == IMX23_SSP) {
ba486a2a JL	241	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818	242	ctrl0 \|= min;
ba486a2a	243	}
010b4818 MV	244
	245	dma_xfer[sg_count].pio[0] = ctrl0;
	246	dma_xfer[sg_count].pio[3] = min;
	247
	248	if (vmalloced_buf) {
	249	vm_page = vmalloc_to_page(buf);
	250	if (!vm_page) {
	251	ret = -ENOMEM;
	252	goto err_vmalloc;
	253	}
	254	sg_buf = page_address(vm_page) +
	255	((size_t)buf & ~PAGE_MASK);
	256	} else {
	257	sg_buf = buf;
	258	}
	259
	260	sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
	261	ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	262	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
010b4818 MV	263
	264	len -= min;
	265	buf += min;
	266
	267	/* Queue the PIO register write transfer. */
	268	desc = dmaengine_prep_slave_sg(ssp->dmach,
	269	(struct scatterlist *)dma_xfer[sg_count].pio,
	270	(ssp->devid == IMX23_SSP) ? 1 : 4,
	271	DMA_TRANS_NONE,
	272	sg_count ? DMA_PREP_INTERRUPT : 0);
	273	if (!desc) {
	274	dev_err(ssp->dev,
	275	"Failed to get PIO reg. write descriptor.\n");
	276	ret = -EINVAL;
	277	goto err_mapped;
	278	}
	279
	280	desc = dmaengine_prep_slave_sg(ssp->dmach,
	281	&dma_xfer[sg_count].sg, 1,
28cad125	282	(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
010b4818 MV	283	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	284
	285	if (!desc) {
	286	dev_err(ssp->dev,
	287	"Failed to get DMA data write descriptor.\n");
	288	ret = -EINVAL;
	289	goto err_mapped;
	290	}
474afc04 MV	291	}
	292
	293	/*
	294	* The last descriptor must have this callback,
	295	* to finish the DMA transaction.
	296	*/
	297	desc->callback = mxs_ssp_dma_irq_callback;
	298	desc->callback_param = spi;
	299
	300	/* Start the transfer. */
	301	dmaengine_submit(desc);
	302	dma_async_issue_pending(ssp->dmach);
	303
	304	ret = wait_for_completion_timeout(&spi->c,
	305	msecs_to_jiffies(SSP_TIMEOUT));
474afc04 MV	306	if (!ret) {
	307	dev_err(ssp->dev, "DMA transfer timeout\n");
	308	ret = -ETIMEDOUT;
44968466	309	dmaengine_terminate_all(ssp->dmach);
010b4818	310	goto err_vmalloc;
474afc04 MV	311	}
	312
	313	ret = 0;
	314
010b4818 MV	315	err_vmalloc:
	316	while (--sg_count >= 0) {
	317	err_mapped:
	318	dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	319	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
474afc04 MV	320	}
474afc04 MV	321
010b4818 MV	322	kfree(dma_xfer);
010b4818 MV	323
474afc04 MV	324	return ret;
	325	}
	326
646781d3 MV	327	static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
646781d3 MV	328	unsigned char *buf, int len,
28cad125	329	unsigned int flags)
646781d3 MV	330	{
	331	struct mxs_ssp *ssp = &spi->ssp;
	332
75e73fa2 TP	333	writel(BM_SSP_CTRL0_IGNORE_CRC,
75e73fa2 TP	334	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
646781d3 MV	335
	336	mxs_spi_set_cs(spi, cs);
	337
	338	while (len--) {
28cad125	339	if (len == 0 && (flags & TXRX_DEASSERT_CS))
f5bc7384 TP	340	writel(BM_SSP_CTRL0_IGNORE_CRC,
f5bc7384 TP	341	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	342
	343	if (ssp->devid == IMX23_SSP) {
	344	writel(BM_SSP_CTRL0_XFER_COUNT,
	345	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	346	writel(1,
	347	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	348	} else {
	349	writel(1, ssp->base + HW_SSP_XFER_SIZE);
	350	}
	351
28cad125	352	if (flags & TXRX_WRITE)
646781d3 MV	353	writel(BM_SSP_CTRL0_READ,
	354	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	355	else
	356	writel(BM_SSP_CTRL0_READ,
	357	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	358
	359	writel(BM_SSP_CTRL0_RUN,
	360	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	361
	362	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
	363	return -ETIMEDOUT;
	364
28cad125	365	if (flags & TXRX_WRITE)
646781d3 MV	366	writel(*buf, ssp->base + HW_SSP_DATA(ssp));
	367
	368	writel(BM_SSP_CTRL0_DATA_XFER,
	369	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	370
28cad125	371	if (!(flags & TXRX_WRITE)) {
646781d3 MV	372	if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
	373	BM_SSP_STATUS_FIFO_EMPTY, 0))
	374	return -ETIMEDOUT;
	375
	376	*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
	377	}
	378
	379	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
	380	return -ETIMEDOUT;
	381
	382	buf++;
	383	}
	384
	385	if (len <= 0)
	386	return 0;
	387
	388	return -ETIMEDOUT;
	389	}
	390
	391	static int mxs_spi_transfer_one(struct spi_master *master,
	392	struct spi_message *m)
	393	{
	394	struct mxs_spi *spi = spi_master_get_devdata(master);
	395	struct mxs_ssp *ssp = &spi->ssp;
646781d3	396	struct spi_transfer t, tmp_t;
28cad125	397	unsigned int flag;
646781d3 MV	398	int status = 0;
	399	int cs;
	400
646781d3 MV	401	cs = m->spi->chip_select;
	402
	403	list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
	404
	405	status = mxs_spi_setup_transfer(m->spi, t);
	406	if (status)
	407	break;
	408
28cad125 TP	409	/* De-assert on last transfer, inverted by cs_change flag */
	410	flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
	411	TXRX_DEASSERT_CS : 0;
474afc04	412	if ((t->rx_buf && t->tx_buf) \|\| (t->rx_dma && t->tx_dma)) {
646781d3 MV	413	dev_err(ssp->dev,
	414	"Cannot send and receive simultaneously\n");
	415	status = -EINVAL;
	416	break;
	417	}
	418
474afc04 MV	419	/*
	420	* Small blocks can be transfered via PIO.
	421	* Measured by empiric means:
	422	*
	423	* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
	424	*
	425	* DMA only: 2.164808 seconds, 473.0KB/s
	426	* Combined: 1.676276 seconds, 610.9KB/s
	427	*/
727c10e3	428	if (t->len < 32) {
474afc04 MV	429	writel(BM_SSP_CTRL1_DMA_ENABLE,
	430	ssp->base + HW_SSP_CTRL1(ssp) +
	431	STMP_OFFSET_REG_CLR);
	432
	433	if (t->tx_buf)
	434	status = mxs_spi_txrx_pio(spi, cs,
	435	(void *)t->tx_buf,
28cad125	436	t->len, flag \| TXRX_WRITE);
474afc04 MV	437	if (t->rx_buf)
	438	status = mxs_spi_txrx_pio(spi, cs,
	439	t->rx_buf, t->len,
28cad125	440	flag);
474afc04 MV	441	} else {
	442	writel(BM_SSP_CTRL1_DMA_ENABLE,
	443	ssp->base + HW_SSP_CTRL1(ssp) +
	444	STMP_OFFSET_REG_SET);
	445
	446	if (t->tx_buf)
	447	status = mxs_spi_txrx_dma(spi, cs,
	448	(void *)t->tx_buf, t->len,
28cad125	449	flag \| TXRX_WRITE);
474afc04 MV	450	if (t->rx_buf)
	451	status = mxs_spi_txrx_dma(spi, cs,
	452	t->rx_buf, t->len,
28cad125	453	flag);
474afc04	454	}
646781d3	455
c895db0f MV	456	if (status) {
c895db0f MV	457	stmp_reset_block(ssp->base);
646781d3	458	break;
c895db0f	459	}
646781d3	460
204e706f	461	m->actual_length += t->len;
646781d3 MV	462	}
646781d3 MV	463
d856f1eb	464	m->status = status;
646781d3 MV	465	spi_finalize_current_message(master);
	466
	467	return status;
	468	}
	469
	470	static const struct of_device_id mxs_spi_dt_ids[] = {
	471	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	472	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	473	{ /* sentinel */ }
	474	};
	475	MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
	476
fd4a319b	477	static int mxs_spi_probe(struct platform_device *pdev)
646781d3 MV	478	{
	479	const struct of_device_id *of_id =
	480	of_match_device(mxs_spi_dt_ids, &pdev->dev);
	481	struct device_node *np = pdev->dev.of_node;
	482	struct spi_master *master;
	483	struct mxs_spi *spi;
	484	struct mxs_ssp *ssp;
26aafa77	485	struct resource *iores;
646781d3 MV	486	struct clk *clk;
646781d3 MV	487	void __iomem *base;
26aafa77 SG	488	int devid, clk_freq;
26aafa77 SG	489	int ret = 0, irq_err;
646781d3	490
e64d07a2 MV	491	/*
	492	* Default clock speed for the SPI core. 160MHz seems to
	493	* work reasonably well with most SPI flashes, so use this
	494	* as a default. Override with "clock-frequency" DT prop.
	495	*/
	496	const int clk_freq_default = 160000000;
	497
646781d3	498	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474afc04	499	irq_err = platform_get_irq(pdev, 0);
796305a2	500	if (irq_err < 0)
646781d3 MV	501	return -EINVAL;
646781d3 MV	502
b0ee5605 TR	503	base = devm_ioremap_resource(&pdev->dev, iores);
	504	if (IS_ERR(base))
	505	return PTR_ERR(base);
646781d3	506
646781d3 MV	507	clk = devm_clk_get(&pdev->dev, NULL);
	508	if (IS_ERR(clk))
	509	return PTR_ERR(clk);
	510
26aafa77 SG	511	devid = (enum mxs_ssp_id) of_id->data;
	512	ret = of_property_read_u32(np, "clock-frequency",
	513	&clk_freq);
	514	if (ret)
e64d07a2	515	clk_freq = clk_freq_default;
646781d3 MV	516
	517	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	518	if (!master)
	519	return -ENOMEM;
	520
	521	master->transfer_one_message = mxs_spi_transfer_one;
	522	master->setup = mxs_spi_setup;
24778be2	523	master->bits_per_word_mask = SPI_BPW_MASK(8);
646781d3 MV	524	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	525	master->num_chipselect = 3;
	526	master->dev.of_node = np;
	527	master->flags = SPI_MASTER_HALF_DUPLEX;
	528
	529	spi = spi_master_get_devdata(master);
	530	ssp = &spi->ssp;
	531	ssp->dev = &pdev->dev;
	532	ssp->clk = clk;
	533	ssp->base = base;
	534	ssp->devid = devid;
474afc04	535
41682e03 MV	536	init_completion(&spi->c);
41682e03 MV	537
474afc04 MV	538	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
	539	DRIVER_NAME, ssp);
	540	if (ret)
	541	goto out_master_free;
	542
26aafa77	543	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
474afc04 MV	544	if (!ssp->dmach) {
474afc04 MV	545	dev_err(ssp->dev, "Failed to request DMA\n");
58ad60bb	546	ret = -ENODEV;
474afc04 MV	547	goto out_master_free;
474afc04 MV	548	}
646781d3	549
9c4a39af FE	550	ret = clk_prepare_enable(ssp->clk);
	551	if (ret)
	552	goto out_dma_release;
	553
e64d07a2	554	clk_set_rate(ssp->clk, clk_freq);
646781d3 MV	555	ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
646781d3 MV	556
8498bce9 FE	557	ret = stmp_reset_block(ssp->base);
	558	if (ret)
	559	goto out_disable_clk;
646781d3 MV	560
	561	platform_set_drvdata(pdev, master);
	562
	563	ret = spi_register_master(master);
	564	if (ret) {
	565	dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
9c4a39af	566	goto out_disable_clk;
646781d3 MV	567	}
	568
	569	return 0;
	570
9c4a39af	571	out_disable_clk:
646781d3	572	clk_disable_unprepare(ssp->clk);
9c4a39af	573	out_dma_release:
e11933f6	574	dma_release_channel(ssp->dmach);
474afc04	575	out_master_free:
646781d3 MV	576	spi_master_put(master);
	577	return ret;
	578	}
	579
fd4a319b	580	static int mxs_spi_remove(struct platform_device *pdev)
646781d3 MV	581	{
	582	struct spi_master *master;
	583	struct mxs_spi *spi;
	584	struct mxs_ssp *ssp;
	585
7d520d28	586	master = spi_master_get(platform_get_drvdata(pdev));
646781d3 MV	587	spi = spi_master_get_devdata(master);
	588	ssp = &spi->ssp;
	589
	590	spi_unregister_master(master);
646781d3	591	clk_disable_unprepare(ssp->clk);
e11933f6	592	dma_release_channel(ssp->dmach);
646781d3 MV	593	spi_master_put(master);
	594
	595	return 0;
	596	}
	597
	598	static struct platform_driver mxs_spi_driver = {
	599	.probe = mxs_spi_probe,
fd4a319b	600	.remove = mxs_spi_remove,
646781d3 MV	601	.driver = {
	602	.name = DRIVER_NAME,
	603	.owner = THIS_MODULE,
	604	.of_match_table = mxs_spi_dt_ids,
	605	},
	606	};
	607
	608	module_platform_driver(mxs_spi_driver);
	609
	610	MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
	611	MODULE_DESCRIPTION("MXS SPI master driver");
	612	MODULE_LICENSE("GPL");
	613	MODULE_ALIAS("platform:mxs-spi");