[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-octeon.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2011, 2012 Cavium, Inc.
 */

#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>

#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-mpi-defs.h>

#define OCTEON_SPI_CFG 0
#define OCTEON_SPI_STS 0x08
#define OCTEON_SPI_TX 0x10
#define OCTEON_SPI_DAT0 0x80

#define OCTEON_SPI_MAX_BYTES 9

#define OCTEON_SPI_MAX_CLOCK_HZ 16000000

struct octeon_spi {
	void __iomem *register_base;
	u64 last_cfg;
	u64 cs_enax;
	int sys_freq;
};

static void octeon_spi_wait_ready(struct octeon_spi *p)
{
	union cvmx_mpi_sts mpi_sts;
	unsigned int loops = 0;

	do {
		if (loops++)
			__delay(500);
		mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS);
	} while (mpi_sts.s.busy);
}

static int octeon_spi_do_transfer(struct octeon_spi *p,
				  struct spi_message *msg,
				  struct spi_transfer *xfer,
				  bool last_xfer)
{
	struct spi_device *spi = msg->spi;
	union cvmx_mpi_cfg mpi_cfg;
	union cvmx_mpi_tx mpi_tx;
	unsigned int clkdiv;
	int mode;
	bool cpha, cpol;
	const u8 *tx_buf;
	u8 *rx_buf;
	int len;
	int i;

	mode = spi->mode;
	cpha = mode & SPI_CPHA;
	cpol = mode & SPI_CPOL;

	clkdiv = p->sys_freq / (2 * xfer->speed_hz);

	mpi_cfg.u64 = 0;

	mpi_cfg.s.clkdiv = clkdiv;
	mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0;
	mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0;
	mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0;
	mpi_cfg.s.idlelo = cpha != cpol;
	mpi_cfg.s.cslate = cpha ? 1 : 0;
	mpi_cfg.s.enable = 1;

	if (spi->chip_select < 4)
		p->cs_enax |= 1ull << (12 + spi->chip_select);
	mpi_cfg.u64 |= p->cs_enax;

	if (mpi_cfg.u64 != p->last_cfg) {
		p->last_cfg = mpi_cfg.u64;
		writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG);
	}
	tx_buf = xfer->tx_buf;
	rx_buf = xfer->rx_buf;
	len = xfer->len;
	while (len > OCTEON_SPI_MAX_BYTES) {
		for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
			u8 d;
			if (tx_buf)
				d = *tx_buf++;
			else
				d = 0;
			writeq(d, p->register_base + OCTEON_SPI_DAT0 + (8 * i));
		}
		mpi_tx.u64 = 0;
		mpi_tx.s.csid = spi->chip_select;
		mpi_tx.s.leavecs = 1;
		mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
		mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
		writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX);

		octeon_spi_wait_ready(p);
		if (rx_buf)
			for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
				u64 v = readq(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
				*rx_buf++ = (u8)v;
			}
		len -= OCTEON_SPI_MAX_BYTES;
	}

	for (i = 0; i < len; i++) {
		u8 d;
		if (tx_buf)
			d = *tx_buf++;
		else
			d = 0;
		writeq(d, p->register_base + OCTEON_SPI_DAT0 + (8 * i));
	}

	mpi_tx.u64 = 0;
	mpi_tx.s.csid = spi->chip_select;
	if (last_xfer)
		mpi_tx.s.leavecs = xfer->cs_change;
	else
		mpi_tx.s.leavecs = !xfer->cs_change;
	mpi_tx.s.txnum = tx_buf ? len : 0;
	mpi_tx.s.totnum = len;
	writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX);

	octeon_spi_wait_ready(p);
	if (rx_buf)
		for (i = 0; i < len; i++) {
			u64 v = readq(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
			*rx_buf++ = (u8)v;
		}

	if (xfer->delay_usecs)
		udelay(xfer->delay_usecs);

	return xfer->len;
}

static int octeon_spi_transfer_one_message(struct spi_master *master,
					   struct spi_message *msg)
{
	struct octeon_spi *p = spi_master_get_devdata(master);
	unsigned int total_len = 0;
	int status = 0;
	struct spi_transfer *xfer;

	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
		bool last_xfer = list_is_last(&xfer->transfer_list,
					      &msg->transfers);
		int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
		if (r < 0) {
			status = r;
			goto err;
		}
		total_len += r;
	}
err:
	msg->status = status;
	msg->actual_length = total_len;
	spi_finalize_current_message(master);
	return status;
}

static int octeon_spi_probe(struct platform_device *pdev)
{
	struct resource *res_mem;
	void __iomem *reg_base;
	struct spi_master *master;
	struct octeon_spi *p;
	int err = -ENOENT;

	master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
	if (!master)
		return -ENOMEM;
	p = spi_master_get_devdata(master);
	platform_set_drvdata(pdev, master);

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
	if (IS_ERR(reg_base)) {
		err = PTR_ERR(reg_base);
		goto fail;
	}

	p->register_base = reg_base;
	p->sys_freq = octeon_get_io_clock_rate();

	master->num_chipselect = 4;
	master->mode_bits = SPI_CPHA |
			    SPI_CPOL |
			    SPI_CS_HIGH |
			    SPI_LSB_FIRST |
			    SPI_3WIRE;

	master->transfer_one_message = octeon_spi_transfer_one_message;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;

	master->dev.of_node = pdev->dev.of_node;
	err = devm_spi_register_master(&pdev->dev, master);
	if (err) {
		dev_err(&pdev->dev, "register master failed: %d\n", err);
		goto fail;
	}

	dev_info(&pdev->dev, "OCTEON SPI bus driver\n");

	return 0;
fail:
	spi_master_put(master);
	return err;
}

static int octeon_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct octeon_spi *p = spi_master_get_devdata(master);

	/* Clear the CSENA* and put everything in a known state. */
	writeq(0, p->register_base + OCTEON_SPI_CFG);

	return 0;
}

static const struct of_device_id octeon_spi_match[] = {
	{ .compatible = "cavium,octeon-3010-spi", },
	{},
};
MODULE_DEVICE_TABLE(of, octeon_spi_match);

static struct platform_driver octeon_spi_driver = {
	.driver = {
		.name		= "spi-octeon",
		.of_match_table = octeon_spi_match,
	},
	.probe		= octeon_spi_probe,
	.remove		= octeon_spi_remove,
};

module_platform_driver(octeon_spi_driver);

MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
MODULE_AUTHOR("David Daney");
MODULE_LICENSE("GPL");
Commit	Line	Data
6b52c00f DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2011, 2012 Cavium, Inc.
	7	*/
	8
	9	#include <linux/platform_device.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/spi/spi.h>
	12	#include <linux/module.h>
	13	#include <linux/delay.h>
6b52c00f DD	14	#include <linux/io.h>
	15	#include <linux/of.h>
	16
	17	#include <asm/octeon/octeon.h>
	18	#include <asm/octeon/cvmx-mpi-defs.h>
	19
	20	#define OCTEON_SPI_CFG 0
	21	#define OCTEON_SPI_STS 0x08
	22	#define OCTEON_SPI_TX 0x10
	23	#define OCTEON_SPI_DAT0 0x80
	24
	25	#define OCTEON_SPI_MAX_BYTES 9
	26
	27	#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
	28
	29	struct octeon_spi {
187fc9b3	30	void __iomem *register_base;
6b52c00f DD	31	u64 last_cfg;
6b52c00f DD	32	u64 cs_enax;
b9e64763	33	int sys_freq;
6b52c00f DD	34	};
6b52c00f DD	35
6b52c00f DD	36	static void octeon_spi_wait_ready(struct octeon_spi *p)
	37	{
	38	union cvmx_mpi_sts mpi_sts;
	39	unsigned int loops = 0;
	40
	41	do {
	42	if (loops++)
	43	__delay(500);
187fc9b3	44	mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS);
6b52c00f DD	45	} while (mpi_sts.s.busy);
	46	}
	47
	48	static int octeon_spi_do_transfer(struct octeon_spi *p,
	49	struct spi_message *msg,
	50	struct spi_transfer *xfer,
	51	bool last_xfer)
	52	{
85fe414d	53	struct spi_device *spi = msg->spi;
6b52c00f DD	54	union cvmx_mpi_cfg mpi_cfg;
	55	union cvmx_mpi_tx mpi_tx;
	56	unsigned int clkdiv;
6b52c00f DD	57	int mode;
6b52c00f DD	58	bool cpha, cpol;
6b52c00f DD	59	const u8 *tx_buf;
	60	u8 *rx_buf;
	61	int len;
	62	int i;
	63
85fe414d	64	mode = spi->mode;
6b52c00f DD	65	cpha = mode & SPI_CPHA;
6b52c00f DD	66	cpol = mode & SPI_CPOL;
6b52c00f	67
b9e64763	68	clkdiv = p->sys_freq / (2 * xfer->speed_hz);
6b52c00f DD	69
	70	mpi_cfg.u64 = 0;
	71
	72	mpi_cfg.s.clkdiv = clkdiv;
	73	mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0;
	74	mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0;
	75	mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0;
	76	mpi_cfg.s.idlelo = cpha != cpol;
	77	mpi_cfg.s.cslate = cpha ? 1 : 0;
	78	mpi_cfg.s.enable = 1;
	79
85fe414d AL	80	if (spi->chip_select < 4)
85fe414d AL	81	p->cs_enax \|= 1ull << (12 + spi->chip_select);
6b52c00f DD	82	mpi_cfg.u64 \|= p->cs_enax;
	83
	84	if (mpi_cfg.u64 != p->last_cfg) {
	85	p->last_cfg = mpi_cfg.u64;
187fc9b3	86	writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG);
6b52c00f DD	87	}
	88	tx_buf = xfer->tx_buf;
	89	rx_buf = xfer->rx_buf;
	90	len = xfer->len;
	91	while (len > OCTEON_SPI_MAX_BYTES) {
	92	for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
	93	u8 d;
	94	if (tx_buf)
	95	d = *tx_buf++;
	96	else
	97	d = 0;
187fc9b3	98	writeq(d, p->register_base + OCTEON_SPI_DAT0 + (8 * i));
6b52c00f DD	99	}
6b52c00f DD	100	mpi_tx.u64 = 0;
85fe414d	101	mpi_tx.s.csid = spi->chip_select;
6b52c00f DD	102	mpi_tx.s.leavecs = 1;
	103	mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
	104	mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
187fc9b3	105	writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX);
6b52c00f DD	106
	107	octeon_spi_wait_ready(p);
	108	if (rx_buf)
	109	for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
187fc9b3	110	u64 v = readq(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
6b52c00f DD	111	*rx_buf++ = (u8)v;
	112	}
	113	len -= OCTEON_SPI_MAX_BYTES;
	114	}
	115
	116	for (i = 0; i < len; i++) {
	117	u8 d;
	118	if (tx_buf)
	119	d = *tx_buf++;
	120	else
	121	d = 0;
187fc9b3	122	writeq(d, p->register_base + OCTEON_SPI_DAT0 + (8 * i));
6b52c00f DD	123	}
	124
	125	mpi_tx.u64 = 0;
85fe414d	126	mpi_tx.s.csid = spi->chip_select;
6b52c00f DD	127	if (last_xfer)
	128	mpi_tx.s.leavecs = xfer->cs_change;
	129	else
	130	mpi_tx.s.leavecs = !xfer->cs_change;
	131	mpi_tx.s.txnum = tx_buf ? len : 0;
	132	mpi_tx.s.totnum = len;
187fc9b3	133	writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX);
6b52c00f DD	134
	135	octeon_spi_wait_ready(p);
	136	if (rx_buf)
	137	for (i = 0; i < len; i++) {
187fc9b3	138	u64 v = readq(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
6b52c00f DD	139	*rx_buf++ = (u8)v;
	140	}
	141
	142	if (xfer->delay_usecs)
	143	udelay(xfer->delay_usecs);
	144
	145	return xfer->len;
	146	}
	147
6b52c00f DD	148	static int octeon_spi_transfer_one_message(struct spi_master *master,
	149	struct spi_message *msg)
	150	{
	151	struct octeon_spi *p = spi_master_get_devdata(master);
	152	unsigned int total_len = 0;
	153	int status = 0;
	154	struct spi_transfer *xfer;
	155
6b52c00f	156	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
0a4e210e AL	157	bool last_xfer = list_is_last(&xfer->transfer_list,
0a4e210e AL	158	&msg->transfers);
6b52c00f DD	159	int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
	160	if (r < 0) {
	161	status = r;
	162	goto err;
	163	}
	164	total_len += r;
	165	}
	166	err:
	167	msg->status = status;
	168	msg->actual_length = total_len;
	169	spi_finalize_current_message(master);
	170	return status;
	171	}
	172
fd4a319b	173	static int octeon_spi_probe(struct platform_device *pdev)
6b52c00f	174	{
6b52c00f	175	struct resource *res_mem;
3ae36c8b	176	void __iomem *reg_base;
6b52c00f DD	177	struct spi_master *master;
	178	struct octeon_spi *p;
	179	int err = -ENOENT;
	180
	181	master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
	182	if (!master)
	183	return -ENOMEM;
	184	p = spi_master_get_devdata(master);
e1b18ea8	185	platform_set_drvdata(pdev, master);
6b52c00f DD	186
6b52c00f DD	187	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3ae36c8b AL	188	reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
	189	if (IS_ERR(reg_base)) {
	190	err = PTR_ERR(reg_base);
6b52c00f DD	191	goto fail;
6b52c00f DD	192	}
3ae36c8b	193
187fc9b3	194	p->register_base = reg_base;
b9e64763	195	p->sys_freq = octeon_get_io_clock_rate();
6b52c00f	196
6b52c00f DD	197	master->num_chipselect = 4;
	198	master->mode_bits = SPI_CPHA \|
	199	SPI_CPOL \|
	200	SPI_CS_HIGH \|
	201	SPI_LSB_FIRST \|
	202	SPI_3WIRE;
	203
6b52c00f	204	master->transfer_one_message = octeon_spi_transfer_one_message;
f79cc88e	205	master->bits_per_word_mask = SPI_BPW_MASK(8);
7984b5ca	206	master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
6b52c00f DD	207
6b52c00f DD	208	master->dev.of_node = pdev->dev.of_node;
22ad2d8d	209	err = devm_spi_register_master(&pdev->dev, master);
6b52c00f DD	210	if (err) {
	211	dev_err(&pdev->dev, "register master failed: %d\n", err);
	212	goto fail;
	213	}
	214
	215	dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
	216
	217	return 0;
	218	fail:
	219	spi_master_put(master);
	220	return err;
	221	}
	222
fd4a319b	223	static int octeon_spi_remove(struct platform_device *pdev)
6b52c00f	224	{
e1b18ea8 AL	225	struct spi_master *master = platform_get_drvdata(pdev);
e1b18ea8 AL	226	struct octeon_spi *p = spi_master_get_devdata(master);
6b52c00f	227
6b52c00f	228	/* Clear the CSENA* and put everything in a known state. */
187fc9b3	229	writeq(0, p->register_base + OCTEON_SPI_CFG);
6b52c00f DD	230
	231	return 0;
	232	}
	233
09355402	234	static const struct of_device_id octeon_spi_match[] = {
6b52c00f DD	235	{ .compatible = "cavium,octeon-3010-spi", },
	236	{},
	237	};
	238	MODULE_DEVICE_TABLE(of, octeon_spi_match);
	239
	240	static struct platform_driver octeon_spi_driver = {
	241	.driver = {
	242	.name = "spi-octeon",
6b52c00f DD	243	.of_match_table = octeon_spi_match,
	244	},
	245	.probe = octeon_spi_probe,
fd4a319b	246	.remove = octeon_spi_remove,
6b52c00f DD	247	};
	248
	249	module_platform_driver(octeon_spi_driver);
	250
	251	MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
	252	MODULE_AUTHOR("David Daney");
	253	MODULE_LICENSE("GPL");