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Commit | Line | Data |
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fdb3c18d | 1 | /* |
ca632f55 | 2 | * MicroWire interface driver for OMAP |
fdb3c18d DB |
3 | * |
4 | * Copyright 2003 MontaVista Software Inc. <source@mvista.com> | |
5 | * | |
6 | * Ported to 2.6 OMAP uwire interface. | |
7 | * Copyright (C) 2004 Texas Instruments. | |
8 | * | |
9 | * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com> | |
10 | * | |
11 | * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface) | |
12 | * Copyright (C) 2006 Nokia | |
13 | * | |
14 | * Many updates by Imre Deak <imre.deak@nokia.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify it | |
17 | * under the terms of the GNU General Public License as published by the | |
18 | * Free Software Foundation; either version 2 of the License, or (at your | |
19 | * option) any later version. | |
20 | * | |
21 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
22 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
23 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | |
24 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
26 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
27 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
28 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
30 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
31 | * | |
32 | * You should have received a copy of the GNU General Public License along | |
33 | * with this program; if not, write to the Free Software Foundation, Inc., | |
34 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
35 | */ | |
36 | #include <linux/kernel.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/platform_device.h> | |
40 | #include <linux/workqueue.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/err.h> | |
43 | #include <linux/clk.h> | |
5a0e3ad6 | 44 | #include <linux/slab.h> |
fdb3c18d DB |
45 | |
46 | #include <linux/spi/spi.h> | |
47 | #include <linux/spi/spi_bitbang.h> | |
d7614de4 | 48 | #include <linux/module.h> |
fdb3c18d | 49 | |
fdb3c18d | 50 | #include <asm/irq.h> |
a09e64fb | 51 | #include <mach/hardware.h> |
fdb3c18d DB |
52 | #include <asm/io.h> |
53 | #include <asm/mach-types.h> | |
54 | ||
70c494c3 | 55 | #include <mach/mux.h> |
68cb700c TL |
56 | |
57 | #include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */ | |
fdb3c18d DB |
58 | |
59 | ||
60 | /* FIXME address is now a platform device resource, | |
61 | * and irqs should show there too... | |
62 | */ | |
63 | #define UWIRE_BASE_PHYS 0xFFFB3000 | |
fdb3c18d DB |
64 | |
65 | /* uWire Registers: */ | |
66 | #define UWIRE_IO_SIZE 0x20 | |
67 | #define UWIRE_TDR 0x00 | |
68 | #define UWIRE_RDR 0x00 | |
69 | #define UWIRE_CSR 0x01 | |
70 | #define UWIRE_SR1 0x02 | |
71 | #define UWIRE_SR2 0x03 | |
72 | #define UWIRE_SR3 0x04 | |
73 | #define UWIRE_SR4 0x05 | |
74 | #define UWIRE_SR5 0x06 | |
75 | ||
76 | /* CSR bits */ | |
77 | #define RDRB (1 << 15) | |
78 | #define CSRB (1 << 14) | |
79 | #define START (1 << 13) | |
80 | #define CS_CMD (1 << 12) | |
81 | ||
82 | /* SR1 or SR2 bits */ | |
83 | #define UWIRE_READ_FALLING_EDGE 0x0001 | |
84 | #define UWIRE_READ_RISING_EDGE 0x0000 | |
85 | #define UWIRE_WRITE_FALLING_EDGE 0x0000 | |
86 | #define UWIRE_WRITE_RISING_EDGE 0x0002 | |
87 | #define UWIRE_CS_ACTIVE_LOW 0x0000 | |
88 | #define UWIRE_CS_ACTIVE_HIGH 0x0004 | |
89 | #define UWIRE_FREQ_DIV_2 0x0000 | |
90 | #define UWIRE_FREQ_DIV_4 0x0008 | |
91 | #define UWIRE_FREQ_DIV_8 0x0010 | |
92 | #define UWIRE_CHK_READY 0x0020 | |
93 | #define UWIRE_CLK_INVERTED 0x0040 | |
94 | ||
95 | ||
96 | struct uwire_spi { | |
97 | struct spi_bitbang bitbang; | |
98 | struct clk *ck; | |
99 | }; | |
100 | ||
101 | struct uwire_state { | |
102 | unsigned bits_per_word; | |
103 | unsigned div1_idx; | |
104 | }; | |
105 | ||
106 | /* REVISIT compile time constant for idx_shift? */ | |
55c381e4 RK |
107 | /* |
108 | * Or, put it in a structure which is used throughout the driver; | |
109 | * that avoids having to issue two loads for each bit of static data. | |
110 | */ | |
fdb3c18d | 111 | static unsigned int uwire_idx_shift; |
55c381e4 | 112 | static void __iomem *uwire_base; |
fdb3c18d DB |
113 | |
114 | static inline void uwire_write_reg(int idx, u16 val) | |
115 | { | |
55c381e4 | 116 | __raw_writew(val, uwire_base + (idx << uwire_idx_shift)); |
fdb3c18d DB |
117 | } |
118 | ||
119 | static inline u16 uwire_read_reg(int idx) | |
120 | { | |
55c381e4 | 121 | return __raw_readw(uwire_base + (idx << uwire_idx_shift)); |
fdb3c18d DB |
122 | } |
123 | ||
124 | static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags) | |
125 | { | |
126 | u16 w, val = 0; | |
127 | int shift, reg; | |
128 | ||
129 | if (flags & UWIRE_CLK_INVERTED) | |
130 | val ^= 0x03; | |
131 | val = flags & 0x3f; | |
132 | if (cs & 1) | |
133 | shift = 6; | |
134 | else | |
135 | shift = 0; | |
136 | if (cs <= 1) | |
137 | reg = UWIRE_SR1; | |
138 | else | |
139 | reg = UWIRE_SR2; | |
140 | ||
141 | w = uwire_read_reg(reg); | |
142 | w &= ~(0x3f << shift); | |
143 | w |= val << shift; | |
144 | uwire_write_reg(reg, w); | |
145 | } | |
146 | ||
147 | static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch) | |
148 | { | |
149 | u16 w; | |
150 | int c = 0; | |
151 | unsigned long max_jiffies = jiffies + HZ; | |
152 | ||
153 | for (;;) { | |
154 | w = uwire_read_reg(UWIRE_CSR); | |
155 | if ((w & mask) == val) | |
156 | break; | |
157 | if (time_after(jiffies, max_jiffies)) { | |
158 | printk(KERN_ERR "%s: timeout. reg=%#06x " | |
159 | "mask=%#06x val=%#06x\n", | |
b687d2a8 | 160 | __func__, w, mask, val); |
fdb3c18d DB |
161 | return -1; |
162 | } | |
163 | c++; | |
164 | if (might_not_catch && c > 64) | |
165 | break; | |
166 | } | |
167 | return 0; | |
168 | } | |
169 | ||
170 | static void uwire_set_clk1_div(int div1_idx) | |
171 | { | |
172 | u16 w; | |
173 | ||
174 | w = uwire_read_reg(UWIRE_SR3); | |
175 | w &= ~(0x03 << 1); | |
176 | w |= div1_idx << 1; | |
177 | uwire_write_reg(UWIRE_SR3, w); | |
178 | } | |
179 | ||
180 | static void uwire_chipselect(struct spi_device *spi, int value) | |
181 | { | |
182 | struct uwire_state *ust = spi->controller_state; | |
183 | u16 w; | |
184 | int old_cs; | |
185 | ||
186 | ||
187 | BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0)); | |
188 | ||
189 | w = uwire_read_reg(UWIRE_CSR); | |
190 | old_cs = (w >> 10) & 0x03; | |
191 | if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) { | |
192 | /* Deselect this CS, or the previous CS */ | |
193 | w &= ~CS_CMD; | |
194 | uwire_write_reg(UWIRE_CSR, w); | |
195 | } | |
196 | /* activate specfied chipselect */ | |
197 | if (value == BITBANG_CS_ACTIVE) { | |
198 | uwire_set_clk1_div(ust->div1_idx); | |
199 | /* invert clock? */ | |
200 | if (spi->mode & SPI_CPOL) | |
201 | uwire_write_reg(UWIRE_SR4, 1); | |
202 | else | |
203 | uwire_write_reg(UWIRE_SR4, 0); | |
204 | ||
205 | w = spi->chip_select << 10; | |
206 | w |= CS_CMD; | |
207 | uwire_write_reg(UWIRE_CSR, w); | |
208 | } | |
209 | } | |
210 | ||
211 | static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t) | |
212 | { | |
213 | struct uwire_state *ust = spi->controller_state; | |
214 | unsigned len = t->len; | |
215 | unsigned bits = ust->bits_per_word; | |
216 | unsigned bytes; | |
217 | u16 val, w; | |
a419aef8 | 218 | int status = 0; |
fdb3c18d DB |
219 | |
220 | if (!t->tx_buf && !t->rx_buf) | |
221 | return 0; | |
222 | ||
223 | /* Microwire doesn't read and write concurrently */ | |
224 | if (t->tx_buf && t->rx_buf) | |
225 | return -EPERM; | |
226 | ||
227 | w = spi->chip_select << 10; | |
228 | w |= CS_CMD; | |
229 | ||
230 | if (t->tx_buf) { | |
231 | const u8 *buf = t->tx_buf; | |
232 | ||
233 | /* NOTE: DMA could be used for TX transfers */ | |
234 | ||
235 | /* write one or two bytes at a time */ | |
236 | while (len >= 1) { | |
237 | /* tx bit 15 is first sent; we byteswap multibyte words | |
238 | * (msb-first) on the way out from memory. | |
239 | */ | |
240 | val = *buf++; | |
241 | if (bits > 8) { | |
242 | bytes = 2; | |
243 | val |= *buf++ << 8; | |
244 | } else | |
245 | bytes = 1; | |
246 | val <<= 16 - bits; | |
247 | ||
248 | #ifdef VERBOSE | |
249 | pr_debug("%s: write-%d =%04x\n", | |
6c7377ab | 250 | dev_name(&spi->dev), bits, val); |
fdb3c18d DB |
251 | #endif |
252 | if (wait_uwire_csr_flag(CSRB, 0, 0)) | |
253 | goto eio; | |
254 | ||
255 | uwire_write_reg(UWIRE_TDR, val); | |
256 | ||
257 | /* start write */ | |
258 | val = START | w | (bits << 5); | |
259 | ||
260 | uwire_write_reg(UWIRE_CSR, val); | |
261 | len -= bytes; | |
262 | ||
263 | /* Wait till write actually starts. | |
264 | * This is needed with MPU clock 60+ MHz. | |
265 | * REVISIT: we may not have time to catch it... | |
266 | */ | |
267 | if (wait_uwire_csr_flag(CSRB, CSRB, 1)) | |
268 | goto eio; | |
269 | ||
270 | status += bytes; | |
271 | } | |
272 | ||
273 | /* REVISIT: save this for later to get more i/o overlap */ | |
274 | if (wait_uwire_csr_flag(CSRB, 0, 0)) | |
275 | goto eio; | |
276 | ||
277 | } else if (t->rx_buf) { | |
278 | u8 *buf = t->rx_buf; | |
279 | ||
280 | /* read one or two bytes at a time */ | |
281 | while (len) { | |
282 | if (bits > 8) { | |
283 | bytes = 2; | |
284 | } else | |
285 | bytes = 1; | |
286 | ||
287 | /* start read */ | |
288 | val = START | w | (bits << 0); | |
289 | uwire_write_reg(UWIRE_CSR, val); | |
290 | len -= bytes; | |
291 | ||
292 | /* Wait till read actually starts */ | |
293 | (void) wait_uwire_csr_flag(CSRB, CSRB, 1); | |
294 | ||
295 | if (wait_uwire_csr_flag(RDRB | CSRB, | |
296 | RDRB, 0)) | |
297 | goto eio; | |
298 | ||
299 | /* rx bit 0 is last received; multibyte words will | |
300 | * be properly byteswapped on the way to memory. | |
301 | */ | |
302 | val = uwire_read_reg(UWIRE_RDR); | |
303 | val &= (1 << bits) - 1; | |
304 | *buf++ = (u8) val; | |
305 | if (bytes == 2) | |
306 | *buf++ = val >> 8; | |
307 | status += bytes; | |
308 | #ifdef VERBOSE | |
309 | pr_debug("%s: read-%d =%04x\n", | |
6c7377ab | 310 | dev_name(&spi->dev), bits, val); |
fdb3c18d DB |
311 | #endif |
312 | ||
313 | } | |
314 | } | |
315 | return status; | |
316 | eio: | |
317 | return -EIO; | |
318 | } | |
319 | ||
320 | static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t) | |
321 | { | |
322 | struct uwire_state *ust = spi->controller_state; | |
323 | struct uwire_spi *uwire; | |
324 | unsigned flags = 0; | |
325 | unsigned bits; | |
326 | unsigned hz; | |
327 | unsigned long rate; | |
328 | int div1_idx; | |
329 | int div1; | |
330 | int div2; | |
331 | int status; | |
332 | ||
333 | uwire = spi_master_get_devdata(spi->master); | |
334 | ||
fdb3c18d DB |
335 | bits = spi->bits_per_word; |
336 | if (t != NULL && t->bits_per_word) | |
337 | bits = t->bits_per_word; | |
fdb3c18d DB |
338 | |
339 | if (bits > 16) { | |
6c7377ab | 340 | pr_debug("%s: wordsize %d?\n", dev_name(&spi->dev), bits); |
fdb3c18d DB |
341 | status = -ENODEV; |
342 | goto done; | |
343 | } | |
344 | ust->bits_per_word = bits; | |
345 | ||
346 | /* mode 0..3, clock inverted separately; | |
347 | * standard nCS signaling; | |
348 | * don't treat DI=high as "not ready" | |
349 | */ | |
350 | if (spi->mode & SPI_CS_HIGH) | |
351 | flags |= UWIRE_CS_ACTIVE_HIGH; | |
352 | ||
353 | if (spi->mode & SPI_CPOL) | |
354 | flags |= UWIRE_CLK_INVERTED; | |
355 | ||
356 | switch (spi->mode & (SPI_CPOL | SPI_CPHA)) { | |
357 | case SPI_MODE_0: | |
358 | case SPI_MODE_3: | |
e5f1b194 | 359 | flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE; |
fdb3c18d DB |
360 | break; |
361 | case SPI_MODE_1: | |
362 | case SPI_MODE_2: | |
e5f1b194 | 363 | flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE; |
fdb3c18d DB |
364 | break; |
365 | } | |
366 | ||
367 | /* assume it's already enabled */ | |
368 | rate = clk_get_rate(uwire->ck); | |
369 | ||
370 | hz = spi->max_speed_hz; | |
371 | if (t != NULL && t->speed_hz) | |
372 | hz = t->speed_hz; | |
373 | ||
374 | if (!hz) { | |
6c7377ab | 375 | pr_debug("%s: zero speed?\n", dev_name(&spi->dev)); |
fdb3c18d DB |
376 | status = -EINVAL; |
377 | goto done; | |
378 | } | |
379 | ||
380 | /* F_INT = mpu_xor_clk / DIV1 */ | |
381 | for (div1_idx = 0; div1_idx < 4; div1_idx++) { | |
382 | switch (div1_idx) { | |
383 | case 0: | |
384 | div1 = 2; | |
385 | break; | |
386 | case 1: | |
387 | div1 = 4; | |
388 | break; | |
389 | case 2: | |
390 | div1 = 7; | |
391 | break; | |
392 | default: | |
393 | case 3: | |
394 | div1 = 10; | |
395 | break; | |
396 | } | |
397 | div2 = (rate / div1 + hz - 1) / hz; | |
398 | if (div2 <= 8) | |
399 | break; | |
400 | } | |
401 | if (div1_idx == 4) { | |
402 | pr_debug("%s: lowest clock %ld, need %d\n", | |
6c7377ab | 403 | dev_name(&spi->dev), rate / 10 / 8, hz); |
fdb3c18d DB |
404 | status = -EDOM; |
405 | goto done; | |
406 | } | |
407 | ||
408 | /* we have to cache this and reset in uwire_chipselect as this is a | |
409 | * global parameter and another uwire device can change it under | |
410 | * us */ | |
411 | ust->div1_idx = div1_idx; | |
412 | uwire_set_clk1_div(div1_idx); | |
413 | ||
414 | rate /= div1; | |
415 | ||
416 | switch (div2) { | |
417 | case 0: | |
418 | case 1: | |
419 | case 2: | |
420 | flags |= UWIRE_FREQ_DIV_2; | |
421 | rate /= 2; | |
422 | break; | |
423 | case 3: | |
424 | case 4: | |
425 | flags |= UWIRE_FREQ_DIV_4; | |
426 | rate /= 4; | |
427 | break; | |
428 | case 5: | |
429 | case 6: | |
430 | case 7: | |
431 | case 8: | |
432 | flags |= UWIRE_FREQ_DIV_8; | |
433 | rate /= 8; | |
434 | break; | |
435 | } | |
436 | omap_uwire_configure_mode(spi->chip_select, flags); | |
437 | pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n", | |
b687d2a8 | 438 | __func__, flags, |
fdb3c18d DB |
439 | clk_get_rate(uwire->ck) / 1000, |
440 | rate / 1000); | |
441 | status = 0; | |
442 | done: | |
443 | return status; | |
444 | } | |
445 | ||
446 | static int uwire_setup(struct spi_device *spi) | |
447 | { | |
448 | struct uwire_state *ust = spi->controller_state; | |
449 | ||
450 | if (ust == NULL) { | |
451 | ust = kzalloc(sizeof(*ust), GFP_KERNEL); | |
452 | if (ust == NULL) | |
453 | return -ENOMEM; | |
454 | spi->controller_state = ust; | |
455 | } | |
456 | ||
457 | return uwire_setup_transfer(spi, NULL); | |
458 | } | |
459 | ||
bb2d1c36 | 460 | static void uwire_cleanup(struct spi_device *spi) |
fdb3c18d DB |
461 | { |
462 | kfree(spi->controller_state); | |
463 | } | |
464 | ||
465 | static void uwire_off(struct uwire_spi *uwire) | |
466 | { | |
467 | uwire_write_reg(UWIRE_SR3, 0); | |
468 | clk_disable(uwire->ck); | |
469 | clk_put(uwire->ck); | |
470 | spi_master_put(uwire->bitbang.master); | |
471 | } | |
472 | ||
2deff8d6 | 473 | static int uwire_probe(struct platform_device *pdev) |
fdb3c18d DB |
474 | { |
475 | struct spi_master *master; | |
476 | struct uwire_spi *uwire; | |
477 | int status; | |
478 | ||
479 | master = spi_alloc_master(&pdev->dev, sizeof *uwire); | |
480 | if (!master) | |
481 | return -ENODEV; | |
482 | ||
483 | uwire = spi_master_get_devdata(master); | |
55c381e4 RK |
484 | |
485 | uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE); | |
486 | if (!uwire_base) { | |
487 | dev_dbg(&pdev->dev, "can't ioremap UWIRE\n"); | |
488 | spi_master_put(master); | |
489 | return -ENOMEM; | |
490 | } | |
491 | ||
24b5a82c | 492 | platform_set_drvdata(pdev, uwire); |
fdb3c18d | 493 | |
b1ad3796 RK |
494 | uwire->ck = clk_get(&pdev->dev, "fck"); |
495 | if (IS_ERR(uwire->ck)) { | |
496 | status = PTR_ERR(uwire->ck); | |
497 | dev_dbg(&pdev->dev, "no functional clock?\n"); | |
fdb3c18d | 498 | spi_master_put(master); |
b1ad3796 | 499 | return status; |
fdb3c18d DB |
500 | } |
501 | clk_enable(uwire->ck); | |
502 | ||
7a8f48f8 | 503 | if (cpu_is_omap7xx()) |
fdb3c18d DB |
504 | uwire_idx_shift = 1; |
505 | else | |
506 | uwire_idx_shift = 2; | |
507 | ||
508 | uwire_write_reg(UWIRE_SR3, 1); | |
509 | ||
e7db06b5 DB |
510 | /* the spi->mode bits understood by this driver: */ |
511 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
512 | ||
70d6027f DB |
513 | master->flags = SPI_MASTER_HALF_DUPLEX; |
514 | ||
fdb3c18d DB |
515 | master->bus_num = 2; /* "official" */ |
516 | master->num_chipselect = 4; | |
517 | master->setup = uwire_setup; | |
518 | master->cleanup = uwire_cleanup; | |
519 | ||
520 | uwire->bitbang.master = master; | |
521 | uwire->bitbang.chipselect = uwire_chipselect; | |
522 | uwire->bitbang.setup_transfer = uwire_setup_transfer; | |
523 | uwire->bitbang.txrx_bufs = uwire_txrx; | |
524 | ||
525 | status = spi_bitbang_start(&uwire->bitbang); | |
55c381e4 | 526 | if (status < 0) { |
fdb3c18d | 527 | uwire_off(uwire); |
55c381e4 RK |
528 | iounmap(uwire_base); |
529 | } | |
fdb3c18d DB |
530 | return status; |
531 | } | |
532 | ||
2deff8d6 | 533 | static int uwire_remove(struct platform_device *pdev) |
fdb3c18d | 534 | { |
24b5a82c | 535 | struct uwire_spi *uwire = platform_get_drvdata(pdev); |
fdb3c18d DB |
536 | int status; |
537 | ||
538 | // FIXME remove all child devices, somewhere ... | |
539 | ||
540 | status = spi_bitbang_stop(&uwire->bitbang); | |
541 | uwire_off(uwire); | |
55c381e4 | 542 | iounmap(uwire_base); |
fdb3c18d DB |
543 | return status; |
544 | } | |
545 | ||
7e38c3c4 KS |
546 | /* work with hotplug and coldplug */ |
547 | MODULE_ALIAS("platform:omap_uwire"); | |
548 | ||
fdb3c18d DB |
549 | static struct platform_driver uwire_driver = { |
550 | .driver = { | |
551 | .name = "omap_uwire", | |
fdb3c18d DB |
552 | .owner = THIS_MODULE, |
553 | }, | |
93e9c900 WS |
554 | .probe = uwire_probe, |
555 | .remove = uwire_remove, | |
fdb3c18d DB |
556 | // suspend ... unuse ck |
557 | // resume ... use ck | |
558 | }; | |
559 | ||
560 | static int __init omap_uwire_init(void) | |
561 | { | |
562 | /* FIXME move these into the relevant board init code. also, include | |
563 | * H3 support; it uses tsc2101 like H2 (on a different chipselect). | |
564 | */ | |
565 | ||
566 | if (machine_is_omap_h2()) { | |
567 | /* defaults: W21 SDO, U18 SDI, V19 SCL */ | |
568 | omap_cfg_reg(N14_1610_UWIRE_CS0); | |
569 | omap_cfg_reg(N15_1610_UWIRE_CS1); | |
570 | } | |
571 | if (machine_is_omap_perseus2()) { | |
572 | /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */ | |
7a8f48f8 AB |
573 | int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000; |
574 | omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9); | |
fdb3c18d DB |
575 | } |
576 | ||
93e9c900 | 577 | return platform_driver_register(&uwire_driver); |
fdb3c18d DB |
578 | } |
579 | ||
580 | static void __exit omap_uwire_exit(void) | |
581 | { | |
582 | platform_driver_unregister(&uwire_driver); | |
583 | } | |
584 | ||
585 | subsys_initcall(omap_uwire_init); | |
586 | module_exit(omap_uwire_exit); | |
587 | ||
588 | MODULE_LICENSE("GPL"); | |
589 |