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ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/dma-mapping.h> | |
53741ed8 RK |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/omap-dma.h> | |
ccdc7bf9 SO |
33 | #include <linux/platform_device.h> |
34 | #include <linux/err.h> | |
35 | #include <linux/clk.h> | |
36 | #include <linux/io.h> | |
5a0e3ad6 | 37 | #include <linux/slab.h> |
1f1a4384 | 38 | #include <linux/pm_runtime.h> |
d5a80031 BC |
39 | #include <linux/of.h> |
40 | #include <linux/of_device.h> | |
ec155afa MP |
41 | #include <linux/pinctrl/consumer.h> |
42 | #include <linux/err.h> | |
ccdc7bf9 SO |
43 | |
44 | #include <linux/spi/spi.h> | |
45 | ||
2203747c | 46 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
47 | |
48 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
27b5284c | 49 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
50 | |
51 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
52 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
53 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
54 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
55 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
56 | #define OMAP2_MCSPI_SYST 0x24 | |
57 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
58 | ||
59 | /* per-channel banks, 0x14 bytes each, first is: */ | |
60 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
61 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
62 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
63 | #define OMAP2_MCSPI_TX0 0x38 | |
64 | #define OMAP2_MCSPI_RX0 0x3c | |
65 | ||
66 | /* per-register bitmasks: */ | |
67 | ||
7a8fa725 JH |
68 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
69 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
70 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 71 | |
7a8fa725 JH |
72 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
73 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 74 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 75 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 76 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
77 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
78 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 79 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
80 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
81 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
82 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
83 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
84 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
85 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
86 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
ccdc7bf9 | 87 | |
7a8fa725 JH |
88 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
89 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
90 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
ccdc7bf9 | 91 | |
7a8fa725 | 92 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
ccdc7bf9 | 93 | |
7a8fa725 | 94 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
95 | |
96 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
97 | struct omap2_mcspi_dma { | |
53741ed8 RK |
98 | struct dma_chan *dma_tx; |
99 | struct dma_chan *dma_rx; | |
ccdc7bf9 SO |
100 | |
101 | int dma_tx_sync_dev; | |
102 | int dma_rx_sync_dev; | |
103 | ||
104 | struct completion dma_tx_completion; | |
105 | struct completion dma_rx_completion; | |
106 | }; | |
107 | ||
108 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
109 | * cache operations; better heuristics consider wordsize and bitrate. | |
110 | */ | |
8b66c134 | 111 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
112 | |
113 | ||
1bd897f8 BC |
114 | /* |
115 | * Used for context save and restore, structure members to be updated whenever | |
116 | * corresponding registers are modified. | |
117 | */ | |
118 | struct omap2_mcspi_regs { | |
119 | u32 modulctrl; | |
120 | u32 wakeupenable; | |
121 | struct list_head cs; | |
122 | }; | |
123 | ||
ccdc7bf9 | 124 | struct omap2_mcspi { |
ccdc7bf9 | 125 | struct spi_master *master; |
ccdc7bf9 SO |
126 | /* Virtual base address of the controller */ |
127 | void __iomem *base; | |
e5480b73 | 128 | unsigned long phys; |
ccdc7bf9 SO |
129 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
130 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 131 | struct device *dev; |
1bd897f8 | 132 | struct omap2_mcspi_regs ctx; |
0384e90b | 133 | unsigned int pin_dir:1; |
ccdc7bf9 SO |
134 | }; |
135 | ||
136 | struct omap2_mcspi_cs { | |
137 | void __iomem *base; | |
e5480b73 | 138 | unsigned long phys; |
ccdc7bf9 | 139 | int word_len; |
89c05372 | 140 | struct list_head node; |
a41ae1ad H |
141 | /* Context save and restore shadow register */ |
142 | u32 chconf0; | |
143 | }; | |
144 | ||
ccdc7bf9 SO |
145 | static inline void mcspi_write_reg(struct spi_master *master, |
146 | int idx, u32 val) | |
147 | { | |
148 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
149 | ||
150 | __raw_writel(val, mcspi->base + idx); | |
151 | } | |
152 | ||
153 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
154 | { | |
155 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
156 | ||
157 | return __raw_readl(mcspi->base + idx); | |
158 | } | |
159 | ||
160 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
161 | int idx, u32 val) | |
162 | { | |
163 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
164 | ||
165 | __raw_writel(val, cs->base + idx); | |
166 | } | |
167 | ||
168 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
169 | { | |
170 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
171 | ||
172 | return __raw_readl(cs->base + idx); | |
173 | } | |
174 | ||
a41ae1ad H |
175 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
176 | { | |
177 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
178 | ||
179 | return cs->chconf0; | |
180 | } | |
181 | ||
182 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
183 | { | |
184 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
185 | ||
186 | cs->chconf0 = val; | |
187 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 188 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
189 | } |
190 | ||
ccdc7bf9 SO |
191 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
192 | int is_read, int enable) | |
193 | { | |
194 | u32 l, rw; | |
195 | ||
a41ae1ad | 196 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
197 | |
198 | if (is_read) /* 1 is read, 0 write */ | |
199 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
200 | else | |
201 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
202 | ||
af4e944d S |
203 | if (enable) |
204 | l |= rw; | |
205 | else | |
206 | l &= ~rw; | |
207 | ||
a41ae1ad | 208 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
209 | } |
210 | ||
211 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
212 | { | |
213 | u32 l; | |
214 | ||
215 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; | |
216 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); | |
4743a0f8 RT |
217 | /* Flash post-writes */ |
218 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
219 | } |
220 | ||
221 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) | |
222 | { | |
223 | u32 l; | |
224 | ||
a41ae1ad | 225 | l = mcspi_cached_chconf0(spi); |
af4e944d S |
226 | if (cs_active) |
227 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
228 | else | |
229 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
230 | ||
a41ae1ad | 231 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
232 | } |
233 | ||
234 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
235 | { | |
1bd897f8 BC |
236 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
237 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
238 | u32 l; |
239 | ||
1bd897f8 BC |
240 | /* |
241 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
242 | * to single-channel master mode |
243 | */ | |
244 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
245 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
246 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 247 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 248 | |
1bd897f8 | 249 | ctx->modulctrl = l; |
a41ae1ad H |
250 | } |
251 | ||
252 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) | |
253 | { | |
1bd897f8 BC |
254 | struct spi_master *spi_cntrl = mcspi->master; |
255 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
256 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
257 | |
258 | /* McSPI: context restore */ | |
1bd897f8 BC |
259 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
260 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 261 | |
1bd897f8 | 262 | list_for_each_entry(cs, &ctx->cs, node) |
89c05372 | 263 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad | 264 | } |
ccdc7bf9 | 265 | |
5fda88f5 S |
266 | static int omap2_prepare_transfer(struct spi_master *master) |
267 | { | |
268 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
269 | ||
270 | pm_runtime_get_sync(mcspi->dev); | |
271 | return 0; | |
272 | } | |
273 | ||
274 | static int omap2_unprepare_transfer(struct spi_master *master) | |
275 | { | |
276 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
277 | ||
278 | pm_runtime_mark_last_busy(mcspi->dev); | |
279 | pm_runtime_put_autosuspend(mcspi->dev); | |
280 | return 0; | |
281 | } | |
282 | ||
2764c500 IK |
283 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
284 | { | |
285 | unsigned long timeout; | |
286 | ||
287 | timeout = jiffies + msecs_to_jiffies(1000); | |
288 | while (!(__raw_readl(reg) & bit)) { | |
289 | if (time_after(jiffies, timeout)) | |
290 | return -1; | |
291 | cpu_relax(); | |
292 | } | |
293 | return 0; | |
294 | } | |
295 | ||
53741ed8 RK |
296 | static void omap2_mcspi_rx_callback(void *data) |
297 | { | |
298 | struct spi_device *spi = data; | |
299 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
300 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
301 | ||
302 | complete(&mcspi_dma->dma_rx_completion); | |
303 | ||
304 | /* We must disable the DMA RX request */ | |
305 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
306 | } | |
307 | ||
308 | static void omap2_mcspi_tx_callback(void *data) | |
309 | { | |
310 | struct spi_device *spi = data; | |
311 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
312 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
313 | ||
314 | complete(&mcspi_dma->dma_tx_completion); | |
315 | ||
316 | /* We must disable the DMA TX request */ | |
317 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
318 | } | |
319 | ||
d7b4394e S |
320 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
321 | struct spi_transfer *xfer, | |
322 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
323 | { |
324 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 325 | struct omap2_mcspi_dma *mcspi_dma; |
8c7494a5 | 326 | unsigned int count; |
ccdc7bf9 SO |
327 | u8 * rx; |
328 | const u8 * tx; | |
2764c500 | 329 | void __iomem *chstat_reg; |
d7b4394e | 330 | struct omap2_mcspi_cs *cs = spi->controller_state; |
ccdc7bf9 SO |
331 | |
332 | mcspi = spi_master_get_devdata(spi->master); | |
333 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e | 334 | count = xfer->len; |
ccdc7bf9 | 335 | |
d7b4394e S |
336 | rx = xfer->rx_buf; |
337 | tx = xfer->tx_buf; | |
2764c500 IK |
338 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
339 | ||
d7b4394e | 340 | if (mcspi_dma->dma_tx) { |
53741ed8 RK |
341 | struct dma_async_tx_descriptor *tx; |
342 | struct scatterlist sg; | |
343 | ||
344 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
345 | ||
346 | sg_init_table(&sg, 1); | |
347 | sg_dma_address(&sg) = xfer->tx_dma; | |
348 | sg_dma_len(&sg) = xfer->len; | |
349 | ||
350 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, | |
d7b4394e | 351 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
53741ed8 RK |
352 | if (tx) { |
353 | tx->callback = omap2_mcspi_tx_callback; | |
354 | tx->callback_param = spi; | |
355 | dmaengine_submit(tx); | |
356 | } else { | |
357 | /* FIXME: fall back to PIO? */ | |
358 | } | |
359 | } | |
d7b4394e S |
360 | dma_async_issue_pending(mcspi_dma->dma_tx); |
361 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
362 | ||
363 | wait_for_completion(&mcspi_dma->dma_tx_completion); | |
364 | dma_unmap_single(mcspi->dev, xfer->tx_dma, count, | |
365 | DMA_TO_DEVICE); | |
366 | ||
367 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
368 | if (rx == NULL) { | |
369 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
370 | OMAP2_MCSPI_CHSTAT_TXS) < 0) | |
371 | dev_err(&spi->dev, "TXS timed out\n"); | |
372 | else if (mcspi_wait_for_reg_bit(chstat_reg, | |
373 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
374 | dev_err(&spi->dev, "EOT timed out\n"); | |
375 | } | |
376 | } | |
53741ed8 | 377 | |
d7b4394e S |
378 | static unsigned |
379 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
380 | struct dma_slave_config cfg, | |
381 | unsigned es) | |
382 | { | |
383 | struct omap2_mcspi *mcspi; | |
384 | struct omap2_mcspi_dma *mcspi_dma; | |
385 | unsigned int count; | |
386 | u32 l; | |
387 | int elements = 0; | |
388 | int word_len, element_count; | |
389 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
390 | mcspi = spi_master_get_devdata(spi->master); | |
391 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
392 | count = xfer->len; | |
393 | word_len = cs->word_len; | |
394 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 395 | |
d7b4394e S |
396 | if (word_len <= 8) |
397 | element_count = count; | |
398 | else if (word_len <= 16) | |
399 | element_count = count >> 1; | |
400 | else /* word_len <= 32 */ | |
401 | element_count = count >> 2; | |
402 | ||
403 | if (mcspi_dma->dma_rx) { | |
53741ed8 RK |
404 | struct dma_async_tx_descriptor *tx; |
405 | struct scatterlist sg; | |
406 | size_t len = xfer->len - es; | |
407 | ||
408 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
409 | ||
410 | if (l & OMAP2_MCSPI_CHCONF_TURBO) | |
411 | len -= es; | |
412 | ||
413 | sg_init_table(&sg, 1); | |
414 | sg_dma_address(&sg) = xfer->rx_dma; | |
415 | sg_dma_len(&sg) = len; | |
416 | ||
417 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, | |
d7b4394e S |
418 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | |
419 | DMA_CTRL_ACK); | |
53741ed8 RK |
420 | if (tx) { |
421 | tx->callback = omap2_mcspi_rx_callback; | |
422 | tx->callback_param = spi; | |
423 | dmaengine_submit(tx); | |
424 | } else { | |
d7b4394e | 425 | /* FIXME: fall back to PIO? */ |
2764c500 | 426 | } |
ccdc7bf9 SO |
427 | } |
428 | ||
d7b4394e S |
429 | dma_async_issue_pending(mcspi_dma->dma_rx); |
430 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 431 | |
d7b4394e S |
432 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
433 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, | |
434 | DMA_FROM_DEVICE); | |
435 | omap2_mcspi_set_enable(spi, 0); | |
53741ed8 | 436 | |
d7b4394e | 437 | elements = element_count - 1; |
4743a0f8 | 438 | |
d7b4394e S |
439 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
440 | elements--; | |
4743a0f8 | 441 | |
57c5c28d | 442 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
d7b4394e | 443 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
57c5c28d EN |
444 | u32 w; |
445 | ||
446 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
447 | if (word_len <= 8) | |
d7b4394e | 448 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 449 | else if (word_len <= 16) |
d7b4394e | 450 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 451 | else /* word_len <= 32 */ |
d7b4394e | 452 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 453 | } else { |
d7b4394e S |
454 | dev_err(&spi->dev, "DMA RX penultimate word empty"); |
455 | count -= (word_len <= 8) ? 2 : | |
456 | (word_len <= 16) ? 4 : | |
457 | /* word_len <= 32 */ 8; | |
458 | omap2_mcspi_set_enable(spi, 1); | |
459 | return count; | |
57c5c28d | 460 | } |
ccdc7bf9 | 461 | } |
d7b4394e S |
462 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
463 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
464 | u32 w; | |
465 | ||
466 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
467 | if (word_len <= 8) | |
468 | ((u8 *)xfer->rx_buf)[elements] = w; | |
469 | else if (word_len <= 16) | |
470 | ((u16 *)xfer->rx_buf)[elements] = w; | |
471 | else /* word_len <= 32 */ | |
472 | ((u32 *)xfer->rx_buf)[elements] = w; | |
473 | } else { | |
474 | dev_err(&spi->dev, "DMA RX last word empty"); | |
475 | count -= (word_len <= 8) ? 1 : | |
476 | (word_len <= 16) ? 2 : | |
477 | /* word_len <= 32 */ 4; | |
478 | } | |
479 | omap2_mcspi_set_enable(spi, 1); | |
480 | return count; | |
481 | } | |
482 | ||
483 | static unsigned | |
484 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
485 | { | |
486 | struct omap2_mcspi *mcspi; | |
487 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
488 | struct omap2_mcspi_dma *mcspi_dma; | |
489 | unsigned int count; | |
490 | u32 l; | |
491 | u8 *rx; | |
492 | const u8 *tx; | |
493 | struct dma_slave_config cfg; | |
494 | enum dma_slave_buswidth width; | |
495 | unsigned es; | |
496 | ||
497 | mcspi = spi_master_get_devdata(spi->master); | |
498 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
499 | l = mcspi_cached_chconf0(spi); | |
500 | ||
501 | ||
502 | if (cs->word_len <= 8) { | |
503 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
504 | es = 1; | |
505 | } else if (cs->word_len <= 16) { | |
506 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
507 | es = 2; | |
508 | } else { | |
509 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
510 | es = 4; | |
511 | } | |
512 | ||
513 | memset(&cfg, 0, sizeof(cfg)); | |
514 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
515 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
516 | cfg.src_addr_width = width; | |
517 | cfg.dst_addr_width = width; | |
518 | cfg.src_maxburst = 1; | |
519 | cfg.dst_maxburst = 1; | |
520 | ||
521 | rx = xfer->rx_buf; | |
522 | tx = xfer->tx_buf; | |
523 | ||
524 | count = xfer->len; | |
525 | ||
526 | if (tx != NULL) | |
527 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
528 | ||
529 | if (rx != NULL) | |
530 | return omap2_mcspi_rx_dma(spi, xfer, cfg, es); | |
531 | ||
ccdc7bf9 SO |
532 | return count; |
533 | } | |
534 | ||
ccdc7bf9 SO |
535 | static unsigned |
536 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
537 | { | |
538 | struct omap2_mcspi *mcspi; | |
539 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
540 | unsigned int count, c; | |
541 | u32 l; | |
542 | void __iomem *base = cs->base; | |
543 | void __iomem *tx_reg; | |
544 | void __iomem *rx_reg; | |
545 | void __iomem *chstat_reg; | |
546 | int word_len; | |
547 | ||
548 | mcspi = spi_master_get_devdata(spi->master); | |
549 | count = xfer->len; | |
550 | c = count; | |
551 | word_len = cs->word_len; | |
552 | ||
a41ae1ad | 553 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
554 | |
555 | /* We store the pre-calculated register addresses on stack to speed | |
556 | * up the transfer loop. */ | |
557 | tx_reg = base + OMAP2_MCSPI_TX0; | |
558 | rx_reg = base + OMAP2_MCSPI_RX0; | |
559 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
560 | ||
adef658d MJ |
561 | if (c < (word_len>>3)) |
562 | return 0; | |
563 | ||
ccdc7bf9 SO |
564 | if (word_len <= 8) { |
565 | u8 *rx; | |
566 | const u8 *tx; | |
567 | ||
568 | rx = xfer->rx_buf; | |
569 | tx = xfer->tx_buf; | |
570 | ||
571 | do { | |
feed9bab | 572 | c -= 1; |
ccdc7bf9 SO |
573 | if (tx != NULL) { |
574 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
575 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
576 | dev_err(&spi->dev, "TXS timed out\n"); | |
577 | goto out; | |
578 | } | |
079a176d | 579 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 580 | word_len, *tx); |
ccdc7bf9 SO |
581 | __raw_writel(*tx++, tx_reg); |
582 | } | |
583 | if (rx != NULL) { | |
584 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
585 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
586 | dev_err(&spi->dev, "RXS timed out\n"); | |
587 | goto out; | |
588 | } | |
4743a0f8 RT |
589 | |
590 | if (c == 1 && tx == NULL && | |
591 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
592 | omap2_mcspi_set_enable(spi, 0); | |
593 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 594 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 595 | word_len, *(rx - 1)); |
4743a0f8 RT |
596 | if (mcspi_wait_for_reg_bit(chstat_reg, |
597 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
598 | dev_err(&spi->dev, | |
599 | "RXS timed out\n"); | |
600 | goto out; | |
601 | } | |
602 | c = 0; | |
603 | } else if (c == 0 && tx == NULL) { | |
604 | omap2_mcspi_set_enable(spi, 0); | |
605 | } | |
606 | ||
ccdc7bf9 | 607 | *rx++ = __raw_readl(rx_reg); |
079a176d | 608 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 609 | word_len, *(rx - 1)); |
ccdc7bf9 | 610 | } |
95c5c3ab | 611 | } while (c); |
ccdc7bf9 SO |
612 | } else if (word_len <= 16) { |
613 | u16 *rx; | |
614 | const u16 *tx; | |
615 | ||
616 | rx = xfer->rx_buf; | |
617 | tx = xfer->tx_buf; | |
618 | do { | |
feed9bab | 619 | c -= 2; |
ccdc7bf9 SO |
620 | if (tx != NULL) { |
621 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
622 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
623 | dev_err(&spi->dev, "TXS timed out\n"); | |
624 | goto out; | |
625 | } | |
079a176d | 626 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 627 | word_len, *tx); |
ccdc7bf9 SO |
628 | __raw_writel(*tx++, tx_reg); |
629 | } | |
630 | if (rx != NULL) { | |
631 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
632 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
633 | dev_err(&spi->dev, "RXS timed out\n"); | |
634 | goto out; | |
635 | } | |
4743a0f8 RT |
636 | |
637 | if (c == 2 && tx == NULL && | |
638 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
639 | omap2_mcspi_set_enable(spi, 0); | |
640 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 641 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 642 | word_len, *(rx - 1)); |
4743a0f8 RT |
643 | if (mcspi_wait_for_reg_bit(chstat_reg, |
644 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
645 | dev_err(&spi->dev, | |
646 | "RXS timed out\n"); | |
647 | goto out; | |
648 | } | |
649 | c = 0; | |
650 | } else if (c == 0 && tx == NULL) { | |
651 | omap2_mcspi_set_enable(spi, 0); | |
652 | } | |
653 | ||
ccdc7bf9 | 654 | *rx++ = __raw_readl(rx_reg); |
079a176d | 655 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 656 | word_len, *(rx - 1)); |
ccdc7bf9 | 657 | } |
95c5c3ab | 658 | } while (c >= 2); |
ccdc7bf9 SO |
659 | } else if (word_len <= 32) { |
660 | u32 *rx; | |
661 | const u32 *tx; | |
662 | ||
663 | rx = xfer->rx_buf; | |
664 | tx = xfer->tx_buf; | |
665 | do { | |
feed9bab | 666 | c -= 4; |
ccdc7bf9 SO |
667 | if (tx != NULL) { |
668 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
669 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
670 | dev_err(&spi->dev, "TXS timed out\n"); | |
671 | goto out; | |
672 | } | |
079a176d | 673 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 674 | word_len, *tx); |
ccdc7bf9 SO |
675 | __raw_writel(*tx++, tx_reg); |
676 | } | |
677 | if (rx != NULL) { | |
678 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
679 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
680 | dev_err(&spi->dev, "RXS timed out\n"); | |
681 | goto out; | |
682 | } | |
4743a0f8 RT |
683 | |
684 | if (c == 4 && tx == NULL && | |
685 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
686 | omap2_mcspi_set_enable(spi, 0); | |
687 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 688 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 689 | word_len, *(rx - 1)); |
4743a0f8 RT |
690 | if (mcspi_wait_for_reg_bit(chstat_reg, |
691 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
692 | dev_err(&spi->dev, | |
693 | "RXS timed out\n"); | |
694 | goto out; | |
695 | } | |
696 | c = 0; | |
697 | } else if (c == 0 && tx == NULL) { | |
698 | omap2_mcspi_set_enable(spi, 0); | |
699 | } | |
700 | ||
ccdc7bf9 | 701 | *rx++ = __raw_readl(rx_reg); |
079a176d | 702 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 703 | word_len, *(rx - 1)); |
ccdc7bf9 | 704 | } |
95c5c3ab | 705 | } while (c >= 4); |
ccdc7bf9 SO |
706 | } |
707 | ||
708 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
709 | if (xfer->rx_buf == NULL) { | |
710 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
711 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
712 | dev_err(&spi->dev, "TXS timed out\n"); | |
713 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
714 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
715 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
716 | |
717 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
718 | * otherwise these rx datas will affect the direct following | |
719 | * RX_ONLY transfer. | |
720 | */ | |
721 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
722 | } |
723 | out: | |
4743a0f8 | 724 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
725 | return count - c; |
726 | } | |
727 | ||
57d9c10d HH |
728 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
729 | { | |
730 | u32 div; | |
731 | ||
732 | for (div = 0; div < 15; div++) | |
733 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
734 | return div; | |
735 | ||
736 | return 15; | |
737 | } | |
738 | ||
ccdc7bf9 SO |
739 | /* called only when no transfer is active to this device */ |
740 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
741 | struct spi_transfer *t) | |
742 | { | |
743 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
744 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 745 | struct spi_master *spi_cntrl; |
ccdc7bf9 SO |
746 | u32 l = 0, div = 0; |
747 | u8 word_len = spi->bits_per_word; | |
9bd4517d | 748 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
749 | |
750 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 751 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
752 | |
753 | if (t != NULL && t->bits_per_word) | |
754 | word_len = t->bits_per_word; | |
755 | ||
756 | cs->word_len = word_len; | |
757 | ||
9bd4517d SE |
758 | if (t && t->speed_hz) |
759 | speed_hz = t->speed_hz; | |
760 | ||
57d9c10d HH |
761 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
762 | div = omap2_mcspi_calc_divisor(speed_hz); | |
ccdc7bf9 | 763 | |
a41ae1ad | 764 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
765 | |
766 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
767 | * REVISIT: this controller could support SPI_3WIRE mode. | |
768 | */ | |
0384e90b DM |
769 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_OUT_D1_IN) { |
770 | l &= ~OMAP2_MCSPI_CHCONF_IS; | |
771 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; | |
772 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
773 | } else { | |
774 | l |= OMAP2_MCSPI_CHCONF_IS; | |
775 | l |= OMAP2_MCSPI_CHCONF_DPE1; | |
776 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; | |
777 | } | |
ccdc7bf9 SO |
778 | |
779 | /* wordlength */ | |
780 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
781 | l |= (word_len - 1) << 7; | |
782 | ||
783 | /* set chipselect polarity; manage with FORCE */ | |
784 | if (!(spi->mode & SPI_CS_HIGH)) | |
785 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
786 | else | |
787 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
788 | ||
789 | /* set clock divisor */ | |
790 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
791 | l |= div << 2; | |
792 | ||
793 | /* set SPI mode 0..3 */ | |
794 | if (spi->mode & SPI_CPOL) | |
795 | l |= OMAP2_MCSPI_CHCONF_POL; | |
796 | else | |
797 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
798 | if (spi->mode & SPI_CPHA) | |
799 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
800 | else | |
801 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
802 | ||
a41ae1ad | 803 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
804 | |
805 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", | |
57d9c10d | 806 | OMAP2_MCSPI_MAX_FREQ >> div, |
ccdc7bf9 SO |
807 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
808 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
ccdc7bf9 SO |
813 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
814 | { | |
815 | struct spi_master *master = spi->master; | |
816 | struct omap2_mcspi *mcspi; | |
817 | struct omap2_mcspi_dma *mcspi_dma; | |
53741ed8 RK |
818 | dma_cap_mask_t mask; |
819 | unsigned sig; | |
ccdc7bf9 SO |
820 | |
821 | mcspi = spi_master_get_devdata(master); | |
822 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
823 | ||
53741ed8 RK |
824 | init_completion(&mcspi_dma->dma_rx_completion); |
825 | init_completion(&mcspi_dma->dma_tx_completion); | |
826 | ||
827 | dma_cap_zero(mask); | |
828 | dma_cap_set(DMA_SLAVE, mask); | |
53741ed8 RK |
829 | sig = mcspi_dma->dma_rx_sync_dev; |
830 | mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
831 | if (!mcspi_dma->dma_rx) { | |
832 | dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n"); | |
ccdc7bf9 SO |
833 | return -EAGAIN; |
834 | } | |
835 | ||
53741ed8 RK |
836 | sig = mcspi_dma->dma_tx_sync_dev; |
837 | mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
838 | if (!mcspi_dma->dma_tx) { | |
839 | dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n"); | |
840 | dma_release_channel(mcspi_dma->dma_rx); | |
841 | mcspi_dma->dma_rx = NULL; | |
ccdc7bf9 SO |
842 | return -EAGAIN; |
843 | } | |
844 | ||
ccdc7bf9 SO |
845 | return 0; |
846 | } | |
847 | ||
ccdc7bf9 SO |
848 | static int omap2_mcspi_setup(struct spi_device *spi) |
849 | { | |
850 | int ret; | |
1bd897f8 BC |
851 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
852 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
853 | struct omap2_mcspi_dma *mcspi_dma; |
854 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
855 | ||
7d077197 | 856 | if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { |
ccdc7bf9 SO |
857 | dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", |
858 | spi->bits_per_word); | |
859 | return -EINVAL; | |
860 | } | |
861 | ||
ccdc7bf9 SO |
862 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
863 | ||
864 | if (!cs) { | |
10aa5a35 | 865 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
866 | if (!cs) |
867 | return -ENOMEM; | |
868 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 869 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
a41ae1ad | 870 | cs->chconf0 = 0; |
ccdc7bf9 | 871 | spi->controller_state = cs; |
89c05372 | 872 | /* Link this to context save list */ |
1bd897f8 | 873 | list_add_tail(&cs->node, &ctx->cs); |
ccdc7bf9 SO |
874 | } |
875 | ||
8c7494a5 | 876 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 SO |
877 | ret = omap2_mcspi_request_dma(spi); |
878 | if (ret < 0) | |
879 | return ret; | |
880 | } | |
881 | ||
034d3dc9 | 882 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
883 | if (ret < 0) |
884 | return ret; | |
a41ae1ad | 885 | |
86eeb6fe | 886 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
887 | pm_runtime_mark_last_busy(mcspi->dev); |
888 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
889 | |
890 | return ret; | |
891 | } | |
892 | ||
893 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
894 | { | |
895 | struct omap2_mcspi *mcspi; | |
896 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 897 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
898 | |
899 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 900 | |
5e774943 SE |
901 | if (spi->controller_state) { |
902 | /* Unlink controller state from context save list */ | |
903 | cs = spi->controller_state; | |
904 | list_del(&cs->node); | |
89c05372 | 905 | |
10aa5a35 | 906 | kfree(cs); |
5e774943 | 907 | } |
ccdc7bf9 | 908 | |
99f1a43f SE |
909 | if (spi->chip_select < spi->master->num_chipselect) { |
910 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
911 | ||
53741ed8 RK |
912 | if (mcspi_dma->dma_rx) { |
913 | dma_release_channel(mcspi_dma->dma_rx); | |
914 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 915 | } |
53741ed8 RK |
916 | if (mcspi_dma->dma_tx) { |
917 | dma_release_channel(mcspi_dma->dma_tx); | |
918 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 919 | } |
ccdc7bf9 SO |
920 | } |
921 | } | |
922 | ||
5fda88f5 | 923 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) |
ccdc7bf9 | 924 | { |
ccdc7bf9 SO |
925 | |
926 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 927 | * -- although this controller would gladly |
ccdc7bf9 SO |
928 | * arbitrate among multiple channels. This corresponds to "single |
929 | * channel" master mode. As a side effect, we need to manage the | |
930 | * chipselect with the FORCE bit ... CS != channel enable. | |
931 | */ | |
ccdc7bf9 | 932 | |
5fda88f5 S |
933 | struct spi_device *spi; |
934 | struct spi_transfer *t = NULL; | |
935 | int cs_active = 0; | |
936 | struct omap2_mcspi_cs *cs; | |
937 | struct omap2_mcspi_device_config *cd; | |
938 | int par_override = 0; | |
939 | int status = 0; | |
940 | u32 chconf; | |
ccdc7bf9 | 941 | |
5fda88f5 S |
942 | spi = m->spi; |
943 | cs = spi->controller_state; | |
944 | cd = spi->controller_data; | |
ccdc7bf9 | 945 | |
5fda88f5 S |
946 | omap2_mcspi_set_enable(spi, 1); |
947 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
948 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | |
949 | status = -EINVAL; | |
950 | break; | |
951 | } | |
952 | if (par_override || t->speed_hz || t->bits_per_word) { | |
953 | par_override = 1; | |
954 | status = omap2_mcspi_setup_transfer(spi, t); | |
955 | if (status < 0) | |
956 | break; | |
957 | if (!t->speed_hz && !t->bits_per_word) | |
958 | par_override = 0; | |
959 | } | |
4743a0f8 | 960 | |
5fda88f5 S |
961 | if (!cs_active) { |
962 | omap2_mcspi_force_cs(spi, 1); | |
963 | cs_active = 1; | |
964 | } | |
4743a0f8 | 965 | |
5fda88f5 S |
966 | chconf = mcspi_cached_chconf0(spi); |
967 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
968 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
ccdc7bf9 | 969 | |
5fda88f5 S |
970 | if (t->tx_buf == NULL) |
971 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
972 | else if (t->rx_buf == NULL) | |
973 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
ccdc7bf9 | 974 | |
5fda88f5 S |
975 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
976 | /* Turbo mode is for more than one word */ | |
977 | if (t->len > ((cs->word_len + 7) >> 3)) | |
978 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
979 | } | |
ccdc7bf9 | 980 | |
5fda88f5 | 981 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 982 | |
5fda88f5 S |
983 | if (t->len) { |
984 | unsigned count; | |
985 | ||
986 | /* RX_ONLY mode needs dummy data in TX reg */ | |
987 | if (t->tx_buf == NULL) | |
988 | __raw_writel(0, cs->base | |
989 | + OMAP2_MCSPI_TX0); | |
ccdc7bf9 | 990 | |
5fda88f5 S |
991 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) |
992 | count = omap2_mcspi_txrx_dma(spi, t); | |
993 | else | |
994 | count = omap2_mcspi_txrx_pio(spi, t); | |
995 | m->actual_length += count; | |
ccdc7bf9 | 996 | |
5fda88f5 S |
997 | if (count != t->len) { |
998 | status = -EIO; | |
999 | break; | |
ccdc7bf9 SO |
1000 | } |
1001 | } | |
1002 | ||
5fda88f5 S |
1003 | if (t->delay_usecs) |
1004 | udelay(t->delay_usecs); | |
ccdc7bf9 | 1005 | |
5fda88f5 S |
1006 | /* ignore the "leave it on after last xfer" hint */ |
1007 | if (t->cs_change) { | |
ccdc7bf9 | 1008 | omap2_mcspi_force_cs(spi, 0); |
5fda88f5 S |
1009 | cs_active = 0; |
1010 | } | |
1011 | } | |
1012 | /* Restore defaults if they were overriden */ | |
1013 | if (par_override) { | |
1014 | par_override = 0; | |
1015 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1016 | } | |
ccdc7bf9 | 1017 | |
5fda88f5 S |
1018 | if (cs_active) |
1019 | omap2_mcspi_force_cs(spi, 0); | |
ccdc7bf9 | 1020 | |
5fda88f5 | 1021 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1022 | |
5fda88f5 | 1023 | m->status = status; |
1f1a4384 | 1024 | |
ccdc7bf9 SO |
1025 | } |
1026 | ||
5fda88f5 S |
1027 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
1028 | struct spi_message *m) | |
ccdc7bf9 SO |
1029 | { |
1030 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 SO |
1031 | struct spi_transfer *t; |
1032 | ||
5fda88f5 | 1033 | mcspi = spi_master_get_devdata(master); |
ccdc7bf9 SO |
1034 | m->actual_length = 0; |
1035 | m->status = 0; | |
1036 | ||
1037 | /* reject invalid messages and transfers */ | |
5fda88f5 | 1038 | if (list_empty(&m->transfers)) |
ccdc7bf9 SO |
1039 | return -EINVAL; |
1040 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
1041 | const void *tx_buf = t->tx_buf; | |
1042 | void *rx_buf = t->rx_buf; | |
1043 | unsigned len = t->len; | |
1044 | ||
1045 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ | |
1046 | || (len && !(rx_buf || tx_buf)) | |
1047 | || (t->bits_per_word && | |
1048 | ( t->bits_per_word < 4 | |
1049 | || t->bits_per_word > 32))) { | |
5fda88f5 | 1050 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
ccdc7bf9 SO |
1051 | t->speed_hz, |
1052 | len, | |
1053 | tx_buf ? "tx" : "", | |
1054 | rx_buf ? "rx" : "", | |
1055 | t->bits_per_word); | |
1056 | return -EINVAL; | |
1057 | } | |
57d9c10d | 1058 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { |
5fda88f5 | 1059 | dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", |
57d9c10d HH |
1060 | t->speed_hz, |
1061 | OMAP2_MCSPI_MAX_FREQ >> 15); | |
ccdc7bf9 SO |
1062 | return -EINVAL; |
1063 | } | |
1064 | ||
1065 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) | |
1066 | continue; | |
1067 | ||
ccdc7bf9 | 1068 | if (tx_buf != NULL) { |
5fda88f5 | 1069 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, |
ccdc7bf9 | 1070 | len, DMA_TO_DEVICE); |
5fda88f5 S |
1071 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { |
1072 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1073 | 'T', len); |
1074 | return -EINVAL; | |
1075 | } | |
1076 | } | |
1077 | if (rx_buf != NULL) { | |
5fda88f5 | 1078 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, |
ccdc7bf9 | 1079 | DMA_FROM_DEVICE); |
5fda88f5 S |
1080 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { |
1081 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1082 | 'R', len); |
1083 | if (tx_buf != NULL) | |
5fda88f5 | 1084 | dma_unmap_single(mcspi->dev, t->tx_dma, |
ccdc7bf9 SO |
1085 | len, DMA_TO_DEVICE); |
1086 | return -EINVAL; | |
1087 | } | |
1088 | } | |
1089 | } | |
1090 | ||
5fda88f5 S |
1091 | omap2_mcspi_work(mcspi, m); |
1092 | spi_finalize_current_message(master); | |
ccdc7bf9 SO |
1093 | return 0; |
1094 | } | |
1095 | ||
24ab3275 | 1096 | static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1097 | { |
1098 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1099 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1100 | int ret = 0; |
ccdc7bf9 | 1101 | |
034d3dc9 | 1102 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1103 | if (ret < 0) |
1104 | return ret; | |
ddb22195 | 1105 | |
39f8052d S |
1106 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
1107 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); | |
1108 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; | |
ccdc7bf9 SO |
1109 | |
1110 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1111 | pm_runtime_mark_last_busy(mcspi->dev); |
1112 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1113 | return 0; |
1114 | } | |
1115 | ||
1f1a4384 G |
1116 | static int omap_mcspi_runtime_resume(struct device *dev) |
1117 | { | |
1118 | struct omap2_mcspi *mcspi; | |
1119 | struct spi_master *master; | |
1120 | ||
1121 | master = dev_get_drvdata(dev); | |
1122 | mcspi = spi_master_get_devdata(master); | |
1123 | omap2_mcspi_restore_ctx(mcspi); | |
1124 | ||
1125 | return 0; | |
1126 | } | |
1127 | ||
d5a80031 BC |
1128 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1129 | .regs_offset = 0, | |
1130 | }; | |
1131 | ||
1132 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1133 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1134 | }; | |
1135 | ||
1136 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1137 | { | |
1138 | .compatible = "ti,omap2-mcspi", | |
1139 | .data = &omap2_pdata, | |
1140 | }, | |
1141 | { | |
1142 | .compatible = "ti,omap4-mcspi", | |
1143 | .data = &omap4_pdata, | |
1144 | }, | |
1145 | { }, | |
1146 | }; | |
1147 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1148 | |
7d6b6d83 | 1149 | static int __devinit omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1150 | { |
1151 | struct spi_master *master; | |
83a01e72 | 1152 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1153 | struct omap2_mcspi *mcspi; |
1154 | struct resource *r; | |
1155 | int status = 0, i; | |
d5a80031 BC |
1156 | u32 regs_offset = 0; |
1157 | static int bus_num = 1; | |
1158 | struct device_node *node = pdev->dev.of_node; | |
1159 | const struct of_device_id *match; | |
ec155afa | 1160 | struct pinctrl *pinctrl; |
ccdc7bf9 SO |
1161 | |
1162 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1163 | if (master == NULL) { | |
1164 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1165 | return -ENOMEM; | |
1166 | } | |
1167 | ||
e7db06b5 DB |
1168 | /* the spi->mode bits understood by this driver: */ |
1169 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
1170 | ||
ccdc7bf9 | 1171 | master->setup = omap2_mcspi_setup; |
5fda88f5 S |
1172 | master->prepare_transfer_hardware = omap2_prepare_transfer; |
1173 | master->unprepare_transfer_hardware = omap2_unprepare_transfer; | |
1174 | master->transfer_one_message = omap2_mcspi_transfer_one_message; | |
ccdc7bf9 | 1175 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 BC |
1176 | master->dev.of_node = node; |
1177 | ||
0384e90b DM |
1178 | dev_set_drvdata(&pdev->dev, master); |
1179 | ||
1180 | mcspi = spi_master_get_devdata(master); | |
1181 | mcspi->master = master; | |
1182 | ||
d5a80031 BC |
1183 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
1184 | if (match) { | |
1185 | u32 num_cs = 1; /* default number of chipselect */ | |
1186 | pdata = match->data; | |
1187 | ||
1188 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1189 | master->num_chipselect = num_cs; | |
1190 | master->bus_num = bus_num++; | |
0384e90b DM |
1191 | if (of_get_property(node, "ti,pindir-d0-in-d1-out", NULL)) |
1192 | mcspi->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT; | |
d5a80031 BC |
1193 | } else { |
1194 | pdata = pdev->dev.platform_data; | |
1195 | master->num_chipselect = pdata->num_cs; | |
1196 | if (pdev->id != -1) | |
1197 | master->bus_num = pdev->id; | |
0384e90b | 1198 | mcspi->pin_dir = pdata->pin_dir; |
d5a80031 BC |
1199 | } |
1200 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 | 1201 | |
ccdc7bf9 SO |
1202 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1203 | if (r == NULL) { | |
1204 | status = -ENODEV; | |
39f1b565 | 1205 | goto free_master; |
ccdc7bf9 | 1206 | } |
1458d160 | 1207 | |
d5a80031 BC |
1208 | r->start += regs_offset; |
1209 | r->end += regs_offset; | |
1458d160 | 1210 | mcspi->phys = r->start; |
ccdc7bf9 | 1211 | |
1a77b127 | 1212 | mcspi->base = devm_request_and_ioremap(&pdev->dev, r); |
55c381e4 RK |
1213 | if (!mcspi->base) { |
1214 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); | |
1215 | status = -ENOMEM; | |
1a77b127 | 1216 | goto free_master; |
55c381e4 | 1217 | } |
ccdc7bf9 | 1218 | |
1f1a4384 | 1219 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1220 | |
1bd897f8 | 1221 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1222 | |
ccdc7bf9 SO |
1223 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
1224 | sizeof(struct omap2_mcspi_dma), | |
1225 | GFP_KERNEL); | |
1226 | ||
1227 | if (mcspi->dma_channels == NULL) | |
1a77b127 | 1228 | goto free_master; |
ccdc7bf9 | 1229 | |
1a5d8190 C |
1230 | for (i = 0; i < master->num_chipselect; i++) { |
1231 | char dma_ch_name[14]; | |
1232 | struct resource *dma_res; | |
1233 | ||
1234 | sprintf(dma_ch_name, "rx%d", i); | |
1235 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | |
1236 | dma_ch_name); | |
1237 | if (!dma_res) { | |
1238 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); | |
1239 | status = -ENODEV; | |
1240 | break; | |
1241 | } | |
1242 | ||
1a5d8190 C |
1243 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
1244 | sprintf(dma_ch_name, "tx%d", i); | |
1245 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | |
1246 | dma_ch_name); | |
1247 | if (!dma_res) { | |
1248 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); | |
1249 | status = -ENODEV; | |
1250 | break; | |
1251 | } | |
1252 | ||
1a5d8190 | 1253 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; |
ccdc7bf9 SO |
1254 | } |
1255 | ||
39f1b565 S |
1256 | if (status < 0) |
1257 | goto dma_chnl_free; | |
1258 | ||
ec155afa MP |
1259 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1260 | if (IS_ERR(pinctrl)) | |
1261 | dev_warn(&pdev->dev, | |
1262 | "pins are not configured from the driver\n"); | |
1263 | ||
27b5284c S |
1264 | pm_runtime_use_autosuspend(&pdev->dev); |
1265 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1266 | pm_runtime_enable(&pdev->dev); |
1267 | ||
1268 | if (status || omap2_mcspi_master_setup(mcspi) < 0) | |
39f1b565 | 1269 | goto disable_pm; |
ccdc7bf9 SO |
1270 | |
1271 | status = spi_register_master(master); | |
1272 | if (status < 0) | |
37a2d84a | 1273 | goto disable_pm; |
ccdc7bf9 SO |
1274 | |
1275 | return status; | |
1276 | ||
39f1b565 | 1277 | disable_pm: |
751c925c | 1278 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1279 | dma_chnl_free: |
1f1a4384 | 1280 | kfree(mcspi->dma_channels); |
39f1b565 | 1281 | free_master: |
37a2d84a | 1282 | spi_master_put(master); |
ccdc7bf9 SO |
1283 | return status; |
1284 | } | |
1285 | ||
7d6b6d83 | 1286 | static int __devexit omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 SO |
1287 | { |
1288 | struct spi_master *master; | |
1289 | struct omap2_mcspi *mcspi; | |
1290 | struct omap2_mcspi_dma *dma_channels; | |
ccdc7bf9 SO |
1291 | |
1292 | master = dev_get_drvdata(&pdev->dev); | |
1293 | mcspi = spi_master_get_devdata(master); | |
1294 | dma_channels = mcspi->dma_channels; | |
1295 | ||
a93a2029 | 1296 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1297 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 SO |
1298 | |
1299 | spi_unregister_master(master); | |
1300 | kfree(dma_channels); | |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
7e38c3c4 KS |
1305 | /* work with hotplug and coldplug */ |
1306 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1307 | ||
42ce7fd6 GC |
1308 | #ifdef CONFIG_SUSPEND |
1309 | /* | |
1310 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1311 | * unactive state when driver was suspend, then force it to unactive state at | |
1312 | * wake up. | |
1313 | */ | |
1314 | static int omap2_mcspi_resume(struct device *dev) | |
1315 | { | |
1316 | struct spi_master *master = dev_get_drvdata(dev); | |
1317 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1318 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1319 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 | 1320 | |
034d3dc9 | 1321 | pm_runtime_get_sync(mcspi->dev); |
1bd897f8 | 1322 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1323 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1324 | /* |
1325 | * We need to toggle CS state for OMAP take this | |
1326 | * change in account. | |
1327 | */ | |
af4e944d | 1328 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
42ce7fd6 | 1329 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
af4e944d | 1330 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
42ce7fd6 GC |
1331 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
1332 | } | |
1333 | } | |
034d3dc9 S |
1334 | pm_runtime_mark_last_busy(mcspi->dev); |
1335 | pm_runtime_put_autosuspend(mcspi->dev); | |
42ce7fd6 GC |
1336 | return 0; |
1337 | } | |
1338 | #else | |
1339 | #define omap2_mcspi_resume NULL | |
1340 | #endif | |
1341 | ||
1342 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1343 | .resume = omap2_mcspi_resume, | |
1f1a4384 | 1344 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1345 | }; |
1346 | ||
ccdc7bf9 SO |
1347 | static struct platform_driver omap2_mcspi_driver = { |
1348 | .driver = { | |
1349 | .name = "omap2_mcspi", | |
1350 | .owner = THIS_MODULE, | |
d5a80031 BC |
1351 | .pm = &omap2_mcspi_pm_ops, |
1352 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1353 | }, |
7d6b6d83 FB |
1354 | .probe = omap2_mcspi_probe, |
1355 | .remove = __devexit_p(omap2_mcspi_remove), | |
ccdc7bf9 SO |
1356 | }; |
1357 | ||
9fdca9df | 1358 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1359 | MODULE_LICENSE("GPL"); |