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ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/dma-mapping.h> | |
53741ed8 RK |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/omap-dma.h> | |
ccdc7bf9 SO |
33 | #include <linux/platform_device.h> |
34 | #include <linux/err.h> | |
35 | #include <linux/clk.h> | |
36 | #include <linux/io.h> | |
5a0e3ad6 | 37 | #include <linux/slab.h> |
1f1a4384 | 38 | #include <linux/pm_runtime.h> |
d5a80031 BC |
39 | #include <linux/of.h> |
40 | #include <linux/of_device.h> | |
ec155afa MP |
41 | #include <linux/pinctrl/consumer.h> |
42 | #include <linux/err.h> | |
ccdc7bf9 SO |
43 | |
44 | #include <linux/spi/spi.h> | |
45 | ||
2203747c | 46 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
47 | |
48 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
27b5284c | 49 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
50 | |
51 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
52 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
53 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
54 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
55 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
56 | #define OMAP2_MCSPI_SYST 0x24 | |
57 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
58 | ||
59 | /* per-channel banks, 0x14 bytes each, first is: */ | |
60 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
61 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
62 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
63 | #define OMAP2_MCSPI_TX0 0x38 | |
64 | #define OMAP2_MCSPI_RX0 0x3c | |
65 | ||
66 | /* per-register bitmasks: */ | |
67 | ||
7a8fa725 JH |
68 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
69 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
70 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 71 | |
7a8fa725 JH |
72 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
73 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 74 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 75 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 76 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
77 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
78 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 79 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
80 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
81 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
82 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
83 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
84 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
85 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
86 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
ccdc7bf9 | 87 | |
7a8fa725 JH |
88 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
89 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
90 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
ccdc7bf9 | 91 | |
7a8fa725 | 92 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
ccdc7bf9 | 93 | |
7a8fa725 | 94 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
95 | |
96 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
97 | struct omap2_mcspi_dma { | |
53741ed8 RK |
98 | struct dma_chan *dma_tx; |
99 | struct dma_chan *dma_rx; | |
ccdc7bf9 SO |
100 | |
101 | int dma_tx_sync_dev; | |
102 | int dma_rx_sync_dev; | |
103 | ||
104 | struct completion dma_tx_completion; | |
105 | struct completion dma_rx_completion; | |
106 | }; | |
107 | ||
108 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
109 | * cache operations; better heuristics consider wordsize and bitrate. | |
110 | */ | |
8b66c134 | 111 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
112 | |
113 | ||
1bd897f8 BC |
114 | /* |
115 | * Used for context save and restore, structure members to be updated whenever | |
116 | * corresponding registers are modified. | |
117 | */ | |
118 | struct omap2_mcspi_regs { | |
119 | u32 modulctrl; | |
120 | u32 wakeupenable; | |
121 | struct list_head cs; | |
122 | }; | |
123 | ||
ccdc7bf9 | 124 | struct omap2_mcspi { |
ccdc7bf9 | 125 | struct spi_master *master; |
ccdc7bf9 SO |
126 | /* Virtual base address of the controller */ |
127 | void __iomem *base; | |
e5480b73 | 128 | unsigned long phys; |
ccdc7bf9 SO |
129 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
130 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 131 | struct device *dev; |
1bd897f8 | 132 | struct omap2_mcspi_regs ctx; |
ccdc7bf9 SO |
133 | }; |
134 | ||
135 | struct omap2_mcspi_cs { | |
136 | void __iomem *base; | |
e5480b73 | 137 | unsigned long phys; |
ccdc7bf9 | 138 | int word_len; |
89c05372 | 139 | struct list_head node; |
a41ae1ad H |
140 | /* Context save and restore shadow register */ |
141 | u32 chconf0; | |
142 | }; | |
143 | ||
ccdc7bf9 SO |
144 | static inline void mcspi_write_reg(struct spi_master *master, |
145 | int idx, u32 val) | |
146 | { | |
147 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
148 | ||
149 | __raw_writel(val, mcspi->base + idx); | |
150 | } | |
151 | ||
152 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
153 | { | |
154 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
155 | ||
156 | return __raw_readl(mcspi->base + idx); | |
157 | } | |
158 | ||
159 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
160 | int idx, u32 val) | |
161 | { | |
162 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
163 | ||
164 | __raw_writel(val, cs->base + idx); | |
165 | } | |
166 | ||
167 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
168 | { | |
169 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
170 | ||
171 | return __raw_readl(cs->base + idx); | |
172 | } | |
173 | ||
a41ae1ad H |
174 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
175 | { | |
176 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
177 | ||
178 | return cs->chconf0; | |
179 | } | |
180 | ||
181 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
182 | { | |
183 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
184 | ||
185 | cs->chconf0 = val; | |
186 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 187 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
188 | } |
189 | ||
ccdc7bf9 SO |
190 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
191 | int is_read, int enable) | |
192 | { | |
193 | u32 l, rw; | |
194 | ||
a41ae1ad | 195 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
196 | |
197 | if (is_read) /* 1 is read, 0 write */ | |
198 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
199 | else | |
200 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
201 | ||
af4e944d S |
202 | if (enable) |
203 | l |= rw; | |
204 | else | |
205 | l &= ~rw; | |
206 | ||
a41ae1ad | 207 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
208 | } |
209 | ||
210 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
211 | { | |
212 | u32 l; | |
213 | ||
214 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; | |
215 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); | |
4743a0f8 RT |
216 | /* Flash post-writes */ |
217 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
218 | } |
219 | ||
220 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) | |
221 | { | |
222 | u32 l; | |
223 | ||
a41ae1ad | 224 | l = mcspi_cached_chconf0(spi); |
af4e944d S |
225 | if (cs_active) |
226 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
227 | else | |
228 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
229 | ||
a41ae1ad | 230 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
231 | } |
232 | ||
233 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
234 | { | |
1bd897f8 BC |
235 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
236 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
237 | u32 l; |
238 | ||
1bd897f8 BC |
239 | /* |
240 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
241 | * to single-channel master mode |
242 | */ | |
243 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
244 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
245 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 246 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 247 | |
1bd897f8 | 248 | ctx->modulctrl = l; |
a41ae1ad H |
249 | } |
250 | ||
251 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) | |
252 | { | |
1bd897f8 BC |
253 | struct spi_master *spi_cntrl = mcspi->master; |
254 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
255 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
256 | |
257 | /* McSPI: context restore */ | |
1bd897f8 BC |
258 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
259 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 260 | |
1bd897f8 | 261 | list_for_each_entry(cs, &ctx->cs, node) |
89c05372 | 262 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad | 263 | } |
ccdc7bf9 | 264 | |
5fda88f5 S |
265 | static int omap2_prepare_transfer(struct spi_master *master) |
266 | { | |
267 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
268 | ||
269 | pm_runtime_get_sync(mcspi->dev); | |
270 | return 0; | |
271 | } | |
272 | ||
273 | static int omap2_unprepare_transfer(struct spi_master *master) | |
274 | { | |
275 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
276 | ||
277 | pm_runtime_mark_last_busy(mcspi->dev); | |
278 | pm_runtime_put_autosuspend(mcspi->dev); | |
279 | return 0; | |
280 | } | |
281 | ||
2764c500 IK |
282 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
283 | { | |
284 | unsigned long timeout; | |
285 | ||
286 | timeout = jiffies + msecs_to_jiffies(1000); | |
287 | while (!(__raw_readl(reg) & bit)) { | |
288 | if (time_after(jiffies, timeout)) | |
289 | return -1; | |
290 | cpu_relax(); | |
291 | } | |
292 | return 0; | |
293 | } | |
294 | ||
53741ed8 RK |
295 | static void omap2_mcspi_rx_callback(void *data) |
296 | { | |
297 | struct spi_device *spi = data; | |
298 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
299 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
300 | ||
301 | complete(&mcspi_dma->dma_rx_completion); | |
302 | ||
303 | /* We must disable the DMA RX request */ | |
304 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
305 | } | |
306 | ||
307 | static void omap2_mcspi_tx_callback(void *data) | |
308 | { | |
309 | struct spi_device *spi = data; | |
310 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
311 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
312 | ||
313 | complete(&mcspi_dma->dma_tx_completion); | |
314 | ||
315 | /* We must disable the DMA TX request */ | |
316 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
317 | } | |
318 | ||
d7b4394e S |
319 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
320 | struct spi_transfer *xfer, | |
321 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
322 | { |
323 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 324 | struct omap2_mcspi_dma *mcspi_dma; |
8c7494a5 | 325 | unsigned int count; |
ccdc7bf9 SO |
326 | u8 * rx; |
327 | const u8 * tx; | |
2764c500 | 328 | void __iomem *chstat_reg; |
d7b4394e | 329 | struct omap2_mcspi_cs *cs = spi->controller_state; |
ccdc7bf9 SO |
330 | |
331 | mcspi = spi_master_get_devdata(spi->master); | |
332 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e | 333 | count = xfer->len; |
ccdc7bf9 | 334 | |
d7b4394e S |
335 | rx = xfer->rx_buf; |
336 | tx = xfer->tx_buf; | |
2764c500 IK |
337 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
338 | ||
d7b4394e | 339 | if (mcspi_dma->dma_tx) { |
53741ed8 RK |
340 | struct dma_async_tx_descriptor *tx; |
341 | struct scatterlist sg; | |
342 | ||
343 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
344 | ||
345 | sg_init_table(&sg, 1); | |
346 | sg_dma_address(&sg) = xfer->tx_dma; | |
347 | sg_dma_len(&sg) = xfer->len; | |
348 | ||
349 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, | |
d7b4394e | 350 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
53741ed8 RK |
351 | if (tx) { |
352 | tx->callback = omap2_mcspi_tx_callback; | |
353 | tx->callback_param = spi; | |
354 | dmaengine_submit(tx); | |
355 | } else { | |
356 | /* FIXME: fall back to PIO? */ | |
357 | } | |
358 | } | |
d7b4394e S |
359 | dma_async_issue_pending(mcspi_dma->dma_tx); |
360 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
361 | ||
362 | wait_for_completion(&mcspi_dma->dma_tx_completion); | |
363 | dma_unmap_single(mcspi->dev, xfer->tx_dma, count, | |
364 | DMA_TO_DEVICE); | |
365 | ||
366 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
367 | if (rx == NULL) { | |
368 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
369 | OMAP2_MCSPI_CHSTAT_TXS) < 0) | |
370 | dev_err(&spi->dev, "TXS timed out\n"); | |
371 | else if (mcspi_wait_for_reg_bit(chstat_reg, | |
372 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
373 | dev_err(&spi->dev, "EOT timed out\n"); | |
374 | } | |
375 | } | |
53741ed8 | 376 | |
d7b4394e S |
377 | static unsigned |
378 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
379 | struct dma_slave_config cfg, | |
380 | unsigned es) | |
381 | { | |
382 | struct omap2_mcspi *mcspi; | |
383 | struct omap2_mcspi_dma *mcspi_dma; | |
384 | unsigned int count; | |
385 | u32 l; | |
386 | int elements = 0; | |
387 | int word_len, element_count; | |
388 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
389 | mcspi = spi_master_get_devdata(spi->master); | |
390 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
391 | count = xfer->len; | |
392 | word_len = cs->word_len; | |
393 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 394 | |
d7b4394e S |
395 | if (word_len <= 8) |
396 | element_count = count; | |
397 | else if (word_len <= 16) | |
398 | element_count = count >> 1; | |
399 | else /* word_len <= 32 */ | |
400 | element_count = count >> 2; | |
401 | ||
402 | if (mcspi_dma->dma_rx) { | |
53741ed8 RK |
403 | struct dma_async_tx_descriptor *tx; |
404 | struct scatterlist sg; | |
405 | size_t len = xfer->len - es; | |
406 | ||
407 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
408 | ||
409 | if (l & OMAP2_MCSPI_CHCONF_TURBO) | |
410 | len -= es; | |
411 | ||
412 | sg_init_table(&sg, 1); | |
413 | sg_dma_address(&sg) = xfer->rx_dma; | |
414 | sg_dma_len(&sg) = len; | |
415 | ||
416 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, | |
d7b4394e S |
417 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | |
418 | DMA_CTRL_ACK); | |
53741ed8 RK |
419 | if (tx) { |
420 | tx->callback = omap2_mcspi_rx_callback; | |
421 | tx->callback_param = spi; | |
422 | dmaengine_submit(tx); | |
423 | } else { | |
d7b4394e | 424 | /* FIXME: fall back to PIO? */ |
2764c500 | 425 | } |
ccdc7bf9 SO |
426 | } |
427 | ||
d7b4394e S |
428 | dma_async_issue_pending(mcspi_dma->dma_rx); |
429 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 430 | |
d7b4394e S |
431 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
432 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, | |
433 | DMA_FROM_DEVICE); | |
434 | omap2_mcspi_set_enable(spi, 0); | |
53741ed8 | 435 | |
d7b4394e | 436 | elements = element_count - 1; |
4743a0f8 | 437 | |
d7b4394e S |
438 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
439 | elements--; | |
4743a0f8 | 440 | |
57c5c28d | 441 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
d7b4394e | 442 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
57c5c28d EN |
443 | u32 w; |
444 | ||
445 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
446 | if (word_len <= 8) | |
d7b4394e | 447 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 448 | else if (word_len <= 16) |
d7b4394e | 449 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 450 | else /* word_len <= 32 */ |
d7b4394e | 451 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 452 | } else { |
d7b4394e S |
453 | dev_err(&spi->dev, "DMA RX penultimate word empty"); |
454 | count -= (word_len <= 8) ? 2 : | |
455 | (word_len <= 16) ? 4 : | |
456 | /* word_len <= 32 */ 8; | |
457 | omap2_mcspi_set_enable(spi, 1); | |
458 | return count; | |
57c5c28d | 459 | } |
ccdc7bf9 | 460 | } |
d7b4394e S |
461 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
462 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
463 | u32 w; | |
464 | ||
465 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
466 | if (word_len <= 8) | |
467 | ((u8 *)xfer->rx_buf)[elements] = w; | |
468 | else if (word_len <= 16) | |
469 | ((u16 *)xfer->rx_buf)[elements] = w; | |
470 | else /* word_len <= 32 */ | |
471 | ((u32 *)xfer->rx_buf)[elements] = w; | |
472 | } else { | |
473 | dev_err(&spi->dev, "DMA RX last word empty"); | |
474 | count -= (word_len <= 8) ? 1 : | |
475 | (word_len <= 16) ? 2 : | |
476 | /* word_len <= 32 */ 4; | |
477 | } | |
478 | omap2_mcspi_set_enable(spi, 1); | |
479 | return count; | |
480 | } | |
481 | ||
482 | static unsigned | |
483 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
484 | { | |
485 | struct omap2_mcspi *mcspi; | |
486 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
487 | struct omap2_mcspi_dma *mcspi_dma; | |
488 | unsigned int count; | |
489 | u32 l; | |
490 | u8 *rx; | |
491 | const u8 *tx; | |
492 | struct dma_slave_config cfg; | |
493 | enum dma_slave_buswidth width; | |
494 | unsigned es; | |
495 | ||
496 | mcspi = spi_master_get_devdata(spi->master); | |
497 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
498 | l = mcspi_cached_chconf0(spi); | |
499 | ||
500 | ||
501 | if (cs->word_len <= 8) { | |
502 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
503 | es = 1; | |
504 | } else if (cs->word_len <= 16) { | |
505 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
506 | es = 2; | |
507 | } else { | |
508 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
509 | es = 4; | |
510 | } | |
511 | ||
512 | memset(&cfg, 0, sizeof(cfg)); | |
513 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
514 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
515 | cfg.src_addr_width = width; | |
516 | cfg.dst_addr_width = width; | |
517 | cfg.src_maxburst = 1; | |
518 | cfg.dst_maxburst = 1; | |
519 | ||
520 | rx = xfer->rx_buf; | |
521 | tx = xfer->tx_buf; | |
522 | ||
523 | count = xfer->len; | |
524 | ||
525 | if (tx != NULL) | |
526 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
527 | ||
528 | if (rx != NULL) | |
529 | return omap2_mcspi_rx_dma(spi, xfer, cfg, es); | |
530 | ||
ccdc7bf9 SO |
531 | return count; |
532 | } | |
533 | ||
ccdc7bf9 SO |
534 | static unsigned |
535 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
536 | { | |
537 | struct omap2_mcspi *mcspi; | |
538 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
539 | unsigned int count, c; | |
540 | u32 l; | |
541 | void __iomem *base = cs->base; | |
542 | void __iomem *tx_reg; | |
543 | void __iomem *rx_reg; | |
544 | void __iomem *chstat_reg; | |
545 | int word_len; | |
546 | ||
547 | mcspi = spi_master_get_devdata(spi->master); | |
548 | count = xfer->len; | |
549 | c = count; | |
550 | word_len = cs->word_len; | |
551 | ||
a41ae1ad | 552 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
553 | |
554 | /* We store the pre-calculated register addresses on stack to speed | |
555 | * up the transfer loop. */ | |
556 | tx_reg = base + OMAP2_MCSPI_TX0; | |
557 | rx_reg = base + OMAP2_MCSPI_RX0; | |
558 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
559 | ||
adef658d MJ |
560 | if (c < (word_len>>3)) |
561 | return 0; | |
562 | ||
ccdc7bf9 SO |
563 | if (word_len <= 8) { |
564 | u8 *rx; | |
565 | const u8 *tx; | |
566 | ||
567 | rx = xfer->rx_buf; | |
568 | tx = xfer->tx_buf; | |
569 | ||
570 | do { | |
feed9bab | 571 | c -= 1; |
ccdc7bf9 SO |
572 | if (tx != NULL) { |
573 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
574 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
575 | dev_err(&spi->dev, "TXS timed out\n"); | |
576 | goto out; | |
577 | } | |
079a176d | 578 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 579 | word_len, *tx); |
ccdc7bf9 SO |
580 | __raw_writel(*tx++, tx_reg); |
581 | } | |
582 | if (rx != NULL) { | |
583 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
584 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
585 | dev_err(&spi->dev, "RXS timed out\n"); | |
586 | goto out; | |
587 | } | |
4743a0f8 RT |
588 | |
589 | if (c == 1 && tx == NULL && | |
590 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
591 | omap2_mcspi_set_enable(spi, 0); | |
592 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 593 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 594 | word_len, *(rx - 1)); |
4743a0f8 RT |
595 | if (mcspi_wait_for_reg_bit(chstat_reg, |
596 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
597 | dev_err(&spi->dev, | |
598 | "RXS timed out\n"); | |
599 | goto out; | |
600 | } | |
601 | c = 0; | |
602 | } else if (c == 0 && tx == NULL) { | |
603 | omap2_mcspi_set_enable(spi, 0); | |
604 | } | |
605 | ||
ccdc7bf9 | 606 | *rx++ = __raw_readl(rx_reg); |
079a176d | 607 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 608 | word_len, *(rx - 1)); |
ccdc7bf9 | 609 | } |
95c5c3ab | 610 | } while (c); |
ccdc7bf9 SO |
611 | } else if (word_len <= 16) { |
612 | u16 *rx; | |
613 | const u16 *tx; | |
614 | ||
615 | rx = xfer->rx_buf; | |
616 | tx = xfer->tx_buf; | |
617 | do { | |
feed9bab | 618 | c -= 2; |
ccdc7bf9 SO |
619 | if (tx != NULL) { |
620 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
621 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
622 | dev_err(&spi->dev, "TXS timed out\n"); | |
623 | goto out; | |
624 | } | |
079a176d | 625 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 626 | word_len, *tx); |
ccdc7bf9 SO |
627 | __raw_writel(*tx++, tx_reg); |
628 | } | |
629 | if (rx != NULL) { | |
630 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
631 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
632 | dev_err(&spi->dev, "RXS timed out\n"); | |
633 | goto out; | |
634 | } | |
4743a0f8 RT |
635 | |
636 | if (c == 2 && tx == NULL && | |
637 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
638 | omap2_mcspi_set_enable(spi, 0); | |
639 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 640 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 641 | word_len, *(rx - 1)); |
4743a0f8 RT |
642 | if (mcspi_wait_for_reg_bit(chstat_reg, |
643 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
644 | dev_err(&spi->dev, | |
645 | "RXS timed out\n"); | |
646 | goto out; | |
647 | } | |
648 | c = 0; | |
649 | } else if (c == 0 && tx == NULL) { | |
650 | omap2_mcspi_set_enable(spi, 0); | |
651 | } | |
652 | ||
ccdc7bf9 | 653 | *rx++ = __raw_readl(rx_reg); |
079a176d | 654 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 655 | word_len, *(rx - 1)); |
ccdc7bf9 | 656 | } |
95c5c3ab | 657 | } while (c >= 2); |
ccdc7bf9 SO |
658 | } else if (word_len <= 32) { |
659 | u32 *rx; | |
660 | const u32 *tx; | |
661 | ||
662 | rx = xfer->rx_buf; | |
663 | tx = xfer->tx_buf; | |
664 | do { | |
feed9bab | 665 | c -= 4; |
ccdc7bf9 SO |
666 | if (tx != NULL) { |
667 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
668 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
669 | dev_err(&spi->dev, "TXS timed out\n"); | |
670 | goto out; | |
671 | } | |
079a176d | 672 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 673 | word_len, *tx); |
ccdc7bf9 SO |
674 | __raw_writel(*tx++, tx_reg); |
675 | } | |
676 | if (rx != NULL) { | |
677 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
678 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
679 | dev_err(&spi->dev, "RXS timed out\n"); | |
680 | goto out; | |
681 | } | |
4743a0f8 RT |
682 | |
683 | if (c == 4 && tx == NULL && | |
684 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
685 | omap2_mcspi_set_enable(spi, 0); | |
686 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 687 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 688 | word_len, *(rx - 1)); |
4743a0f8 RT |
689 | if (mcspi_wait_for_reg_bit(chstat_reg, |
690 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
691 | dev_err(&spi->dev, | |
692 | "RXS timed out\n"); | |
693 | goto out; | |
694 | } | |
695 | c = 0; | |
696 | } else if (c == 0 && tx == NULL) { | |
697 | omap2_mcspi_set_enable(spi, 0); | |
698 | } | |
699 | ||
ccdc7bf9 | 700 | *rx++ = __raw_readl(rx_reg); |
079a176d | 701 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 702 | word_len, *(rx - 1)); |
ccdc7bf9 | 703 | } |
95c5c3ab | 704 | } while (c >= 4); |
ccdc7bf9 SO |
705 | } |
706 | ||
707 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
708 | if (xfer->rx_buf == NULL) { | |
709 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
710 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
711 | dev_err(&spi->dev, "TXS timed out\n"); | |
712 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
713 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
714 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
715 | |
716 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
717 | * otherwise these rx datas will affect the direct following | |
718 | * RX_ONLY transfer. | |
719 | */ | |
720 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
721 | } |
722 | out: | |
4743a0f8 | 723 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
724 | return count - c; |
725 | } | |
726 | ||
57d9c10d HH |
727 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
728 | { | |
729 | u32 div; | |
730 | ||
731 | for (div = 0; div < 15; div++) | |
732 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
733 | return div; | |
734 | ||
735 | return 15; | |
736 | } | |
737 | ||
ccdc7bf9 SO |
738 | /* called only when no transfer is active to this device */ |
739 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
740 | struct spi_transfer *t) | |
741 | { | |
742 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
743 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 744 | struct spi_master *spi_cntrl; |
ccdc7bf9 SO |
745 | u32 l = 0, div = 0; |
746 | u8 word_len = spi->bits_per_word; | |
9bd4517d | 747 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
748 | |
749 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 750 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
751 | |
752 | if (t != NULL && t->bits_per_word) | |
753 | word_len = t->bits_per_word; | |
754 | ||
755 | cs->word_len = word_len; | |
756 | ||
9bd4517d SE |
757 | if (t && t->speed_hz) |
758 | speed_hz = t->speed_hz; | |
759 | ||
57d9c10d HH |
760 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
761 | div = omap2_mcspi_calc_divisor(speed_hz); | |
ccdc7bf9 | 762 | |
a41ae1ad | 763 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
764 | |
765 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
766 | * REVISIT: this controller could support SPI_3WIRE mode. | |
767 | */ | |
768 | l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1); | |
769 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
770 | ||
771 | /* wordlength */ | |
772 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
773 | l |= (word_len - 1) << 7; | |
774 | ||
775 | /* set chipselect polarity; manage with FORCE */ | |
776 | if (!(spi->mode & SPI_CS_HIGH)) | |
777 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
778 | else | |
779 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
780 | ||
781 | /* set clock divisor */ | |
782 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
783 | l |= div << 2; | |
784 | ||
785 | /* set SPI mode 0..3 */ | |
786 | if (spi->mode & SPI_CPOL) | |
787 | l |= OMAP2_MCSPI_CHCONF_POL; | |
788 | else | |
789 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
790 | if (spi->mode & SPI_CPHA) | |
791 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
792 | else | |
793 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
794 | ||
a41ae1ad | 795 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
796 | |
797 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", | |
57d9c10d | 798 | OMAP2_MCSPI_MAX_FREQ >> div, |
ccdc7bf9 SO |
799 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
800 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
ccdc7bf9 SO |
805 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
806 | { | |
807 | struct spi_master *master = spi->master; | |
808 | struct omap2_mcspi *mcspi; | |
809 | struct omap2_mcspi_dma *mcspi_dma; | |
53741ed8 RK |
810 | dma_cap_mask_t mask; |
811 | unsigned sig; | |
ccdc7bf9 SO |
812 | |
813 | mcspi = spi_master_get_devdata(master); | |
814 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
815 | ||
53741ed8 RK |
816 | init_completion(&mcspi_dma->dma_rx_completion); |
817 | init_completion(&mcspi_dma->dma_tx_completion); | |
818 | ||
819 | dma_cap_zero(mask); | |
820 | dma_cap_set(DMA_SLAVE, mask); | |
53741ed8 RK |
821 | sig = mcspi_dma->dma_rx_sync_dev; |
822 | mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
823 | if (!mcspi_dma->dma_rx) { | |
824 | dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n"); | |
ccdc7bf9 SO |
825 | return -EAGAIN; |
826 | } | |
827 | ||
53741ed8 RK |
828 | sig = mcspi_dma->dma_tx_sync_dev; |
829 | mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
830 | if (!mcspi_dma->dma_tx) { | |
831 | dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n"); | |
832 | dma_release_channel(mcspi_dma->dma_rx); | |
833 | mcspi_dma->dma_rx = NULL; | |
ccdc7bf9 SO |
834 | return -EAGAIN; |
835 | } | |
836 | ||
ccdc7bf9 SO |
837 | return 0; |
838 | } | |
839 | ||
ccdc7bf9 SO |
840 | static int omap2_mcspi_setup(struct spi_device *spi) |
841 | { | |
842 | int ret; | |
1bd897f8 BC |
843 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
844 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
845 | struct omap2_mcspi_dma *mcspi_dma; |
846 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
847 | ||
7d077197 | 848 | if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { |
ccdc7bf9 SO |
849 | dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", |
850 | spi->bits_per_word); | |
851 | return -EINVAL; | |
852 | } | |
853 | ||
ccdc7bf9 SO |
854 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
855 | ||
856 | if (!cs) { | |
10aa5a35 | 857 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
858 | if (!cs) |
859 | return -ENOMEM; | |
860 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 861 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
a41ae1ad | 862 | cs->chconf0 = 0; |
ccdc7bf9 | 863 | spi->controller_state = cs; |
89c05372 | 864 | /* Link this to context save list */ |
1bd897f8 | 865 | list_add_tail(&cs->node, &ctx->cs); |
ccdc7bf9 SO |
866 | } |
867 | ||
8c7494a5 | 868 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 SO |
869 | ret = omap2_mcspi_request_dma(spi); |
870 | if (ret < 0) | |
871 | return ret; | |
872 | } | |
873 | ||
034d3dc9 | 874 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
875 | if (ret < 0) |
876 | return ret; | |
a41ae1ad | 877 | |
86eeb6fe | 878 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
879 | pm_runtime_mark_last_busy(mcspi->dev); |
880 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
881 | |
882 | return ret; | |
883 | } | |
884 | ||
885 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
886 | { | |
887 | struct omap2_mcspi *mcspi; | |
888 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 889 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
890 | |
891 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 892 | |
5e774943 SE |
893 | if (spi->controller_state) { |
894 | /* Unlink controller state from context save list */ | |
895 | cs = spi->controller_state; | |
896 | list_del(&cs->node); | |
89c05372 | 897 | |
10aa5a35 | 898 | kfree(cs); |
5e774943 | 899 | } |
ccdc7bf9 | 900 | |
99f1a43f SE |
901 | if (spi->chip_select < spi->master->num_chipselect) { |
902 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
903 | ||
53741ed8 RK |
904 | if (mcspi_dma->dma_rx) { |
905 | dma_release_channel(mcspi_dma->dma_rx); | |
906 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 907 | } |
53741ed8 RK |
908 | if (mcspi_dma->dma_tx) { |
909 | dma_release_channel(mcspi_dma->dma_tx); | |
910 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 911 | } |
ccdc7bf9 SO |
912 | } |
913 | } | |
914 | ||
5fda88f5 | 915 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) |
ccdc7bf9 | 916 | { |
ccdc7bf9 SO |
917 | |
918 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 919 | * -- although this controller would gladly |
ccdc7bf9 SO |
920 | * arbitrate among multiple channels. This corresponds to "single |
921 | * channel" master mode. As a side effect, we need to manage the | |
922 | * chipselect with the FORCE bit ... CS != channel enable. | |
923 | */ | |
ccdc7bf9 | 924 | |
5fda88f5 S |
925 | struct spi_device *spi; |
926 | struct spi_transfer *t = NULL; | |
927 | int cs_active = 0; | |
928 | struct omap2_mcspi_cs *cs; | |
929 | struct omap2_mcspi_device_config *cd; | |
930 | int par_override = 0; | |
931 | int status = 0; | |
932 | u32 chconf; | |
ccdc7bf9 | 933 | |
5fda88f5 S |
934 | spi = m->spi; |
935 | cs = spi->controller_state; | |
936 | cd = spi->controller_data; | |
ccdc7bf9 | 937 | |
5fda88f5 S |
938 | omap2_mcspi_set_enable(spi, 1); |
939 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
940 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | |
941 | status = -EINVAL; | |
942 | break; | |
943 | } | |
944 | if (par_override || t->speed_hz || t->bits_per_word) { | |
945 | par_override = 1; | |
946 | status = omap2_mcspi_setup_transfer(spi, t); | |
947 | if (status < 0) | |
948 | break; | |
949 | if (!t->speed_hz && !t->bits_per_word) | |
950 | par_override = 0; | |
951 | } | |
4743a0f8 | 952 | |
5fda88f5 S |
953 | if (!cs_active) { |
954 | omap2_mcspi_force_cs(spi, 1); | |
955 | cs_active = 1; | |
956 | } | |
4743a0f8 | 957 | |
5fda88f5 S |
958 | chconf = mcspi_cached_chconf0(spi); |
959 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
960 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
ccdc7bf9 | 961 | |
5fda88f5 S |
962 | if (t->tx_buf == NULL) |
963 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
964 | else if (t->rx_buf == NULL) | |
965 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
ccdc7bf9 | 966 | |
5fda88f5 S |
967 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
968 | /* Turbo mode is for more than one word */ | |
969 | if (t->len > ((cs->word_len + 7) >> 3)) | |
970 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
971 | } | |
ccdc7bf9 | 972 | |
5fda88f5 | 973 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 974 | |
5fda88f5 S |
975 | if (t->len) { |
976 | unsigned count; | |
977 | ||
978 | /* RX_ONLY mode needs dummy data in TX reg */ | |
979 | if (t->tx_buf == NULL) | |
980 | __raw_writel(0, cs->base | |
981 | + OMAP2_MCSPI_TX0); | |
ccdc7bf9 | 982 | |
5fda88f5 S |
983 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) |
984 | count = omap2_mcspi_txrx_dma(spi, t); | |
985 | else | |
986 | count = omap2_mcspi_txrx_pio(spi, t); | |
987 | m->actual_length += count; | |
ccdc7bf9 | 988 | |
5fda88f5 S |
989 | if (count != t->len) { |
990 | status = -EIO; | |
991 | break; | |
ccdc7bf9 SO |
992 | } |
993 | } | |
994 | ||
5fda88f5 S |
995 | if (t->delay_usecs) |
996 | udelay(t->delay_usecs); | |
ccdc7bf9 | 997 | |
5fda88f5 S |
998 | /* ignore the "leave it on after last xfer" hint */ |
999 | if (t->cs_change) { | |
ccdc7bf9 | 1000 | omap2_mcspi_force_cs(spi, 0); |
5fda88f5 S |
1001 | cs_active = 0; |
1002 | } | |
1003 | } | |
1004 | /* Restore defaults if they were overriden */ | |
1005 | if (par_override) { | |
1006 | par_override = 0; | |
1007 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1008 | } | |
ccdc7bf9 | 1009 | |
5fda88f5 S |
1010 | if (cs_active) |
1011 | omap2_mcspi_force_cs(spi, 0); | |
ccdc7bf9 | 1012 | |
5fda88f5 | 1013 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1014 | |
5fda88f5 | 1015 | m->status = status; |
1f1a4384 | 1016 | |
ccdc7bf9 SO |
1017 | } |
1018 | ||
5fda88f5 S |
1019 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
1020 | struct spi_message *m) | |
ccdc7bf9 SO |
1021 | { |
1022 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 SO |
1023 | struct spi_transfer *t; |
1024 | ||
5fda88f5 | 1025 | mcspi = spi_master_get_devdata(master); |
ccdc7bf9 SO |
1026 | m->actual_length = 0; |
1027 | m->status = 0; | |
1028 | ||
1029 | /* reject invalid messages and transfers */ | |
5fda88f5 | 1030 | if (list_empty(&m->transfers)) |
ccdc7bf9 SO |
1031 | return -EINVAL; |
1032 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
1033 | const void *tx_buf = t->tx_buf; | |
1034 | void *rx_buf = t->rx_buf; | |
1035 | unsigned len = t->len; | |
1036 | ||
1037 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ | |
1038 | || (len && !(rx_buf || tx_buf)) | |
1039 | || (t->bits_per_word && | |
1040 | ( t->bits_per_word < 4 | |
1041 | || t->bits_per_word > 32))) { | |
5fda88f5 | 1042 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
ccdc7bf9 SO |
1043 | t->speed_hz, |
1044 | len, | |
1045 | tx_buf ? "tx" : "", | |
1046 | rx_buf ? "rx" : "", | |
1047 | t->bits_per_word); | |
1048 | return -EINVAL; | |
1049 | } | |
57d9c10d | 1050 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { |
5fda88f5 | 1051 | dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", |
57d9c10d HH |
1052 | t->speed_hz, |
1053 | OMAP2_MCSPI_MAX_FREQ >> 15); | |
ccdc7bf9 SO |
1054 | return -EINVAL; |
1055 | } | |
1056 | ||
1057 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) | |
1058 | continue; | |
1059 | ||
ccdc7bf9 | 1060 | if (tx_buf != NULL) { |
5fda88f5 | 1061 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, |
ccdc7bf9 | 1062 | len, DMA_TO_DEVICE); |
5fda88f5 S |
1063 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { |
1064 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1065 | 'T', len); |
1066 | return -EINVAL; | |
1067 | } | |
1068 | } | |
1069 | if (rx_buf != NULL) { | |
5fda88f5 | 1070 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, |
ccdc7bf9 | 1071 | DMA_FROM_DEVICE); |
5fda88f5 S |
1072 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { |
1073 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1074 | 'R', len); |
1075 | if (tx_buf != NULL) | |
5fda88f5 | 1076 | dma_unmap_single(mcspi->dev, t->tx_dma, |
ccdc7bf9 SO |
1077 | len, DMA_TO_DEVICE); |
1078 | return -EINVAL; | |
1079 | } | |
1080 | } | |
1081 | } | |
1082 | ||
5fda88f5 S |
1083 | omap2_mcspi_work(mcspi, m); |
1084 | spi_finalize_current_message(master); | |
ccdc7bf9 SO |
1085 | return 0; |
1086 | } | |
1087 | ||
24ab3275 | 1088 | static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1089 | { |
1090 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1091 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1092 | int ret = 0; |
ccdc7bf9 | 1093 | |
034d3dc9 | 1094 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1095 | if (ret < 0) |
1096 | return ret; | |
ddb22195 | 1097 | |
39f8052d S |
1098 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
1099 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); | |
1100 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; | |
ccdc7bf9 SO |
1101 | |
1102 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1103 | pm_runtime_mark_last_busy(mcspi->dev); |
1104 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1105 | return 0; |
1106 | } | |
1107 | ||
1f1a4384 G |
1108 | static int omap_mcspi_runtime_resume(struct device *dev) |
1109 | { | |
1110 | struct omap2_mcspi *mcspi; | |
1111 | struct spi_master *master; | |
1112 | ||
1113 | master = dev_get_drvdata(dev); | |
1114 | mcspi = spi_master_get_devdata(master); | |
1115 | omap2_mcspi_restore_ctx(mcspi); | |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
d5a80031 BC |
1120 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1121 | .regs_offset = 0, | |
1122 | }; | |
1123 | ||
1124 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1125 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1126 | }; | |
1127 | ||
1128 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1129 | { | |
1130 | .compatible = "ti,omap2-mcspi", | |
1131 | .data = &omap2_pdata, | |
1132 | }, | |
1133 | { | |
1134 | .compatible = "ti,omap4-mcspi", | |
1135 | .data = &omap4_pdata, | |
1136 | }, | |
1137 | { }, | |
1138 | }; | |
1139 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1140 | |
7d6b6d83 | 1141 | static int __devinit omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1142 | { |
1143 | struct spi_master *master; | |
83a01e72 | 1144 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1145 | struct omap2_mcspi *mcspi; |
1146 | struct resource *r; | |
1147 | int status = 0, i; | |
d5a80031 BC |
1148 | u32 regs_offset = 0; |
1149 | static int bus_num = 1; | |
1150 | struct device_node *node = pdev->dev.of_node; | |
1151 | const struct of_device_id *match; | |
ec155afa | 1152 | struct pinctrl *pinctrl; |
ccdc7bf9 SO |
1153 | |
1154 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1155 | if (master == NULL) { | |
1156 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1157 | return -ENOMEM; | |
1158 | } | |
1159 | ||
e7db06b5 DB |
1160 | /* the spi->mode bits understood by this driver: */ |
1161 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
1162 | ||
ccdc7bf9 | 1163 | master->setup = omap2_mcspi_setup; |
5fda88f5 S |
1164 | master->prepare_transfer_hardware = omap2_prepare_transfer; |
1165 | master->unprepare_transfer_hardware = omap2_unprepare_transfer; | |
1166 | master->transfer_one_message = omap2_mcspi_transfer_one_message; | |
ccdc7bf9 | 1167 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 BC |
1168 | master->dev.of_node = node; |
1169 | ||
1170 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); | |
1171 | if (match) { | |
1172 | u32 num_cs = 1; /* default number of chipselect */ | |
1173 | pdata = match->data; | |
1174 | ||
1175 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1176 | master->num_chipselect = num_cs; | |
1177 | master->bus_num = bus_num++; | |
1178 | } else { | |
1179 | pdata = pdev->dev.platform_data; | |
1180 | master->num_chipselect = pdata->num_cs; | |
1181 | if (pdev->id != -1) | |
1182 | master->bus_num = pdev->id; | |
1183 | } | |
1184 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 SO |
1185 | |
1186 | dev_set_drvdata(&pdev->dev, master); | |
1187 | ||
1188 | mcspi = spi_master_get_devdata(master); | |
1189 | mcspi->master = master; | |
1190 | ||
1191 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1192 | if (r == NULL) { | |
1193 | status = -ENODEV; | |
39f1b565 | 1194 | goto free_master; |
ccdc7bf9 | 1195 | } |
1458d160 | 1196 | |
d5a80031 BC |
1197 | r->start += regs_offset; |
1198 | r->end += regs_offset; | |
1458d160 | 1199 | mcspi->phys = r->start; |
ccdc7bf9 | 1200 | |
1a77b127 | 1201 | mcspi->base = devm_request_and_ioremap(&pdev->dev, r); |
55c381e4 RK |
1202 | if (!mcspi->base) { |
1203 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); | |
1204 | status = -ENOMEM; | |
1a77b127 | 1205 | goto free_master; |
55c381e4 | 1206 | } |
ccdc7bf9 | 1207 | |
1f1a4384 | 1208 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1209 | |
1bd897f8 | 1210 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1211 | |
ccdc7bf9 SO |
1212 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
1213 | sizeof(struct omap2_mcspi_dma), | |
1214 | GFP_KERNEL); | |
1215 | ||
1216 | if (mcspi->dma_channels == NULL) | |
1a77b127 | 1217 | goto free_master; |
ccdc7bf9 | 1218 | |
1a5d8190 C |
1219 | for (i = 0; i < master->num_chipselect; i++) { |
1220 | char dma_ch_name[14]; | |
1221 | struct resource *dma_res; | |
1222 | ||
1223 | sprintf(dma_ch_name, "rx%d", i); | |
1224 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | |
1225 | dma_ch_name); | |
1226 | if (!dma_res) { | |
1227 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); | |
1228 | status = -ENODEV; | |
1229 | break; | |
1230 | } | |
1231 | ||
1a5d8190 C |
1232 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
1233 | sprintf(dma_ch_name, "tx%d", i); | |
1234 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, | |
1235 | dma_ch_name); | |
1236 | if (!dma_res) { | |
1237 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); | |
1238 | status = -ENODEV; | |
1239 | break; | |
1240 | } | |
1241 | ||
1a5d8190 | 1242 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; |
ccdc7bf9 SO |
1243 | } |
1244 | ||
39f1b565 S |
1245 | if (status < 0) |
1246 | goto dma_chnl_free; | |
1247 | ||
ec155afa MP |
1248 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1249 | if (IS_ERR(pinctrl)) | |
1250 | dev_warn(&pdev->dev, | |
1251 | "pins are not configured from the driver\n"); | |
1252 | ||
27b5284c S |
1253 | pm_runtime_use_autosuspend(&pdev->dev); |
1254 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1255 | pm_runtime_enable(&pdev->dev); |
1256 | ||
1257 | if (status || omap2_mcspi_master_setup(mcspi) < 0) | |
39f1b565 | 1258 | goto disable_pm; |
ccdc7bf9 SO |
1259 | |
1260 | status = spi_register_master(master); | |
1261 | if (status < 0) | |
37a2d84a | 1262 | goto disable_pm; |
ccdc7bf9 SO |
1263 | |
1264 | return status; | |
1265 | ||
39f1b565 | 1266 | disable_pm: |
751c925c | 1267 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1268 | dma_chnl_free: |
1f1a4384 | 1269 | kfree(mcspi->dma_channels); |
39f1b565 | 1270 | free_master: |
37a2d84a | 1271 | spi_master_put(master); |
ccdc7bf9 SO |
1272 | return status; |
1273 | } | |
1274 | ||
7d6b6d83 | 1275 | static int __devexit omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 SO |
1276 | { |
1277 | struct spi_master *master; | |
1278 | struct omap2_mcspi *mcspi; | |
1279 | struct omap2_mcspi_dma *dma_channels; | |
ccdc7bf9 SO |
1280 | |
1281 | master = dev_get_drvdata(&pdev->dev); | |
1282 | mcspi = spi_master_get_devdata(master); | |
1283 | dma_channels = mcspi->dma_channels; | |
1284 | ||
a93a2029 | 1285 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1286 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 SO |
1287 | |
1288 | spi_unregister_master(master); | |
1289 | kfree(dma_channels); | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
7e38c3c4 KS |
1294 | /* work with hotplug and coldplug */ |
1295 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1296 | ||
42ce7fd6 GC |
1297 | #ifdef CONFIG_SUSPEND |
1298 | /* | |
1299 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1300 | * unactive state when driver was suspend, then force it to unactive state at | |
1301 | * wake up. | |
1302 | */ | |
1303 | static int omap2_mcspi_resume(struct device *dev) | |
1304 | { | |
1305 | struct spi_master *master = dev_get_drvdata(dev); | |
1306 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1307 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1308 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 | 1309 | |
034d3dc9 | 1310 | pm_runtime_get_sync(mcspi->dev); |
1bd897f8 | 1311 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1312 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1313 | /* |
1314 | * We need to toggle CS state for OMAP take this | |
1315 | * change in account. | |
1316 | */ | |
af4e944d | 1317 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
42ce7fd6 | 1318 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
af4e944d | 1319 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
42ce7fd6 GC |
1320 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
1321 | } | |
1322 | } | |
034d3dc9 S |
1323 | pm_runtime_mark_last_busy(mcspi->dev); |
1324 | pm_runtime_put_autosuspend(mcspi->dev); | |
42ce7fd6 GC |
1325 | return 0; |
1326 | } | |
1327 | #else | |
1328 | #define omap2_mcspi_resume NULL | |
1329 | #endif | |
1330 | ||
1331 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1332 | .resume = omap2_mcspi_resume, | |
1f1a4384 | 1333 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1334 | }; |
1335 | ||
ccdc7bf9 SO |
1336 | static struct platform_driver omap2_mcspi_driver = { |
1337 | .driver = { | |
1338 | .name = "omap2_mcspi", | |
1339 | .owner = THIS_MODULE, | |
d5a80031 BC |
1340 | .pm = &omap2_mcspi_pm_ops, |
1341 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1342 | }, |
7d6b6d83 FB |
1343 | .probe = omap2_mcspi_probe, |
1344 | .remove = __devexit_p(omap2_mcspi_remove), | |
ccdc7bf9 SO |
1345 | }; |
1346 | ||
9fdca9df | 1347 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1348 | MODULE_LICENSE("GPL"); |