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ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
ccdc7bf9 SO |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
ccdc7bf9 SO |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/dma-mapping.h> | |
53741ed8 RK |
25 | #include <linux/dmaengine.h> |
26 | #include <linux/omap-dma.h> | |
ccdc7bf9 SO |
27 | #include <linux/platform_device.h> |
28 | #include <linux/err.h> | |
29 | #include <linux/clk.h> | |
30 | #include <linux/io.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
1f1a4384 | 32 | #include <linux/pm_runtime.h> |
d5a80031 BC |
33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | |
d33f473d | 35 | #include <linux/gcd.h> |
ccdc7bf9 SO |
36 | |
37 | #include <linux/spi/spi.h> | |
38 | ||
2203747c | 39 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
40 | |
41 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
faee9b05 | 42 | #define OMAP2_MCSPI_MAX_DIVIDER 4096 |
d33f473d IS |
43 | #define OMAP2_MCSPI_MAX_FIFODEPTH 64 |
44 | #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF | |
27b5284c | 45 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
46 | |
47 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
48 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
49 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
50 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
51 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
52 | #define OMAP2_MCSPI_SYST 0x24 | |
53 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
d33f473d | 54 | #define OMAP2_MCSPI_XFERLEVEL 0x7c |
ccdc7bf9 SO |
55 | |
56 | /* per-channel banks, 0x14 bytes each, first is: */ | |
57 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
58 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
59 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
60 | #define OMAP2_MCSPI_TX0 0x38 | |
61 | #define OMAP2_MCSPI_RX0 0x3c | |
62 | ||
63 | /* per-register bitmasks: */ | |
d33f473d | 64 | #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) |
ccdc7bf9 | 65 | |
7a8fa725 JH |
66 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
67 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
68 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 69 | |
7a8fa725 JH |
70 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
71 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 72 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 73 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 74 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
75 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
76 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 77 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
78 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
79 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
80 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
81 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
82 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
83 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
84 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
d33f473d IS |
85 | #define OMAP2_MCSPI_CHCONF_FFET BIT(27) |
86 | #define OMAP2_MCSPI_CHCONF_FFER BIT(28) | |
faee9b05 | 87 | #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) |
ccdc7bf9 | 88 | |
7a8fa725 JH |
89 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
90 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
91 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
d33f473d | 92 | #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) |
ccdc7bf9 | 93 | |
7a8fa725 | 94 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
faee9b05 | 95 | #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) |
ccdc7bf9 | 96 | |
7a8fa725 | 97 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
98 | |
99 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
100 | struct omap2_mcspi_dma { | |
53741ed8 RK |
101 | struct dma_chan *dma_tx; |
102 | struct dma_chan *dma_rx; | |
ccdc7bf9 SO |
103 | |
104 | int dma_tx_sync_dev; | |
105 | int dma_rx_sync_dev; | |
106 | ||
107 | struct completion dma_tx_completion; | |
108 | struct completion dma_rx_completion; | |
74f3aaad MP |
109 | |
110 | char dma_rx_ch_name[14]; | |
111 | char dma_tx_ch_name[14]; | |
ccdc7bf9 SO |
112 | }; |
113 | ||
114 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
115 | * cache operations; better heuristics consider wordsize and bitrate. | |
116 | */ | |
8b66c134 | 117 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
118 | |
119 | ||
1bd897f8 BC |
120 | /* |
121 | * Used for context save and restore, structure members to be updated whenever | |
122 | * corresponding registers are modified. | |
123 | */ | |
124 | struct omap2_mcspi_regs { | |
125 | u32 modulctrl; | |
126 | u32 wakeupenable; | |
127 | struct list_head cs; | |
128 | }; | |
129 | ||
ccdc7bf9 | 130 | struct omap2_mcspi { |
ccdc7bf9 | 131 | struct spi_master *master; |
ccdc7bf9 SO |
132 | /* Virtual base address of the controller */ |
133 | void __iomem *base; | |
e5480b73 | 134 | unsigned long phys; |
ccdc7bf9 SO |
135 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
136 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 137 | struct device *dev; |
1bd897f8 | 138 | struct omap2_mcspi_regs ctx; |
d33f473d | 139 | int fifo_depth; |
0384e90b | 140 | unsigned int pin_dir:1; |
ccdc7bf9 SO |
141 | }; |
142 | ||
143 | struct omap2_mcspi_cs { | |
144 | void __iomem *base; | |
e5480b73 | 145 | unsigned long phys; |
ccdc7bf9 | 146 | int word_len; |
97ca0d6c | 147 | u16 mode; |
89c05372 | 148 | struct list_head node; |
a41ae1ad | 149 | /* Context save and restore shadow register */ |
faee9b05 | 150 | u32 chconf0, chctrl0; |
a41ae1ad H |
151 | }; |
152 | ||
ccdc7bf9 SO |
153 | static inline void mcspi_write_reg(struct spi_master *master, |
154 | int idx, u32 val) | |
155 | { | |
156 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
157 | ||
21b2ce5e | 158 | writel_relaxed(val, mcspi->base + idx); |
ccdc7bf9 SO |
159 | } |
160 | ||
161 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
162 | { | |
163 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
164 | ||
21b2ce5e | 165 | return readl_relaxed(mcspi->base + idx); |
ccdc7bf9 SO |
166 | } |
167 | ||
168 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
169 | int idx, u32 val) | |
170 | { | |
171 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
172 | ||
21b2ce5e | 173 | writel_relaxed(val, cs->base + idx); |
ccdc7bf9 SO |
174 | } |
175 | ||
176 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
177 | { | |
178 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
179 | ||
21b2ce5e | 180 | return readl_relaxed(cs->base + idx); |
ccdc7bf9 SO |
181 | } |
182 | ||
a41ae1ad H |
183 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
184 | { | |
185 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
186 | ||
187 | return cs->chconf0; | |
188 | } | |
189 | ||
190 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
191 | { | |
192 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
193 | ||
194 | cs->chconf0 = val; | |
195 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 196 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
197 | } |
198 | ||
56cd5c15 IS |
199 | static inline int mcspi_bytes_per_word(int word_len) |
200 | { | |
201 | if (word_len <= 8) | |
202 | return 1; | |
203 | else if (word_len <= 16) | |
204 | return 2; | |
205 | else /* word_len <= 32 */ | |
206 | return 4; | |
207 | } | |
208 | ||
ccdc7bf9 SO |
209 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
210 | int is_read, int enable) | |
211 | { | |
212 | u32 l, rw; | |
213 | ||
a41ae1ad | 214 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
215 | |
216 | if (is_read) /* 1 is read, 0 write */ | |
217 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
218 | else | |
219 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
220 | ||
af4e944d S |
221 | if (enable) |
222 | l |= rw; | |
223 | else | |
224 | l &= ~rw; | |
225 | ||
a41ae1ad | 226 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
227 | } |
228 | ||
229 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
230 | { | |
faee9b05 | 231 | struct omap2_mcspi_cs *cs = spi->controller_state; |
ccdc7bf9 SO |
232 | u32 l; |
233 | ||
faee9b05 SS |
234 | l = cs->chctrl0; |
235 | if (enable) | |
236 | l |= OMAP2_MCSPI_CHCTRL_EN; | |
237 | else | |
238 | l &= ~OMAP2_MCSPI_CHCTRL_EN; | |
239 | cs->chctrl0 = l; | |
240 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
4743a0f8 RT |
241 | /* Flash post-writes */ |
242 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
243 | } |
244 | ||
245 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) | |
246 | { | |
247 | u32 l; | |
248 | ||
a41ae1ad | 249 | l = mcspi_cached_chconf0(spi); |
af4e944d S |
250 | if (cs_active) |
251 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
252 | else | |
253 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
254 | ||
a41ae1ad | 255 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
256 | } |
257 | ||
258 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
259 | { | |
1bd897f8 BC |
260 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
261 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
262 | u32 l; |
263 | ||
1bd897f8 BC |
264 | /* |
265 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
266 | * to single-channel master mode |
267 | */ | |
268 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
269 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
270 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 271 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 272 | |
1bd897f8 | 273 | ctx->modulctrl = l; |
a41ae1ad H |
274 | } |
275 | ||
d33f473d IS |
276 | static void omap2_mcspi_set_fifo(const struct spi_device *spi, |
277 | struct spi_transfer *t, int enable) | |
278 | { | |
279 | struct spi_master *master = spi->master; | |
280 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
281 | struct omap2_mcspi *mcspi; | |
282 | unsigned int wcnt; | |
5db542ed | 283 | int max_fifo_depth, fifo_depth, bytes_per_word; |
d33f473d IS |
284 | u32 chconf, xferlevel; |
285 | ||
286 | mcspi = spi_master_get_devdata(master); | |
287 | ||
288 | chconf = mcspi_cached_chconf0(spi); | |
289 | if (enable) { | |
290 | bytes_per_word = mcspi_bytes_per_word(cs->word_len); | |
291 | if (t->len % bytes_per_word != 0) | |
292 | goto disable_fifo; | |
293 | ||
5db542ed IS |
294 | if (t->rx_buf != NULL && t->tx_buf != NULL) |
295 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; | |
296 | else | |
297 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; | |
298 | ||
299 | fifo_depth = gcd(t->len, max_fifo_depth); | |
d33f473d IS |
300 | if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) |
301 | goto disable_fifo; | |
302 | ||
303 | wcnt = t->len / bytes_per_word; | |
304 | if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) | |
305 | goto disable_fifo; | |
306 | ||
307 | xferlevel = wcnt << 16; | |
308 | if (t->rx_buf != NULL) { | |
309 | chconf |= OMAP2_MCSPI_CHCONF_FFER; | |
310 | xferlevel |= (fifo_depth - 1) << 8; | |
5db542ed IS |
311 | } |
312 | if (t->tx_buf != NULL) { | |
d33f473d IS |
313 | chconf |= OMAP2_MCSPI_CHCONF_FFET; |
314 | xferlevel |= fifo_depth - 1; | |
315 | } | |
316 | ||
317 | mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); | |
318 | mcspi_write_chconf0(spi, chconf); | |
319 | mcspi->fifo_depth = fifo_depth; | |
320 | ||
321 | return; | |
322 | } | |
323 | ||
324 | disable_fifo: | |
325 | if (t->rx_buf != NULL) | |
326 | chconf &= ~OMAP2_MCSPI_CHCONF_FFER; | |
3d0763c0 JV |
327 | |
328 | if (t->tx_buf != NULL) | |
d33f473d IS |
329 | chconf &= ~OMAP2_MCSPI_CHCONF_FFET; |
330 | ||
331 | mcspi_write_chconf0(spi, chconf); | |
332 | mcspi->fifo_depth = 0; | |
333 | } | |
334 | ||
a41ae1ad H |
335 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
336 | { | |
1bd897f8 BC |
337 | struct spi_master *spi_cntrl = mcspi->master; |
338 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
339 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
340 | |
341 | /* McSPI: context restore */ | |
1bd897f8 BC |
342 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
343 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 344 | |
1bd897f8 | 345 | list_for_each_entry(cs, &ctx->cs, node) |
21b2ce5e | 346 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad | 347 | } |
ccdc7bf9 | 348 | |
2764c500 IK |
349 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
350 | { | |
351 | unsigned long timeout; | |
352 | ||
353 | timeout = jiffies + msecs_to_jiffies(1000); | |
21b2ce5e | 354 | while (!(readl_relaxed(reg) & bit)) { |
ff23fa3b | 355 | if (time_after(jiffies, timeout)) { |
21b2ce5e | 356 | if (!(readl_relaxed(reg) & bit)) |
ff23fa3b SAS |
357 | return -ETIMEDOUT; |
358 | else | |
359 | return 0; | |
360 | } | |
2764c500 IK |
361 | cpu_relax(); |
362 | } | |
363 | return 0; | |
364 | } | |
365 | ||
53741ed8 RK |
366 | static void omap2_mcspi_rx_callback(void *data) |
367 | { | |
368 | struct spi_device *spi = data; | |
369 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
370 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
371 | ||
53741ed8 RK |
372 | /* We must disable the DMA RX request */ |
373 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
830379e0 FB |
374 | |
375 | complete(&mcspi_dma->dma_rx_completion); | |
53741ed8 RK |
376 | } |
377 | ||
378 | static void omap2_mcspi_tx_callback(void *data) | |
379 | { | |
380 | struct spi_device *spi = data; | |
381 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
382 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
383 | ||
53741ed8 RK |
384 | /* We must disable the DMA TX request */ |
385 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
830379e0 FB |
386 | |
387 | complete(&mcspi_dma->dma_tx_completion); | |
53741ed8 RK |
388 | } |
389 | ||
d7b4394e S |
390 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
391 | struct spi_transfer *xfer, | |
392 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
393 | { |
394 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 395 | struct omap2_mcspi_dma *mcspi_dma; |
8c7494a5 | 396 | unsigned int count; |
ccdc7bf9 SO |
397 | |
398 | mcspi = spi_master_get_devdata(spi->master); | |
399 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e | 400 | count = xfer->len; |
ccdc7bf9 | 401 | |
d7b4394e | 402 | if (mcspi_dma->dma_tx) { |
53741ed8 RK |
403 | struct dma_async_tx_descriptor *tx; |
404 | struct scatterlist sg; | |
405 | ||
406 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
407 | ||
408 | sg_init_table(&sg, 1); | |
409 | sg_dma_address(&sg) = xfer->tx_dma; | |
410 | sg_dma_len(&sg) = xfer->len; | |
411 | ||
412 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, | |
d7b4394e | 413 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
53741ed8 RK |
414 | if (tx) { |
415 | tx->callback = omap2_mcspi_tx_callback; | |
416 | tx->callback_param = spi; | |
417 | dmaengine_submit(tx); | |
418 | } else { | |
419 | /* FIXME: fall back to PIO? */ | |
420 | } | |
421 | } | |
d7b4394e S |
422 | dma_async_issue_pending(mcspi_dma->dma_tx); |
423 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
424 | ||
d7b4394e | 425 | } |
53741ed8 | 426 | |
d7b4394e S |
427 | static unsigned |
428 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
429 | struct dma_slave_config cfg, | |
430 | unsigned es) | |
431 | { | |
432 | struct omap2_mcspi *mcspi; | |
433 | struct omap2_mcspi_dma *mcspi_dma; | |
d33f473d | 434 | unsigned int count, dma_count; |
d7b4394e S |
435 | u32 l; |
436 | int elements = 0; | |
437 | int word_len, element_count; | |
438 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
439 | mcspi = spi_master_get_devdata(spi->master); | |
440 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
441 | count = xfer->len; | |
d33f473d IS |
442 | dma_count = xfer->len; |
443 | ||
444 | if (mcspi->fifo_depth == 0) | |
445 | dma_count -= es; | |
446 | ||
d7b4394e S |
447 | word_len = cs->word_len; |
448 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 449 | |
d7b4394e S |
450 | if (word_len <= 8) |
451 | element_count = count; | |
452 | else if (word_len <= 16) | |
453 | element_count = count >> 1; | |
454 | else /* word_len <= 32 */ | |
455 | element_count = count >> 2; | |
456 | ||
457 | if (mcspi_dma->dma_rx) { | |
53741ed8 RK |
458 | struct dma_async_tx_descriptor *tx; |
459 | struct scatterlist sg; | |
53741ed8 RK |
460 | |
461 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
462 | ||
d33f473d IS |
463 | if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) |
464 | dma_count -= es; | |
53741ed8 RK |
465 | |
466 | sg_init_table(&sg, 1); | |
467 | sg_dma_address(&sg) = xfer->rx_dma; | |
d33f473d | 468 | sg_dma_len(&sg) = dma_count; |
53741ed8 RK |
469 | |
470 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, | |
d7b4394e S |
471 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | |
472 | DMA_CTRL_ACK); | |
53741ed8 RK |
473 | if (tx) { |
474 | tx->callback = omap2_mcspi_rx_callback; | |
475 | tx->callback_param = spi; | |
476 | dmaengine_submit(tx); | |
477 | } else { | |
d7b4394e | 478 | /* FIXME: fall back to PIO? */ |
2764c500 | 479 | } |
ccdc7bf9 SO |
480 | } |
481 | ||
d7b4394e S |
482 | dma_async_issue_pending(mcspi_dma->dma_rx); |
483 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 484 | |
d7b4394e S |
485 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
486 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, | |
487 | DMA_FROM_DEVICE); | |
d33f473d IS |
488 | |
489 | if (mcspi->fifo_depth > 0) | |
490 | return count; | |
491 | ||
d7b4394e | 492 | omap2_mcspi_set_enable(spi, 0); |
53741ed8 | 493 | |
d7b4394e | 494 | elements = element_count - 1; |
4743a0f8 | 495 | |
d7b4394e S |
496 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
497 | elements--; | |
4743a0f8 | 498 | |
57c5c28d | 499 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
d7b4394e | 500 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
57c5c28d EN |
501 | u32 w; |
502 | ||
503 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
504 | if (word_len <= 8) | |
d7b4394e | 505 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 506 | else if (word_len <= 16) |
d7b4394e | 507 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 508 | else /* word_len <= 32 */ |
d7b4394e | 509 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 510 | } else { |
56cd5c15 | 511 | int bytes_per_word = mcspi_bytes_per_word(word_len); |
a1829d2b | 512 | dev_err(&spi->dev, "DMA RX penultimate word empty\n"); |
56cd5c15 | 513 | count -= (bytes_per_word << 1); |
d7b4394e S |
514 | omap2_mcspi_set_enable(spi, 1); |
515 | return count; | |
57c5c28d | 516 | } |
ccdc7bf9 | 517 | } |
d7b4394e S |
518 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
519 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
520 | u32 w; | |
521 | ||
522 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
523 | if (word_len <= 8) | |
524 | ((u8 *)xfer->rx_buf)[elements] = w; | |
525 | else if (word_len <= 16) | |
526 | ((u16 *)xfer->rx_buf)[elements] = w; | |
527 | else /* word_len <= 32 */ | |
528 | ((u32 *)xfer->rx_buf)[elements] = w; | |
529 | } else { | |
a1829d2b | 530 | dev_err(&spi->dev, "DMA RX last word empty\n"); |
56cd5c15 | 531 | count -= mcspi_bytes_per_word(word_len); |
d7b4394e S |
532 | } |
533 | omap2_mcspi_set_enable(spi, 1); | |
534 | return count; | |
535 | } | |
536 | ||
537 | static unsigned | |
538 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
539 | { | |
540 | struct omap2_mcspi *mcspi; | |
541 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
542 | struct omap2_mcspi_dma *mcspi_dma; | |
543 | unsigned int count; | |
544 | u32 l; | |
545 | u8 *rx; | |
546 | const u8 *tx; | |
547 | struct dma_slave_config cfg; | |
548 | enum dma_slave_buswidth width; | |
549 | unsigned es; | |
d33f473d | 550 | u32 burst; |
e47a682a | 551 | void __iomem *chstat_reg; |
d33f473d IS |
552 | void __iomem *irqstat_reg; |
553 | int wait_res; | |
d7b4394e S |
554 | |
555 | mcspi = spi_master_get_devdata(spi->master); | |
556 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
557 | l = mcspi_cached_chconf0(spi); | |
558 | ||
559 | ||
560 | if (cs->word_len <= 8) { | |
561 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
562 | es = 1; | |
563 | } else if (cs->word_len <= 16) { | |
564 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
565 | es = 2; | |
566 | } else { | |
567 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
568 | es = 4; | |
569 | } | |
570 | ||
d33f473d IS |
571 | count = xfer->len; |
572 | burst = 1; | |
573 | ||
574 | if (mcspi->fifo_depth > 0) { | |
575 | if (count > mcspi->fifo_depth) | |
576 | burst = mcspi->fifo_depth / es; | |
577 | else | |
578 | burst = count / es; | |
579 | } | |
580 | ||
d7b4394e S |
581 | memset(&cfg, 0, sizeof(cfg)); |
582 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
583 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
584 | cfg.src_addr_width = width; | |
585 | cfg.dst_addr_width = width; | |
d33f473d IS |
586 | cfg.src_maxburst = burst; |
587 | cfg.dst_maxburst = burst; | |
d7b4394e S |
588 | |
589 | rx = xfer->rx_buf; | |
590 | tx = xfer->tx_buf; | |
591 | ||
d7b4394e S |
592 | if (tx != NULL) |
593 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
594 | ||
595 | if (rx != NULL) | |
e47a682a S |
596 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); |
597 | ||
598 | if (tx != NULL) { | |
e47a682a S |
599 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
600 | dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, | |
601 | DMA_TO_DEVICE); | |
602 | ||
d33f473d IS |
603 | if (mcspi->fifo_depth > 0) { |
604 | irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; | |
605 | ||
606 | if (mcspi_wait_for_reg_bit(irqstat_reg, | |
607 | OMAP2_MCSPI_IRQSTATUS_EOW) < 0) | |
608 | dev_err(&spi->dev, "EOW timed out\n"); | |
609 | ||
610 | mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, | |
611 | OMAP2_MCSPI_IRQSTATUS_EOW); | |
612 | } | |
613 | ||
e47a682a S |
614 | /* for TX_ONLY mode, be sure all words have shifted out */ |
615 | if (rx == NULL) { | |
d33f473d IS |
616 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
617 | if (mcspi->fifo_depth > 0) { | |
618 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
619 | OMAP2_MCSPI_CHSTAT_TXFFE); | |
620 | if (wait_res < 0) | |
621 | dev_err(&spi->dev, "TXFFE timed out\n"); | |
622 | } else { | |
623 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
624 | OMAP2_MCSPI_CHSTAT_TXS); | |
625 | if (wait_res < 0) | |
626 | dev_err(&spi->dev, "TXS timed out\n"); | |
627 | } | |
628 | if (wait_res >= 0 && | |
629 | (mcspi_wait_for_reg_bit(chstat_reg, | |
630 | OMAP2_MCSPI_CHSTAT_EOT) < 0)) | |
e47a682a S |
631 | dev_err(&spi->dev, "EOT timed out\n"); |
632 | } | |
633 | } | |
ccdc7bf9 SO |
634 | return count; |
635 | } | |
636 | ||
ccdc7bf9 SO |
637 | static unsigned |
638 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
639 | { | |
640 | struct omap2_mcspi *mcspi; | |
641 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
642 | unsigned int count, c; | |
643 | u32 l; | |
644 | void __iomem *base = cs->base; | |
645 | void __iomem *tx_reg; | |
646 | void __iomem *rx_reg; | |
647 | void __iomem *chstat_reg; | |
648 | int word_len; | |
649 | ||
650 | mcspi = spi_master_get_devdata(spi->master); | |
651 | count = xfer->len; | |
652 | c = count; | |
653 | word_len = cs->word_len; | |
654 | ||
a41ae1ad | 655 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
656 | |
657 | /* We store the pre-calculated register addresses on stack to speed | |
658 | * up the transfer loop. */ | |
659 | tx_reg = base + OMAP2_MCSPI_TX0; | |
660 | rx_reg = base + OMAP2_MCSPI_RX0; | |
661 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
662 | ||
adef658d MJ |
663 | if (c < (word_len>>3)) |
664 | return 0; | |
665 | ||
ccdc7bf9 SO |
666 | if (word_len <= 8) { |
667 | u8 *rx; | |
668 | const u8 *tx; | |
669 | ||
670 | rx = xfer->rx_buf; | |
671 | tx = xfer->tx_buf; | |
672 | ||
673 | do { | |
feed9bab | 674 | c -= 1; |
ccdc7bf9 SO |
675 | if (tx != NULL) { |
676 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
677 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
678 | dev_err(&spi->dev, "TXS timed out\n"); | |
679 | goto out; | |
680 | } | |
079a176d | 681 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 682 | word_len, *tx); |
21b2ce5e | 683 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
684 | } |
685 | if (rx != NULL) { | |
686 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
687 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
688 | dev_err(&spi->dev, "RXS timed out\n"); | |
689 | goto out; | |
690 | } | |
4743a0f8 RT |
691 | |
692 | if (c == 1 && tx == NULL && | |
693 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
694 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 695 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 696 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 697 | word_len, *(rx - 1)); |
4743a0f8 RT |
698 | if (mcspi_wait_for_reg_bit(chstat_reg, |
699 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
700 | dev_err(&spi->dev, | |
701 | "RXS timed out\n"); | |
702 | goto out; | |
703 | } | |
704 | c = 0; | |
705 | } else if (c == 0 && tx == NULL) { | |
706 | omap2_mcspi_set_enable(spi, 0); | |
707 | } | |
708 | ||
21b2ce5e | 709 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 710 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 711 | word_len, *(rx - 1)); |
ccdc7bf9 | 712 | } |
95c5c3ab | 713 | } while (c); |
ccdc7bf9 SO |
714 | } else if (word_len <= 16) { |
715 | u16 *rx; | |
716 | const u16 *tx; | |
717 | ||
718 | rx = xfer->rx_buf; | |
719 | tx = xfer->tx_buf; | |
720 | do { | |
feed9bab | 721 | c -= 2; |
ccdc7bf9 SO |
722 | if (tx != NULL) { |
723 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
724 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
725 | dev_err(&spi->dev, "TXS timed out\n"); | |
726 | goto out; | |
727 | } | |
079a176d | 728 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 729 | word_len, *tx); |
21b2ce5e | 730 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
731 | } |
732 | if (rx != NULL) { | |
733 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
734 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
735 | dev_err(&spi->dev, "RXS timed out\n"); | |
736 | goto out; | |
737 | } | |
4743a0f8 RT |
738 | |
739 | if (c == 2 && tx == NULL && | |
740 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
741 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 742 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 743 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 744 | word_len, *(rx - 1)); |
4743a0f8 RT |
745 | if (mcspi_wait_for_reg_bit(chstat_reg, |
746 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
747 | dev_err(&spi->dev, | |
748 | "RXS timed out\n"); | |
749 | goto out; | |
750 | } | |
751 | c = 0; | |
752 | } else if (c == 0 && tx == NULL) { | |
753 | omap2_mcspi_set_enable(spi, 0); | |
754 | } | |
755 | ||
21b2ce5e | 756 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 757 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 758 | word_len, *(rx - 1)); |
ccdc7bf9 | 759 | } |
95c5c3ab | 760 | } while (c >= 2); |
ccdc7bf9 SO |
761 | } else if (word_len <= 32) { |
762 | u32 *rx; | |
763 | const u32 *tx; | |
764 | ||
765 | rx = xfer->rx_buf; | |
766 | tx = xfer->tx_buf; | |
767 | do { | |
feed9bab | 768 | c -= 4; |
ccdc7bf9 SO |
769 | if (tx != NULL) { |
770 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
771 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
772 | dev_err(&spi->dev, "TXS timed out\n"); | |
773 | goto out; | |
774 | } | |
079a176d | 775 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 776 | word_len, *tx); |
21b2ce5e | 777 | writel_relaxed(*tx++, tx_reg); |
ccdc7bf9 SO |
778 | } |
779 | if (rx != NULL) { | |
780 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
781 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
782 | dev_err(&spi->dev, "RXS timed out\n"); | |
783 | goto out; | |
784 | } | |
4743a0f8 RT |
785 | |
786 | if (c == 4 && tx == NULL && | |
787 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
788 | omap2_mcspi_set_enable(spi, 0); | |
21b2ce5e | 789 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 790 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 791 | word_len, *(rx - 1)); |
4743a0f8 RT |
792 | if (mcspi_wait_for_reg_bit(chstat_reg, |
793 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
794 | dev_err(&spi->dev, | |
795 | "RXS timed out\n"); | |
796 | goto out; | |
797 | } | |
798 | c = 0; | |
799 | } else if (c == 0 && tx == NULL) { | |
800 | omap2_mcspi_set_enable(spi, 0); | |
801 | } | |
802 | ||
21b2ce5e | 803 | *rx++ = readl_relaxed(rx_reg); |
079a176d | 804 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 805 | word_len, *(rx - 1)); |
ccdc7bf9 | 806 | } |
95c5c3ab | 807 | } while (c >= 4); |
ccdc7bf9 SO |
808 | } |
809 | ||
810 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
811 | if (xfer->rx_buf == NULL) { | |
812 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
813 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
814 | dev_err(&spi->dev, "TXS timed out\n"); | |
815 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
816 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
817 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
818 | |
819 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
820 | * otherwise these rx datas will affect the direct following | |
821 | * RX_ONLY transfer. | |
822 | */ | |
823 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
824 | } |
825 | out: | |
4743a0f8 | 826 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
827 | return count - c; |
828 | } | |
829 | ||
57d9c10d HH |
830 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
831 | { | |
832 | u32 div; | |
833 | ||
834 | for (div = 0; div < 15; div++) | |
835 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
836 | return div; | |
837 | ||
838 | return 15; | |
839 | } | |
840 | ||
ccdc7bf9 SO |
841 | /* called only when no transfer is active to this device */ |
842 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
843 | struct spi_transfer *t) | |
844 | { | |
845 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
846 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 847 | struct spi_master *spi_cntrl; |
faee9b05 | 848 | u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; |
ccdc7bf9 | 849 | u8 word_len = spi->bits_per_word; |
9bd4517d | 850 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
851 | |
852 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 853 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
854 | |
855 | if (t != NULL && t->bits_per_word) | |
856 | word_len = t->bits_per_word; | |
857 | ||
858 | cs->word_len = word_len; | |
859 | ||
9bd4517d SE |
860 | if (t && t->speed_hz) |
861 | speed_hz = t->speed_hz; | |
862 | ||
57d9c10d | 863 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
faee9b05 SS |
864 | if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { |
865 | clkd = omap2_mcspi_calc_divisor(speed_hz); | |
866 | speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; | |
867 | clkg = 0; | |
868 | } else { | |
869 | div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; | |
870 | speed_hz = OMAP2_MCSPI_MAX_FREQ / div; | |
871 | clkd = (div - 1) & 0xf; | |
872 | extclk = (div - 1) >> 4; | |
873 | clkg = OMAP2_MCSPI_CHCONF_CLKG; | |
874 | } | |
ccdc7bf9 | 875 | |
a41ae1ad | 876 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
877 | |
878 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
879 | * REVISIT: this controller could support SPI_3WIRE mode. | |
880 | */ | |
2cd45179 | 881 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { |
0384e90b DM |
882 | l &= ~OMAP2_MCSPI_CHCONF_IS; |
883 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; | |
884 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
885 | } else { | |
886 | l |= OMAP2_MCSPI_CHCONF_IS; | |
887 | l |= OMAP2_MCSPI_CHCONF_DPE1; | |
888 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; | |
889 | } | |
ccdc7bf9 SO |
890 | |
891 | /* wordlength */ | |
892 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
893 | l |= (word_len - 1) << 7; | |
894 | ||
895 | /* set chipselect polarity; manage with FORCE */ | |
896 | if (!(spi->mode & SPI_CS_HIGH)) | |
897 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
898 | else | |
899 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
900 | ||
901 | /* set clock divisor */ | |
902 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
faee9b05 SS |
903 | l |= clkd << 2; |
904 | ||
905 | /* set clock granularity */ | |
906 | l &= ~OMAP2_MCSPI_CHCONF_CLKG; | |
907 | l |= clkg; | |
908 | if (clkg) { | |
909 | cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; | |
910 | cs->chctrl0 |= extclk << 8; | |
911 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); | |
912 | } | |
ccdc7bf9 SO |
913 | |
914 | /* set SPI mode 0..3 */ | |
915 | if (spi->mode & SPI_CPOL) | |
916 | l |= OMAP2_MCSPI_CHCONF_POL; | |
917 | else | |
918 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
919 | if (spi->mode & SPI_CPHA) | |
920 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
921 | else | |
922 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
923 | ||
a41ae1ad | 924 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 | 925 | |
97ca0d6c MG |
926 | cs->mode = spi->mode; |
927 | ||
ccdc7bf9 | 928 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
faee9b05 | 929 | speed_hz, |
ccdc7bf9 SO |
930 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
931 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
ddc5cdf1 TL |
936 | /* |
937 | * Note that we currently allow DMA only if we get a channel | |
938 | * for both rx and tx. Otherwise we'll do PIO for both rx and tx. | |
939 | */ | |
ccdc7bf9 SO |
940 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
941 | { | |
942 | struct spi_master *master = spi->master; | |
943 | struct omap2_mcspi *mcspi; | |
944 | struct omap2_mcspi_dma *mcspi_dma; | |
53741ed8 RK |
945 | dma_cap_mask_t mask; |
946 | unsigned sig; | |
ccdc7bf9 SO |
947 | |
948 | mcspi = spi_master_get_devdata(master); | |
949 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
950 | ||
53741ed8 RK |
951 | init_completion(&mcspi_dma->dma_rx_completion); |
952 | init_completion(&mcspi_dma->dma_tx_completion); | |
953 | ||
954 | dma_cap_zero(mask); | |
955 | dma_cap_set(DMA_SLAVE, mask); | |
53741ed8 | 956 | sig = mcspi_dma->dma_rx_sync_dev; |
74f3aaad MP |
957 | |
958 | mcspi_dma->dma_rx = | |
959 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
960 | &sig, &master->dev, | |
961 | mcspi_dma->dma_rx_ch_name); | |
ddc5cdf1 TL |
962 | if (!mcspi_dma->dma_rx) |
963 | goto no_dma; | |
ccdc7bf9 | 964 | |
53741ed8 | 965 | sig = mcspi_dma->dma_tx_sync_dev; |
74f3aaad MP |
966 | mcspi_dma->dma_tx = |
967 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
968 | &sig, &master->dev, | |
969 | mcspi_dma->dma_tx_ch_name); | |
970 | ||
53741ed8 | 971 | if (!mcspi_dma->dma_tx) { |
53741ed8 RK |
972 | dma_release_channel(mcspi_dma->dma_rx); |
973 | mcspi_dma->dma_rx = NULL; | |
ddc5cdf1 | 974 | goto no_dma; |
ccdc7bf9 SO |
975 | } |
976 | ||
ccdc7bf9 | 977 | return 0; |
ddc5cdf1 TL |
978 | |
979 | no_dma: | |
980 | dev_warn(&spi->dev, "not using DMA for McSPI\n"); | |
981 | return -EAGAIN; | |
ccdc7bf9 SO |
982 | } |
983 | ||
ccdc7bf9 SO |
984 | static int omap2_mcspi_setup(struct spi_device *spi) |
985 | { | |
986 | int ret; | |
1bd897f8 BC |
987 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
988 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
989 | struct omap2_mcspi_dma *mcspi_dma; |
990 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
991 | ||
ccdc7bf9 SO |
992 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
993 | ||
994 | if (!cs) { | |
10aa5a35 | 995 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
996 | if (!cs) |
997 | return -ENOMEM; | |
998 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 999 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
97ca0d6c | 1000 | cs->mode = 0; |
a41ae1ad | 1001 | cs->chconf0 = 0; |
faee9b05 | 1002 | cs->chctrl0 = 0; |
ccdc7bf9 | 1003 | spi->controller_state = cs; |
89c05372 | 1004 | /* Link this to context save list */ |
1bd897f8 | 1005 | list_add_tail(&cs->node, &ctx->cs); |
ccdc7bf9 SO |
1006 | } |
1007 | ||
8c7494a5 | 1008 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 | 1009 | ret = omap2_mcspi_request_dma(spi); |
ddc5cdf1 | 1010 | if (ret < 0 && ret != -EAGAIN) |
ccdc7bf9 SO |
1011 | return ret; |
1012 | } | |
1013 | ||
034d3dc9 | 1014 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1015 | if (ret < 0) |
1016 | return ret; | |
a41ae1ad | 1017 | |
86eeb6fe | 1018 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
1019 | pm_runtime_mark_last_busy(mcspi->dev); |
1020 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1021 | |
1022 | return ret; | |
1023 | } | |
1024 | ||
1025 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
1026 | { | |
1027 | struct omap2_mcspi *mcspi; | |
1028 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 1029 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
1030 | |
1031 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 1032 | |
5e774943 SE |
1033 | if (spi->controller_state) { |
1034 | /* Unlink controller state from context save list */ | |
1035 | cs = spi->controller_state; | |
1036 | list_del(&cs->node); | |
89c05372 | 1037 | |
10aa5a35 | 1038 | kfree(cs); |
5e774943 | 1039 | } |
ccdc7bf9 | 1040 | |
99f1a43f SE |
1041 | if (spi->chip_select < spi->master->num_chipselect) { |
1042 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
1043 | ||
53741ed8 RK |
1044 | if (mcspi_dma->dma_rx) { |
1045 | dma_release_channel(mcspi_dma->dma_rx); | |
1046 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 1047 | } |
53741ed8 RK |
1048 | if (mcspi_dma->dma_tx) { |
1049 | dma_release_channel(mcspi_dma->dma_tx); | |
1050 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 1051 | } |
ccdc7bf9 SO |
1052 | } |
1053 | } | |
1054 | ||
5fda88f5 | 1055 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) |
ccdc7bf9 | 1056 | { |
ccdc7bf9 SO |
1057 | |
1058 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 1059 | * -- although this controller would gladly |
ccdc7bf9 SO |
1060 | * arbitrate among multiple channels. This corresponds to "single |
1061 | * channel" master mode. As a side effect, we need to manage the | |
1062 | * chipselect with the FORCE bit ... CS != channel enable. | |
1063 | */ | |
ccdc7bf9 | 1064 | |
5fda88f5 S |
1065 | struct spi_device *spi; |
1066 | struct spi_transfer *t = NULL; | |
5cbc7ca9 | 1067 | struct spi_master *master; |
ddc5cdf1 | 1068 | struct omap2_mcspi_dma *mcspi_dma; |
5fda88f5 S |
1069 | int cs_active = 0; |
1070 | struct omap2_mcspi_cs *cs; | |
1071 | struct omap2_mcspi_device_config *cd; | |
1072 | int par_override = 0; | |
1073 | int status = 0; | |
1074 | u32 chconf; | |
ccdc7bf9 | 1075 | |
5fda88f5 | 1076 | spi = m->spi; |
5cbc7ca9 | 1077 | master = spi->master; |
ddc5cdf1 | 1078 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
5fda88f5 S |
1079 | cs = spi->controller_state; |
1080 | cd = spi->controller_data; | |
ccdc7bf9 | 1081 | |
97ca0d6c MG |
1082 | /* |
1083 | * The slave driver could have changed spi->mode in which case | |
1084 | * it will be different from cs->mode (the current hardware setup). | |
1085 | * If so, set par_override (even though its not a parity issue) so | |
1086 | * omap2_mcspi_setup_transfer will be called to configure the hardware | |
1087 | * with the correct mode on the first iteration of the loop below. | |
1088 | */ | |
1089 | if (spi->mode != cs->mode) | |
1090 | par_override = 1; | |
1091 | ||
d33f473d | 1092 | omap2_mcspi_set_enable(spi, 0); |
5fda88f5 S |
1093 | list_for_each_entry(t, &m->transfers, transfer_list) { |
1094 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | |
1095 | status = -EINVAL; | |
1096 | break; | |
1097 | } | |
2bd16e3e SS |
1098 | if (par_override || |
1099 | (t->speed_hz != spi->max_speed_hz) || | |
1100 | (t->bits_per_word != spi->bits_per_word)) { | |
5fda88f5 S |
1101 | par_override = 1; |
1102 | status = omap2_mcspi_setup_transfer(spi, t); | |
1103 | if (status < 0) | |
1104 | break; | |
2bd16e3e SS |
1105 | if (t->speed_hz == spi->max_speed_hz && |
1106 | t->bits_per_word == spi->bits_per_word) | |
5fda88f5 S |
1107 | par_override = 0; |
1108 | } | |
5cbc7ca9 MB |
1109 | if (cd && cd->cs_per_word) { |
1110 | chconf = mcspi->ctx.modulctrl; | |
1111 | chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1112 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1113 | mcspi->ctx.modulctrl = | |
1114 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1115 | } | |
1116 | ||
4743a0f8 | 1117 | |
5fda88f5 S |
1118 | if (!cs_active) { |
1119 | omap2_mcspi_force_cs(spi, 1); | |
1120 | cs_active = 1; | |
1121 | } | |
4743a0f8 | 1122 | |
5fda88f5 S |
1123 | chconf = mcspi_cached_chconf0(spi); |
1124 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
1125 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
ccdc7bf9 | 1126 | |
5fda88f5 S |
1127 | if (t->tx_buf == NULL) |
1128 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
1129 | else if (t->rx_buf == NULL) | |
1130 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
ccdc7bf9 | 1131 | |
5fda88f5 S |
1132 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
1133 | /* Turbo mode is for more than one word */ | |
1134 | if (t->len > ((cs->word_len + 7) >> 3)) | |
1135 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
1136 | } | |
ccdc7bf9 | 1137 | |
5fda88f5 | 1138 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 1139 | |
5fda88f5 S |
1140 | if (t->len) { |
1141 | unsigned count; | |
1142 | ||
d33f473d IS |
1143 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1144 | (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) | |
1145 | omap2_mcspi_set_fifo(spi, t, 1); | |
1146 | ||
1147 | omap2_mcspi_set_enable(spi, 1); | |
1148 | ||
5fda88f5 S |
1149 | /* RX_ONLY mode needs dummy data in TX reg */ |
1150 | if (t->tx_buf == NULL) | |
21b2ce5e | 1151 | writel_relaxed(0, cs->base |
5fda88f5 | 1152 | + OMAP2_MCSPI_TX0); |
ccdc7bf9 | 1153 | |
ddc5cdf1 TL |
1154 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1155 | (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) | |
5fda88f5 S |
1156 | count = omap2_mcspi_txrx_dma(spi, t); |
1157 | else | |
1158 | count = omap2_mcspi_txrx_pio(spi, t); | |
1159 | m->actual_length += count; | |
ccdc7bf9 | 1160 | |
5fda88f5 S |
1161 | if (count != t->len) { |
1162 | status = -EIO; | |
1163 | break; | |
ccdc7bf9 SO |
1164 | } |
1165 | } | |
1166 | ||
5fda88f5 S |
1167 | if (t->delay_usecs) |
1168 | udelay(t->delay_usecs); | |
ccdc7bf9 | 1169 | |
5fda88f5 S |
1170 | /* ignore the "leave it on after last xfer" hint */ |
1171 | if (t->cs_change) { | |
ccdc7bf9 | 1172 | omap2_mcspi_force_cs(spi, 0); |
5fda88f5 S |
1173 | cs_active = 0; |
1174 | } | |
d33f473d IS |
1175 | |
1176 | omap2_mcspi_set_enable(spi, 0); | |
1177 | ||
1178 | if (mcspi->fifo_depth > 0) | |
1179 | omap2_mcspi_set_fifo(spi, t, 0); | |
5fda88f5 S |
1180 | } |
1181 | /* Restore defaults if they were overriden */ | |
1182 | if (par_override) { | |
1183 | par_override = 0; | |
1184 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1185 | } | |
ccdc7bf9 | 1186 | |
5fda88f5 S |
1187 | if (cs_active) |
1188 | omap2_mcspi_force_cs(spi, 0); | |
ccdc7bf9 | 1189 | |
5cbc7ca9 MB |
1190 | if (cd && cd->cs_per_word) { |
1191 | chconf = mcspi->ctx.modulctrl; | |
1192 | chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1193 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1194 | mcspi->ctx.modulctrl = | |
1195 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1196 | } | |
1197 | ||
5fda88f5 | 1198 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1199 | |
d33f473d IS |
1200 | if (mcspi->fifo_depth > 0 && t) |
1201 | omap2_mcspi_set_fifo(spi, t, 0); | |
1f1a4384 | 1202 | |
d33f473d | 1203 | m->status = status; |
ccdc7bf9 SO |
1204 | } |
1205 | ||
5fda88f5 | 1206 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
18dd6199 | 1207 | struct spi_message *m) |
ccdc7bf9 | 1208 | { |
ddc5cdf1 | 1209 | struct spi_device *spi; |
ccdc7bf9 | 1210 | struct omap2_mcspi *mcspi; |
ddc5cdf1 | 1211 | struct omap2_mcspi_dma *mcspi_dma; |
ccdc7bf9 | 1212 | struct spi_transfer *t; |
c5a06e75 | 1213 | int status; |
ccdc7bf9 | 1214 | |
ddc5cdf1 | 1215 | spi = m->spi; |
5fda88f5 | 1216 | mcspi = spi_master_get_devdata(master); |
ddc5cdf1 | 1217 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
ccdc7bf9 SO |
1218 | m->actual_length = 0; |
1219 | m->status = 0; | |
1220 | ||
ccdc7bf9 SO |
1221 | list_for_each_entry(t, &m->transfers, transfer_list) { |
1222 | const void *tx_buf = t->tx_buf; | |
1223 | void *rx_buf = t->rx_buf; | |
1224 | unsigned len = t->len; | |
1225 | ||
aca0924b | 1226 | if ((len && !(rx_buf || tx_buf))) { |
5fda88f5 | 1227 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
ccdc7bf9 SO |
1228 | t->speed_hz, |
1229 | len, | |
1230 | tx_buf ? "tx" : "", | |
1231 | rx_buf ? "rx" : "", | |
1232 | t->bits_per_word); | |
c5a06e75 FC |
1233 | status = -EINVAL; |
1234 | goto out; | |
ccdc7bf9 | 1235 | } |
ccdc7bf9 SO |
1236 | |
1237 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) | |
1238 | continue; | |
1239 | ||
ddc5cdf1 | 1240 | if (mcspi_dma->dma_tx && tx_buf != NULL) { |
5fda88f5 | 1241 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, |
ccdc7bf9 | 1242 | len, DMA_TO_DEVICE); |
5fda88f5 S |
1243 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { |
1244 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 | 1245 | 'T', len); |
c5a06e75 FC |
1246 | status = -EINVAL; |
1247 | goto out; | |
ccdc7bf9 SO |
1248 | } |
1249 | } | |
ddc5cdf1 | 1250 | if (mcspi_dma->dma_rx && rx_buf != NULL) { |
5fda88f5 | 1251 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, |
ccdc7bf9 | 1252 | DMA_FROM_DEVICE); |
5fda88f5 S |
1253 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { |
1254 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1255 | 'R', len); |
1256 | if (tx_buf != NULL) | |
5fda88f5 | 1257 | dma_unmap_single(mcspi->dev, t->tx_dma, |
ccdc7bf9 | 1258 | len, DMA_TO_DEVICE); |
c5a06e75 FC |
1259 | status = -EINVAL; |
1260 | goto out; | |
ccdc7bf9 SO |
1261 | } |
1262 | } | |
1263 | } | |
1264 | ||
5fda88f5 | 1265 | omap2_mcspi_work(mcspi, m); |
c5a06e75 FC |
1266 | /* spi_finalize_current_message() changes the status inside the |
1267 | * spi_message, save the status here. */ | |
1268 | status = m->status; | |
1269 | out: | |
5fda88f5 | 1270 | spi_finalize_current_message(master); |
c5a06e75 | 1271 | return status; |
ccdc7bf9 SO |
1272 | } |
1273 | ||
fd4a319b | 1274 | static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1275 | { |
1276 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1277 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1278 | int ret = 0; |
ccdc7bf9 | 1279 | |
034d3dc9 | 1280 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1281 | if (ret < 0) |
1282 | return ret; | |
ddb22195 | 1283 | |
39f8052d | 1284 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
18dd6199 | 1285 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
39f8052d | 1286 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
ccdc7bf9 SO |
1287 | |
1288 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1289 | pm_runtime_mark_last_busy(mcspi->dev); |
1290 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1291 | return 0; |
1292 | } | |
1293 | ||
1f1a4384 G |
1294 | static int omap_mcspi_runtime_resume(struct device *dev) |
1295 | { | |
1296 | struct omap2_mcspi *mcspi; | |
1297 | struct spi_master *master; | |
1298 | ||
1299 | master = dev_get_drvdata(dev); | |
1300 | mcspi = spi_master_get_devdata(master); | |
1301 | omap2_mcspi_restore_ctx(mcspi); | |
1302 | ||
1303 | return 0; | |
1304 | } | |
1305 | ||
d5a80031 BC |
1306 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1307 | .regs_offset = 0, | |
1308 | }; | |
1309 | ||
1310 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1311 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1312 | }; | |
1313 | ||
1314 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1315 | { | |
1316 | .compatible = "ti,omap2-mcspi", | |
1317 | .data = &omap2_pdata, | |
1318 | }, | |
1319 | { | |
1320 | .compatible = "ti,omap4-mcspi", | |
1321 | .data = &omap4_pdata, | |
1322 | }, | |
1323 | { }, | |
1324 | }; | |
1325 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1326 | |
fd4a319b | 1327 | static int omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1328 | { |
1329 | struct spi_master *master; | |
83a01e72 | 1330 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1331 | struct omap2_mcspi *mcspi; |
1332 | struct resource *r; | |
1333 | int status = 0, i; | |
d5a80031 BC |
1334 | u32 regs_offset = 0; |
1335 | static int bus_num = 1; | |
1336 | struct device_node *node = pdev->dev.of_node; | |
1337 | const struct of_device_id *match; | |
ccdc7bf9 SO |
1338 | |
1339 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1340 | if (master == NULL) { | |
1341 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1342 | return -ENOMEM; | |
1343 | } | |
1344 | ||
e7db06b5 DB |
1345 | /* the spi->mode bits understood by this driver: */ |
1346 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 1347 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
ccdc7bf9 | 1348 | master->setup = omap2_mcspi_setup; |
f0278a1a | 1349 | master->auto_runtime_pm = true; |
5fda88f5 | 1350 | master->transfer_one_message = omap2_mcspi_transfer_one_message; |
ccdc7bf9 | 1351 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 | 1352 | master->dev.of_node = node; |
aca0924b AL |
1353 | master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; |
1354 | master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; | |
d5a80031 | 1355 | |
24b5a82c | 1356 | platform_set_drvdata(pdev, master); |
0384e90b DM |
1357 | |
1358 | mcspi = spi_master_get_devdata(master); | |
1359 | mcspi->master = master; | |
1360 | ||
d5a80031 BC |
1361 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
1362 | if (match) { | |
1363 | u32 num_cs = 1; /* default number of chipselect */ | |
1364 | pdata = match->data; | |
1365 | ||
1366 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1367 | master->num_chipselect = num_cs; | |
1368 | master->bus_num = bus_num++; | |
2cd45179 DM |
1369 | if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) |
1370 | mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; | |
d5a80031 | 1371 | } else { |
8074cf06 | 1372 | pdata = dev_get_platdata(&pdev->dev); |
d5a80031 BC |
1373 | master->num_chipselect = pdata->num_cs; |
1374 | if (pdev->id != -1) | |
1375 | master->bus_num = pdev->id; | |
0384e90b | 1376 | mcspi->pin_dir = pdata->pin_dir; |
d5a80031 BC |
1377 | } |
1378 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 | 1379 | |
ccdc7bf9 SO |
1380 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1381 | if (r == NULL) { | |
1382 | status = -ENODEV; | |
39f1b565 | 1383 | goto free_master; |
ccdc7bf9 | 1384 | } |
1458d160 | 1385 | |
d5a80031 BC |
1386 | r->start += regs_offset; |
1387 | r->end += regs_offset; | |
1458d160 | 1388 | mcspi->phys = r->start; |
ccdc7bf9 | 1389 | |
b0ee5605 TR |
1390 | mcspi->base = devm_ioremap_resource(&pdev->dev, r); |
1391 | if (IS_ERR(mcspi->base)) { | |
1392 | status = PTR_ERR(mcspi->base); | |
1a77b127 | 1393 | goto free_master; |
55c381e4 | 1394 | } |
ccdc7bf9 | 1395 | |
1f1a4384 | 1396 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1397 | |
1bd897f8 | 1398 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1399 | |
a6f936db AL |
1400 | mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, |
1401 | sizeof(struct omap2_mcspi_dma), | |
1402 | GFP_KERNEL); | |
1403 | if (mcspi->dma_channels == NULL) { | |
1404 | status = -ENOMEM; | |
1a77b127 | 1405 | goto free_master; |
a6f936db | 1406 | } |
ccdc7bf9 | 1407 | |
1a5d8190 | 1408 | for (i = 0; i < master->num_chipselect; i++) { |
74f3aaad MP |
1409 | char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; |
1410 | char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name; | |
1a5d8190 C |
1411 | struct resource *dma_res; |
1412 | ||
74f3aaad MP |
1413 | sprintf(dma_rx_ch_name, "rx%d", i); |
1414 | if (!pdev->dev.of_node) { | |
1415 | dma_res = | |
1416 | platform_get_resource_byname(pdev, | |
1417 | IORESOURCE_DMA, | |
1418 | dma_rx_ch_name); | |
1419 | if (!dma_res) { | |
1420 | dev_dbg(&pdev->dev, | |
1421 | "cannot get DMA RX channel\n"); | |
1422 | status = -ENODEV; | |
1423 | break; | |
1424 | } | |
1a5d8190 | 1425 | |
74f3aaad MP |
1426 | mcspi->dma_channels[i].dma_rx_sync_dev = |
1427 | dma_res->start; | |
1a5d8190 | 1428 | } |
74f3aaad MP |
1429 | sprintf(dma_tx_ch_name, "tx%d", i); |
1430 | if (!pdev->dev.of_node) { | |
1431 | dma_res = | |
1432 | platform_get_resource_byname(pdev, | |
1433 | IORESOURCE_DMA, | |
1434 | dma_tx_ch_name); | |
1435 | if (!dma_res) { | |
1436 | dev_dbg(&pdev->dev, | |
1437 | "cannot get DMA TX channel\n"); | |
1438 | status = -ENODEV; | |
1439 | break; | |
1440 | } | |
1a5d8190 | 1441 | |
74f3aaad MP |
1442 | mcspi->dma_channels[i].dma_tx_sync_dev = |
1443 | dma_res->start; | |
1444 | } | |
ccdc7bf9 SO |
1445 | } |
1446 | ||
39f1b565 | 1447 | if (status < 0) |
a6f936db | 1448 | goto free_master; |
39f1b565 | 1449 | |
27b5284c S |
1450 | pm_runtime_use_autosuspend(&pdev->dev); |
1451 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1452 | pm_runtime_enable(&pdev->dev); |
1453 | ||
142e07be WY |
1454 | status = omap2_mcspi_master_setup(mcspi); |
1455 | if (status < 0) | |
39f1b565 | 1456 | goto disable_pm; |
ccdc7bf9 | 1457 | |
b95e02b7 | 1458 | status = devm_spi_register_master(&pdev->dev, master); |
ccdc7bf9 | 1459 | if (status < 0) |
37a2d84a | 1460 | goto disable_pm; |
ccdc7bf9 SO |
1461 | |
1462 | return status; | |
1463 | ||
39f1b565 | 1464 | disable_pm: |
751c925c | 1465 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1466 | free_master: |
37a2d84a | 1467 | spi_master_put(master); |
ccdc7bf9 SO |
1468 | return status; |
1469 | } | |
1470 | ||
fd4a319b | 1471 | static int omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 | 1472 | { |
a6f936db AL |
1473 | struct spi_master *master = platform_get_drvdata(pdev); |
1474 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
ccdc7bf9 | 1475 | |
a93a2029 | 1476 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1477 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 | 1478 | |
ccdc7bf9 SO |
1479 | return 0; |
1480 | } | |
1481 | ||
7e38c3c4 KS |
1482 | /* work with hotplug and coldplug */ |
1483 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1484 | ||
42ce7fd6 GC |
1485 | #ifdef CONFIG_SUSPEND |
1486 | /* | |
1487 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1488 | * unactive state when driver was suspend, then force it to unactive state at | |
1489 | * wake up. | |
1490 | */ | |
1491 | static int omap2_mcspi_resume(struct device *dev) | |
1492 | { | |
1493 | struct spi_master *master = dev_get_drvdata(dev); | |
1494 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1495 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1496 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 | 1497 | |
034d3dc9 | 1498 | pm_runtime_get_sync(mcspi->dev); |
1bd897f8 | 1499 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1500 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1501 | /* |
1502 | * We need to toggle CS state for OMAP take this | |
1503 | * change in account. | |
1504 | */ | |
af4e944d | 1505 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1506 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
af4e944d | 1507 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
21b2ce5e | 1508 | writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
42ce7fd6 GC |
1509 | } |
1510 | } | |
034d3dc9 S |
1511 | pm_runtime_mark_last_busy(mcspi->dev); |
1512 | pm_runtime_put_autosuspend(mcspi->dev); | |
42ce7fd6 GC |
1513 | return 0; |
1514 | } | |
1515 | #else | |
1516 | #define omap2_mcspi_resume NULL | |
1517 | #endif | |
1518 | ||
1519 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1520 | .resume = omap2_mcspi_resume, | |
1f1a4384 | 1521 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1522 | }; |
1523 | ||
ccdc7bf9 SO |
1524 | static struct platform_driver omap2_mcspi_driver = { |
1525 | .driver = { | |
1526 | .name = "omap2_mcspi", | |
d5a80031 BC |
1527 | .pm = &omap2_mcspi_pm_ops, |
1528 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1529 | }, |
7d6b6d83 | 1530 | .probe = omap2_mcspi_probe, |
fd4a319b | 1531 | .remove = omap2_mcspi_remove, |
ccdc7bf9 SO |
1532 | }; |
1533 | ||
9fdca9df | 1534 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1535 | MODULE_LICENSE("GPL"); |