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Commit | Line | Data |
---|---|---|
60cadec9 | 1 | /* |
ca632f55 | 2 | * Marvell Orion SPI controller driver |
60cadec9 SA |
3 | * |
4 | * Author: Shadi Ammouri <shadi@marvell.com> | |
5 | * Copyright (C) 2007-2008 Marvell Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
60cadec9 SA |
12 | #include <linux/interrupt.h> |
13 | #include <linux/delay.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/spi/spi.h> | |
d7614de4 | 18 | #include <linux/module.h> |
5c678694 | 19 | #include <linux/pm_runtime.h> |
f814f9ac | 20 | #include <linux/of.h> |
b3c195b3 | 21 | #include <linux/of_address.h> |
df59fa7f | 22 | #include <linux/of_device.h> |
4574b886 | 23 | #include <linux/clk.h> |
895248f8 | 24 | #include <linux/sizes.h> |
b28b9149 | 25 | #include <linux/gpio.h> |
60cadec9 SA |
26 | #include <asm/unaligned.h> |
27 | ||
28 | #define DRIVER_NAME "orion_spi" | |
29 | ||
5c678694 RK |
30 | /* Runtime PM autosuspend timeout: PM is fairly light on this driver */ |
31 | #define SPI_AUTOSUSPEND_TIMEOUT 200 | |
32 | ||
23244404 KW |
33 | /* Some SoCs using this driver support up to 8 chip selects. |
34 | * It is up to the implementer to only use the chip selects | |
35 | * that are available. | |
36 | */ | |
37 | #define ORION_NUM_CHIPSELECTS 8 | |
38 | ||
60cadec9 SA |
39 | #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ |
40 | ||
41 | #define ORION_SPI_IF_CTRL_REG 0x00 | |
42 | #define ORION_SPI_IF_CONFIG_REG 0x04 | |
1017f424 BS |
43 | #define ORION_SPI_IF_RXLSBF BIT(14) |
44 | #define ORION_SPI_IF_TXLSBF BIT(13) | |
60cadec9 SA |
45 | #define ORION_SPI_DATA_OUT_REG 0x08 |
46 | #define ORION_SPI_DATA_IN_REG 0x0c | |
47 | #define ORION_SPI_INT_CAUSE_REG 0x10 | |
38d6211e NH |
48 | #define ORION_SPI_TIMING_PARAMS_REG 0x18 |
49 | ||
b3c195b3 SR |
50 | /* Register for the "Direct Mode" */ |
51 | #define SPI_DIRECT_WRITE_CONFIG_REG 0x20 | |
52 | ||
38d6211e NH |
53 | #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6) |
54 | #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6) | |
55 | #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6) | |
60cadec9 | 56 | |
b15d5d70 JG |
57 | #define ORION_SPI_MODE_CPOL (1 << 11) |
58 | #define ORION_SPI_MODE_CPHA (1 << 12) | |
60cadec9 SA |
59 | #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) |
60 | #define ORION_SPI_CLK_PRESCALE_MASK 0x1F | |
df59fa7f | 61 | #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF |
b15d5d70 JG |
62 | #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ |
63 | ORION_SPI_MODE_CPHA) | |
23244404 KW |
64 | #define ORION_SPI_CS_MASK 0x1C |
65 | #define ORION_SPI_CS_SHIFT 2 | |
66 | #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ | |
67 | ORION_SPI_CS_MASK) | |
60cadec9 | 68 | |
df59fa7f GU |
69 | enum orion_spi_type { |
70 | ORION_SPI, | |
71 | ARMADA_SPI, | |
72 | }; | |
73 | ||
74 | struct orion_spi_dev { | |
75 | enum orion_spi_type typ; | |
ce2f6ea1 GC |
76 | /* |
77 | * min_divisor and max_hz should be exclusive, the only we can | |
78 | * have both is for managing the armada-370-spi case with old | |
79 | * device tree | |
80 | */ | |
81 | unsigned long max_hz; | |
df59fa7f GU |
82 | unsigned int min_divisor; |
83 | unsigned int max_divisor; | |
84 | u32 prescale_mask; | |
38d6211e | 85 | bool is_errata_50mhz_ac; |
df59fa7f GU |
86 | }; |
87 | ||
b3c195b3 SR |
88 | struct orion_direct_acc { |
89 | void __iomem *vaddr; | |
90 | u32 size; | |
91 | }; | |
92 | ||
60cadec9 | 93 | struct orion_spi { |
60cadec9 SA |
94 | struct spi_master *master; |
95 | void __iomem *base; | |
4574b886 | 96 | struct clk *clk; |
df59fa7f | 97 | const struct orion_spi_dev *devdata; |
b3c195b3 SR |
98 | |
99 | struct orion_direct_acc direct_access[ORION_NUM_CHIPSELECTS]; | |
60cadec9 SA |
100 | }; |
101 | ||
60cadec9 SA |
102 | static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) |
103 | { | |
104 | return orion_spi->base + reg; | |
105 | } | |
106 | ||
107 | static inline void | |
108 | orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) | |
109 | { | |
110 | void __iomem *reg_addr = spi_reg(orion_spi, reg); | |
111 | u32 val; | |
112 | ||
113 | val = readl(reg_addr); | |
114 | val |= mask; | |
115 | writel(val, reg_addr); | |
116 | } | |
117 | ||
118 | static inline void | |
119 | orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) | |
120 | { | |
121 | void __iomem *reg_addr = spi_reg(orion_spi, reg); | |
122 | u32 val; | |
123 | ||
124 | val = readl(reg_addr); | |
125 | val &= ~mask; | |
126 | writel(val, reg_addr); | |
127 | } | |
128 | ||
60cadec9 SA |
129 | static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) |
130 | { | |
131 | u32 tclk_hz; | |
132 | u32 rate; | |
133 | u32 prescale; | |
134 | u32 reg; | |
135 | struct orion_spi *orion_spi; | |
df59fa7f | 136 | const struct orion_spi_dev *devdata; |
60cadec9 SA |
137 | |
138 | orion_spi = spi_master_get_devdata(spi->master); | |
df59fa7f | 139 | devdata = orion_spi->devdata; |
60cadec9 | 140 | |
4574b886 | 141 | tclk_hz = clk_get_rate(orion_spi->clk); |
60cadec9 | 142 | |
df59fa7f | 143 | if (devdata->typ == ARMADA_SPI) { |
7243e0b2 UKK |
144 | /* |
145 | * Given the core_clk (tclk_hz) and the target rate (speed) we | |
146 | * determine the best values for SPR (in [0 .. 15]) and SPPR (in | |
147 | * [0..7]) such that | |
148 | * | |
149 | * core_clk / (SPR * 2 ** SPPR) | |
150 | * | |
151 | * is as big as possible but not bigger than speed. | |
152 | */ | |
60cadec9 | 153 | |
7243e0b2 UKK |
154 | /* best integer divider: */ |
155 | unsigned divider = DIV_ROUND_UP(tclk_hz, speed); | |
156 | unsigned spr, sppr; | |
157 | ||
158 | if (divider < 16) { | |
159 | /* This is the easy case, divider is less than 16 */ | |
160 | spr = divider; | |
161 | sppr = 0; | |
162 | ||
163 | } else { | |
164 | unsigned two_pow_sppr; | |
165 | /* | |
166 | * Find the highest bit set in divider. This and the | |
167 | * three next bits define SPR (apart from rounding). | |
168 | * SPPR is then the number of zero bits that must be | |
169 | * appended: | |
170 | */ | |
171 | sppr = fls(divider) - 4; | |
172 | ||
173 | /* | |
174 | * As SPR only has 4 bits, we have to round divider up | |
175 | * to the next multiple of 2 ** sppr. | |
176 | */ | |
177 | two_pow_sppr = 1 << sppr; | |
178 | divider = (divider + two_pow_sppr - 1) & -two_pow_sppr; | |
179 | ||
180 | /* | |
181 | * recalculate sppr as rounding up divider might have | |
182 | * increased it enough to change the position of the | |
183 | * highest set bit. In this case the bit that now | |
184 | * doesn't make it into SPR is 0, so there is no need to | |
185 | * round again. | |
186 | */ | |
187 | sppr = fls(divider) - 4; | |
188 | spr = divider >> sppr; | |
189 | ||
190 | /* | |
191 | * Now do range checking. SPR is constructed to have a | |
192 | * width of 4 bits, so this is fine for sure. So we | |
193 | * still need to check for sppr to fit into 3 bits: | |
194 | */ | |
195 | if (sppr > 7) | |
196 | return -EINVAL; | |
197 | } | |
df59fa7f | 198 | |
7243e0b2 | 199 | prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr; |
df59fa7f GU |
200 | } else { |
201 | /* | |
202 | * the supported rates are: 4,6,8...30 | |
203 | * round up as we look for equal or less speed | |
204 | */ | |
205 | rate = DIV_ROUND_UP(tclk_hz, speed); | |
206 | rate = roundup(rate, 2); | |
207 | ||
208 | /* check if requested speed is too small */ | |
209 | if (rate > 30) | |
210 | return -EINVAL; | |
60cadec9 | 211 | |
df59fa7f GU |
212 | if (rate < 4) |
213 | rate = 4; | |
214 | ||
215 | /* Convert the rate to SPI clock divisor value. */ | |
216 | prescale = 0x10 + rate/2; | |
217 | } | |
60cadec9 SA |
218 | |
219 | reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); | |
df59fa7f | 220 | reg = ((reg & ~devdata->prescale_mask) | prescale); |
60cadec9 SA |
221 | writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
b15d5d70 JG |
226 | static void |
227 | orion_spi_mode_set(struct spi_device *spi) | |
228 | { | |
229 | u32 reg; | |
230 | struct orion_spi *orion_spi; | |
231 | ||
232 | orion_spi = spi_master_get_devdata(spi->master); | |
233 | ||
234 | reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); | |
235 | reg &= ~ORION_SPI_MODE_MASK; | |
236 | if (spi->mode & SPI_CPOL) | |
237 | reg |= ORION_SPI_MODE_CPOL; | |
238 | if (spi->mode & SPI_CPHA) | |
239 | reg |= ORION_SPI_MODE_CPHA; | |
1017f424 BS |
240 | if (spi->mode & SPI_LSB_FIRST) |
241 | reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF; | |
242 | else | |
243 | reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF); | |
244 | ||
b15d5d70 JG |
245 | writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); |
246 | } | |
247 | ||
38d6211e NH |
248 | static void |
249 | orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed) | |
250 | { | |
251 | u32 reg; | |
252 | struct orion_spi *orion_spi; | |
253 | ||
254 | orion_spi = spi_master_get_devdata(spi->master); | |
255 | ||
256 | /* | |
257 | * Erratum description: (Erratum NO. FE-9144572) The device | |
258 | * SPI interface supports frequencies of up to 50 MHz. | |
259 | * However, due to this erratum, when the device core clock is | |
260 | * 250 MHz and the SPI interfaces is configured for 50MHz SPI | |
261 | * clock and CPOL=CPHA=1 there might occur data corruption on | |
262 | * reads from the SPI device. | |
263 | * Erratum Workaround: | |
264 | * Work in one of the following configurations: | |
265 | * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration | |
266 | * Register". | |
267 | * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1 | |
268 | * Register" before setting the interface. | |
269 | */ | |
270 | reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); | |
271 | reg &= ~ORION_SPI_TMISO_SAMPLE_MASK; | |
272 | ||
273 | if (clk_get_rate(orion_spi->clk) == 250000000 && | |
274 | speed == 50000000 && spi->mode & SPI_CPOL && | |
275 | spi->mode & SPI_CPHA) | |
276 | reg |= ORION_SPI_TMISO_SAMPLE_2; | |
277 | else | |
278 | reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */ | |
279 | ||
280 | writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); | |
281 | } | |
282 | ||
60cadec9 SA |
283 | /* |
284 | * called only when no transfer is active on the bus | |
285 | */ | |
286 | static int | |
287 | orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) | |
288 | { | |
289 | struct orion_spi *orion_spi; | |
290 | unsigned int speed = spi->max_speed_hz; | |
291 | unsigned int bits_per_word = spi->bits_per_word; | |
292 | int rc; | |
293 | ||
294 | orion_spi = spi_master_get_devdata(spi->master); | |
295 | ||
296 | if ((t != NULL) && t->speed_hz) | |
297 | speed = t->speed_hz; | |
298 | ||
299 | if ((t != NULL) && t->bits_per_word) | |
300 | bits_per_word = t->bits_per_word; | |
301 | ||
b15d5d70 JG |
302 | orion_spi_mode_set(spi); |
303 | ||
38d6211e NH |
304 | if (orion_spi->devdata->is_errata_50mhz_ac) |
305 | orion_spi_50mhz_ac_timing_erratum(spi, speed); | |
306 | ||
60cadec9 SA |
307 | rc = orion_spi_baudrate_set(spi, speed); |
308 | if (rc) | |
309 | return rc; | |
310 | ||
495b3358 AL |
311 | if (bits_per_word == 16) |
312 | orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, | |
313 | ORION_SPI_IF_8_16_BIT_MODE); | |
314 | else | |
315 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG, | |
316 | ORION_SPI_IF_8_16_BIT_MODE); | |
317 | ||
318 | return 0; | |
60cadec9 SA |
319 | } |
320 | ||
75872ebe | 321 | static void orion_spi_set_cs(struct spi_device *spi, bool enable) |
60cadec9 | 322 | { |
75872ebe | 323 | struct orion_spi *orion_spi; |
b28b9149 CP |
324 | int cs; |
325 | ||
326 | if (gpio_is_valid(spi->cs_gpio)) | |
327 | cs = 0; | |
328 | else | |
329 | cs = spi->chip_select; | |
75872ebe KW |
330 | |
331 | orion_spi = spi_master_get_devdata(spi->master); | |
332 | ||
23244404 KW |
333 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK); |
334 | orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, | |
b28b9149 | 335 | ORION_SPI_CS(cs)); |
23244404 | 336 | |
75872ebe KW |
337 | /* Chip select logic is inverted from spi_set_cs */ |
338 | if (!enable) | |
60cadec9 SA |
339 | orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); |
340 | else | |
341 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); | |
342 | } | |
343 | ||
344 | static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi) | |
345 | { | |
346 | int i; | |
347 | ||
348 | for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { | |
349 | if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) | |
350 | return 1; | |
b8434048 JH |
351 | |
352 | udelay(1); | |
60cadec9 SA |
353 | } |
354 | ||
355 | return -1; | |
356 | } | |
357 | ||
358 | static inline int | |
359 | orion_spi_write_read_8bit(struct spi_device *spi, | |
360 | const u8 **tx_buf, u8 **rx_buf) | |
361 | { | |
362 | void __iomem *tx_reg, *rx_reg, *int_reg; | |
363 | struct orion_spi *orion_spi; | |
364 | ||
365 | orion_spi = spi_master_get_devdata(spi->master); | |
366 | tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); | |
367 | rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); | |
368 | int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); | |
369 | ||
370 | /* clear the interrupt cause register */ | |
371 | writel(0x0, int_reg); | |
372 | ||
373 | if (tx_buf && *tx_buf) | |
374 | writel(*(*tx_buf)++, tx_reg); | |
375 | else | |
376 | writel(0, tx_reg); | |
377 | ||
378 | if (orion_spi_wait_till_ready(orion_spi) < 0) { | |
379 | dev_err(&spi->dev, "TXS timed out\n"); | |
380 | return -1; | |
381 | } | |
382 | ||
383 | if (rx_buf && *rx_buf) | |
384 | *(*rx_buf)++ = readl(rx_reg); | |
385 | ||
386 | return 1; | |
387 | } | |
388 | ||
389 | static inline int | |
390 | orion_spi_write_read_16bit(struct spi_device *spi, | |
391 | const u16 **tx_buf, u16 **rx_buf) | |
392 | { | |
393 | void __iomem *tx_reg, *rx_reg, *int_reg; | |
394 | struct orion_spi *orion_spi; | |
395 | ||
396 | orion_spi = spi_master_get_devdata(spi->master); | |
397 | tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); | |
398 | rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); | |
399 | int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); | |
400 | ||
401 | /* clear the interrupt cause register */ | |
402 | writel(0x0, int_reg); | |
403 | ||
404 | if (tx_buf && *tx_buf) | |
405 | writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); | |
406 | else | |
407 | writel(0, tx_reg); | |
408 | ||
409 | if (orion_spi_wait_till_ready(orion_spi) < 0) { | |
410 | dev_err(&spi->dev, "TXS timed out\n"); | |
411 | return -1; | |
412 | } | |
413 | ||
414 | if (rx_buf && *rx_buf) | |
415 | put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++); | |
416 | ||
417 | return 1; | |
418 | } | |
419 | ||
420 | static unsigned int | |
421 | orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) | |
422 | { | |
60cadec9 SA |
423 | unsigned int count; |
424 | int word_len; | |
b3c195b3 SR |
425 | struct orion_spi *orion_spi; |
426 | int cs = spi->chip_select; | |
60cadec9 | 427 | |
60cadec9 SA |
428 | word_len = spi->bits_per_word; |
429 | count = xfer->len; | |
430 | ||
b3c195b3 SR |
431 | orion_spi = spi_master_get_devdata(spi->master); |
432 | ||
433 | /* | |
434 | * Use SPI direct write mode if base address is available. Otherwise | |
435 | * fall back to PIO mode for this transfer. | |
436 | */ | |
437 | if ((orion_spi->direct_access[cs].vaddr) && (xfer->tx_buf) && | |
438 | (word_len == 8)) { | |
439 | unsigned int cnt = count / 4; | |
440 | unsigned int rem = count % 4; | |
441 | ||
442 | /* | |
443 | * Send the TX-data to the SPI device via the direct | |
444 | * mapped address window | |
445 | */ | |
446 | iowrite32_rep(orion_spi->direct_access[cs].vaddr, | |
447 | xfer->tx_buf, cnt); | |
448 | if (rem) { | |
449 | u32 *buf = (u32 *)xfer->tx_buf; | |
450 | ||
451 | iowrite8_rep(orion_spi->direct_access[cs].vaddr, | |
452 | &buf[cnt], rem); | |
453 | } | |
454 | ||
455 | return count; | |
456 | } | |
457 | ||
60cadec9 SA |
458 | if (word_len == 8) { |
459 | const u8 *tx = xfer->tx_buf; | |
460 | u8 *rx = xfer->rx_buf; | |
461 | ||
462 | do { | |
463 | if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0) | |
464 | goto out; | |
465 | count--; | |
466 | } while (count); | |
467 | } else if (word_len == 16) { | |
468 | const u16 *tx = xfer->tx_buf; | |
469 | u16 *rx = xfer->rx_buf; | |
470 | ||
471 | do { | |
472 | if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0) | |
473 | goto out; | |
474 | count -= 2; | |
475 | } while (count); | |
476 | } | |
477 | ||
478 | out: | |
479 | return xfer->len - count; | |
480 | } | |
481 | ||
75872ebe KW |
482 | static int orion_spi_transfer_one(struct spi_master *master, |
483 | struct spi_device *spi, | |
484 | struct spi_transfer *t) | |
60cadec9 | 485 | { |
ba59a807 | 486 | int status = 0; |
60cadec9 | 487 | |
75872ebe | 488 | status = orion_spi_setup_transfer(spi, t); |
ba59a807 | 489 | if (status < 0) |
75872ebe | 490 | return status; |
60cadec9 | 491 | |
75872ebe KW |
492 | if (t->len) |
493 | orion_spi_write_read(spi, t); | |
ba59a807 | 494 | |
75872ebe KW |
495 | return status; |
496 | } | |
ba59a807 | 497 | |
75872ebe KW |
498 | static int orion_spi_setup(struct spi_device *spi) |
499 | { | |
500 | return orion_spi_setup_transfer(spi, NULL); | |
60cadec9 SA |
501 | } |
502 | ||
2deff8d6 | 503 | static int orion_spi_reset(struct orion_spi *orion_spi) |
60cadec9 SA |
504 | { |
505 | /* Verify that the CS is deasserted */ | |
75872ebe | 506 | orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); |
b3c195b3 SR |
507 | |
508 | /* Don't deassert CS between the direct mapped SPI transfers */ | |
509 | writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG)); | |
510 | ||
60cadec9 SA |
511 | return 0; |
512 | } | |
513 | ||
df59fa7f GU |
514 | static const struct orion_spi_dev orion_spi_dev_data = { |
515 | .typ = ORION_SPI, | |
516 | .min_divisor = 4, | |
517 | .max_divisor = 30, | |
518 | .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, | |
519 | }; | |
520 | ||
4dacccfa | 521 | static const struct orion_spi_dev armada_370_spi_dev_data = { |
df59fa7f | 522 | .typ = ARMADA_SPI, |
ce2f6ea1 | 523 | .min_divisor = 4, |
df59fa7f | 524 | .max_divisor = 1920, |
ce2f6ea1 | 525 | .max_hz = 50000000, |
df59fa7f GU |
526 | .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, |
527 | }; | |
528 | ||
4dacccfa GC |
529 | static const struct orion_spi_dev armada_xp_spi_dev_data = { |
530 | .typ = ARMADA_SPI, | |
531 | .max_hz = 50000000, | |
532 | .max_divisor = 1920, | |
533 | .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, | |
534 | }; | |
535 | ||
536 | static const struct orion_spi_dev armada_375_spi_dev_data = { | |
537 | .typ = ARMADA_SPI, | |
538 | .min_divisor = 15, | |
539 | .max_divisor = 1920, | |
540 | .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, | |
541 | }; | |
542 | ||
38d6211e NH |
543 | static const struct orion_spi_dev armada_380_spi_dev_data = { |
544 | .typ = ARMADA_SPI, | |
545 | .max_hz = 50000000, | |
546 | .max_divisor = 1920, | |
547 | .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, | |
548 | .is_errata_50mhz_ac = true, | |
549 | }; | |
550 | ||
df59fa7f | 551 | static const struct of_device_id orion_spi_of_match_table[] = { |
4dacccfa GC |
552 | { |
553 | .compatible = "marvell,orion-spi", | |
554 | .data = &orion_spi_dev_data, | |
555 | }, | |
556 | { | |
557 | .compatible = "marvell,armada-370-spi", | |
558 | .data = &armada_370_spi_dev_data, | |
559 | }, | |
560 | { | |
561 | .compatible = "marvell,armada-375-spi", | |
562 | .data = &armada_375_spi_dev_data, | |
563 | }, | |
564 | { | |
565 | .compatible = "marvell,armada-380-spi", | |
38d6211e | 566 | .data = &armada_380_spi_dev_data, |
4dacccfa GC |
567 | }, |
568 | { | |
569 | .compatible = "marvell,armada-390-spi", | |
570 | .data = &armada_xp_spi_dev_data, | |
571 | }, | |
572 | { | |
573 | .compatible = "marvell,armada-xp-spi", | |
574 | .data = &armada_xp_spi_dev_data, | |
575 | }, | |
576 | ||
df59fa7f GU |
577 | {} |
578 | }; | |
579 | MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); | |
580 | ||
2deff8d6 | 581 | static int orion_spi_probe(struct platform_device *pdev) |
60cadec9 | 582 | { |
df59fa7f GU |
583 | const struct of_device_id *of_id; |
584 | const struct orion_spi_dev *devdata; | |
60cadec9 SA |
585 | struct spi_master *master; |
586 | struct orion_spi *spi; | |
587 | struct resource *r; | |
4574b886 | 588 | unsigned long tclk_hz; |
60cadec9 | 589 | int status = 0; |
b3c195b3 | 590 | struct device_node *np; |
60cadec9 | 591 | |
3fed8068 | 592 | master = spi_alloc_master(&pdev->dev, sizeof(*spi)); |
60cadec9 SA |
593 | if (master == NULL) { |
594 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
595 | return -ENOMEM; | |
596 | } | |
597 | ||
598 | if (pdev->id != -1) | |
599 | master->bus_num = pdev->id; | |
f814f9ac | 600 | if (pdev->dev.of_node) { |
e06871cd | 601 | u32 cell_index; |
b8434048 | 602 | |
e06871cd TP |
603 | if (!of_property_read_u32(pdev->dev.of_node, "cell-index", |
604 | &cell_index)) | |
605 | master->bus_num = cell_index; | |
f814f9ac | 606 | } |
60cadec9 | 607 | |
1017f424 BS |
608 | /* we support all 4 SPI modes and LSB first option */ |
609 | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST; | |
75872ebe KW |
610 | master->set_cs = orion_spi_set_cs; |
611 | master->transfer_one = orion_spi_transfer_one; | |
60cadec9 | 612 | master->num_chipselect = ORION_NUM_CHIPSELECTS; |
75872ebe | 613 | master->setup = orion_spi_setup; |
495b3358 | 614 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
5c678694 | 615 | master->auto_runtime_pm = true; |
b28b9149 | 616 | master->flags = SPI_MASTER_GPIO_SS; |
60cadec9 | 617 | |
24b5a82c | 618 | platform_set_drvdata(pdev, master); |
60cadec9 SA |
619 | |
620 | spi = spi_master_get_devdata(master); | |
621 | spi->master = master; | |
60cadec9 | 622 | |
df59fa7f | 623 | of_id = of_match_device(orion_spi_of_match_table, &pdev->dev); |
9a2d3635 | 624 | devdata = (of_id) ? of_id->data : &orion_spi_dev_data; |
df59fa7f GU |
625 | spi->devdata = devdata; |
626 | ||
bb489841 | 627 | spi->clk = devm_clk_get(&pdev->dev, NULL); |
4574b886 AL |
628 | if (IS_ERR(spi->clk)) { |
629 | status = PTR_ERR(spi->clk); | |
630 | goto out; | |
631 | } | |
632 | ||
c85012ad RK |
633 | status = clk_prepare_enable(spi->clk); |
634 | if (status) | |
635 | goto out; | |
636 | ||
4574b886 | 637 | tclk_hz = clk_get_rate(spi->clk); |
ce2f6ea1 GC |
638 | |
639 | /* | |
640 | * With old device tree, armada-370-spi could be used with | |
641 | * Armada XP, however for this SoC the maximum frequency is | |
642 | * 50MHz instead of tclk/4. On Armada 370, tclk cannot be | |
643 | * higher than 200MHz. So, in order to be able to handle both | |
644 | * SoCs, we can take the minimum of 50MHz and tclk/4. | |
645 | */ | |
646 | if (of_device_is_compatible(pdev->dev.of_node, | |
647 | "marvell,armada-370-spi")) | |
648 | master->max_speed_hz = min(devdata->max_hz, | |
649 | DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); | |
4dacccfa | 650 | else if (devdata->min_divisor) |
ce2f6ea1 GC |
651 | master->max_speed_hz = |
652 | DIV_ROUND_UP(tclk_hz, devdata->min_divisor); | |
4dacccfa GC |
653 | else |
654 | master->max_speed_hz = devdata->max_hz; | |
df59fa7f | 655 | master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); |
60cadec9 SA |
656 | |
657 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1729ce34 MB |
658 | spi->base = devm_ioremap_resource(&pdev->dev, r); |
659 | if (IS_ERR(spi->base)) { | |
660 | status = PTR_ERR(spi->base); | |
4574b886 | 661 | goto out_rel_clk; |
60cadec9 SA |
662 | } |
663 | ||
b3c195b3 SR |
664 | /* Scan all SPI devices of this controller for direct mapped devices */ |
665 | for_each_available_child_of_node(pdev->dev.of_node, np) { | |
666 | u32 cs; | |
667 | ||
668 | /* Get chip-select number from the "reg" property */ | |
669 | status = of_property_read_u32(np, "reg", &cs); | |
670 | if (status) { | |
671 | dev_err(&pdev->dev, | |
672 | "%s has no valid 'reg' property (%d)\n", | |
673 | np->full_name, status); | |
674 | status = 0; | |
675 | continue; | |
676 | } | |
677 | ||
678 | /* | |
679 | * Check if an address is configured for this SPI device. If | |
680 | * not, the MBus mapping via the 'ranges' property in the 'soc' | |
681 | * node is not configured and this device should not use the | |
682 | * direct mode. In this case, just continue with the next | |
683 | * device. | |
684 | */ | |
685 | status = of_address_to_resource(pdev->dev.of_node, cs + 1, r); | |
686 | if (status) | |
687 | continue; | |
688 | ||
689 | /* | |
690 | * Only map one page for direct access. This is enough for the | |
691 | * simple TX transfer which only writes to the first word. | |
692 | * This needs to get extended for the direct SPI-NOR / SPI-NAND | |
693 | * support, once this gets implemented. | |
694 | */ | |
695 | spi->direct_access[cs].vaddr = devm_ioremap(&pdev->dev, | |
696 | r->start, | |
697 | PAGE_SIZE); | |
57c624ae WY |
698 | if (!spi->direct_access[cs].vaddr) { |
699 | status = -ENOMEM; | |
b3c195b3 SR |
700 | goto out_rel_clk; |
701 | } | |
702 | spi->direct_access[cs].size = PAGE_SIZE; | |
703 | ||
704 | dev_info(&pdev->dev, "CS%d configured for direct access\n", cs); | |
705 | } | |
706 | ||
5c678694 RK |
707 | pm_runtime_set_active(&pdev->dev); |
708 | pm_runtime_use_autosuspend(&pdev->dev); | |
709 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
710 | pm_runtime_enable(&pdev->dev); | |
711 | ||
14033816 WY |
712 | status = orion_spi_reset(spi); |
713 | if (status < 0) | |
5c678694 RK |
714 | goto out_rel_pm; |
715 | ||
716 | pm_runtime_mark_last_busy(&pdev->dev); | |
717 | pm_runtime_put_autosuspend(&pdev->dev); | |
60cadec9 | 718 | |
f814f9ac | 719 | master->dev.of_node = pdev->dev.of_node; |
5c678694 | 720 | status = spi_register_master(master); |
60cadec9 | 721 | if (status < 0) |
5c678694 | 722 | goto out_rel_pm; |
60cadec9 SA |
723 | |
724 | return status; | |
725 | ||
5c678694 RK |
726 | out_rel_pm: |
727 | pm_runtime_disable(&pdev->dev); | |
4574b886 AL |
728 | out_rel_clk: |
729 | clk_disable_unprepare(spi->clk); | |
60cadec9 SA |
730 | out: |
731 | spi_master_put(master); | |
732 | return status; | |
733 | } | |
734 | ||
735 | ||
2deff8d6 | 736 | static int orion_spi_remove(struct platform_device *pdev) |
60cadec9 | 737 | { |
5c678694 RK |
738 | struct spi_master *master = platform_get_drvdata(pdev); |
739 | struct orion_spi *spi = spi_master_get_devdata(master); | |
60cadec9 | 740 | |
5c678694 | 741 | pm_runtime_get_sync(&pdev->dev); |
4574b886 | 742 | clk_disable_unprepare(spi->clk); |
4574b886 | 743 | |
5c678694 RK |
744 | spi_unregister_master(master); |
745 | pm_runtime_disable(&pdev->dev); | |
746 | ||
60cadec9 SA |
747 | return 0; |
748 | } | |
749 | ||
750 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
751 | ||
ec833050 | 752 | #ifdef CONFIG_PM |
5c678694 RK |
753 | static int orion_spi_runtime_suspend(struct device *dev) |
754 | { | |
755 | struct spi_master *master = dev_get_drvdata(dev); | |
756 | struct orion_spi *spi = spi_master_get_devdata(master); | |
757 | ||
758 | clk_disable_unprepare(spi->clk); | |
759 | return 0; | |
760 | } | |
761 | ||
762 | static int orion_spi_runtime_resume(struct device *dev) | |
763 | { | |
764 | struct spi_master *master = dev_get_drvdata(dev); | |
765 | struct orion_spi *spi = spi_master_get_devdata(master); | |
766 | ||
767 | return clk_prepare_enable(spi->clk); | |
768 | } | |
769 | #endif | |
770 | ||
771 | static const struct dev_pm_ops orion_spi_pm_ops = { | |
772 | SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend, | |
773 | orion_spi_runtime_resume, | |
774 | NULL) | |
775 | }; | |
776 | ||
60cadec9 SA |
777 | static struct platform_driver orion_spi_driver = { |
778 | .driver = { | |
779 | .name = DRIVER_NAME, | |
5c678694 | 780 | .pm = &orion_spi_pm_ops, |
f814f9ac | 781 | .of_match_table = of_match_ptr(orion_spi_of_match_table), |
60cadec9 | 782 | }, |
41ab724a | 783 | .probe = orion_spi_probe, |
2deff8d6 | 784 | .remove = orion_spi_remove, |
60cadec9 SA |
785 | }; |
786 | ||
41ab724a | 787 | module_platform_driver(orion_spi_driver); |
60cadec9 SA |
788 | |
789 | MODULE_DESCRIPTION("Orion SPI driver"); | |
790 | MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); | |
791 | MODULE_LICENSE("GPL"); |