[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-ppc4xx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * SPI_PPC4XX SPI controller driver.
 *
 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
 *
 * Based in part on drivers/spi/spi_s3c24xx.c
 *
 * Copyright (c) 2006 Ben Dooks
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 */

/*
 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
 * generate an interrupt to the CPU. This can cause high CPU utilization.
 * This driver allows platforms to reduce the interrupt load on the CPU
 * during SPI transfers by setting max_speed_hz via the device tree.
 */

#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/wait.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/interrupt.h>
#include <linux/delay.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>

#include <linux/io.h>
#include <asm/dcr.h>
#include <asm/dcr-regs.h>

/* bits in mode register - bit 0 is MSb */

/*
 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
 * Note: This is the inverse of CPHA.
 */
#define SPI_PPC4XX_MODE_SCP	(0x80 >> 3)

/* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
#define SPI_PPC4XX_MODE_SPE	(0x80 >> 4)

/*
 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
 * Note: This is identical to SPI_LSB_FIRST.
 */
#define SPI_PPC4XX_MODE_RD	(0x80 >> 5)

/*
 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
 * Note: This is identical to CPOL.
 */
#define SPI_PPC4XX_MODE_CI	(0x80 >> 6)

/*
 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
 */
#define SPI_PPC4XX_MODE_IL	(0x80 >> 7)

/* bits in control register */
/* starts a transfer when set */
#define SPI_PPC4XX_CR_STR	(0x80 >> 7)

/* bits in status register */
/* port is busy with a transfer */
#define SPI_PPC4XX_SR_BSY	(0x80 >> 6)
/* RxD ready */
#define SPI_PPC4XX_SR_RBR	(0x80 >> 7)

/* clock settings (SCP and CI) for various SPI modes */
#define SPI_CLK_MODE0	(SPI_PPC4XX_MODE_SCP | 0)
#define SPI_CLK_MODE1	(0 | 0)
#define SPI_CLK_MODE2	(SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
#define SPI_CLK_MODE3	(0 | SPI_PPC4XX_MODE_CI)

#define DRIVER_NAME	"spi_ppc4xx_of"

struct spi_ppc4xx_regs {
	u8 mode;
	u8 rxd;
	u8 txd;
	u8 cr;
	u8 sr;
	u8 dummy;
	/*
	 * Clock divisor modulus register
	 * This uses the following formula:
	 *    SCPClkOut = OPBCLK/(4(CDM + 1))
	 * or
	 *    CDM = (OPBCLK/4*SCPClkOut) - 1
	 * bit 0 is the MSb!
	 */
	u8 cdm;
};

/* SPI Controller driver's private data. */
struct ppc4xx_spi {
	/* bitbang has to be first */
	struct spi_bitbang bitbang;
	struct completion done;

	u64 mapbase;
	u64 mapsize;
	int irqnum;
	/* need this to set the SPI clock */
	unsigned int opb_freq;

	/* for transfers */
	int len;
	int count;
	/* data buffers */
	const unsigned char *tx;
	unsigned char *rx;

	struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
	struct spi_master *master;
	struct device *dev;
};

/* need this so we can set the clock in the chipselect routine */
struct spi_ppc4xx_cs {
	u8 mode;
};

static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
{
	struct ppc4xx_spi *hw;
	u8 data;

	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
		t->tx_buf, t->rx_buf, t->len);

	hw = spi_master_get_devdata(spi->master);

	hw->tx = t->tx_buf;
	hw->rx = t->rx_buf;
	hw->len = t->len;
	hw->count = 0;

	/* send the first byte */
	data = hw->tx ? hw->tx[0] : 0;
	out_8(&hw->regs->txd, data);
	out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
	wait_for_completion(&hw->done);

	return hw->count;
}

static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
	struct spi_ppc4xx_cs *cs = spi->controller_state;
	int scr;
	u8 cdm = 0;
	u32 speed;
	u8 bits_per_word;

	/* Start with the generic configuration for this device. */
	bits_per_word = spi->bits_per_word;
	speed = spi->max_speed_hz;

	/*
	 * Modify the configuration if the transfer overrides it.  Do not allow
	 * the transfer to overwrite the generic configuration with zeros.
	 */
	if (t) {
		if (t->bits_per_word)
			bits_per_word = t->bits_per_word;

		if (t->speed_hz)
			speed = min(t->speed_hz, spi->max_speed_hz);
	}

	if (!speed || (speed > spi->max_speed_hz)) {
		dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
		return -EINVAL;
	}

	/* Write new configuration */
	out_8(&hw->regs->mode, cs->mode);

	/* Set the clock */
	/* opb_freq was already divided by 4 */
	scr = (hw->opb_freq / speed) - 1;
	if (scr > 0)
		cdm = min(scr, 0xff);

	dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);

	if (in_8(&hw->regs->cdm) != cdm)
		out_8(&hw->regs->cdm, cdm);

	mutex_lock(&hw->bitbang.lock);
	if (!hw->bitbang.busy) {
		hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
		/* Need to ndelay here? */
	}
	mutex_unlock(&hw->bitbang.lock);

	return 0;
}

static int spi_ppc4xx_setup(struct spi_device *spi)
{
	struct spi_ppc4xx_cs *cs = spi->controller_state;

	if (!spi->max_speed_hz) {
		dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
		return -EINVAL;
	}

	if (cs == NULL) {
		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}

	/*
	 * We set all bits of the SPI0_MODE register, so,
	 * no need to read-modify-write
	 */
	cs->mode = SPI_PPC4XX_MODE_SPE;

	switch (spi->mode & SPI_MODE_X_MASK) {
	case SPI_MODE_0:
		cs->mode |= SPI_CLK_MODE0;
		break;
	case SPI_MODE_1:
		cs->mode |= SPI_CLK_MODE1;
		break;
	case SPI_MODE_2:
		cs->mode |= SPI_CLK_MODE2;
		break;
	case SPI_MODE_3:
		cs->mode |= SPI_CLK_MODE3;
		break;
	}

	if (spi->mode & SPI_LSB_FIRST)
		cs->mode |= SPI_PPC4XX_MODE_RD;

	return 0;
}

static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
{
	struct ppc4xx_spi *hw;
	u8 status;
	u8 data;
	unsigned int count;

	hw = (struct ppc4xx_spi *)dev_id;

	status = in_8(&hw->regs->sr);
	if (!status)
		return IRQ_NONE;

	/*
	 * BSY de-asserts one cycle after the transfer is complete.  The
	 * interrupt is asserted after the transfer is complete.  The exact
	 * relationship is not documented, hence this code.
	 */

	if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
		u8 lstatus;
		int cnt = 0;

		dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
		do {
			ndelay(10);
			lstatus = in_8(&hw->regs->sr);
		} while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);

		if (cnt >= 100) {
			dev_err(hw->dev, "busywait: too many loops!\n");
			complete(&hw->done);
			return IRQ_HANDLED;
		} else {
			/* status is always 1 (RBR) here */
			status = in_8(&hw->regs->sr);
			dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
		}
	}

	count = hw->count;
	hw->count++;

	/* RBR triggered this interrupt.  Therefore, data must be ready. */
	data = in_8(&hw->regs->rxd);
	if (hw->rx)
		hw->rx[count] = data;

	count++;

	if (count < hw->len) {
		data = hw->tx ? hw->tx[count] : 0;
		out_8(&hw->regs->txd, data);
		out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
	} else {
		complete(&hw->done);
	}

	return IRQ_HANDLED;
}

static void spi_ppc4xx_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}

static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
{
	/*
	 * On all 4xx PPC's the SPI bus is shared/multiplexed with
	 * the 2nd I2C bus. We need to enable the SPI bus before
	 * using it.
	 */

	/* need to clear bit 14 to enable SPC */
	dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
}

/*
 * platform_device layer stuff...
 */
static int spi_ppc4xx_of_probe(struct platform_device *op)
{
	struct ppc4xx_spi *hw;
	struct spi_master *master;
	struct spi_bitbang *bbp;
	struct resource resource;
	struct device_node *np = op->dev.of_node;
	struct device *dev = &op->dev;
	struct device_node *opbnp;
	int ret;
	const unsigned int *clk;

	master = spi_alloc_master(dev, sizeof(*hw));
	if (master == NULL)
		return -ENOMEM;
	master->dev.of_node = np;
	platform_set_drvdata(op, master);
	hw = spi_master_get_devdata(master);
	hw->master = master;
	hw->dev = dev;

	init_completion(&hw->done);

	/* Setup the state for the bitbang driver */
	bbp = &hw->bitbang;
	bbp->master = hw->master;
	bbp->setup_transfer = spi_ppc4xx_setupxfer;
	bbp->txrx_bufs = spi_ppc4xx_txrx;
	bbp->use_dma = 0;
	bbp->master->setup = spi_ppc4xx_setup;
	bbp->master->cleanup = spi_ppc4xx_cleanup;
	bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
	bbp->master->use_gpio_descriptors = true;
	/*
	 * The SPI core will count the number of GPIO descriptors to figure
	 * out the number of chip selects available on the platform.
	 */
	bbp->master->num_chipselect = 0;

	/* the spi->mode bits understood by this driver: */
	bbp->master->mode_bits =
		SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;

	/* Get the clock for the OPB */
	opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
	if (opbnp == NULL) {
		dev_err(dev, "OPB: cannot find node\n");
		ret = -ENODEV;
		goto free_master;
	}
	/* Get the clock (Hz) for the OPB */
	clk = of_get_property(opbnp, "clock-frequency", NULL);
	if (clk == NULL) {
		dev_err(dev, "OPB: no clock-frequency property set\n");
		of_node_put(opbnp);
		ret = -ENODEV;
		goto free_master;
	}
	hw->opb_freq = *clk;
	hw->opb_freq >>= 2;
	of_node_put(opbnp);

	ret = of_address_to_resource(np, 0, &resource);
	if (ret) {
		dev_err(dev, "error while parsing device node resource\n");
		goto free_master;
	}
	hw->mapbase = resource.start;
	hw->mapsize = resource_size(&resource);

	/* Sanity check */
	if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
		dev_err(dev, "too small to map registers\n");
		ret = -EINVAL;
		goto free_master;
	}

	/* Request IRQ */
	hw->irqnum = irq_of_parse_and_map(np, 0);
	ret = request_irq(hw->irqnum, spi_ppc4xx_int,
			  0, "spi_ppc4xx_of", (void *)hw);
	if (ret) {
		dev_err(dev, "unable to allocate interrupt\n");
		goto free_master;
	}

	if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
		dev_err(dev, "resource unavailable\n");
		ret = -EBUSY;
		goto request_mem_error;
	}

	hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));

	if (!hw->regs) {
		dev_err(dev, "unable to memory map registers\n");
		ret = -ENXIO;
		goto map_io_error;
	}

	spi_ppc4xx_enable(hw);

	/* Finally register our spi controller */
	dev->dma_mask = 0;
	ret = spi_bitbang_start(bbp);
	if (ret) {
		dev_err(dev, "failed to register SPI master\n");
		goto unmap_regs;
	}

	dev_info(dev, "driver initialized\n");

	return 0;

unmap_regs:
	iounmap(hw->regs);
map_io_error:
	release_mem_region(hw->mapbase, hw->mapsize);
request_mem_error:
	free_irq(hw->irqnum, hw);
free_master:
	spi_master_put(master);

	dev_err(dev, "initialization failed\n");
	return ret;
}

static int spi_ppc4xx_of_remove(struct platform_device *op)
{
	struct spi_master *master = platform_get_drvdata(op);
	struct ppc4xx_spi *hw = spi_master_get_devdata(master);

	spi_bitbang_stop(&hw->bitbang);
	release_mem_region(hw->mapbase, hw->mapsize);
	free_irq(hw->irqnum, hw);
	iounmap(hw->regs);
	spi_master_put(master);
	return 0;
}

static const struct of_device_id spi_ppc4xx_of_match[] = {
	{ .compatible = "ibm,ppc4xx-spi", },
	{},
};

MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);

static struct platform_driver spi_ppc4xx_of_driver = {
	.probe = spi_ppc4xx_of_probe,
	.remove = spi_ppc4xx_of_remove,
	.driver = {
		.name = DRIVER_NAME,
		.of_match_table = spi_ppc4xx_of_match,
	},
};
module_platform_driver(spi_ppc4xx_of_driver);

MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
44dab88e SF	2	/*
	3	* SPI_PPC4XX SPI controller driver.
	4	*
	5	* Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
	6	* Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
	7	* Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
	8	*
	9	* Based in part on drivers/spi/spi_s3c24xx.c
	10	*
	11	* Copyright (c) 2006 Ben Dooks
	12	* Copyright (c) 2006 Simtec Electronics
	13	* Ben Dooks <ben@simtec.co.uk>
44dab88e SF	14	*/
	15
	16	/*
	17	* The PPC4xx SPI controller has no FIFO so each sent/received byte will
	18	* generate an interrupt to the CPU. This can cause high CPU utilization.
	19	* This driver allows platforms to reduce the interrupt load on the CPU
	20	* during SPI transfers by setting max_speed_hz via the device tree.
	21	*/
	22
	23	#include <linux/module.h>
44dab88e	24	#include <linux/sched.h>
5a0e3ad6	25	#include <linux/slab.h>
44dab88e SF	26	#include <linux/errno.h>
44dab88e SF	27	#include <linux/wait.h>
c11eede6 RH	28	#include <linux/of_address.h>
c11eede6 RH	29	#include <linux/of_irq.h>
44dab88e	30	#include <linux/of_platform.h>
44dab88e SF	31	#include <linux/interrupt.h>
	32	#include <linux/delay.h>
	33
44dab88e SF	34	#include <linux/spi/spi.h>
	35	#include <linux/spi/spi_bitbang.h>
	36
66fe7403	37	#include <linux/io.h>
44dab88e SF	38	#include <asm/dcr.h>
	39	#include <asm/dcr-regs.h>
	40
	41	/* bits in mode register - bit 0 is MSb */
	42
	43	/*
	44	* SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
	45	* SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
	46	* Note: This is the inverse of CPHA.
	47	*/
	48	#define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
	49
	50	/* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
	51	#define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
	52
	53	/*
	54	* SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
	55	* SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
	56	* Note: This is identical to SPI_LSB_FIRST.
	57	*/
	58	#define SPI_PPC4XX_MODE_RD (0x80 >> 5)
	59
	60	/*
	61	* SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
	62	* SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
	63	* Note: This is identical to CPOL.
	64	*/
	65	#define SPI_PPC4XX_MODE_CI (0x80 >> 6)
	66
	67	/*
	68	* SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
	69	* SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
	70	*/
	71	#define SPI_PPC4XX_MODE_IL (0x80 >> 7)
	72
	73	/* bits in control register */
	74	/* starts a transfer when set */
	75	#define SPI_PPC4XX_CR_STR (0x80 >> 7)
	76
	77	/* bits in status register */
	78	/* port is busy with a transfer */
	79	#define SPI_PPC4XX_SR_BSY (0x80 >> 6)
	80	/* RxD ready */
	81	#define SPI_PPC4XX_SR_RBR (0x80 >> 7)
	82
	83	/* clock settings (SCP and CI) for various SPI modes */
	84	#define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP \| 0)
	85	#define SPI_CLK_MODE1 (0 \| 0)
	86	#define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP \| SPI_PPC4XX_MODE_CI)
	87	#define SPI_CLK_MODE3 (0 \| SPI_PPC4XX_MODE_CI)
	88
	89	#define DRIVER_NAME "spi_ppc4xx_of"
	90
	91	struct spi_ppc4xx_regs {
	92	u8 mode;
	93	u8 rxd;
	94	u8 txd;
	95	u8 cr;
	96	u8 sr;
	97	u8 dummy;
	98	/*
	99	* Clock divisor modulus register
886db6ac	100	* This uses the following formula:
44dab88e SF	101	* SCPClkOut = OPBCLK/(4(CDM + 1))
	102	* or
	103	* CDM = (OPBCLK/4*SCPClkOut) - 1
	104	* bit 0 is the MSb!
	105	*/
	106	u8 cdm;
	107	};
	108
	109	/* SPI Controller driver's private data. */
	110	struct ppc4xx_spi {
	111	/* bitbang has to be first */
	112	struct spi_bitbang bitbang;
	113	struct completion done;
	114
	115	u64 mapbase;
	116	u64 mapsize;
	117	int irqnum;
	118	/* need this to set the SPI clock */
	119	unsigned int opb_freq;
	120
	121	/* for transfers */
	122	int len;
	123	int count;
	124	/* data buffers */
	125	const unsigned char *tx;
	126	unsigned char *rx;
	127
44dab88e SF	128	struct spi_ppc4xx_regs __iomem regs; / pointer to the registers */
	129	struct spi_master *master;
	130	struct device *dev;
	131	};
	132
	133	/* need this so we can set the clock in the chipselect routine */
	134	struct spi_ppc4xx_cs {
	135	u8 mode;
	136	};
	137
	138	static int spi_ppc4xx_txrx(struct spi_device spi, struct spi_transfer t)
	139	{
	140	struct ppc4xx_spi *hw;
	141	u8 data;
	142
	143	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
	144	t->tx_buf, t->rx_buf, t->len);
	145
	146	hw = spi_master_get_devdata(spi->master);
	147
	148	hw->tx = t->tx_buf;
	149	hw->rx = t->rx_buf;
	150	hw->len = t->len;
	151	hw->count = 0;
	152
	153	/* send the first byte */
	154	data = hw->tx ? hw->tx[0] : 0;
	155	out_8(&hw->regs->txd, data);
	156	out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
	157	wait_for_completion(&hw->done);
	158
	159	return hw->count;
	160	}
	161
	162	static int spi_ppc4xx_setupxfer(struct spi_device spi, struct spi_transfer t)
	163	{
	164	struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
	165	struct spi_ppc4xx_cs *cs = spi->controller_state;
	166	int scr;
	167	u8 cdm = 0;
	168	u32 speed;
	169	u8 bits_per_word;
	170
	171	/* Start with the generic configuration for this device. */
	172	bits_per_word = spi->bits_per_word;
	173	speed = spi->max_speed_hz;
	174
	175	/*
	176	* Modify the configuration if the transfer overrides it. Do not allow
	177	* the transfer to overwrite the generic configuration with zeros.
	178	*/
	179	if (t) {
	180	if (t->bits_per_word)
	181	bits_per_word = t->bits_per_word;
	182
	183	if (t->speed_hz)
	184	speed = min(t->speed_hz, spi->max_speed_hz);
	185	}
	186
44dab88e SF	187	if (!speed \|\| (speed > spi->max_speed_hz)) {
	188	dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
	189	return -EINVAL;
	190	}
	191
886db6ac	192	/* Write new configuration */
44dab88e SF	193	out_8(&hw->regs->mode, cs->mode);
	194
	195	/* Set the clock */
	196	/* opb_freq was already divided by 4 */
	197	scr = (hw->opb_freq / speed) - 1;
	198	if (scr > 0)
	199	cdm = min(scr, 0xff);
	200
	201	dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
	202
	203	if (in_8(&hw->regs->cdm) != cdm)
	204	out_8(&hw->regs->cdm, cdm);
	205
c15f6ed3	206	mutex_lock(&hw->bitbang.lock);
44dab88e SF	207	if (!hw->bitbang.busy) {
	208	hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
	209	/* Need to ndelay here? */
	210	}
c15f6ed3	211	mutex_unlock(&hw->bitbang.lock);
44dab88e SF	212
	213	return 0;
	214	}
	215
	216	static int spi_ppc4xx_setup(struct spi_device *spi)
	217	{
	218	struct spi_ppc4xx_cs *cs = spi->controller_state;
	219
44dab88e SF	220	if (!spi->max_speed_hz) {
	221	dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
	222	return -EINVAL;
	223	}
	224
	225	if (cs == NULL) {
07c74f84	226	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
44dab88e SF	227	if (!cs)
	228	return -ENOMEM;
	229	spi->controller_state = cs;
	230	}
	231
	232	/*
	233	* We set all bits of the SPI0_MODE register, so,
	234	* no need to read-modify-write
	235	*/
	236	cs->mode = SPI_PPC4XX_MODE_SPE;
	237
4ccf0557	238	switch (spi->mode & SPI_MODE_X_MASK) {
44dab88e SF	239	case SPI_MODE_0:
	240	cs->mode \|= SPI_CLK_MODE0;
	241	break;
	242	case SPI_MODE_1:
	243	cs->mode \|= SPI_CLK_MODE1;
	244	break;
	245	case SPI_MODE_2:
	246	cs->mode \|= SPI_CLK_MODE2;
	247	break;
	248	case SPI_MODE_3:
	249	cs->mode \|= SPI_CLK_MODE3;
	250	break;
	251	}
	252
	253	if (spi->mode & SPI_LSB_FIRST)
	254	cs->mode \|= SPI_PPC4XX_MODE_RD;
	255
	256	return 0;
	257	}
	258
44dab88e SF	259	static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
	260	{
	261	struct ppc4xx_spi *hw;
	262	u8 status;
	263	u8 data;
	264	unsigned int count;
	265
	266	hw = (struct ppc4xx_spi *)dev_id;
	267
	268	status = in_8(&hw->regs->sr);
	269	if (!status)
	270	return IRQ_NONE;
	271
	272	/*
	273	* BSY de-asserts one cycle after the transfer is complete. The
	274	* interrupt is asserted after the transfer is complete. The exact
	275	* relationship is not documented, hence this code.
	276	*/
	277
	278	if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
	279	u8 lstatus;
	280	int cnt = 0;
	281
	282	dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
	283	do {
	284	ndelay(10);
	285	lstatus = in_8(&hw->regs->sr);
	286	} while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
	287
	288	if (cnt >= 100) {
	289	dev_err(hw->dev, "busywait: too many loops!\n");
	290	complete(&hw->done);
	291	return IRQ_HANDLED;
	292	} else {
	293	/* status is always 1 (RBR) here */
	294	status = in_8(&hw->regs->sr);
	295	dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
	296	}
	297	}
	298
	299	count = hw->count;
	300	hw->count++;
	301
	302	/* RBR triggered this interrupt. Therefore, data must be ready. */
	303	data = in_8(&hw->regs->rxd);
	304	if (hw->rx)
	305	hw->rx[count] = data;
	306
	307	count++;
	308
	309	if (count < hw->len) {
	310	data = hw->tx ? hw->tx[count] : 0;
	311	out_8(&hw->regs->txd, data);
	312	out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
	313	} else {
	314	complete(&hw->done);
	315	}
	316
	317	return IRQ_HANDLED;
	318	}
	319
	320	static void spi_ppc4xx_cleanup(struct spi_device *spi)
	321	{
	322	kfree(spi->controller_state);
323	}
324
325	static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
326	{
327	/*
328	* On all 4xx PPC's the SPI bus is shared/multiplexed with
db56d030	329	* the 2nd I2C bus. We need to enable the SPI bus before
44dab88e SF	330	* using it.
	331	*/
	332
	333	/* need to clear bit 14 to enable SPC */
	334	dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
	335	}
	336
44dab88e	337	/*
2dc11581	338	* platform_device layer stuff...
44dab88e	339	*/
2deff8d6	340	static int spi_ppc4xx_of_probe(struct platform_device *op)
44dab88e SF	341	{
	342	struct ppc4xx_spi *hw;
	343	struct spi_master *master;
	344	struct spi_bitbang *bbp;
	345	struct resource resource;
b5355078	346	struct device_node *np = op->dev.of_node;
44dab88e SF	347	struct device *dev = &op->dev;
	348	struct device_node *opbnp;
	349	int ret;
44dab88e SF	350	const unsigned int *clk;
44dab88e SF	351
07c74f84	352	master = spi_alloc_master(dev, sizeof(*hw));
44dab88e SF	353	if (master == NULL)
44dab88e SF	354	return -ENOMEM;
12b15e83	355	master->dev.of_node = np;
24b5a82c	356	platform_set_drvdata(op, master);
44dab88e	357	hw = spi_master_get_devdata(master);
94c69f76	358	hw->master = master;
44dab88e SF	359	hw->dev = dev;
	360
	361	init_completion(&hw->done);
	362
44dab88e SF	363	/* Setup the state for the bitbang driver */
	364	bbp = &hw->bitbang;
	365	bbp->master = hw->master;
	366	bbp->setup_transfer = spi_ppc4xx_setupxfer;
44dab88e SF	367	bbp->txrx_bufs = spi_ppc4xx_txrx;
	368	bbp->use_dma = 0;
	369	bbp->master->setup = spi_ppc4xx_setup;
	370	bbp->master->cleanup = spi_ppc4xx_cleanup;
24778be2	371	bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
47267732 LW	372	bbp->master->use_gpio_descriptors = true;
	373	/*
	374	* The SPI core will count the number of GPIO descriptors to figure
	375	* out the number of chip selects available on the platform.
	376	*/
	377	bbp->master->num_chipselect = 0;
44dab88e	378
44dab88e SF	379	/* the spi->mode bits understood by this driver: */
	380	bbp->master->mode_bits =
	381	SPI_CPHA \| SPI_CPOL \| SPI_CS_HIGH \| SPI_LSB_FIRST;
	382
44dab88e SF	383	/* Get the clock for the OPB */
	384	opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
	385	if (opbnp == NULL) {
	386	dev_err(dev, "OPB: cannot find node\n");
	387	ret = -ENODEV;
47267732	388	goto free_master;
44dab88e SF	389	}
	390	/* Get the clock (Hz) for the OPB */
	391	clk = of_get_property(opbnp, "clock-frequency", NULL);
	392	if (clk == NULL) {
	393	dev_err(dev, "OPB: no clock-frequency property set\n");
	394	of_node_put(opbnp);
	395	ret = -ENODEV;
47267732	396	goto free_master;
44dab88e SF	397	}
	398	hw->opb_freq = *clk;
	399	hw->opb_freq >>= 2;
	400	of_node_put(opbnp);
	401
	402	ret = of_address_to_resource(np, 0, &resource);
	403	if (ret) {
	404	dev_err(dev, "error while parsing device node resource\n");
47267732	405	goto free_master;
44dab88e SF	406	}
44dab88e SF	407	hw->mapbase = resource.start;
8e2943c0	408	hw->mapsize = resource_size(&resource);
44dab88e SF	409
	410	/* Sanity check */
	411	if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
	412	dev_err(dev, "too small to map registers\n");
	413	ret = -EINVAL;
47267732	414	goto free_master;
44dab88e SF	415	}
	416
	417	/* Request IRQ */
	418	hw->irqnum = irq_of_parse_and_map(np, 0);
	419	ret = request_irq(hw->irqnum, spi_ppc4xx_int,
38ada214	420	0, "spi_ppc4xx_of", (void *)hw);
44dab88e SF	421	if (ret) {
44dab88e SF	422	dev_err(dev, "unable to allocate interrupt\n");
47267732	423	goto free_master;
44dab88e SF	424	}
	425
	426	if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
	427	dev_err(dev, "resource unavailable\n");
	428	ret = -EBUSY;
	429	goto request_mem_error;
	430	}
	431
	432	hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
	433
	434	if (!hw->regs) {
	435	dev_err(dev, "unable to memory map registers\n");
	436	ret = -ENXIO;
	437	goto map_io_error;
	438	}
	439
	440	spi_ppc4xx_enable(hw);
	441
	442	/* Finally register our spi controller */
	443	dev->dma_mask = 0;
	444	ret = spi_bitbang_start(bbp);
	445	if (ret) {
	446	dev_err(dev, "failed to register SPI master\n");
	447	goto unmap_regs;
	448	}
	449
	450	dev_info(dev, "driver initialized\n");
44dab88e SF	451
	452	return 0;
	453
	454	unmap_regs:
	455	iounmap(hw->regs);
	456	map_io_error:
	457	release_mem_region(hw->mapbase, hw->mapsize);
	458	request_mem_error:
	459	free_irq(hw->irqnum, hw);
44dab88e	460	free_master:
44dab88e SF	461	spi_master_put(master);
	462
	463	dev_err(dev, "initialization failed\n");
	464	return ret;
	465	}
	466
2deff8d6	467	static int spi_ppc4xx_of_remove(struct platform_device *op)
44dab88e	468	{
24b5a82c	469	struct spi_master *master = platform_get_drvdata(op);
44dab88e SF	470	struct ppc4xx_spi *hw = spi_master_get_devdata(master);
	471
	472	spi_bitbang_stop(&hw->bitbang);
44dab88e SF	473	release_mem_region(hw->mapbase, hw->mapsize);
	474	free_irq(hw->irqnum, hw);
	475	iounmap(hw->regs);
94c69f76	476	spi_master_put(master);
44dab88e SF	477	return 0;
	478	}
	479
631e61b7	480	static const struct of_device_id spi_ppc4xx_of_match[] = {
44dab88e SF	481	{ .compatible = "ibm,ppc4xx-spi", },
	482	{},
	483	};
	484
	485	MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
	486
18d306d1	487	static struct platform_driver spi_ppc4xx_of_driver = {
44dab88e	488	.probe = spi_ppc4xx_of_probe,
2deff8d6	489	.remove = spi_ppc4xx_of_remove,
44dab88e SF	490	.driver = {
44dab88e SF	491	.name = DRIVER_NAME,
4018294b	492	.of_match_table = spi_ppc4xx_of_match,
44dab88e SF	493	},
44dab88e SF	494	};
940ab889	495	module_platform_driver(spi_ppc4xx_of_driver);
44dab88e SF	496
	497	MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
	498	MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
	499	MODULE_LICENSE("GPL");