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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
44dab88e SF |
2 | /* |
3 | * SPI_PPC4XX SPI controller driver. | |
4 | * | |
5 | * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de> | |
6 | * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering | |
7 | * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com> | |
8 | * | |
9 | * Based in part on drivers/spi/spi_s3c24xx.c | |
10 | * | |
11 | * Copyright (c) 2006 Ben Dooks | |
12 | * Copyright (c) 2006 Simtec Electronics | |
13 | * Ben Dooks <ben@simtec.co.uk> | |
44dab88e SF |
14 | */ |
15 | ||
16 | /* | |
17 | * The PPC4xx SPI controller has no FIFO so each sent/received byte will | |
18 | * generate an interrupt to the CPU. This can cause high CPU utilization. | |
19 | * This driver allows platforms to reduce the interrupt load on the CPU | |
20 | * during SPI transfers by setting max_speed_hz via the device tree. | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
44dab88e | 24 | #include <linux/sched.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
44dab88e SF |
26 | #include <linux/errno.h> |
27 | #include <linux/wait.h> | |
c11eede6 RH |
28 | #include <linux/of_address.h> |
29 | #include <linux/of_irq.h> | |
44dab88e | 30 | #include <linux/of_platform.h> |
44dab88e SF |
31 | #include <linux/of_gpio.h> |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/delay.h> | |
34 | ||
35 | #include <linux/gpio.h> | |
36 | #include <linux/spi/spi.h> | |
37 | #include <linux/spi/spi_bitbang.h> | |
38 | ||
39 | #include <asm/io.h> | |
40 | #include <asm/dcr.h> | |
41 | #include <asm/dcr-regs.h> | |
42 | ||
43 | /* bits in mode register - bit 0 is MSb */ | |
44 | ||
45 | /* | |
46 | * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock" | |
47 | * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock" | |
48 | * Note: This is the inverse of CPHA. | |
49 | */ | |
50 | #define SPI_PPC4XX_MODE_SCP (0x80 >> 3) | |
51 | ||
52 | /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */ | |
53 | #define SPI_PPC4XX_MODE_SPE (0x80 >> 4) | |
54 | ||
55 | /* | |
56 | * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode | |
57 | * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode | |
58 | * Note: This is identical to SPI_LSB_FIRST. | |
59 | */ | |
60 | #define SPI_PPC4XX_MODE_RD (0x80 >> 5) | |
61 | ||
62 | /* | |
63 | * SPI_PPC4XX_MODE_CI = 0 means "clock idles low" | |
64 | * SPI_PPC4XX_MODE_CI = 1 means "clock idles high" | |
65 | * Note: This is identical to CPOL. | |
66 | */ | |
67 | #define SPI_PPC4XX_MODE_CI (0x80 >> 6) | |
68 | ||
69 | /* | |
70 | * SPI_PPC4XX_MODE_IL = 0 means "loopback disable" | |
71 | * SPI_PPC4XX_MODE_IL = 1 means "loopback enable" | |
72 | */ | |
73 | #define SPI_PPC4XX_MODE_IL (0x80 >> 7) | |
74 | ||
75 | /* bits in control register */ | |
76 | /* starts a transfer when set */ | |
77 | #define SPI_PPC4XX_CR_STR (0x80 >> 7) | |
78 | ||
79 | /* bits in status register */ | |
80 | /* port is busy with a transfer */ | |
81 | #define SPI_PPC4XX_SR_BSY (0x80 >> 6) | |
82 | /* RxD ready */ | |
83 | #define SPI_PPC4XX_SR_RBR (0x80 >> 7) | |
84 | ||
85 | /* clock settings (SCP and CI) for various SPI modes */ | |
86 | #define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0) | |
87 | #define SPI_CLK_MODE1 (0 | 0) | |
88 | #define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI) | |
89 | #define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI) | |
90 | ||
91 | #define DRIVER_NAME "spi_ppc4xx_of" | |
92 | ||
93 | struct spi_ppc4xx_regs { | |
94 | u8 mode; | |
95 | u8 rxd; | |
96 | u8 txd; | |
97 | u8 cr; | |
98 | u8 sr; | |
99 | u8 dummy; | |
100 | /* | |
101 | * Clock divisor modulus register | |
886db6ac | 102 | * This uses the following formula: |
44dab88e SF |
103 | * SCPClkOut = OPBCLK/(4(CDM + 1)) |
104 | * or | |
105 | * CDM = (OPBCLK/4*SCPClkOut) - 1 | |
106 | * bit 0 is the MSb! | |
107 | */ | |
108 | u8 cdm; | |
109 | }; | |
110 | ||
111 | /* SPI Controller driver's private data. */ | |
112 | struct ppc4xx_spi { | |
113 | /* bitbang has to be first */ | |
114 | struct spi_bitbang bitbang; | |
115 | struct completion done; | |
116 | ||
117 | u64 mapbase; | |
118 | u64 mapsize; | |
119 | int irqnum; | |
120 | /* need this to set the SPI clock */ | |
121 | unsigned int opb_freq; | |
122 | ||
123 | /* for transfers */ | |
124 | int len; | |
125 | int count; | |
126 | /* data buffers */ | |
127 | const unsigned char *tx; | |
128 | unsigned char *rx; | |
129 | ||
130 | int *gpios; | |
131 | ||
132 | struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */ | |
133 | struct spi_master *master; | |
134 | struct device *dev; | |
135 | }; | |
136 | ||
137 | /* need this so we can set the clock in the chipselect routine */ | |
138 | struct spi_ppc4xx_cs { | |
139 | u8 mode; | |
140 | }; | |
141 | ||
142 | static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t) | |
143 | { | |
144 | struct ppc4xx_spi *hw; | |
145 | u8 data; | |
146 | ||
147 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", | |
148 | t->tx_buf, t->rx_buf, t->len); | |
149 | ||
150 | hw = spi_master_get_devdata(spi->master); | |
151 | ||
152 | hw->tx = t->tx_buf; | |
153 | hw->rx = t->rx_buf; | |
154 | hw->len = t->len; | |
155 | hw->count = 0; | |
156 | ||
157 | /* send the first byte */ | |
158 | data = hw->tx ? hw->tx[0] : 0; | |
159 | out_8(&hw->regs->txd, data); | |
160 | out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); | |
161 | wait_for_completion(&hw->done); | |
162 | ||
163 | return hw->count; | |
164 | } | |
165 | ||
166 | static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t) | |
167 | { | |
168 | struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master); | |
169 | struct spi_ppc4xx_cs *cs = spi->controller_state; | |
170 | int scr; | |
171 | u8 cdm = 0; | |
172 | u32 speed; | |
173 | u8 bits_per_word; | |
174 | ||
175 | /* Start with the generic configuration for this device. */ | |
176 | bits_per_word = spi->bits_per_word; | |
177 | speed = spi->max_speed_hz; | |
178 | ||
179 | /* | |
180 | * Modify the configuration if the transfer overrides it. Do not allow | |
181 | * the transfer to overwrite the generic configuration with zeros. | |
182 | */ | |
183 | if (t) { | |
184 | if (t->bits_per_word) | |
185 | bits_per_word = t->bits_per_word; | |
186 | ||
187 | if (t->speed_hz) | |
188 | speed = min(t->speed_hz, spi->max_speed_hz); | |
189 | } | |
190 | ||
44dab88e SF |
191 | if (!speed || (speed > spi->max_speed_hz)) { |
192 | dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed); | |
193 | return -EINVAL; | |
194 | } | |
195 | ||
886db6ac | 196 | /* Write new configuration */ |
44dab88e SF |
197 | out_8(&hw->regs->mode, cs->mode); |
198 | ||
199 | /* Set the clock */ | |
200 | /* opb_freq was already divided by 4 */ | |
201 | scr = (hw->opb_freq / speed) - 1; | |
202 | if (scr > 0) | |
203 | cdm = min(scr, 0xff); | |
204 | ||
205 | dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed); | |
206 | ||
207 | if (in_8(&hw->regs->cdm) != cdm) | |
208 | out_8(&hw->regs->cdm, cdm); | |
209 | ||
c15f6ed3 | 210 | mutex_lock(&hw->bitbang.lock); |
44dab88e SF |
211 | if (!hw->bitbang.busy) { |
212 | hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); | |
213 | /* Need to ndelay here? */ | |
214 | } | |
c15f6ed3 | 215 | mutex_unlock(&hw->bitbang.lock); |
44dab88e SF |
216 | |
217 | return 0; | |
218 | } | |
219 | ||
220 | static int spi_ppc4xx_setup(struct spi_device *spi) | |
221 | { | |
222 | struct spi_ppc4xx_cs *cs = spi->controller_state; | |
223 | ||
44dab88e SF |
224 | if (!spi->max_speed_hz) { |
225 | dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n"); | |
226 | return -EINVAL; | |
227 | } | |
228 | ||
229 | if (cs == NULL) { | |
230 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
231 | if (!cs) | |
232 | return -ENOMEM; | |
233 | spi->controller_state = cs; | |
234 | } | |
235 | ||
236 | /* | |
237 | * We set all bits of the SPI0_MODE register, so, | |
238 | * no need to read-modify-write | |
239 | */ | |
240 | cs->mode = SPI_PPC4XX_MODE_SPE; | |
241 | ||
242 | switch (spi->mode & (SPI_CPHA | SPI_CPOL)) { | |
243 | case SPI_MODE_0: | |
244 | cs->mode |= SPI_CLK_MODE0; | |
245 | break; | |
246 | case SPI_MODE_1: | |
247 | cs->mode |= SPI_CLK_MODE1; | |
248 | break; | |
249 | case SPI_MODE_2: | |
250 | cs->mode |= SPI_CLK_MODE2; | |
251 | break; | |
252 | case SPI_MODE_3: | |
253 | cs->mode |= SPI_CLK_MODE3; | |
254 | break; | |
255 | } | |
256 | ||
257 | if (spi->mode & SPI_LSB_FIRST) | |
258 | cs->mode |= SPI_PPC4XX_MODE_RD; | |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
263 | static void spi_ppc4xx_chipsel(struct spi_device *spi, int value) | |
264 | { | |
265 | struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master); | |
266 | unsigned int cs = spi->chip_select; | |
267 | unsigned int cspol; | |
268 | ||
269 | /* | |
270 | * If there are no chip selects at all, or if this is the special | |
271 | * case of a non-existent (dummy) chip select, do nothing. | |
272 | */ | |
273 | ||
274 | if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST) | |
275 | return; | |
276 | ||
277 | cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; | |
278 | if (value == BITBANG_CS_INACTIVE) | |
279 | cspol = !cspol; | |
280 | ||
281 | gpio_set_value(hw->gpios[cs], cspol); | |
282 | } | |
283 | ||
284 | static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id) | |
285 | { | |
286 | struct ppc4xx_spi *hw; | |
287 | u8 status; | |
288 | u8 data; | |
289 | unsigned int count; | |
290 | ||
291 | hw = (struct ppc4xx_spi *)dev_id; | |
292 | ||
293 | status = in_8(&hw->regs->sr); | |
294 | if (!status) | |
295 | return IRQ_NONE; | |
296 | ||
297 | /* | |
298 | * BSY de-asserts one cycle after the transfer is complete. The | |
299 | * interrupt is asserted after the transfer is complete. The exact | |
300 | * relationship is not documented, hence this code. | |
301 | */ | |
302 | ||
303 | if (unlikely(status & SPI_PPC4XX_SR_BSY)) { | |
304 | u8 lstatus; | |
305 | int cnt = 0; | |
306 | ||
307 | dev_dbg(hw->dev, "got interrupt but spi still busy?\n"); | |
308 | do { | |
309 | ndelay(10); | |
310 | lstatus = in_8(&hw->regs->sr); | |
311 | } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY); | |
312 | ||
313 | if (cnt >= 100) { | |
314 | dev_err(hw->dev, "busywait: too many loops!\n"); | |
315 | complete(&hw->done); | |
316 | return IRQ_HANDLED; | |
317 | } else { | |
318 | /* status is always 1 (RBR) here */ | |
319 | status = in_8(&hw->regs->sr); | |
320 | dev_dbg(hw->dev, "loops %d status %x\n", cnt, status); | |
321 | } | |
322 | } | |
323 | ||
324 | count = hw->count; | |
325 | hw->count++; | |
326 | ||
327 | /* RBR triggered this interrupt. Therefore, data must be ready. */ | |
328 | data = in_8(&hw->regs->rxd); | |
329 | if (hw->rx) | |
330 | hw->rx[count] = data; | |
331 | ||
332 | count++; | |
333 | ||
334 | if (count < hw->len) { | |
335 | data = hw->tx ? hw->tx[count] : 0; | |
336 | out_8(&hw->regs->txd, data); | |
337 | out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); | |
338 | } else { | |
339 | complete(&hw->done); | |
340 | } | |
341 | ||
342 | return IRQ_HANDLED; | |
343 | } | |
344 | ||
345 | static void spi_ppc4xx_cleanup(struct spi_device *spi) | |
346 | { | |
347 | kfree(spi->controller_state); | |
348 | } | |
349 | ||
350 | static void spi_ppc4xx_enable(struct ppc4xx_spi *hw) | |
351 | { | |
352 | /* | |
353 | * On all 4xx PPC's the SPI bus is shared/multiplexed with | |
354 | * the 2nd I2C bus. We need to enable the the SPI bus before | |
355 | * using it. | |
356 | */ | |
357 | ||
358 | /* need to clear bit 14 to enable SPC */ | |
359 | dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0); | |
360 | } | |
361 | ||
362 | static void free_gpios(struct ppc4xx_spi *hw) | |
363 | { | |
364 | if (hw->master->num_chipselect) { | |
365 | int i; | |
366 | for (i = 0; i < hw->master->num_chipselect; i++) | |
367 | if (gpio_is_valid(hw->gpios[i])) | |
368 | gpio_free(hw->gpios[i]); | |
369 | ||
370 | kfree(hw->gpios); | |
371 | hw->gpios = NULL; | |
372 | } | |
373 | } | |
374 | ||
375 | /* | |
2dc11581 | 376 | * platform_device layer stuff... |
44dab88e | 377 | */ |
2deff8d6 | 378 | static int spi_ppc4xx_of_probe(struct platform_device *op) |
44dab88e SF |
379 | { |
380 | struct ppc4xx_spi *hw; | |
381 | struct spi_master *master; | |
382 | struct spi_bitbang *bbp; | |
383 | struct resource resource; | |
b5355078 | 384 | struct device_node *np = op->dev.of_node; |
44dab88e SF |
385 | struct device *dev = &op->dev; |
386 | struct device_node *opbnp; | |
387 | int ret; | |
388 | int num_gpios; | |
389 | const unsigned int *clk; | |
390 | ||
391 | master = spi_alloc_master(dev, sizeof *hw); | |
392 | if (master == NULL) | |
393 | return -ENOMEM; | |
12b15e83 | 394 | master->dev.of_node = np; |
24b5a82c | 395 | platform_set_drvdata(op, master); |
44dab88e | 396 | hw = spi_master_get_devdata(master); |
94c69f76 | 397 | hw->master = master; |
44dab88e SF |
398 | hw->dev = dev; |
399 | ||
400 | init_completion(&hw->done); | |
401 | ||
402 | /* | |
403 | * A count of zero implies a single SPI device without any chip-select. | |
404 | * Note that of_gpio_count counts all gpios assigned to this spi master. | |
405 | * This includes both "null" gpio's and real ones. | |
406 | */ | |
407 | num_gpios = of_gpio_count(np); | |
e80beb27 | 408 | if (num_gpios > 0) { |
44dab88e SF |
409 | int i; |
410 | ||
797236f1 | 411 | hw->gpios = kcalloc(num_gpios, sizeof(*hw->gpios), GFP_KERNEL); |
44dab88e SF |
412 | if (!hw->gpios) { |
413 | ret = -ENOMEM; | |
414 | goto free_master; | |
415 | } | |
416 | ||
417 | for (i = 0; i < num_gpios; i++) { | |
418 | int gpio; | |
419 | enum of_gpio_flags flags; | |
420 | ||
421 | gpio = of_get_gpio_flags(np, i, &flags); | |
422 | hw->gpios[i] = gpio; | |
423 | ||
424 | if (gpio_is_valid(gpio)) { | |
425 | /* Real CS - set the initial state. */ | |
426 | ret = gpio_request(gpio, np->name); | |
427 | if (ret < 0) { | |
ffcaef5a ME |
428 | dev_err(dev, |
429 | "can't request gpio #%d: %d\n", | |
430 | i, ret); | |
44dab88e SF |
431 | goto free_gpios; |
432 | } | |
433 | ||
434 | gpio_direction_output(gpio, | |
435 | !!(flags & OF_GPIO_ACTIVE_LOW)); | |
436 | } else if (gpio == -EEXIST) { | |
437 | ; /* No CS, but that's OK. */ | |
438 | } else { | |
439 | dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); | |
440 | ret = -EINVAL; | |
441 | goto free_gpios; | |
442 | } | |
443 | } | |
444 | } | |
445 | ||
446 | /* Setup the state for the bitbang driver */ | |
447 | bbp = &hw->bitbang; | |
448 | bbp->master = hw->master; | |
449 | bbp->setup_transfer = spi_ppc4xx_setupxfer; | |
450 | bbp->chipselect = spi_ppc4xx_chipsel; | |
451 | bbp->txrx_bufs = spi_ppc4xx_txrx; | |
452 | bbp->use_dma = 0; | |
453 | bbp->master->setup = spi_ppc4xx_setup; | |
454 | bbp->master->cleanup = spi_ppc4xx_cleanup; | |
24778be2 | 455 | bbp->master->bits_per_word_mask = SPI_BPW_MASK(8); |
44dab88e | 456 | |
44dab88e SF |
457 | /* the spi->mode bits understood by this driver: */ |
458 | bbp->master->mode_bits = | |
459 | SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST; | |
460 | ||
461 | /* this many pins in all GPIO controllers */ | |
e80beb27 | 462 | bbp->master->num_chipselect = num_gpios > 0 ? num_gpios : 0; |
44dab88e SF |
463 | |
464 | /* Get the clock for the OPB */ | |
465 | opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb"); | |
466 | if (opbnp == NULL) { | |
467 | dev_err(dev, "OPB: cannot find node\n"); | |
468 | ret = -ENODEV; | |
469 | goto free_gpios; | |
470 | } | |
471 | /* Get the clock (Hz) for the OPB */ | |
472 | clk = of_get_property(opbnp, "clock-frequency", NULL); | |
473 | if (clk == NULL) { | |
474 | dev_err(dev, "OPB: no clock-frequency property set\n"); | |
475 | of_node_put(opbnp); | |
476 | ret = -ENODEV; | |
477 | goto free_gpios; | |
478 | } | |
479 | hw->opb_freq = *clk; | |
480 | hw->opb_freq >>= 2; | |
481 | of_node_put(opbnp); | |
482 | ||
483 | ret = of_address_to_resource(np, 0, &resource); | |
484 | if (ret) { | |
485 | dev_err(dev, "error while parsing device node resource\n"); | |
486 | goto free_gpios; | |
487 | } | |
488 | hw->mapbase = resource.start; | |
8e2943c0 | 489 | hw->mapsize = resource_size(&resource); |
44dab88e SF |
490 | |
491 | /* Sanity check */ | |
492 | if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) { | |
493 | dev_err(dev, "too small to map registers\n"); | |
494 | ret = -EINVAL; | |
495 | goto free_gpios; | |
496 | } | |
497 | ||
498 | /* Request IRQ */ | |
499 | hw->irqnum = irq_of_parse_and_map(np, 0); | |
500 | ret = request_irq(hw->irqnum, spi_ppc4xx_int, | |
38ada214 | 501 | 0, "spi_ppc4xx_of", (void *)hw); |
44dab88e SF |
502 | if (ret) { |
503 | dev_err(dev, "unable to allocate interrupt\n"); | |
504 | goto free_gpios; | |
505 | } | |
506 | ||
507 | if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) { | |
508 | dev_err(dev, "resource unavailable\n"); | |
509 | ret = -EBUSY; | |
510 | goto request_mem_error; | |
511 | } | |
512 | ||
513 | hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs)); | |
514 | ||
515 | if (!hw->regs) { | |
516 | dev_err(dev, "unable to memory map registers\n"); | |
517 | ret = -ENXIO; | |
518 | goto map_io_error; | |
519 | } | |
520 | ||
521 | spi_ppc4xx_enable(hw); | |
522 | ||
523 | /* Finally register our spi controller */ | |
524 | dev->dma_mask = 0; | |
525 | ret = spi_bitbang_start(bbp); | |
526 | if (ret) { | |
527 | dev_err(dev, "failed to register SPI master\n"); | |
528 | goto unmap_regs; | |
529 | } | |
530 | ||
531 | dev_info(dev, "driver initialized\n"); | |
44dab88e SF |
532 | |
533 | return 0; | |
534 | ||
535 | unmap_regs: | |
536 | iounmap(hw->regs); | |
537 | map_io_error: | |
538 | release_mem_region(hw->mapbase, hw->mapsize); | |
539 | request_mem_error: | |
540 | free_irq(hw->irqnum, hw); | |
541 | free_gpios: | |
542 | free_gpios(hw); | |
543 | free_master: | |
44dab88e SF |
544 | spi_master_put(master); |
545 | ||
546 | dev_err(dev, "initialization failed\n"); | |
547 | return ret; | |
548 | } | |
549 | ||
2deff8d6 | 550 | static int spi_ppc4xx_of_remove(struct platform_device *op) |
44dab88e | 551 | { |
24b5a82c | 552 | struct spi_master *master = platform_get_drvdata(op); |
44dab88e SF |
553 | struct ppc4xx_spi *hw = spi_master_get_devdata(master); |
554 | ||
555 | spi_bitbang_stop(&hw->bitbang); | |
44dab88e SF |
556 | release_mem_region(hw->mapbase, hw->mapsize); |
557 | free_irq(hw->irqnum, hw); | |
558 | iounmap(hw->regs); | |
559 | free_gpios(hw); | |
94c69f76 | 560 | spi_master_put(master); |
44dab88e SF |
561 | return 0; |
562 | } | |
563 | ||
631e61b7 | 564 | static const struct of_device_id spi_ppc4xx_of_match[] = { |
44dab88e SF |
565 | { .compatible = "ibm,ppc4xx-spi", }, |
566 | {}, | |
567 | }; | |
568 | ||
569 | MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match); | |
570 | ||
18d306d1 | 571 | static struct platform_driver spi_ppc4xx_of_driver = { |
44dab88e | 572 | .probe = spi_ppc4xx_of_probe, |
2deff8d6 | 573 | .remove = spi_ppc4xx_of_remove, |
44dab88e SF |
574 | .driver = { |
575 | .name = DRIVER_NAME, | |
4018294b | 576 | .of_match_table = spi_ppc4xx_of_match, |
44dab88e SF |
577 | }, |
578 | }; | |
940ab889 | 579 | module_platform_driver(spi_ppc4xx_of_driver); |
44dab88e SF |
580 | |
581 | MODULE_AUTHOR("Gary Jennejohn & Stefan Roese"); | |
582 | MODULE_DESCRIPTION("Simple PPC4xx SPI Driver"); | |
583 | MODULE_LICENSE("GPL"); |