]>
Commit | Line | Data |
---|---|---|
e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/errno.h> | |
cbfd6a21 | 25 | #include <linux/err.h> |
e0c9905e SS |
26 | #include <linux/interrupt.h> |
27 | #include <linux/platform_device.h> | |
8348c259 | 28 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 29 | #include <linux/spi/spi.h> |
e0c9905e | 30 | #include <linux/delay.h> |
a7bb3909 | 31 | #include <linux/gpio.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
3343b7a6 | 33 | #include <linux/clk.h> |
7d94a505 | 34 | #include <linux/pm_runtime.h> |
a3496855 | 35 | #include <linux/acpi.h> |
e0c9905e SS |
36 | |
37 | #include <asm/io.h> | |
38 | #include <asm/irq.h> | |
e0c9905e | 39 | #include <asm/delay.h> |
e0c9905e | 40 | |
cd7bed00 | 41 | #include "spi-pxa2xx.h" |
e0c9905e SS |
42 | |
43 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 44 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 45 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 46 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
47 | |
48 | #define MAX_BUSES 3 | |
49 | ||
f1f640a9 VS |
50 | #define TIMOUT_DFLT 1000 |
51 | ||
b97c74bd NF |
52 | /* |
53 | * for testing SSCR1 changes that require SSP restart, basically | |
54 | * everything except the service and interrupt enables, the pxa270 developer | |
55 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
56 | * list, but the PXA255 dev man says all bits without really meaning the | |
57 | * service and interrupt enables | |
58 | */ | |
59 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 60 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
61 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
62 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
63 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
64 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 65 | |
e5262d05 WC |
66 | #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ |
67 | | QUARK_X1000_SSCR1_EFWR \ | |
68 | | QUARK_X1000_SSCR1_RFT \ | |
69 | | QUARK_X1000_SSCR1_TFT \ | |
70 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
71 | ||
a0d2642e MW |
72 | #define LPSS_RX_THRESH_DFLT 64 |
73 | #define LPSS_TX_LOTHRESH_DFLT 160 | |
74 | #define LPSS_TX_HITHRESH_DFLT 224 | |
75 | ||
e5262d05 WC |
76 | struct quark_spi_rate { |
77 | u32 bitrate; | |
78 | u32 dds_clk_rate; | |
79 | u32 clk_div; | |
80 | }; | |
81 | ||
82 | /* | |
83 | * 'rate', 'dds', 'clk_div' lookup table, which is defined in | |
84 | * the Quark SPI datasheet. | |
85 | */ | |
86 | static const struct quark_spi_rate quark_spi_rate_table[] = { | |
87 | /* bitrate, dds_clk_rate, clk_div */ | |
88 | {50000000, 0x800000, 0}, | |
89 | {40000000, 0x666666, 0}, | |
90 | {25000000, 0x400000, 0}, | |
91 | {20000000, 0x666666, 1}, | |
92 | {16667000, 0x800000, 2}, | |
93 | {13333000, 0x666666, 2}, | |
94 | {12500000, 0x200000, 0}, | |
95 | {10000000, 0x800000, 4}, | |
96 | {8000000, 0x666666, 4}, | |
97 | {6250000, 0x400000, 3}, | |
98 | {5000000, 0x400000, 4}, | |
99 | {4000000, 0x666666, 9}, | |
100 | {3125000, 0x80000, 0}, | |
101 | {2500000, 0x400000, 9}, | |
102 | {2000000, 0x666666, 19}, | |
103 | {1563000, 0x40000, 0}, | |
104 | {1250000, 0x200000, 9}, | |
105 | {1000000, 0x400000, 24}, | |
106 | {800000, 0x666666, 49}, | |
107 | {781250, 0x20000, 0}, | |
108 | {625000, 0x200000, 19}, | |
109 | {500000, 0x400000, 49}, | |
110 | {400000, 0x666666, 99}, | |
111 | {390625, 0x10000, 0}, | |
112 | {250000, 0x400000, 99}, | |
113 | {200000, 0x666666, 199}, | |
114 | {195313, 0x8000, 0}, | |
115 | {125000, 0x100000, 49}, | |
116 | {100000, 0x200000, 124}, | |
117 | {50000, 0x100000, 124}, | |
118 | {25000, 0x80000, 124}, | |
119 | {10016, 0x20000, 77}, | |
120 | {5040, 0x20000, 154}, | |
121 | {1002, 0x8000, 194}, | |
122 | }; | |
123 | ||
a0d2642e | 124 | /* Offset from drv_data->lpss_base */ |
1de70612 MW |
125 | #define GENERAL_REG 0x08 |
126 | #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) | |
0054e28d | 127 | #define SSP_REG 0x0c |
a0d2642e MW |
128 | #define SPI_CS_CONTROL 0x18 |
129 | #define SPI_CS_CONTROL_SW_MODE BIT(0) | |
130 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | |
131 | ||
132 | static bool is_lpss_ssp(const struct driver_data *drv_data) | |
133 | { | |
134 | return drv_data->ssp_type == LPSS_SSP; | |
135 | } | |
136 | ||
e5262d05 WC |
137 | static bool is_quark_x1000_ssp(const struct driver_data *drv_data) |
138 | { | |
139 | return drv_data->ssp_type == QUARK_X1000_SSP; | |
140 | } | |
141 | ||
4fdb2424 WC |
142 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
143 | { | |
144 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
145 | case QUARK_X1000_SSP: |
146 | return QUARK_X1000_SSCR1_CHANGE_MASK; | |
4fdb2424 WC |
147 | default: |
148 | return SSCR1_CHANGE_MASK; | |
149 | } | |
150 | } | |
151 | ||
152 | static u32 | |
153 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
154 | { | |
155 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
156 | case QUARK_X1000_SSP: |
157 | return RX_THRESH_QUARK_X1000_DFLT; | |
4fdb2424 WC |
158 | default: |
159 | return RX_THRESH_DFLT; | |
160 | } | |
161 | } | |
162 | ||
163 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
164 | { | |
165 | void __iomem *reg = drv_data->ioaddr; | |
166 | u32 mask; | |
167 | ||
168 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
169 | case QUARK_X1000_SSP: |
170 | mask = QUARK_X1000_SSSR_TFL_MASK; | |
171 | break; | |
4fdb2424 WC |
172 | default: |
173 | mask = SSSR_TFL_MASK; | |
174 | break; | |
175 | } | |
176 | ||
177 | return (read_SSSR(reg) & mask) == mask; | |
178 | } | |
179 | ||
180 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
181 | u32 *sccr1_reg) | |
182 | { | |
183 | u32 mask; | |
184 | ||
185 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
186 | case QUARK_X1000_SSP: |
187 | mask = QUARK_X1000_SSCR1_RFT; | |
188 | break; | |
4fdb2424 WC |
189 | default: |
190 | mask = SSCR1_RFT; | |
191 | break; | |
192 | } | |
193 | *sccr1_reg &= ~mask; | |
194 | } | |
195 | ||
196 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
197 | u32 *sccr1_reg, u32 threshold) | |
198 | { | |
199 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
200 | case QUARK_X1000_SSP: |
201 | *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); | |
202 | break; | |
4fdb2424 WC |
203 | default: |
204 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
205 | break; | |
206 | } | |
207 | } | |
208 | ||
209 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
210 | u32 clk_div, u8 bits) | |
211 | { | |
212 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
213 | case QUARK_X1000_SSP: |
214 | return clk_div | |
215 | | QUARK_X1000_SSCR0_Motorola | |
216 | | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) | |
217 | | SSCR0_SSE; | |
4fdb2424 WC |
218 | default: |
219 | return clk_div | |
220 | | SSCR0_Motorola | |
221 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
222 | | SSCR0_SSE | |
223 | | (bits > 16 ? SSCR0_EDSS : 0); | |
224 | } | |
225 | } | |
226 | ||
a0d2642e MW |
227 | /* |
228 | * Read and write LPSS SSP private registers. Caller must first check that | |
229 | * is_lpss_ssp() returns true before these can be called. | |
230 | */ | |
231 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
232 | { | |
233 | WARN_ON(!drv_data->lpss_base); | |
234 | return readl(drv_data->lpss_base + offset); | |
235 | } | |
236 | ||
237 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
238 | unsigned offset, u32 value) | |
239 | { | |
240 | WARN_ON(!drv_data->lpss_base); | |
241 | writel(value, drv_data->lpss_base + offset); | |
242 | } | |
243 | ||
244 | /* | |
245 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
246 | * @drv_data: pointer to the driver private data | |
247 | * | |
248 | * Perform LPSS SSP specific setup. This function must be called first if | |
249 | * one is going to use LPSS SSP private registers. | |
250 | */ | |
251 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
252 | { | |
253 | unsigned offset = 0x400; | |
254 | u32 value, orig; | |
255 | ||
256 | if (!is_lpss_ssp(drv_data)) | |
257 | return; | |
258 | ||
259 | /* | |
260 | * Perform auto-detection of the LPSS SSP private registers. They | |
261 | * can be either at 1k or 2k offset from the base address. | |
262 | */ | |
263 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
264 | ||
e61f487f | 265 | /* Test SPI_CS_CONTROL_SW_MODE bit enabling */ |
a0d2642e MW |
266 | value = orig | SPI_CS_CONTROL_SW_MODE; |
267 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
268 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
269 | if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { | |
270 | offset = 0x800; | |
271 | goto detection_done; | |
272 | } | |
273 | ||
e61f487f CCE |
274 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); |
275 | ||
276 | /* Test SPI_CS_CONTROL_SW_MODE bit disabling */ | |
277 | value = orig & ~SPI_CS_CONTROL_SW_MODE; | |
a0d2642e MW |
278 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); |
279 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
e61f487f | 280 | if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) { |
a0d2642e MW |
281 | offset = 0x800; |
282 | goto detection_done; | |
283 | } | |
284 | ||
285 | detection_done: | |
286 | /* Now set the LPSS base */ | |
287 | drv_data->lpss_base = drv_data->ioaddr + offset; | |
288 | ||
289 | /* Enable software chip select control */ | |
290 | value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | |
291 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
0054e28d MW |
292 | |
293 | /* Enable multiblock DMA transfers */ | |
1de70612 | 294 | if (drv_data->master_info->enable_dma) { |
0054e28d | 295 | __lpss_ssp_write_priv(drv_data, SSP_REG, 1); |
1de70612 MW |
296 | |
297 | value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); | |
298 | value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; | |
299 | __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); | |
300 | } | |
a0d2642e MW |
301 | } |
302 | ||
303 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
304 | { | |
305 | u32 value; | |
306 | ||
307 | if (!is_lpss_ssp(drv_data)) | |
308 | return; | |
309 | ||
310 | value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); | |
311 | if (enable) | |
312 | value &= ~SPI_CS_CONTROL_CS_HIGH; | |
313 | else | |
314 | value |= SPI_CS_CONTROL_CS_HIGH; | |
315 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
316 | } | |
317 | ||
a7bb3909 EM |
318 | static void cs_assert(struct driver_data *drv_data) |
319 | { | |
320 | struct chip_data *chip = drv_data->cur_chip; | |
321 | ||
2a8626a9 SAS |
322 | if (drv_data->ssp_type == CE4100_SSP) { |
323 | write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); | |
324 | return; | |
325 | } | |
326 | ||
a7bb3909 EM |
327 | if (chip->cs_control) { |
328 | chip->cs_control(PXA2XX_CS_ASSERT); | |
329 | return; | |
330 | } | |
331 | ||
a0d2642e | 332 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 333 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
334 | return; |
335 | } | |
336 | ||
337 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
338 | } |
339 | ||
340 | static void cs_deassert(struct driver_data *drv_data) | |
341 | { | |
342 | struct chip_data *chip = drv_data->cur_chip; | |
343 | ||
2a8626a9 SAS |
344 | if (drv_data->ssp_type == CE4100_SSP) |
345 | return; | |
346 | ||
a7bb3909 | 347 | if (chip->cs_control) { |
2b2562d3 | 348 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
349 | return; |
350 | } | |
351 | ||
a0d2642e | 352 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 353 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
354 | return; |
355 | } | |
356 | ||
357 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
358 | } |
359 | ||
cd7bed00 | 360 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
361 | { |
362 | unsigned long limit = loops_per_jiffy << 1; | |
363 | ||
cf43369d | 364 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
365 | |
366 | do { | |
367 | while (read_SSSR(reg) & SSSR_RNE) { | |
368 | read_SSDR(reg); | |
369 | } | |
306c68aa | 370 | } while ((read_SSSR(reg) & SSSR_BSY) && --limit); |
2a8626a9 | 371 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
372 | |
373 | return limit; | |
374 | } | |
375 | ||
8d94cc50 | 376 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 377 | { |
cf43369d | 378 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 379 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 380 | |
4fdb2424 | 381 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
382 | || (drv_data->tx == drv_data->tx_end)) |
383 | return 0; | |
384 | ||
385 | write_SSDR(0, reg); | |
386 | drv_data->tx += n_bytes; | |
387 | ||
388 | return 1; | |
e0c9905e SS |
389 | } |
390 | ||
8d94cc50 | 391 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 392 | { |
cf43369d | 393 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 394 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
395 | |
396 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 397 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
398 | read_SSDR(reg); |
399 | drv_data->rx += n_bytes; | |
400 | } | |
8d94cc50 SS |
401 | |
402 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
403 | } |
404 | ||
8d94cc50 | 405 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 406 | { |
cf43369d | 407 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 408 | |
4fdb2424 | 409 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
410 | || (drv_data->tx == drv_data->tx_end)) |
411 | return 0; | |
412 | ||
413 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
414 | ++drv_data->tx; | |
415 | ||
416 | return 1; | |
e0c9905e SS |
417 | } |
418 | ||
8d94cc50 | 419 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 420 | { |
cf43369d | 421 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
422 | |
423 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 424 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
425 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
426 | ++drv_data->rx; | |
427 | } | |
8d94cc50 SS |
428 | |
429 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
430 | } |
431 | ||
8d94cc50 | 432 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 433 | { |
cf43369d | 434 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 435 | |
4fdb2424 | 436 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
437 | || (drv_data->tx == drv_data->tx_end)) |
438 | return 0; | |
439 | ||
440 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
441 | drv_data->tx += 2; | |
442 | ||
443 | return 1; | |
e0c9905e SS |
444 | } |
445 | ||
8d94cc50 | 446 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 447 | { |
cf43369d | 448 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
449 | |
450 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 451 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
452 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
453 | drv_data->rx += 2; | |
454 | } | |
8d94cc50 SS |
455 | |
456 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 457 | } |
8d94cc50 SS |
458 | |
459 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 460 | { |
cf43369d | 461 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 462 | |
4fdb2424 | 463 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
464 | || (drv_data->tx == drv_data->tx_end)) |
465 | return 0; | |
466 | ||
467 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
468 | drv_data->tx += 4; | |
469 | ||
470 | return 1; | |
e0c9905e SS |
471 | } |
472 | ||
8d94cc50 | 473 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 474 | { |
cf43369d | 475 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
476 | |
477 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 478 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
479 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
480 | drv_data->rx += 4; | |
481 | } | |
8d94cc50 SS |
482 | |
483 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
484 | } |
485 | ||
cd7bed00 | 486 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
487 | { |
488 | struct spi_message *msg = drv_data->cur_msg; | |
489 | struct spi_transfer *trans = drv_data->cur_transfer; | |
490 | ||
491 | /* Move to next transfer */ | |
492 | if (trans->transfer_list.next != &msg->transfers) { | |
493 | drv_data->cur_transfer = | |
494 | list_entry(trans->transfer_list.next, | |
495 | struct spi_transfer, | |
496 | transfer_list); | |
497 | return RUNNING_STATE; | |
498 | } else | |
499 | return DONE_STATE; | |
500 | } | |
501 | ||
e0c9905e | 502 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 503 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
504 | { |
505 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 506 | struct spi_message *msg; |
e0c9905e | 507 | |
5daa3ba0 SS |
508 | msg = drv_data->cur_msg; |
509 | drv_data->cur_msg = NULL; | |
510 | drv_data->cur_transfer = NULL; | |
5daa3ba0 | 511 | |
23e2c2aa | 512 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e0c9905e SS |
513 | transfer_list); |
514 | ||
8423597d NF |
515 | /* Delay if requested before any change in chip select */ |
516 | if (last_transfer->delay_usecs) | |
517 | udelay(last_transfer->delay_usecs); | |
518 | ||
519 | /* Drop chip select UNLESS cs_change is true or we are returning | |
520 | * a message with an error, or next message is for another chip | |
521 | */ | |
e0c9905e | 522 | if (!last_transfer->cs_change) |
a7bb3909 | 523 | cs_deassert(drv_data); |
8423597d NF |
524 | else { |
525 | struct spi_message *next_msg; | |
526 | ||
527 | /* Holding of cs was hinted, but we need to make sure | |
528 | * the next message is for the same chip. Don't waste | |
529 | * time with the following tests unless this was hinted. | |
530 | * | |
531 | * We cannot postpone this until pump_messages, because | |
532 | * after calling msg->complete (below) the driver that | |
533 | * sent the current message could be unloaded, which | |
534 | * could invalidate the cs_control() callback... | |
535 | */ | |
536 | ||
537 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 538 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
539 | |
540 | /* see if the next and current messages point | |
541 | * to the same chip | |
542 | */ | |
543 | if (next_msg && next_msg->spi != msg->spi) | |
544 | next_msg = NULL; | |
545 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 546 | cs_deassert(drv_data); |
8423597d | 547 | } |
e0c9905e | 548 | |
7f86bde9 | 549 | spi_finalize_current_message(drv_data->master); |
a7bb3909 | 550 | drv_data->cur_chip = NULL; |
e0c9905e SS |
551 | } |
552 | ||
579d3bb2 SAS |
553 | static void reset_sccr1(struct driver_data *drv_data) |
554 | { | |
555 | void __iomem *reg = drv_data->ioaddr; | |
556 | struct chip_data *chip = drv_data->cur_chip; | |
557 | u32 sccr1_reg; | |
558 | ||
559 | sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; | |
560 | sccr1_reg &= ~SSCR1_RFT; | |
561 | sccr1_reg |= chip->threshold; | |
562 | write_SSCR1(sccr1_reg, reg); | |
563 | } | |
564 | ||
8d94cc50 | 565 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 566 | { |
cf43369d | 567 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 568 | |
8d94cc50 | 569 | /* Stop and reset SSP */ |
2a8626a9 | 570 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 571 | reset_sccr1(drv_data); |
2a8626a9 | 572 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 573 | write_SSTO(0, reg); |
cd7bed00 | 574 | pxa2xx_spi_flush(drv_data); |
8d94cc50 | 575 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); |
e0c9905e | 576 | |
8d94cc50 | 577 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 578 | |
8d94cc50 SS |
579 | drv_data->cur_msg->state = ERROR_STATE; |
580 | tasklet_schedule(&drv_data->pump_transfers); | |
581 | } | |
5daa3ba0 | 582 | |
8d94cc50 SS |
583 | static void int_transfer_complete(struct driver_data *drv_data) |
584 | { | |
cf43369d | 585 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 586 | |
8d94cc50 | 587 | /* Stop SSP */ |
2a8626a9 | 588 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 589 | reset_sccr1(drv_data); |
2a8626a9 | 590 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 591 | write_SSTO(0, reg); |
e0c9905e | 592 | |
25985edc | 593 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
594 | drv_data->cur_msg->actual_length += drv_data->len - |
595 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 596 | |
8423597d NF |
597 | /* Transfer delays and chip select release are |
598 | * handled in pump_transfers or giveback | |
599 | */ | |
e0c9905e | 600 | |
8d94cc50 | 601 | /* Move to next transfer */ |
cd7bed00 | 602 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 603 | |
8d94cc50 SS |
604 | /* Schedule transfer tasklet */ |
605 | tasklet_schedule(&drv_data->pump_transfers); | |
606 | } | |
e0c9905e | 607 | |
8d94cc50 SS |
608 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
609 | { | |
cf43369d | 610 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 611 | |
8d94cc50 SS |
612 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
613 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 614 | |
8d94cc50 | 615 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 616 | |
8d94cc50 SS |
617 | if (irq_status & SSSR_ROR) { |
618 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
619 | return IRQ_HANDLED; | |
620 | } | |
e0c9905e | 621 | |
8d94cc50 SS |
622 | if (irq_status & SSSR_TINT) { |
623 | write_SSSR(SSSR_TINT, reg); | |
624 | if (drv_data->read(drv_data)) { | |
625 | int_transfer_complete(drv_data); | |
626 | return IRQ_HANDLED; | |
627 | } | |
628 | } | |
e0c9905e | 629 | |
8d94cc50 SS |
630 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
631 | do { | |
632 | if (drv_data->read(drv_data)) { | |
633 | int_transfer_complete(drv_data); | |
634 | return IRQ_HANDLED; | |
635 | } | |
636 | } while (drv_data->write(drv_data)); | |
e0c9905e | 637 | |
8d94cc50 SS |
638 | if (drv_data->read(drv_data)) { |
639 | int_transfer_complete(drv_data); | |
640 | return IRQ_HANDLED; | |
641 | } | |
e0c9905e | 642 | |
8d94cc50 | 643 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
644 | u32 bytes_left; |
645 | u32 sccr1_reg; | |
646 | ||
647 | sccr1_reg = read_SSCR1(reg); | |
648 | sccr1_reg &= ~SSCR1_TIE; | |
649 | ||
650 | /* | |
651 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 652 | * remaining RX bytes. |
579d3bb2 | 653 | */ |
2a8626a9 | 654 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 655 | u32 rx_thre; |
579d3bb2 | 656 | |
4fdb2424 | 657 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
658 | |
659 | bytes_left = drv_data->rx_end - drv_data->rx; | |
660 | switch (drv_data->n_bytes) { | |
661 | case 4: | |
662 | bytes_left >>= 1; | |
663 | case 2: | |
664 | bytes_left >>= 1; | |
8d94cc50 | 665 | } |
579d3bb2 | 666 | |
4fdb2424 WC |
667 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
668 | if (rx_thre > bytes_left) | |
669 | rx_thre = bytes_left; | |
579d3bb2 | 670 | |
4fdb2424 | 671 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 672 | } |
579d3bb2 | 673 | write_SSCR1(sccr1_reg, reg); |
e0c9905e SS |
674 | } |
675 | ||
5daa3ba0 SS |
676 | /* We did something */ |
677 | return IRQ_HANDLED; | |
e0c9905e SS |
678 | } |
679 | ||
7d12e780 | 680 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 681 | { |
c7bec5ab | 682 | struct driver_data *drv_data = dev_id; |
cf43369d | 683 | void __iomem *reg = drv_data->ioaddr; |
7d94a505 | 684 | u32 sccr1_reg; |
49cbb1e0 SAS |
685 | u32 mask = drv_data->mask_sr; |
686 | u32 status; | |
687 | ||
7d94a505 MW |
688 | /* |
689 | * The IRQ might be shared with other peripherals so we must first | |
690 | * check that are we RPM suspended or not. If we are we assume that | |
691 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
692 | * interrupt is enabled). | |
693 | */ | |
694 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
695 | return IRQ_NONE; | |
696 | ||
269e4a41 MW |
697 | /* |
698 | * If the device is not yet in RPM suspended state and we get an | |
699 | * interrupt that is meant for another device, check if status bits | |
700 | * are all set to one. That means that the device is already | |
701 | * powered off. | |
702 | */ | |
49cbb1e0 | 703 | status = read_SSSR(reg); |
269e4a41 MW |
704 | if (status == ~0) |
705 | return IRQ_NONE; | |
706 | ||
707 | sccr1_reg = read_SSCR1(reg); | |
49cbb1e0 SAS |
708 | |
709 | /* Ignore possible writes if we don't need to write */ | |
710 | if (!(sccr1_reg & SSCR1_TIE)) | |
711 | mask &= ~SSSR_TFS; | |
712 | ||
713 | if (!(status & mask)) | |
714 | return IRQ_NONE; | |
e0c9905e SS |
715 | |
716 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
717 | |
718 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
719 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
2a8626a9 | 720 | if (!pxa25x_ssp_comp(drv_data)) |
5daa3ba0 | 721 | write_SSTO(0, reg); |
2a8626a9 | 722 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 723 | |
f6bd03a7 JN |
724 | dev_err(&drv_data->pdev->dev, |
725 | "bad message state in interrupt handler\n"); | |
5daa3ba0 | 726 | |
e0c9905e SS |
727 | /* Never fail */ |
728 | return IRQ_HANDLED; | |
729 | } | |
730 | ||
731 | return drv_data->transfer_handler(drv_data); | |
732 | } | |
733 | ||
e5262d05 WC |
734 | /* |
735 | * The Quark SPI data sheet gives a table, and for the given 'rate', | |
736 | * the 'dds' and 'clk_div' can be found in the table. | |
737 | */ | |
738 | static u32 quark_x1000_set_clk_regvals(u32 rate, u32 *dds, u32 *clk_div) | |
739 | { | |
740 | unsigned int i; | |
741 | ||
742 | for (i = 0; i < ARRAY_SIZE(quark_spi_rate_table); i++) { | |
743 | if (rate >= quark_spi_rate_table[i].bitrate) { | |
744 | *dds = quark_spi_rate_table[i].dds_clk_rate; | |
745 | *clk_div = quark_spi_rate_table[i].clk_div; | |
746 | return quark_spi_rate_table[i].bitrate; | |
747 | } | |
748 | } | |
749 | ||
750 | *dds = quark_spi_rate_table[i-1].dds_clk_rate; | |
751 | *clk_div = quark_spi_rate_table[i-1].clk_div; | |
752 | ||
753 | return quark_spi_rate_table[i-1].bitrate; | |
754 | } | |
755 | ||
3343b7a6 | 756 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 757 | { |
3343b7a6 MW |
758 | unsigned long ssp_clk = drv_data->max_clk_rate; |
759 | const struct ssp_device *ssp = drv_data->ssp; | |
760 | ||
761 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 762 | |
2a8626a9 | 763 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
2f1a74e5 | 764 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; |
765 | else | |
766 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
767 | } | |
768 | ||
e5262d05 WC |
769 | static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, |
770 | struct chip_data *chip, int rate) | |
771 | { | |
772 | u32 clk_div; | |
773 | ||
774 | switch (drv_data->ssp_type) { | |
775 | case QUARK_X1000_SSP: | |
776 | quark_x1000_set_clk_regvals(rate, &chip->dds_rate, &clk_div); | |
777 | return clk_div << 8; | |
778 | default: | |
779 | return ssp_get_clk_div(drv_data, rate); | |
780 | } | |
781 | } | |
782 | ||
e0c9905e SS |
783 | static void pump_transfers(unsigned long data) |
784 | { | |
785 | struct driver_data *drv_data = (struct driver_data *)data; | |
786 | struct spi_message *message = NULL; | |
787 | struct spi_transfer *transfer = NULL; | |
788 | struct spi_transfer *previous = NULL; | |
789 | struct chip_data *chip = NULL; | |
cf43369d | 790 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
791 | u32 clk_div = 0; |
792 | u8 bits = 0; | |
793 | u32 speed = 0; | |
794 | u32 cr0; | |
8d94cc50 SS |
795 | u32 cr1; |
796 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
797 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
4fdb2424 | 798 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); |
e0c9905e SS |
799 | |
800 | /* Get current state information */ | |
801 | message = drv_data->cur_msg; | |
802 | transfer = drv_data->cur_transfer; | |
803 | chip = drv_data->cur_chip; | |
804 | ||
805 | /* Handle for abort */ | |
806 | if (message->state == ERROR_STATE) { | |
807 | message->status = -EIO; | |
5daa3ba0 | 808 | giveback(drv_data); |
e0c9905e SS |
809 | return; |
810 | } | |
811 | ||
812 | /* Handle end of message */ | |
813 | if (message->state == DONE_STATE) { | |
814 | message->status = 0; | |
5daa3ba0 | 815 | giveback(drv_data); |
e0c9905e SS |
816 | return; |
817 | } | |
818 | ||
8423597d | 819 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
820 | if (message->state == RUNNING_STATE) { |
821 | previous = list_entry(transfer->transfer_list.prev, | |
822 | struct spi_transfer, | |
823 | transfer_list); | |
824 | if (previous->delay_usecs) | |
825 | udelay(previous->delay_usecs); | |
8423597d NF |
826 | |
827 | /* Drop chip select only if cs_change is requested */ | |
828 | if (previous->cs_change) | |
a7bb3909 | 829 | cs_deassert(drv_data); |
e0c9905e SS |
830 | } |
831 | ||
cd7bed00 MW |
832 | /* Check if we can DMA this transfer */ |
833 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
834 | |
835 | /* reject already-mapped transfers; PIO won't always work */ | |
836 | if (message->is_dma_mapped | |
837 | || transfer->rx_dma || transfer->tx_dma) { | |
838 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
839 | "pump_transfers: mapped transfer length of " |
840 | "%u is greater than %d\n", | |
7e964455 NF |
841 | transfer->len, MAX_DMA_LEN); |
842 | message->status = -EINVAL; | |
843 | giveback(drv_data); | |
844 | return; | |
845 | } | |
846 | ||
847 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
848 | dev_warn_ratelimited(&message->spi->dev, |
849 | "pump_transfers: DMA disabled for transfer length %ld " | |
850 | "greater than %d\n", | |
851 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
852 | } |
853 | ||
e0c9905e | 854 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 855 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
856 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
857 | message->status = -EIO; | |
5daa3ba0 | 858 | giveback(drv_data); |
e0c9905e SS |
859 | return; |
860 | } | |
9708c121 | 861 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
862 | drv_data->tx = (void *)transfer->tx_buf; |
863 | drv_data->tx_end = drv_data->tx + transfer->len; | |
864 | drv_data->rx = transfer->rx_buf; | |
865 | drv_data->rx_end = drv_data->rx + transfer->len; | |
866 | drv_data->rx_dma = transfer->rx_dma; | |
867 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 868 | drv_data->len = transfer->len; |
e0c9905e SS |
869 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
870 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
871 | |
872 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 873 | cr0 = chip->cr0; |
9708c121 SS |
874 | if (transfer->speed_hz || transfer->bits_per_word) { |
875 | ||
9708c121 SS |
876 | bits = chip->bits_per_word; |
877 | speed = chip->speed_hz; | |
878 | ||
879 | if (transfer->speed_hz) | |
880 | speed = transfer->speed_hz; | |
881 | ||
882 | if (transfer->bits_per_word) | |
883 | bits = transfer->bits_per_word; | |
884 | ||
e5262d05 | 885 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed); |
9708c121 SS |
886 | |
887 | if (bits <= 8) { | |
888 | drv_data->n_bytes = 1; | |
9708c121 SS |
889 | drv_data->read = drv_data->read != null_reader ? |
890 | u8_reader : null_reader; | |
891 | drv_data->write = drv_data->write != null_writer ? | |
892 | u8_writer : null_writer; | |
893 | } else if (bits <= 16) { | |
894 | drv_data->n_bytes = 2; | |
9708c121 SS |
895 | drv_data->read = drv_data->read != null_reader ? |
896 | u16_reader : null_reader; | |
897 | drv_data->write = drv_data->write != null_writer ? | |
898 | u16_writer : null_writer; | |
899 | } else if (bits <= 32) { | |
900 | drv_data->n_bytes = 4; | |
9708c121 SS |
901 | drv_data->read = drv_data->read != null_reader ? |
902 | u32_reader : null_reader; | |
903 | drv_data->write = drv_data->write != null_writer ? | |
904 | u32_writer : null_writer; | |
905 | } | |
8d94cc50 SS |
906 | /* if bits/word is changed in dma mode, then must check the |
907 | * thresholds and burst also */ | |
908 | if (chip->enable_dma) { | |
cd7bed00 MW |
909 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
910 | message->spi, | |
8d94cc50 SS |
911 | bits, &dma_burst, |
912 | &dma_thresh)) | |
f6bd03a7 JN |
913 | dev_warn_ratelimited(&message->spi->dev, |
914 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 | 915 | } |
9708c121 | 916 | |
4fdb2424 | 917 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); |
9708c121 SS |
918 | } |
919 | ||
e0c9905e SS |
920 | message->state = RUNNING_STATE; |
921 | ||
7e964455 | 922 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
923 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
924 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 925 | if (drv_data->dma_mapped) { |
e0c9905e SS |
926 | |
927 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
928 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
929 | ||
930 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 931 | |
8d94cc50 SS |
932 | /* Clear status and start DMA engine */ |
933 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e | 934 | write_SSSR(drv_data->clear_sr, reg); |
cd7bed00 MW |
935 | |
936 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
937 | } else { |
938 | /* Ensure we have the correct interrupt handler */ | |
939 | drv_data->transfer_handler = interrupt_transfer; | |
940 | ||
8d94cc50 SS |
941 | /* Clear status */ |
942 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 943 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
944 | } |
945 | ||
a0d2642e MW |
946 | if (is_lpss_ssp(drv_data)) { |
947 | if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) | |
948 | write_SSIRF(chip->lpss_rx_threshold, reg); | |
949 | if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) | |
950 | write_SSITF(chip->lpss_tx_threshold, reg); | |
951 | } | |
952 | ||
e5262d05 WC |
953 | if (is_quark_x1000_ssp(drv_data) && |
954 | (read_DDS_RATE(reg) != chip->dds_rate)) | |
955 | write_DDS_RATE(chip->dds_rate, reg); | |
956 | ||
8d94cc50 | 957 | /* see if we need to reload the config registers */ |
4fdb2424 WC |
958 | if ((read_SSCR0(reg) != cr0) || |
959 | (read_SSCR1(reg) & change_mask) != (cr1 & change_mask)) { | |
8d94cc50 | 960 | |
b97c74bd | 961 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 962 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
2a8626a9 | 963 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e | 964 | write_SSTO(chip->timeout, reg); |
b97c74bd | 965 | /* first set CR1 without interrupt and service enables */ |
4fdb2424 | 966 | write_SSCR1(cr1 & change_mask, reg); |
b97c74bd | 967 | /* restart the SSP */ |
8d94cc50 | 968 | write_SSCR0(cr0, reg); |
b97c74bd | 969 | |
8d94cc50 | 970 | } else { |
2a8626a9 | 971 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 972 | write_SSTO(chip->timeout, reg); |
e0c9905e | 973 | } |
b97c74bd | 974 | |
a7bb3909 | 975 | cs_assert(drv_data); |
b97c74bd NF |
976 | |
977 | /* after chip select, release the data by enabling service | |
978 | * requests and interrupts, without changing any mode bits */ | |
979 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
980 | } |
981 | ||
7f86bde9 MW |
982 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
983 | struct spi_message *msg) | |
e0c9905e | 984 | { |
7f86bde9 | 985 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 986 | |
7f86bde9 | 987 | drv_data->cur_msg = msg; |
e0c9905e SS |
988 | /* Initial message state*/ |
989 | drv_data->cur_msg->state = START_STATE; | |
990 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
991 | struct spi_transfer, | |
992 | transfer_list); | |
993 | ||
8d94cc50 SS |
994 | /* prepare to setup the SSP, in pump_transfers, using the per |
995 | * chip configuration */ | |
e0c9905e | 996 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
997 | |
998 | /* Mark as busy and launch transfers */ | |
999 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
1000 | return 0; |
1001 | } | |
1002 | ||
7d94a505 MW |
1003 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
1004 | { | |
1005 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1006 | ||
1007 | /* Disable the SSP now */ | |
1008 | write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, | |
1009 | drv_data->ioaddr); | |
1010 | ||
7d94a505 MW |
1011 | return 0; |
1012 | } | |
1013 | ||
a7bb3909 EM |
1014 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1015 | struct pxa2xx_spi_chip *chip_info) | |
1016 | { | |
1017 | int err = 0; | |
1018 | ||
1019 | if (chip == NULL || chip_info == NULL) | |
1020 | return 0; | |
1021 | ||
1022 | /* NOTE: setup() can be called multiple times, possibly with | |
1023 | * different chip_info, release previously requested GPIO | |
1024 | */ | |
1025 | if (gpio_is_valid(chip->gpio_cs)) | |
1026 | gpio_free(chip->gpio_cs); | |
1027 | ||
1028 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1029 | if (chip_info->cs_control) { | |
1030 | chip->cs_control = chip_info->cs_control; | |
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1035 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1036 | if (err) { | |
f6bd03a7 JN |
1037 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
1038 | chip_info->gpio_cs); | |
a7bb3909 EM |
1039 | return err; |
1040 | } | |
1041 | ||
1042 | chip->gpio_cs = chip_info->gpio_cs; | |
1043 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1044 | ||
1045 | err = gpio_direction_output(chip->gpio_cs, | |
1046 | !chip->gpio_cs_inverted); | |
1047 | } | |
1048 | ||
1049 | return err; | |
1050 | } | |
1051 | ||
e0c9905e SS |
1052 | static int setup(struct spi_device *spi) |
1053 | { | |
1054 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1055 | struct chip_data *chip; | |
1056 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1057 | unsigned int clk_div; | |
a0d2642e MW |
1058 | uint tx_thres, tx_hi_thres, rx_thres; |
1059 | ||
e5262d05 WC |
1060 | switch (drv_data->ssp_type) { |
1061 | case QUARK_X1000_SSP: | |
1062 | tx_thres = TX_THRESH_QUARK_X1000_DFLT; | |
1063 | tx_hi_thres = 0; | |
1064 | rx_thres = RX_THRESH_QUARK_X1000_DFLT; | |
1065 | break; | |
1066 | case LPSS_SSP: | |
a0d2642e MW |
1067 | tx_thres = LPSS_TX_LOTHRESH_DFLT; |
1068 | tx_hi_thres = LPSS_TX_HITHRESH_DFLT; | |
1069 | rx_thres = LPSS_RX_THRESH_DFLT; | |
e5262d05 WC |
1070 | break; |
1071 | default: | |
a0d2642e MW |
1072 | tx_thres = TX_THRESH_DFLT; |
1073 | tx_hi_thres = 0; | |
1074 | rx_thres = RX_THRESH_DFLT; | |
e5262d05 | 1075 | break; |
a0d2642e | 1076 | } |
e0c9905e | 1077 | |
8d94cc50 | 1078 | /* Only alloc on first setup */ |
e0c9905e | 1079 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1080 | if (!chip) { |
e0c9905e | 1081 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 1082 | if (!chip) |
e0c9905e SS |
1083 | return -ENOMEM; |
1084 | ||
2a8626a9 SAS |
1085 | if (drv_data->ssp_type == CE4100_SSP) { |
1086 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
1087 | dev_err(&spi->dev, |
1088 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
1089 | kfree(chip); |
1090 | return -EINVAL; | |
1091 | } | |
1092 | ||
1093 | chip->frm = spi->chip_select; | |
1094 | } else | |
1095 | chip->gpio_cs = -1; | |
e0c9905e | 1096 | chip->enable_dma = 0; |
f1f640a9 | 1097 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1098 | } |
1099 | ||
8d94cc50 SS |
1100 | /* protocol drivers may change the chip settings, so... |
1101 | * if chip_info exists, use it */ | |
1102 | chip_info = spi->controller_data; | |
1103 | ||
e0c9905e | 1104 | /* chip_info isn't always needed */ |
8d94cc50 | 1105 | chip->cr1 = 0; |
e0c9905e | 1106 | if (chip_info) { |
f1f640a9 VS |
1107 | if (chip_info->timeout) |
1108 | chip->timeout = chip_info->timeout; | |
1109 | if (chip_info->tx_threshold) | |
1110 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
1111 | if (chip_info->tx_hi_threshold) |
1112 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
1113 | if (chip_info->rx_threshold) |
1114 | rx_thres = chip_info->rx_threshold; | |
1115 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 1116 | chip->dma_threshold = 0; |
e0c9905e SS |
1117 | if (chip_info->enable_loopback) |
1118 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
1119 | } else if (ACPI_HANDLE(&spi->dev)) { |
1120 | /* | |
1121 | * Slave devices enumerated from ACPI namespace don't | |
1122 | * usually have chip_info but we still might want to use | |
1123 | * DMA with them. | |
1124 | */ | |
1125 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
1126 | } |
1127 | ||
a0d2642e MW |
1128 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
1129 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
1130 | | SSITF_TxHiThresh(tx_hi_thres); | |
1131 | ||
8d94cc50 SS |
1132 | /* set dma burst and threshold outside of chip_info path so that if |
1133 | * chip_info goes away after setting chip->enable_dma, the | |
1134 | * burst and threshold can still respond to changes in bits_per_word */ | |
1135 | if (chip->enable_dma) { | |
1136 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
1137 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1138 | spi->bits_per_word, | |
8d94cc50 SS |
1139 | &chip->dma_burst_size, |
1140 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1141 | dev_warn(&spi->dev, |
1142 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
1143 | } |
1144 | } | |
1145 | ||
e5262d05 | 1146 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz); |
9708c121 | 1147 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e | 1148 | |
4fdb2424 WC |
1149 | chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, |
1150 | spi->bits_per_word); | |
e5262d05 WC |
1151 | switch (drv_data->ssp_type) { |
1152 | case QUARK_X1000_SSP: | |
1153 | chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) | |
1154 | & QUARK_X1000_SSCR1_RFT) | |
1155 | | (QUARK_X1000_SSCR1_TxTresh(tx_thres) | |
1156 | & QUARK_X1000_SSCR1_TFT); | |
1157 | break; | |
1158 | default: | |
1159 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | |
1160 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1161 | break; | |
1162 | } | |
1163 | ||
7f6ee1ad JC |
1164 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1165 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1166 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 1167 | |
b833172f MW |
1168 | if (spi->mode & SPI_LOOP) |
1169 | chip->cr1 |= SSCR1_LBM; | |
1170 | ||
e0c9905e | 1171 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
2a8626a9 | 1172 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 1173 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 1174 | drv_data->max_clk_rate |
c9840daa EM |
1175 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
1176 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 1177 | else |
7d077197 | 1178 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 1179 | drv_data->max_clk_rate / 2 |
c9840daa EM |
1180 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
1181 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
1182 | |
1183 | if (spi->bits_per_word <= 8) { | |
1184 | chip->n_bytes = 1; | |
e0c9905e SS |
1185 | chip->read = u8_reader; |
1186 | chip->write = u8_writer; | |
1187 | } else if (spi->bits_per_word <= 16) { | |
1188 | chip->n_bytes = 2; | |
e0c9905e SS |
1189 | chip->read = u16_reader; |
1190 | chip->write = u16_writer; | |
1191 | } else if (spi->bits_per_word <= 32) { | |
e5262d05 WC |
1192 | if (!is_quark_x1000_ssp(drv_data)) |
1193 | chip->cr0 |= SSCR0_EDSS; | |
e0c9905e | 1194 | chip->n_bytes = 4; |
e0c9905e SS |
1195 | chip->read = u32_reader; |
1196 | chip->write = u32_writer; | |
e0c9905e | 1197 | } |
9708c121 | 1198 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1199 | |
1200 | spi_set_ctldata(spi, chip); | |
1201 | ||
2a8626a9 SAS |
1202 | if (drv_data->ssp_type == CE4100_SSP) |
1203 | return 0; | |
1204 | ||
a7bb3909 | 1205 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1206 | } |
1207 | ||
0ffa0285 | 1208 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1209 | { |
0ffa0285 | 1210 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1211 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1212 | |
7348d82a DR |
1213 | if (!chip) |
1214 | return; | |
1215 | ||
2a8626a9 | 1216 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1217 | gpio_free(chip->gpio_cs); |
1218 | ||
e0c9905e SS |
1219 | kfree(chip); |
1220 | } | |
1221 | ||
a3496855 | 1222 | #ifdef CONFIG_ACPI |
a3496855 MW |
1223 | static struct pxa2xx_spi_master * |
1224 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1225 | { | |
1226 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1227 | struct acpi_device *adev; |
1228 | struct ssp_device *ssp; | |
1229 | struct resource *res; | |
1230 | int devid; | |
1231 | ||
1232 | if (!ACPI_HANDLE(&pdev->dev) || | |
1233 | acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1234 | return NULL; | |
1235 | ||
cc0ee987 | 1236 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1237 | if (!pdata) |
a3496855 | 1238 | return NULL; |
a3496855 MW |
1239 | |
1240 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1241 | if (!res) | |
1242 | return NULL; | |
1243 | ||
1244 | ssp = &pdata->ssp; | |
1245 | ||
1246 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1247 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1248 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1249 | return NULL; |
a3496855 MW |
1250 | |
1251 | ssp->clk = devm_clk_get(&pdev->dev, NULL); | |
1252 | ssp->irq = platform_get_irq(pdev, 0); | |
1253 | ssp->type = LPSS_SSP; | |
1254 | ssp->pdev = pdev; | |
1255 | ||
1256 | ssp->port_id = -1; | |
1257 | if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) | |
1258 | ssp->port_id = devid; | |
1259 | ||
1260 | pdata->num_chipselect = 1; | |
cddb339b | 1261 | pdata->enable_dma = true; |
a3496855 MW |
1262 | |
1263 | return pdata; | |
1264 | } | |
1265 | ||
1266 | static struct acpi_device_id pxa2xx_spi_acpi_match[] = { | |
1267 | { "INT33C0", 0 }, | |
1268 | { "INT33C1", 0 }, | |
54acbd96 MW |
1269 | { "INT3430", 0 }, |
1270 | { "INT3431", 0 }, | |
4b30f2a1 | 1271 | { "80860F0E", 0 }, |
aca26364 | 1272 | { "8086228E", 0 }, |
a3496855 MW |
1273 | { }, |
1274 | }; | |
1275 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1276 | #else | |
1277 | static inline struct pxa2xx_spi_master * | |
1278 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1279 | { | |
1280 | return NULL; | |
1281 | } | |
1282 | #endif | |
1283 | ||
fd4a319b | 1284 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1285 | { |
1286 | struct device *dev = &pdev->dev; | |
1287 | struct pxa2xx_spi_master *platform_info; | |
1288 | struct spi_master *master; | |
65a00a20 | 1289 | struct driver_data *drv_data; |
2f1a74e5 | 1290 | struct ssp_device *ssp; |
65a00a20 | 1291 | int status; |
e0c9905e | 1292 | |
851bacf5 MW |
1293 | platform_info = dev_get_platdata(dev); |
1294 | if (!platform_info) { | |
a3496855 MW |
1295 | platform_info = pxa2xx_spi_acpi_get_pdata(pdev); |
1296 | if (!platform_info) { | |
1297 | dev_err(&pdev->dev, "missing platform data\n"); | |
1298 | return -ENODEV; | |
1299 | } | |
851bacf5 | 1300 | } |
e0c9905e | 1301 | |
baffe169 | 1302 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1303 | if (!ssp) |
1304 | ssp = &platform_info->ssp; | |
1305 | ||
1306 | if (!ssp->mmio_base) { | |
1307 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1308 | return -ENODEV; |
1309 | } | |
1310 | ||
1311 | /* Allocate master with space for drv_data and null dma buffer */ | |
1312 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1313 | if (!master) { | |
65a00a20 | 1314 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1315 | pxa_ssp_free(ssp); |
e0c9905e SS |
1316 | return -ENOMEM; |
1317 | } | |
1318 | drv_data = spi_master_get_devdata(master); | |
1319 | drv_data->master = master; | |
1320 | drv_data->master_info = platform_info; | |
1321 | drv_data->pdev = pdev; | |
2f1a74e5 | 1322 | drv_data->ssp = ssp; |
e0c9905e | 1323 | |
21486af0 | 1324 | master->dev.parent = &pdev->dev; |
21486af0 | 1325 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1326 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1327 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1328 | |
851bacf5 | 1329 | master->bus_num = ssp->port_id; |
e0c9905e | 1330 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 1331 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1332 | master->cleanup = cleanup; |
1333 | master->setup = setup; | |
7f86bde9 | 1334 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1335 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
7dd62787 | 1336 | master->auto_runtime_pm = true; |
e0c9905e | 1337 | |
2f1a74e5 | 1338 | drv_data->ssp_type = ssp->type; |
2b9b84f4 | 1339 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
e0c9905e | 1340 | |
2f1a74e5 | 1341 | drv_data->ioaddr = ssp->mmio_base; |
1342 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1343 | if (pxa25x_ssp_comp(drv_data)) { |
e5262d05 WC |
1344 | switch (drv_data->ssp_type) { |
1345 | case QUARK_X1000_SSP: | |
1346 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
1347 | break; | |
1348 | default: | |
1349 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
1350 | break; | |
1351 | } | |
1352 | ||
e0c9905e SS |
1353 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1354 | drv_data->dma_cr1 = 0; | |
1355 | drv_data->clear_sr = SSSR_ROR; | |
1356 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1357 | } else { | |
24778be2 | 1358 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1359 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1360 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1361 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1362 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1363 | } | |
1364 | ||
49cbb1e0 SAS |
1365 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1366 | drv_data); | |
e0c9905e | 1367 | if (status < 0) { |
65a00a20 | 1368 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1369 | goto out_error_master_alloc; |
1370 | } | |
1371 | ||
1372 | /* Setup DMA if requested */ | |
1373 | drv_data->tx_channel = -1; | |
1374 | drv_data->rx_channel = -1; | |
1375 | if (platform_info->enable_dma) { | |
cd7bed00 MW |
1376 | status = pxa2xx_spi_dma_setup(drv_data); |
1377 | if (status) { | |
cddb339b | 1378 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1379 | platform_info->enable_dma = false; |
e0c9905e | 1380 | } |
e0c9905e SS |
1381 | } |
1382 | ||
1383 | /* Enable SOC clock */ | |
3343b7a6 MW |
1384 | clk_prepare_enable(ssp->clk); |
1385 | ||
1386 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | |
e0c9905e SS |
1387 | |
1388 | /* Load default SSP configuration */ | |
1389 | write_SSCR0(0, drv_data->ioaddr); | |
e5262d05 WC |
1390 | switch (drv_data->ssp_type) { |
1391 | case QUARK_X1000_SSP: | |
1392 | write_SSCR1(QUARK_X1000_SSCR1_RxTresh( | |
1393 | RX_THRESH_QUARK_X1000_DFLT) | | |
1394 | QUARK_X1000_SSCR1_TxTresh( | |
1395 | TX_THRESH_QUARK_X1000_DFLT), | |
1396 | drv_data->ioaddr); | |
1397 | ||
1398 | /* using the Motorola SPI protocol and use 8 bit frame */ | |
1399 | write_SSCR0(QUARK_X1000_SSCR0_Motorola | |
1400 | | QUARK_X1000_SSCR0_DataSize(8), | |
1401 | drv_data->ioaddr); | |
1402 | break; | |
1403 | default: | |
1404 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | | |
1405 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1406 | drv_data->ioaddr); | |
1407 | write_SSCR0(SSCR0_SCR(2) | |
1408 | | SSCR0_Motorola | |
1409 | | SSCR0_DataSize(8), | |
1410 | drv_data->ioaddr); | |
1411 | break; | |
1412 | } | |
1413 | ||
2a8626a9 | 1414 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e | 1415 | write_SSTO(0, drv_data->ioaddr); |
e5262d05 WC |
1416 | |
1417 | if (!is_quark_x1000_ssp(drv_data)) | |
1418 | write_SSPSP(0, drv_data->ioaddr); | |
e0c9905e | 1419 | |
a0d2642e MW |
1420 | lpss_ssp_setup(drv_data); |
1421 | ||
7f86bde9 MW |
1422 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1423 | (unsigned long)drv_data); | |
e0c9905e | 1424 | |
836d1a22 AO |
1425 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1426 | pm_runtime_use_autosuspend(&pdev->dev); | |
1427 | pm_runtime_set_active(&pdev->dev); | |
1428 | pm_runtime_enable(&pdev->dev); | |
1429 | ||
e0c9905e SS |
1430 | /* Register with the SPI framework */ |
1431 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1432 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1433 | if (status != 0) { |
1434 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1435 | goto out_error_clock_enabled; |
e0c9905e SS |
1436 | } |
1437 | ||
1438 | return status; | |
1439 | ||
e0c9905e | 1440 | out_error_clock_enabled: |
3343b7a6 | 1441 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1442 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1443 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1444 | |
1445 | out_error_master_alloc: | |
1446 | spi_master_put(master); | |
baffe169 | 1447 | pxa_ssp_free(ssp); |
e0c9905e SS |
1448 | return status; |
1449 | } | |
1450 | ||
1451 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1452 | { | |
1453 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1454 | struct ssp_device *ssp; |
e0c9905e SS |
1455 | |
1456 | if (!drv_data) | |
1457 | return 0; | |
51e911e2 | 1458 | ssp = drv_data->ssp; |
e0c9905e | 1459 | |
7d94a505 MW |
1460 | pm_runtime_get_sync(&pdev->dev); |
1461 | ||
e0c9905e SS |
1462 | /* Disable the SSP at the peripheral and SOC level */ |
1463 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1464 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1465 | |
1466 | /* Release DMA */ | |
cd7bed00 MW |
1467 | if (drv_data->master_info->enable_dma) |
1468 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1469 | |
7d94a505 MW |
1470 | pm_runtime_put_noidle(&pdev->dev); |
1471 | pm_runtime_disable(&pdev->dev); | |
1472 | ||
e0c9905e | 1473 | /* Release IRQ */ |
2f1a74e5 | 1474 | free_irq(ssp->irq, drv_data); |
1475 | ||
1476 | /* Release SSP */ | |
baffe169 | 1477 | pxa_ssp_free(ssp); |
e0c9905e | 1478 | |
e0c9905e SS |
1479 | return 0; |
1480 | } | |
1481 | ||
1482 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1483 | { | |
1484 | int status = 0; | |
1485 | ||
1486 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1487 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1488 | } | |
1489 | ||
382cebb0 | 1490 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1491 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1492 | { |
86d2593a | 1493 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1494 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1495 | int status = 0; |
1496 | ||
7f86bde9 | 1497 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1498 | if (status != 0) |
1499 | return status; | |
1500 | write_SSCR0(0, drv_data->ioaddr); | |
2b9375b9 DES |
1501 | |
1502 | if (!pm_runtime_suspended(dev)) | |
1503 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1504 | |
1505 | return 0; | |
1506 | } | |
1507 | ||
86d2593a | 1508 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1509 | { |
86d2593a | 1510 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1511 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1512 | int status = 0; |
1513 | ||
cd7bed00 | 1514 | pxa2xx_spi_dma_resume(drv_data); |
148da331 | 1515 | |
e0c9905e | 1516 | /* Enable the SSP clock */ |
2b9375b9 DES |
1517 | if (!pm_runtime_suspended(dev)) |
1518 | clk_prepare_enable(ssp->clk); | |
e0c9905e | 1519 | |
c50325f7 CCE |
1520 | /* Restore LPSS private register bits */ |
1521 | lpss_ssp_setup(drv_data); | |
1522 | ||
e0c9905e | 1523 | /* Start the queue running */ |
7f86bde9 | 1524 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1525 | if (status != 0) { |
86d2593a | 1526 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1527 | return status; |
1528 | } | |
1529 | ||
1530 | return 0; | |
1531 | } | |
7d94a505 MW |
1532 | #endif |
1533 | ||
1534 | #ifdef CONFIG_PM_RUNTIME | |
1535 | static int pxa2xx_spi_runtime_suspend(struct device *dev) | |
1536 | { | |
1537 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1538 | ||
1539 | clk_disable_unprepare(drv_data->ssp->clk); | |
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1544 | { | |
1545 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1546 | ||
1547 | clk_prepare_enable(drv_data->ssp->clk); | |
1548 | return 0; | |
1549 | } | |
1550 | #endif | |
86d2593a | 1551 | |
47145210 | 1552 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1553 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1554 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1555 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1556 | }; |
e0c9905e SS |
1557 | |
1558 | static struct platform_driver driver = { | |
1559 | .driver = { | |
86d2593a | 1560 | .name = "pxa2xx-spi", |
86d2593a | 1561 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1562 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1563 | }, |
fbd29a14 | 1564 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1565 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1566 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1567 | }; |
1568 | ||
1569 | static int __init pxa2xx_spi_init(void) | |
1570 | { | |
fbd29a14 | 1571 | return platform_driver_register(&driver); |
e0c9905e | 1572 | } |
5b61a749 | 1573 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1574 | |
1575 | static void __exit pxa2xx_spi_exit(void) | |
1576 | { | |
1577 | platform_driver_unregister(&driver); | |
1578 | } | |
1579 | module_exit(pxa2xx_spi_exit); |