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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
e0c9905e SS |
14 | */ |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/errno.h> | |
cbfd6a21 | 21 | #include <linux/err.h> |
e0c9905e | 22 | #include <linux/interrupt.h> |
9df461ec | 23 | #include <linux/kernel.h> |
e0c9905e | 24 | #include <linux/platform_device.h> |
8348c259 | 25 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 26 | #include <linux/spi/spi.h> |
e0c9905e | 27 | #include <linux/delay.h> |
a7bb3909 | 28 | #include <linux/gpio.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
3343b7a6 | 30 | #include <linux/clk.h> |
7d94a505 | 31 | #include <linux/pm_runtime.h> |
a3496855 | 32 | #include <linux/acpi.h> |
e0c9905e | 33 | |
cd7bed00 | 34 | #include "spi-pxa2xx.h" |
e0c9905e SS |
35 | |
36 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 37 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 38 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 39 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e | 40 | |
f1f640a9 VS |
41 | #define TIMOUT_DFLT 1000 |
42 | ||
b97c74bd NF |
43 | /* |
44 | * for testing SSCR1 changes that require SSP restart, basically | |
45 | * everything except the service and interrupt enables, the pxa270 developer | |
46 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
47 | * list, but the PXA255 dev man says all bits without really meaning the | |
48 | * service and interrupt enables | |
49 | */ | |
50 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 51 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
52 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
53 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
54 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
55 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 56 | |
e5262d05 WC |
57 | #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ |
58 | | QUARK_X1000_SSCR1_EFWR \ | |
59 | | QUARK_X1000_SSCR1_RFT \ | |
60 | | QUARK_X1000_SSCR1_TFT \ | |
61 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
62 | ||
a0d2642e MW |
63 | #define LPSS_RX_THRESH_DFLT 64 |
64 | #define LPSS_TX_LOTHRESH_DFLT 160 | |
65 | #define LPSS_TX_HITHRESH_DFLT 224 | |
66 | ||
67 | /* Offset from drv_data->lpss_base */ | |
1de70612 MW |
68 | #define GENERAL_REG 0x08 |
69 | #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) | |
0054e28d | 70 | #define SSP_REG 0x0c |
a0d2642e MW |
71 | #define SPI_CS_CONTROL 0x18 |
72 | #define SPI_CS_CONTROL_SW_MODE BIT(0) | |
73 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | |
74 | ||
75 | static bool is_lpss_ssp(const struct driver_data *drv_data) | |
76 | { | |
03fbf488 JN |
77 | switch (drv_data->ssp_type) { |
78 | case LPSS_LPT_SSP: | |
79 | case LPSS_BYT_SSP: | |
80 | return true; | |
81 | default: | |
82 | return false; | |
83 | } | |
a0d2642e MW |
84 | } |
85 | ||
e5262d05 WC |
86 | static bool is_quark_x1000_ssp(const struct driver_data *drv_data) |
87 | { | |
88 | return drv_data->ssp_type == QUARK_X1000_SSP; | |
89 | } | |
90 | ||
4fdb2424 WC |
91 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
92 | { | |
93 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
94 | case QUARK_X1000_SSP: |
95 | return QUARK_X1000_SSCR1_CHANGE_MASK; | |
4fdb2424 WC |
96 | default: |
97 | return SSCR1_CHANGE_MASK; | |
98 | } | |
99 | } | |
100 | ||
101 | static u32 | |
102 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
103 | { | |
104 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
105 | case QUARK_X1000_SSP: |
106 | return RX_THRESH_QUARK_X1000_DFLT; | |
4fdb2424 WC |
107 | default: |
108 | return RX_THRESH_DFLT; | |
109 | } | |
110 | } | |
111 | ||
112 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
113 | { | |
4fdb2424 WC |
114 | u32 mask; |
115 | ||
116 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
117 | case QUARK_X1000_SSP: |
118 | mask = QUARK_X1000_SSSR_TFL_MASK; | |
119 | break; | |
4fdb2424 WC |
120 | default: |
121 | mask = SSSR_TFL_MASK; | |
122 | break; | |
123 | } | |
124 | ||
c039dd27 | 125 | return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; |
4fdb2424 WC |
126 | } |
127 | ||
128 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
129 | u32 *sccr1_reg) | |
130 | { | |
131 | u32 mask; | |
132 | ||
133 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
134 | case QUARK_X1000_SSP: |
135 | mask = QUARK_X1000_SSCR1_RFT; | |
136 | break; | |
4fdb2424 WC |
137 | default: |
138 | mask = SSCR1_RFT; | |
139 | break; | |
140 | } | |
141 | *sccr1_reg &= ~mask; | |
142 | } | |
143 | ||
144 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
145 | u32 *sccr1_reg, u32 threshold) | |
146 | { | |
147 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
148 | case QUARK_X1000_SSP: |
149 | *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); | |
150 | break; | |
4fdb2424 WC |
151 | default: |
152 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
153 | break; | |
154 | } | |
155 | } | |
156 | ||
157 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
158 | u32 clk_div, u8 bits) | |
159 | { | |
160 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
161 | case QUARK_X1000_SSP: |
162 | return clk_div | |
163 | | QUARK_X1000_SSCR0_Motorola | |
164 | | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) | |
165 | | SSCR0_SSE; | |
4fdb2424 WC |
166 | default: |
167 | return clk_div | |
168 | | SSCR0_Motorola | |
169 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
170 | | SSCR0_SSE | |
171 | | (bits > 16 ? SSCR0_EDSS : 0); | |
172 | } | |
173 | } | |
174 | ||
a0d2642e MW |
175 | /* |
176 | * Read and write LPSS SSP private registers. Caller must first check that | |
177 | * is_lpss_ssp() returns true before these can be called. | |
178 | */ | |
179 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
180 | { | |
181 | WARN_ON(!drv_data->lpss_base); | |
182 | return readl(drv_data->lpss_base + offset); | |
183 | } | |
184 | ||
185 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
186 | unsigned offset, u32 value) | |
187 | { | |
188 | WARN_ON(!drv_data->lpss_base); | |
189 | writel(value, drv_data->lpss_base + offset); | |
190 | } | |
191 | ||
192 | /* | |
193 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
194 | * @drv_data: pointer to the driver private data | |
195 | * | |
196 | * Perform LPSS SSP specific setup. This function must be called first if | |
197 | * one is going to use LPSS SSP private registers. | |
198 | */ | |
199 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
200 | { | |
201 | unsigned offset = 0x400; | |
202 | u32 value, orig; | |
203 | ||
a0d2642e MW |
204 | /* |
205 | * Perform auto-detection of the LPSS SSP private registers. They | |
206 | * can be either at 1k or 2k offset from the base address. | |
207 | */ | |
208 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
209 | ||
e61f487f | 210 | /* Test SPI_CS_CONTROL_SW_MODE bit enabling */ |
a0d2642e MW |
211 | value = orig | SPI_CS_CONTROL_SW_MODE; |
212 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
213 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
214 | if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { | |
215 | offset = 0x800; | |
216 | goto detection_done; | |
217 | } | |
218 | ||
e61f487f CCE |
219 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); |
220 | ||
221 | /* Test SPI_CS_CONTROL_SW_MODE bit disabling */ | |
222 | value = orig & ~SPI_CS_CONTROL_SW_MODE; | |
a0d2642e MW |
223 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); |
224 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
e61f487f | 225 | if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) { |
a0d2642e MW |
226 | offset = 0x800; |
227 | goto detection_done; | |
228 | } | |
229 | ||
230 | detection_done: | |
231 | /* Now set the LPSS base */ | |
232 | drv_data->lpss_base = drv_data->ioaddr + offset; | |
233 | ||
234 | /* Enable software chip select control */ | |
235 | value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | |
236 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
0054e28d MW |
237 | |
238 | /* Enable multiblock DMA transfers */ | |
1de70612 | 239 | if (drv_data->master_info->enable_dma) { |
0054e28d | 240 | __lpss_ssp_write_priv(drv_data, SSP_REG, 1); |
1de70612 MW |
241 | |
242 | value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); | |
243 | value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; | |
244 | __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); | |
245 | } | |
a0d2642e MW |
246 | } |
247 | ||
248 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
249 | { | |
250 | u32 value; | |
251 | ||
a0d2642e MW |
252 | value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); |
253 | if (enable) | |
254 | value &= ~SPI_CS_CONTROL_CS_HIGH; | |
255 | else | |
256 | value |= SPI_CS_CONTROL_CS_HIGH; | |
257 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
258 | } | |
259 | ||
a7bb3909 EM |
260 | static void cs_assert(struct driver_data *drv_data) |
261 | { | |
262 | struct chip_data *chip = drv_data->cur_chip; | |
263 | ||
2a8626a9 | 264 | if (drv_data->ssp_type == CE4100_SSP) { |
c039dd27 | 265 | pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm); |
2a8626a9 SAS |
266 | return; |
267 | } | |
268 | ||
a7bb3909 EM |
269 | if (chip->cs_control) { |
270 | chip->cs_control(PXA2XX_CS_ASSERT); | |
271 | return; | |
272 | } | |
273 | ||
a0d2642e | 274 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 275 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
276 | return; |
277 | } | |
278 | ||
7566bcc7 JN |
279 | if (is_lpss_ssp(drv_data)) |
280 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
281 | } |
282 | ||
283 | static void cs_deassert(struct driver_data *drv_data) | |
284 | { | |
285 | struct chip_data *chip = drv_data->cur_chip; | |
286 | ||
2a8626a9 SAS |
287 | if (drv_data->ssp_type == CE4100_SSP) |
288 | return; | |
289 | ||
a7bb3909 | 290 | if (chip->cs_control) { |
2b2562d3 | 291 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
292 | return; |
293 | } | |
294 | ||
a0d2642e | 295 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 296 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
297 | return; |
298 | } | |
299 | ||
7566bcc7 JN |
300 | if (is_lpss_ssp(drv_data)) |
301 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
302 | } |
303 | ||
cd7bed00 | 304 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
305 | { |
306 | unsigned long limit = loops_per_jiffy << 1; | |
307 | ||
e0c9905e | 308 | do { |
c039dd27 JN |
309 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
310 | pxa2xx_spi_read(drv_data, SSDR); | |
311 | } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); | |
2a8626a9 | 312 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
313 | |
314 | return limit; | |
315 | } | |
316 | ||
8d94cc50 | 317 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 318 | { |
9708c121 | 319 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 320 | |
4fdb2424 | 321 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
322 | || (drv_data->tx == drv_data->tx_end)) |
323 | return 0; | |
324 | ||
c039dd27 | 325 | pxa2xx_spi_write(drv_data, SSDR, 0); |
8d94cc50 SS |
326 | drv_data->tx += n_bytes; |
327 | ||
328 | return 1; | |
e0c9905e SS |
329 | } |
330 | ||
8d94cc50 | 331 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 332 | { |
9708c121 | 333 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 334 | |
c039dd27 JN |
335 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
336 | && (drv_data->rx < drv_data->rx_end)) { | |
337 | pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
338 | drv_data->rx += n_bytes; |
339 | } | |
8d94cc50 SS |
340 | |
341 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
342 | } |
343 | ||
8d94cc50 | 344 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 345 | { |
4fdb2424 | 346 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
347 | || (drv_data->tx == drv_data->tx_end)) |
348 | return 0; | |
349 | ||
c039dd27 | 350 | pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); |
8d94cc50 SS |
351 | ++drv_data->tx; |
352 | ||
353 | return 1; | |
e0c9905e SS |
354 | } |
355 | ||
8d94cc50 | 356 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 357 | { |
c039dd27 JN |
358 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
359 | && (drv_data->rx < drv_data->rx_end)) { | |
360 | *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
361 | ++drv_data->rx; |
362 | } | |
8d94cc50 SS |
363 | |
364 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
365 | } |
366 | ||
8d94cc50 | 367 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 368 | { |
4fdb2424 | 369 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
370 | || (drv_data->tx == drv_data->tx_end)) |
371 | return 0; | |
372 | ||
c039dd27 | 373 | pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); |
8d94cc50 SS |
374 | drv_data->tx += 2; |
375 | ||
376 | return 1; | |
e0c9905e SS |
377 | } |
378 | ||
8d94cc50 | 379 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 380 | { |
c039dd27 JN |
381 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
382 | && (drv_data->rx < drv_data->rx_end)) { | |
383 | *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
384 | drv_data->rx += 2; |
385 | } | |
8d94cc50 SS |
386 | |
387 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 388 | } |
8d94cc50 SS |
389 | |
390 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 391 | { |
4fdb2424 | 392 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
393 | || (drv_data->tx == drv_data->tx_end)) |
394 | return 0; | |
395 | ||
c039dd27 | 396 | pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); |
8d94cc50 SS |
397 | drv_data->tx += 4; |
398 | ||
399 | return 1; | |
e0c9905e SS |
400 | } |
401 | ||
8d94cc50 | 402 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 403 | { |
c039dd27 JN |
404 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
405 | && (drv_data->rx < drv_data->rx_end)) { | |
406 | *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
407 | drv_data->rx += 4; |
408 | } | |
8d94cc50 SS |
409 | |
410 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
411 | } |
412 | ||
cd7bed00 | 413 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
414 | { |
415 | struct spi_message *msg = drv_data->cur_msg; | |
416 | struct spi_transfer *trans = drv_data->cur_transfer; | |
417 | ||
418 | /* Move to next transfer */ | |
419 | if (trans->transfer_list.next != &msg->transfers) { | |
420 | drv_data->cur_transfer = | |
421 | list_entry(trans->transfer_list.next, | |
422 | struct spi_transfer, | |
423 | transfer_list); | |
424 | return RUNNING_STATE; | |
425 | } else | |
426 | return DONE_STATE; | |
427 | } | |
428 | ||
e0c9905e | 429 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 430 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
431 | { |
432 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 433 | struct spi_message *msg; |
e0c9905e | 434 | |
5daa3ba0 SS |
435 | msg = drv_data->cur_msg; |
436 | drv_data->cur_msg = NULL; | |
437 | drv_data->cur_transfer = NULL; | |
5daa3ba0 | 438 | |
23e2c2aa | 439 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e0c9905e SS |
440 | transfer_list); |
441 | ||
8423597d NF |
442 | /* Delay if requested before any change in chip select */ |
443 | if (last_transfer->delay_usecs) | |
444 | udelay(last_transfer->delay_usecs); | |
445 | ||
446 | /* Drop chip select UNLESS cs_change is true or we are returning | |
447 | * a message with an error, or next message is for another chip | |
448 | */ | |
e0c9905e | 449 | if (!last_transfer->cs_change) |
a7bb3909 | 450 | cs_deassert(drv_data); |
8423597d NF |
451 | else { |
452 | struct spi_message *next_msg; | |
453 | ||
454 | /* Holding of cs was hinted, but we need to make sure | |
455 | * the next message is for the same chip. Don't waste | |
456 | * time with the following tests unless this was hinted. | |
457 | * | |
458 | * We cannot postpone this until pump_messages, because | |
459 | * after calling msg->complete (below) the driver that | |
460 | * sent the current message could be unloaded, which | |
461 | * could invalidate the cs_control() callback... | |
462 | */ | |
463 | ||
464 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 465 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
466 | |
467 | /* see if the next and current messages point | |
468 | * to the same chip | |
469 | */ | |
470 | if (next_msg && next_msg->spi != msg->spi) | |
471 | next_msg = NULL; | |
472 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 473 | cs_deassert(drv_data); |
8423597d | 474 | } |
e0c9905e | 475 | |
a7bb3909 | 476 | drv_data->cur_chip = NULL; |
c957e8f0 | 477 | spi_finalize_current_message(drv_data->master); |
e0c9905e SS |
478 | } |
479 | ||
579d3bb2 SAS |
480 | static void reset_sccr1(struct driver_data *drv_data) |
481 | { | |
579d3bb2 SAS |
482 | struct chip_data *chip = drv_data->cur_chip; |
483 | u32 sccr1_reg; | |
484 | ||
c039dd27 | 485 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; |
579d3bb2 SAS |
486 | sccr1_reg &= ~SSCR1_RFT; |
487 | sccr1_reg |= chip->threshold; | |
c039dd27 | 488 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
579d3bb2 SAS |
489 | } |
490 | ||
8d94cc50 | 491 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 492 | { |
8d94cc50 | 493 | /* Stop and reset SSP */ |
2a8626a9 | 494 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 495 | reset_sccr1(drv_data); |
2a8626a9 | 496 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 497 | pxa2xx_spi_write(drv_data, SSTO, 0); |
cd7bed00 | 498 | pxa2xx_spi_flush(drv_data); |
c039dd27 JN |
499 | pxa2xx_spi_write(drv_data, SSCR0, |
500 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
e0c9905e | 501 | |
8d94cc50 | 502 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 503 | |
8d94cc50 SS |
504 | drv_data->cur_msg->state = ERROR_STATE; |
505 | tasklet_schedule(&drv_data->pump_transfers); | |
506 | } | |
5daa3ba0 | 507 | |
8d94cc50 SS |
508 | static void int_transfer_complete(struct driver_data *drv_data) |
509 | { | |
8d94cc50 | 510 | /* Stop SSP */ |
2a8626a9 | 511 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 512 | reset_sccr1(drv_data); |
2a8626a9 | 513 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 514 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e0c9905e | 515 | |
25985edc | 516 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
517 | drv_data->cur_msg->actual_length += drv_data->len - |
518 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 519 | |
8423597d NF |
520 | /* Transfer delays and chip select release are |
521 | * handled in pump_transfers or giveback | |
522 | */ | |
e0c9905e | 523 | |
8d94cc50 | 524 | /* Move to next transfer */ |
cd7bed00 | 525 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 526 | |
8d94cc50 SS |
527 | /* Schedule transfer tasklet */ |
528 | tasklet_schedule(&drv_data->pump_transfers); | |
529 | } | |
e0c9905e | 530 | |
8d94cc50 SS |
531 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
532 | { | |
c039dd27 JN |
533 | u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? |
534 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 535 | |
c039dd27 | 536 | u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; |
e0c9905e | 537 | |
8d94cc50 SS |
538 | if (irq_status & SSSR_ROR) { |
539 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
540 | return IRQ_HANDLED; | |
541 | } | |
e0c9905e | 542 | |
8d94cc50 | 543 | if (irq_status & SSSR_TINT) { |
c039dd27 | 544 | pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); |
8d94cc50 SS |
545 | if (drv_data->read(drv_data)) { |
546 | int_transfer_complete(drv_data); | |
547 | return IRQ_HANDLED; | |
548 | } | |
549 | } | |
e0c9905e | 550 | |
8d94cc50 SS |
551 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
552 | do { | |
553 | if (drv_data->read(drv_data)) { | |
554 | int_transfer_complete(drv_data); | |
555 | return IRQ_HANDLED; | |
556 | } | |
557 | } while (drv_data->write(drv_data)); | |
e0c9905e | 558 | |
8d94cc50 SS |
559 | if (drv_data->read(drv_data)) { |
560 | int_transfer_complete(drv_data); | |
561 | return IRQ_HANDLED; | |
562 | } | |
e0c9905e | 563 | |
8d94cc50 | 564 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
565 | u32 bytes_left; |
566 | u32 sccr1_reg; | |
567 | ||
c039dd27 | 568 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
579d3bb2 SAS |
569 | sccr1_reg &= ~SSCR1_TIE; |
570 | ||
571 | /* | |
572 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 573 | * remaining RX bytes. |
579d3bb2 | 574 | */ |
2a8626a9 | 575 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 576 | u32 rx_thre; |
579d3bb2 | 577 | |
4fdb2424 | 578 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
579 | |
580 | bytes_left = drv_data->rx_end - drv_data->rx; | |
581 | switch (drv_data->n_bytes) { | |
582 | case 4: | |
583 | bytes_left >>= 1; | |
584 | case 2: | |
585 | bytes_left >>= 1; | |
8d94cc50 | 586 | } |
579d3bb2 | 587 | |
4fdb2424 WC |
588 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
589 | if (rx_thre > bytes_left) | |
590 | rx_thre = bytes_left; | |
579d3bb2 | 591 | |
4fdb2424 | 592 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 593 | } |
c039dd27 | 594 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
e0c9905e SS |
595 | } |
596 | ||
5daa3ba0 SS |
597 | /* We did something */ |
598 | return IRQ_HANDLED; | |
e0c9905e SS |
599 | } |
600 | ||
7d12e780 | 601 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 602 | { |
c7bec5ab | 603 | struct driver_data *drv_data = dev_id; |
7d94a505 | 604 | u32 sccr1_reg; |
49cbb1e0 SAS |
605 | u32 mask = drv_data->mask_sr; |
606 | u32 status; | |
607 | ||
7d94a505 MW |
608 | /* |
609 | * The IRQ might be shared with other peripherals so we must first | |
610 | * check that are we RPM suspended or not. If we are we assume that | |
611 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
612 | * interrupt is enabled). | |
613 | */ | |
614 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
615 | return IRQ_NONE; | |
616 | ||
269e4a41 MW |
617 | /* |
618 | * If the device is not yet in RPM suspended state and we get an | |
619 | * interrupt that is meant for another device, check if status bits | |
620 | * are all set to one. That means that the device is already | |
621 | * powered off. | |
622 | */ | |
c039dd27 | 623 | status = pxa2xx_spi_read(drv_data, SSSR); |
269e4a41 MW |
624 | if (status == ~0) |
625 | return IRQ_NONE; | |
626 | ||
c039dd27 | 627 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
49cbb1e0 SAS |
628 | |
629 | /* Ignore possible writes if we don't need to write */ | |
630 | if (!(sccr1_reg & SSCR1_TIE)) | |
631 | mask &= ~SSSR_TFS; | |
632 | ||
633 | if (!(status & mask)) | |
634 | return IRQ_NONE; | |
e0c9905e SS |
635 | |
636 | if (!drv_data->cur_msg) { | |
5daa3ba0 | 637 | |
c039dd27 JN |
638 | pxa2xx_spi_write(drv_data, SSCR0, |
639 | pxa2xx_spi_read(drv_data, SSCR0) | |
640 | & ~SSCR0_SSE); | |
641 | pxa2xx_spi_write(drv_data, SSCR1, | |
642 | pxa2xx_spi_read(drv_data, SSCR1) | |
643 | & ~drv_data->int_cr1); | |
2a8626a9 | 644 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 645 | pxa2xx_spi_write(drv_data, SSTO, 0); |
2a8626a9 | 646 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 647 | |
f6bd03a7 JN |
648 | dev_err(&drv_data->pdev->dev, |
649 | "bad message state in interrupt handler\n"); | |
5daa3ba0 | 650 | |
e0c9905e SS |
651 | /* Never fail */ |
652 | return IRQ_HANDLED; | |
653 | } | |
654 | ||
655 | return drv_data->transfer_handler(drv_data); | |
656 | } | |
657 | ||
e5262d05 | 658 | /* |
9df461ec AS |
659 | * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply |
660 | * input frequency by fractions of 2^24. It also has a divider by 5. | |
661 | * | |
662 | * There are formulas to get baud rate value for given input frequency and | |
663 | * divider parameters, such as DDS_CLK_RATE and SCR: | |
664 | * | |
665 | * Fsys = 200MHz | |
666 | * | |
667 | * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) | |
668 | * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) | |
669 | * | |
670 | * DDS_CLK_RATE either 2^n or 2^n / 5. | |
671 | * SCR is in range 0 .. 255 | |
672 | * | |
673 | * Divisor = 5^i * 2^j * 2 * k | |
674 | * i = [0, 1] i = 1 iff j = 0 or j > 3 | |
675 | * j = [0, 23] j = 0 iff i = 1 | |
676 | * k = [1, 256] | |
677 | * Special case: j = 0, i = 1: Divisor = 2 / 5 | |
678 | * | |
679 | * Accordingly to the specification the recommended values for DDS_CLK_RATE | |
680 | * are: | |
681 | * Case 1: 2^n, n = [0, 23] | |
682 | * Case 2: 2^24 * 2 / 5 (0x666666) | |
683 | * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) | |
684 | * | |
685 | * In all cases the lowest possible value is better. | |
686 | * | |
687 | * The function calculates parameters for all cases and chooses the one closest | |
688 | * to the asked baud rate. | |
e5262d05 | 689 | */ |
9df461ec AS |
690 | static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) |
691 | { | |
692 | unsigned long xtal = 200000000; | |
693 | unsigned long fref = xtal / 2; /* mandatory division by 2, | |
694 | see (2) */ | |
695 | /* case 3 */ | |
696 | unsigned long fref1 = fref / 2; /* case 1 */ | |
697 | unsigned long fref2 = fref * 2 / 5; /* case 2 */ | |
698 | unsigned long scale; | |
699 | unsigned long q, q1, q2; | |
700 | long r, r1, r2; | |
701 | u32 mul; | |
702 | ||
703 | /* Case 1 */ | |
704 | ||
705 | /* Set initial value for DDS_CLK_RATE */ | |
706 | mul = (1 << 24) >> 1; | |
707 | ||
708 | /* Calculate initial quot */ | |
709 | q1 = DIV_ROUND_CLOSEST(fref1, rate); | |
710 | ||
711 | /* Scale q1 if it's too big */ | |
712 | if (q1 > 256) { | |
713 | /* Scale q1 to range [1, 512] */ | |
714 | scale = fls_long(q1 - 1); | |
715 | if (scale > 9) { | |
716 | q1 >>= scale - 9; | |
717 | mul >>= scale - 9; | |
e5262d05 | 718 | } |
9df461ec AS |
719 | |
720 | /* Round the result if we have a remainder */ | |
721 | q1 += q1 & 1; | |
722 | } | |
723 | ||
724 | /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ | |
725 | scale = __ffs(q1); | |
726 | q1 >>= scale; | |
727 | mul >>= scale; | |
728 | ||
729 | /* Get the remainder */ | |
730 | r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); | |
731 | ||
732 | /* Case 2 */ | |
733 | ||
734 | q2 = DIV_ROUND_CLOSEST(fref2, rate); | |
735 | r2 = abs(fref2 / q2 - rate); | |
736 | ||
737 | /* | |
738 | * Choose the best between two: less remainder we have the better. We | |
739 | * can't go case 2 if q2 is greater than 256 since SCR register can | |
740 | * hold only values 0 .. 255. | |
741 | */ | |
742 | if (r2 >= r1 || q2 > 256) { | |
743 | /* case 1 is better */ | |
744 | r = r1; | |
745 | q = q1; | |
746 | } else { | |
747 | /* case 2 is better */ | |
748 | r = r2; | |
749 | q = q2; | |
750 | mul = (1 << 24) * 2 / 5; | |
e5262d05 WC |
751 | } |
752 | ||
9df461ec AS |
753 | /* Check case 3 only If the divisor is big enough */ |
754 | if (fref / rate >= 80) { | |
755 | u64 fssp; | |
756 | u32 m; | |
757 | ||
758 | /* Calculate initial quot */ | |
759 | q1 = DIV_ROUND_CLOSEST(fref, rate); | |
760 | m = (1 << 24) / q1; | |
761 | ||
762 | /* Get the remainder */ | |
763 | fssp = (u64)fref * m; | |
764 | do_div(fssp, 1 << 24); | |
765 | r1 = abs(fssp - rate); | |
766 | ||
767 | /* Choose this one if it suits better */ | |
768 | if (r1 < r) { | |
769 | /* case 3 is better */ | |
770 | q = 1; | |
771 | mul = m; | |
772 | } | |
773 | } | |
e5262d05 | 774 | |
9df461ec AS |
775 | *dds = mul; |
776 | return q - 1; | |
e5262d05 WC |
777 | } |
778 | ||
3343b7a6 | 779 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 780 | { |
3343b7a6 MW |
781 | unsigned long ssp_clk = drv_data->max_clk_rate; |
782 | const struct ssp_device *ssp = drv_data->ssp; | |
783 | ||
784 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 785 | |
2a8626a9 | 786 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
025ffe88 | 787 | return (ssp_clk / (2 * rate) - 1) & 0xff; |
2f1a74e5 | 788 | else |
025ffe88 | 789 | return (ssp_clk / rate - 1) & 0xfff; |
2f1a74e5 | 790 | } |
791 | ||
e5262d05 WC |
792 | static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, |
793 | struct chip_data *chip, int rate) | |
794 | { | |
025ffe88 | 795 | unsigned int clk_div; |
e5262d05 WC |
796 | |
797 | switch (drv_data->ssp_type) { | |
798 | case QUARK_X1000_SSP: | |
9df461ec | 799 | clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); |
eecacf73 | 800 | break; |
e5262d05 | 801 | default: |
025ffe88 | 802 | clk_div = ssp_get_clk_div(drv_data, rate); |
eecacf73 | 803 | break; |
e5262d05 | 804 | } |
025ffe88 | 805 | return clk_div << 8; |
e5262d05 WC |
806 | } |
807 | ||
e0c9905e SS |
808 | static void pump_transfers(unsigned long data) |
809 | { | |
810 | struct driver_data *drv_data = (struct driver_data *)data; | |
811 | struct spi_message *message = NULL; | |
812 | struct spi_transfer *transfer = NULL; | |
813 | struct spi_transfer *previous = NULL; | |
814 | struct chip_data *chip = NULL; | |
9708c121 SS |
815 | u32 clk_div = 0; |
816 | u8 bits = 0; | |
817 | u32 speed = 0; | |
818 | u32 cr0; | |
8d94cc50 SS |
819 | u32 cr1; |
820 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
821 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
4fdb2424 | 822 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); |
e0c9905e SS |
823 | |
824 | /* Get current state information */ | |
825 | message = drv_data->cur_msg; | |
826 | transfer = drv_data->cur_transfer; | |
827 | chip = drv_data->cur_chip; | |
828 | ||
829 | /* Handle for abort */ | |
830 | if (message->state == ERROR_STATE) { | |
831 | message->status = -EIO; | |
5daa3ba0 | 832 | giveback(drv_data); |
e0c9905e SS |
833 | return; |
834 | } | |
835 | ||
836 | /* Handle end of message */ | |
837 | if (message->state == DONE_STATE) { | |
838 | message->status = 0; | |
5daa3ba0 | 839 | giveback(drv_data); |
e0c9905e SS |
840 | return; |
841 | } | |
842 | ||
8423597d | 843 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
844 | if (message->state == RUNNING_STATE) { |
845 | previous = list_entry(transfer->transfer_list.prev, | |
846 | struct spi_transfer, | |
847 | transfer_list); | |
848 | if (previous->delay_usecs) | |
849 | udelay(previous->delay_usecs); | |
8423597d NF |
850 | |
851 | /* Drop chip select only if cs_change is requested */ | |
852 | if (previous->cs_change) | |
a7bb3909 | 853 | cs_deassert(drv_data); |
e0c9905e SS |
854 | } |
855 | ||
cd7bed00 MW |
856 | /* Check if we can DMA this transfer */ |
857 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
858 | |
859 | /* reject already-mapped transfers; PIO won't always work */ | |
860 | if (message->is_dma_mapped | |
861 | || transfer->rx_dma || transfer->tx_dma) { | |
862 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
863 | "pump_transfers: mapped transfer length of " |
864 | "%u is greater than %d\n", | |
7e964455 NF |
865 | transfer->len, MAX_DMA_LEN); |
866 | message->status = -EINVAL; | |
867 | giveback(drv_data); | |
868 | return; | |
869 | } | |
870 | ||
871 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
872 | dev_warn_ratelimited(&message->spi->dev, |
873 | "pump_transfers: DMA disabled for transfer length %ld " | |
874 | "greater than %d\n", | |
875 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
876 | } |
877 | ||
e0c9905e | 878 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 879 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
880 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
881 | message->status = -EIO; | |
5daa3ba0 | 882 | giveback(drv_data); |
e0c9905e SS |
883 | return; |
884 | } | |
9708c121 | 885 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
886 | drv_data->tx = (void *)transfer->tx_buf; |
887 | drv_data->tx_end = drv_data->tx + transfer->len; | |
888 | drv_data->rx = transfer->rx_buf; | |
889 | drv_data->rx_end = drv_data->rx + transfer->len; | |
890 | drv_data->rx_dma = transfer->rx_dma; | |
891 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 892 | drv_data->len = transfer->len; |
e0c9905e SS |
893 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
894 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
895 | |
896 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 897 | cr0 = chip->cr0; |
9708c121 SS |
898 | if (transfer->speed_hz || transfer->bits_per_word) { |
899 | ||
9708c121 SS |
900 | bits = chip->bits_per_word; |
901 | speed = chip->speed_hz; | |
902 | ||
903 | if (transfer->speed_hz) | |
904 | speed = transfer->speed_hz; | |
905 | ||
906 | if (transfer->bits_per_word) | |
907 | bits = transfer->bits_per_word; | |
908 | ||
e5262d05 | 909 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed); |
9708c121 SS |
910 | |
911 | if (bits <= 8) { | |
912 | drv_data->n_bytes = 1; | |
9708c121 SS |
913 | drv_data->read = drv_data->read != null_reader ? |
914 | u8_reader : null_reader; | |
915 | drv_data->write = drv_data->write != null_writer ? | |
916 | u8_writer : null_writer; | |
917 | } else if (bits <= 16) { | |
918 | drv_data->n_bytes = 2; | |
9708c121 SS |
919 | drv_data->read = drv_data->read != null_reader ? |
920 | u16_reader : null_reader; | |
921 | drv_data->write = drv_data->write != null_writer ? | |
922 | u16_writer : null_writer; | |
923 | } else if (bits <= 32) { | |
924 | drv_data->n_bytes = 4; | |
9708c121 SS |
925 | drv_data->read = drv_data->read != null_reader ? |
926 | u32_reader : null_reader; | |
927 | drv_data->write = drv_data->write != null_writer ? | |
928 | u32_writer : null_writer; | |
929 | } | |
8d94cc50 SS |
930 | /* if bits/word is changed in dma mode, then must check the |
931 | * thresholds and burst also */ | |
932 | if (chip->enable_dma) { | |
cd7bed00 MW |
933 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
934 | message->spi, | |
8d94cc50 SS |
935 | bits, &dma_burst, |
936 | &dma_thresh)) | |
f6bd03a7 JN |
937 | dev_warn_ratelimited(&message->spi->dev, |
938 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 | 939 | } |
9708c121 | 940 | |
4fdb2424 | 941 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); |
9708c121 SS |
942 | } |
943 | ||
e0c9905e SS |
944 | message->state = RUNNING_STATE; |
945 | ||
7e964455 | 946 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
947 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
948 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 949 | if (drv_data->dma_mapped) { |
e0c9905e SS |
950 | |
951 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
952 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
953 | ||
954 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 955 | |
8d94cc50 SS |
956 | /* Clear status and start DMA engine */ |
957 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
c039dd27 | 958 | pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); |
cd7bed00 MW |
959 | |
960 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
961 | } else { |
962 | /* Ensure we have the correct interrupt handler */ | |
963 | drv_data->transfer_handler = interrupt_transfer; | |
964 | ||
8d94cc50 SS |
965 | /* Clear status */ |
966 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 967 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
968 | } |
969 | ||
a0d2642e | 970 | if (is_lpss_ssp(drv_data)) { |
c039dd27 JN |
971 | if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) |
972 | != chip->lpss_rx_threshold) | |
973 | pxa2xx_spi_write(drv_data, SSIRF, | |
974 | chip->lpss_rx_threshold); | |
975 | if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) | |
976 | != chip->lpss_tx_threshold) | |
977 | pxa2xx_spi_write(drv_data, SSITF, | |
978 | chip->lpss_tx_threshold); | |
a0d2642e MW |
979 | } |
980 | ||
e5262d05 | 981 | if (is_quark_x1000_ssp(drv_data) && |
c039dd27 JN |
982 | (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) |
983 | pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); | |
e5262d05 | 984 | |
8d94cc50 | 985 | /* see if we need to reload the config registers */ |
c039dd27 JN |
986 | if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) |
987 | || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) | |
988 | != (cr1 & change_mask)) { | |
b97c74bd | 989 | /* stop the SSP, and update the other bits */ |
c039dd27 | 990 | pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); |
2a8626a9 | 991 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 992 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
b97c74bd | 993 | /* first set CR1 without interrupt and service enables */ |
c039dd27 | 994 | pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); |
b97c74bd | 995 | /* restart the SSP */ |
c039dd27 | 996 | pxa2xx_spi_write(drv_data, SSCR0, cr0); |
b97c74bd | 997 | |
8d94cc50 | 998 | } else { |
2a8626a9 | 999 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1000 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
e0c9905e | 1001 | } |
b97c74bd | 1002 | |
a7bb3909 | 1003 | cs_assert(drv_data); |
b97c74bd NF |
1004 | |
1005 | /* after chip select, release the data by enabling service | |
1006 | * requests and interrupts, without changing any mode bits */ | |
c039dd27 | 1007 | pxa2xx_spi_write(drv_data, SSCR1, cr1); |
e0c9905e SS |
1008 | } |
1009 | ||
7f86bde9 MW |
1010 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
1011 | struct spi_message *msg) | |
e0c9905e | 1012 | { |
7f86bde9 | 1013 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 1014 | |
7f86bde9 | 1015 | drv_data->cur_msg = msg; |
e0c9905e SS |
1016 | /* Initial message state*/ |
1017 | drv_data->cur_msg->state = START_STATE; | |
1018 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1019 | struct spi_transfer, | |
1020 | transfer_list); | |
1021 | ||
8d94cc50 SS |
1022 | /* prepare to setup the SSP, in pump_transfers, using the per |
1023 | * chip configuration */ | |
e0c9905e | 1024 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1025 | |
1026 | /* Mark as busy and launch transfers */ | |
1027 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
1028 | return 0; |
1029 | } | |
1030 | ||
7d94a505 MW |
1031 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
1032 | { | |
1033 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1034 | ||
1035 | /* Disable the SSP now */ | |
c039dd27 JN |
1036 | pxa2xx_spi_write(drv_data, SSCR0, |
1037 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
7d94a505 | 1038 | |
7d94a505 MW |
1039 | return 0; |
1040 | } | |
1041 | ||
a7bb3909 EM |
1042 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1043 | struct pxa2xx_spi_chip *chip_info) | |
1044 | { | |
1045 | int err = 0; | |
1046 | ||
1047 | if (chip == NULL || chip_info == NULL) | |
1048 | return 0; | |
1049 | ||
1050 | /* NOTE: setup() can be called multiple times, possibly with | |
1051 | * different chip_info, release previously requested GPIO | |
1052 | */ | |
1053 | if (gpio_is_valid(chip->gpio_cs)) | |
1054 | gpio_free(chip->gpio_cs); | |
1055 | ||
1056 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1057 | if (chip_info->cs_control) { | |
1058 | chip->cs_control = chip_info->cs_control; | |
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1063 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1064 | if (err) { | |
f6bd03a7 JN |
1065 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
1066 | chip_info->gpio_cs); | |
a7bb3909 EM |
1067 | return err; |
1068 | } | |
1069 | ||
1070 | chip->gpio_cs = chip_info->gpio_cs; | |
1071 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1072 | ||
1073 | err = gpio_direction_output(chip->gpio_cs, | |
1074 | !chip->gpio_cs_inverted); | |
1075 | } | |
1076 | ||
1077 | return err; | |
1078 | } | |
1079 | ||
e0c9905e SS |
1080 | static int setup(struct spi_device *spi) |
1081 | { | |
1082 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1083 | struct chip_data *chip; | |
1084 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1085 | unsigned int clk_div; | |
a0d2642e MW |
1086 | uint tx_thres, tx_hi_thres, rx_thres; |
1087 | ||
e5262d05 WC |
1088 | switch (drv_data->ssp_type) { |
1089 | case QUARK_X1000_SSP: | |
1090 | tx_thres = TX_THRESH_QUARK_X1000_DFLT; | |
1091 | tx_hi_thres = 0; | |
1092 | rx_thres = RX_THRESH_QUARK_X1000_DFLT; | |
1093 | break; | |
03fbf488 JN |
1094 | case LPSS_LPT_SSP: |
1095 | case LPSS_BYT_SSP: | |
a0d2642e MW |
1096 | tx_thres = LPSS_TX_LOTHRESH_DFLT; |
1097 | tx_hi_thres = LPSS_TX_HITHRESH_DFLT; | |
1098 | rx_thres = LPSS_RX_THRESH_DFLT; | |
e5262d05 WC |
1099 | break; |
1100 | default: | |
a0d2642e MW |
1101 | tx_thres = TX_THRESH_DFLT; |
1102 | tx_hi_thres = 0; | |
1103 | rx_thres = RX_THRESH_DFLT; | |
e5262d05 | 1104 | break; |
a0d2642e | 1105 | } |
e0c9905e | 1106 | |
8d94cc50 | 1107 | /* Only alloc on first setup */ |
e0c9905e | 1108 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1109 | if (!chip) { |
e0c9905e | 1110 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 1111 | if (!chip) |
e0c9905e SS |
1112 | return -ENOMEM; |
1113 | ||
2a8626a9 SAS |
1114 | if (drv_data->ssp_type == CE4100_SSP) { |
1115 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
1116 | dev_err(&spi->dev, |
1117 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
1118 | kfree(chip); |
1119 | return -EINVAL; | |
1120 | } | |
1121 | ||
1122 | chip->frm = spi->chip_select; | |
1123 | } else | |
1124 | chip->gpio_cs = -1; | |
e0c9905e | 1125 | chip->enable_dma = 0; |
f1f640a9 | 1126 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1127 | } |
1128 | ||
8d94cc50 SS |
1129 | /* protocol drivers may change the chip settings, so... |
1130 | * if chip_info exists, use it */ | |
1131 | chip_info = spi->controller_data; | |
1132 | ||
e0c9905e | 1133 | /* chip_info isn't always needed */ |
8d94cc50 | 1134 | chip->cr1 = 0; |
e0c9905e | 1135 | if (chip_info) { |
f1f640a9 VS |
1136 | if (chip_info->timeout) |
1137 | chip->timeout = chip_info->timeout; | |
1138 | if (chip_info->tx_threshold) | |
1139 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
1140 | if (chip_info->tx_hi_threshold) |
1141 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
1142 | if (chip_info->rx_threshold) |
1143 | rx_thres = chip_info->rx_threshold; | |
1144 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 1145 | chip->dma_threshold = 0; |
e0c9905e SS |
1146 | if (chip_info->enable_loopback) |
1147 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
1148 | } else if (ACPI_HANDLE(&spi->dev)) { |
1149 | /* | |
1150 | * Slave devices enumerated from ACPI namespace don't | |
1151 | * usually have chip_info but we still might want to use | |
1152 | * DMA with them. | |
1153 | */ | |
1154 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
1155 | } |
1156 | ||
a0d2642e MW |
1157 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
1158 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
1159 | | SSITF_TxHiThresh(tx_hi_thres); | |
1160 | ||
8d94cc50 SS |
1161 | /* set dma burst and threshold outside of chip_info path so that if |
1162 | * chip_info goes away after setting chip->enable_dma, the | |
1163 | * burst and threshold can still respond to changes in bits_per_word */ | |
1164 | if (chip->enable_dma) { | |
1165 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
1166 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1167 | spi->bits_per_word, | |
8d94cc50 SS |
1168 | &chip->dma_burst_size, |
1169 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1170 | dev_warn(&spi->dev, |
1171 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
1172 | } |
1173 | } | |
1174 | ||
e5262d05 | 1175 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz); |
9708c121 | 1176 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e | 1177 | |
4fdb2424 WC |
1178 | chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, |
1179 | spi->bits_per_word); | |
e5262d05 WC |
1180 | switch (drv_data->ssp_type) { |
1181 | case QUARK_X1000_SSP: | |
1182 | chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) | |
1183 | & QUARK_X1000_SSCR1_RFT) | |
1184 | | (QUARK_X1000_SSCR1_TxTresh(tx_thres) | |
1185 | & QUARK_X1000_SSCR1_TFT); | |
1186 | break; | |
1187 | default: | |
1188 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | |
1189 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1190 | break; | |
1191 | } | |
1192 | ||
7f6ee1ad JC |
1193 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1194 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1195 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 1196 | |
b833172f MW |
1197 | if (spi->mode & SPI_LOOP) |
1198 | chip->cr1 |= SSCR1_LBM; | |
1199 | ||
e0c9905e | 1200 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
2a8626a9 | 1201 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 1202 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 1203 | drv_data->max_clk_rate |
c9840daa EM |
1204 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
1205 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 1206 | else |
7d077197 | 1207 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 1208 | drv_data->max_clk_rate / 2 |
c9840daa EM |
1209 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
1210 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
1211 | |
1212 | if (spi->bits_per_word <= 8) { | |
1213 | chip->n_bytes = 1; | |
e0c9905e SS |
1214 | chip->read = u8_reader; |
1215 | chip->write = u8_writer; | |
1216 | } else if (spi->bits_per_word <= 16) { | |
1217 | chip->n_bytes = 2; | |
e0c9905e SS |
1218 | chip->read = u16_reader; |
1219 | chip->write = u16_writer; | |
1220 | } else if (spi->bits_per_word <= 32) { | |
e5262d05 WC |
1221 | if (!is_quark_x1000_ssp(drv_data)) |
1222 | chip->cr0 |= SSCR0_EDSS; | |
e0c9905e | 1223 | chip->n_bytes = 4; |
e0c9905e SS |
1224 | chip->read = u32_reader; |
1225 | chip->write = u32_writer; | |
e0c9905e | 1226 | } |
9708c121 | 1227 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1228 | |
1229 | spi_set_ctldata(spi, chip); | |
1230 | ||
2a8626a9 SAS |
1231 | if (drv_data->ssp_type == CE4100_SSP) |
1232 | return 0; | |
1233 | ||
a7bb3909 | 1234 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1235 | } |
1236 | ||
0ffa0285 | 1237 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1238 | { |
0ffa0285 | 1239 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1240 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1241 | |
7348d82a DR |
1242 | if (!chip) |
1243 | return; | |
1244 | ||
2a8626a9 | 1245 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1246 | gpio_free(chip->gpio_cs); |
1247 | ||
e0c9905e SS |
1248 | kfree(chip); |
1249 | } | |
1250 | ||
a3496855 | 1251 | #ifdef CONFIG_ACPI |
03fbf488 JN |
1252 | |
1253 | static struct acpi_device_id pxa2xx_spi_acpi_match[] = { | |
1254 | { "INT33C0", LPSS_LPT_SSP }, | |
1255 | { "INT33C1", LPSS_LPT_SSP }, | |
1256 | { "INT3430", LPSS_LPT_SSP }, | |
1257 | { "INT3431", LPSS_LPT_SSP }, | |
1258 | { "80860F0E", LPSS_BYT_SSP }, | |
1259 | { "8086228E", LPSS_BYT_SSP }, | |
1260 | { }, | |
1261 | }; | |
1262 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1263 | ||
a3496855 MW |
1264 | static struct pxa2xx_spi_master * |
1265 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1266 | { | |
1267 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1268 | struct acpi_device *adev; |
1269 | struct ssp_device *ssp; | |
1270 | struct resource *res; | |
03fbf488 JN |
1271 | const struct acpi_device_id *id; |
1272 | int devid, type; | |
a3496855 MW |
1273 | |
1274 | if (!ACPI_HANDLE(&pdev->dev) || | |
1275 | acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
1276 | return NULL; | |
1277 | ||
03fbf488 JN |
1278 | id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev); |
1279 | if (id) | |
1280 | type = (int)id->driver_data; | |
1281 | else | |
1282 | return NULL; | |
1283 | ||
cc0ee987 | 1284 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1285 | if (!pdata) |
a3496855 | 1286 | return NULL; |
a3496855 MW |
1287 | |
1288 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1289 | if (!res) | |
1290 | return NULL; | |
1291 | ||
1292 | ssp = &pdata->ssp; | |
1293 | ||
1294 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1295 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1296 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1297 | return NULL; |
a3496855 MW |
1298 | |
1299 | ssp->clk = devm_clk_get(&pdev->dev, NULL); | |
1300 | ssp->irq = platform_get_irq(pdev, 0); | |
03fbf488 | 1301 | ssp->type = type; |
a3496855 MW |
1302 | ssp->pdev = pdev; |
1303 | ||
1304 | ssp->port_id = -1; | |
1305 | if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid)) | |
1306 | ssp->port_id = devid; | |
1307 | ||
1308 | pdata->num_chipselect = 1; | |
cddb339b | 1309 | pdata->enable_dma = true; |
a3496855 MW |
1310 | |
1311 | return pdata; | |
1312 | } | |
1313 | ||
a3496855 MW |
1314 | #else |
1315 | static inline struct pxa2xx_spi_master * | |
1316 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1317 | { | |
1318 | return NULL; | |
1319 | } | |
1320 | #endif | |
1321 | ||
fd4a319b | 1322 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1323 | { |
1324 | struct device *dev = &pdev->dev; | |
1325 | struct pxa2xx_spi_master *platform_info; | |
1326 | struct spi_master *master; | |
65a00a20 | 1327 | struct driver_data *drv_data; |
2f1a74e5 | 1328 | struct ssp_device *ssp; |
65a00a20 | 1329 | int status; |
c039dd27 | 1330 | u32 tmp; |
e0c9905e | 1331 | |
851bacf5 MW |
1332 | platform_info = dev_get_platdata(dev); |
1333 | if (!platform_info) { | |
a3496855 MW |
1334 | platform_info = pxa2xx_spi_acpi_get_pdata(pdev); |
1335 | if (!platform_info) { | |
1336 | dev_err(&pdev->dev, "missing platform data\n"); | |
1337 | return -ENODEV; | |
1338 | } | |
851bacf5 | 1339 | } |
e0c9905e | 1340 | |
baffe169 | 1341 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1342 | if (!ssp) |
1343 | ssp = &platform_info->ssp; | |
1344 | ||
1345 | if (!ssp->mmio_base) { | |
1346 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1347 | return -ENODEV; |
1348 | } | |
1349 | ||
1350 | /* Allocate master with space for drv_data and null dma buffer */ | |
1351 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1352 | if (!master) { | |
65a00a20 | 1353 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1354 | pxa_ssp_free(ssp); |
e0c9905e SS |
1355 | return -ENOMEM; |
1356 | } | |
1357 | drv_data = spi_master_get_devdata(master); | |
1358 | drv_data->master = master; | |
1359 | drv_data->master_info = platform_info; | |
1360 | drv_data->pdev = pdev; | |
2f1a74e5 | 1361 | drv_data->ssp = ssp; |
e0c9905e | 1362 | |
21486af0 | 1363 | master->dev.parent = &pdev->dev; |
21486af0 | 1364 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1365 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1366 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1367 | |
851bacf5 | 1368 | master->bus_num = ssp->port_id; |
e0c9905e | 1369 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 1370 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1371 | master->cleanup = cleanup; |
1372 | master->setup = setup; | |
7f86bde9 | 1373 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1374 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
7dd62787 | 1375 | master->auto_runtime_pm = true; |
e0c9905e | 1376 | |
2f1a74e5 | 1377 | drv_data->ssp_type = ssp->type; |
2b9b84f4 | 1378 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
e0c9905e | 1379 | |
2f1a74e5 | 1380 | drv_data->ioaddr = ssp->mmio_base; |
1381 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1382 | if (pxa25x_ssp_comp(drv_data)) { |
e5262d05 WC |
1383 | switch (drv_data->ssp_type) { |
1384 | case QUARK_X1000_SSP: | |
1385 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
1386 | break; | |
1387 | default: | |
1388 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
1389 | break; | |
1390 | } | |
1391 | ||
e0c9905e SS |
1392 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1393 | drv_data->dma_cr1 = 0; | |
1394 | drv_data->clear_sr = SSSR_ROR; | |
1395 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1396 | } else { | |
24778be2 | 1397 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1398 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1399 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1400 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1401 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1402 | } | |
1403 | ||
49cbb1e0 SAS |
1404 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1405 | drv_data); | |
e0c9905e | 1406 | if (status < 0) { |
65a00a20 | 1407 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1408 | goto out_error_master_alloc; |
1409 | } | |
1410 | ||
1411 | /* Setup DMA if requested */ | |
1412 | drv_data->tx_channel = -1; | |
1413 | drv_data->rx_channel = -1; | |
1414 | if (platform_info->enable_dma) { | |
cd7bed00 MW |
1415 | status = pxa2xx_spi_dma_setup(drv_data); |
1416 | if (status) { | |
cddb339b | 1417 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1418 | platform_info->enable_dma = false; |
e0c9905e | 1419 | } |
e0c9905e SS |
1420 | } |
1421 | ||
1422 | /* Enable SOC clock */ | |
3343b7a6 MW |
1423 | clk_prepare_enable(ssp->clk); |
1424 | ||
1425 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | |
e0c9905e SS |
1426 | |
1427 | /* Load default SSP configuration */ | |
c039dd27 | 1428 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
e5262d05 WC |
1429 | switch (drv_data->ssp_type) { |
1430 | case QUARK_X1000_SSP: | |
c039dd27 JN |
1431 | tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1432 | | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); | |
1433 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
e5262d05 WC |
1434 | |
1435 | /* using the Motorola SPI protocol and use 8 bit frame */ | |
c039dd27 JN |
1436 | pxa2xx_spi_write(drv_data, SSCR0, |
1437 | QUARK_X1000_SSCR0_Motorola | |
1438 | | QUARK_X1000_SSCR0_DataSize(8)); | |
e5262d05 WC |
1439 | break; |
1440 | default: | |
c039dd27 JN |
1441 | tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | |
1442 | SSCR1_TxTresh(TX_THRESH_DFLT); | |
1443 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
1444 | tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); | |
1445 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
e5262d05 WC |
1446 | break; |
1447 | } | |
1448 | ||
2a8626a9 | 1449 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1450 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e5262d05 WC |
1451 | |
1452 | if (!is_quark_x1000_ssp(drv_data)) | |
c039dd27 | 1453 | pxa2xx_spi_write(drv_data, SSPSP, 0); |
e0c9905e | 1454 | |
7566bcc7 JN |
1455 | if (is_lpss_ssp(drv_data)) |
1456 | lpss_ssp_setup(drv_data); | |
a0d2642e | 1457 | |
7f86bde9 MW |
1458 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1459 | (unsigned long)drv_data); | |
e0c9905e | 1460 | |
836d1a22 AO |
1461 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1462 | pm_runtime_use_autosuspend(&pdev->dev); | |
1463 | pm_runtime_set_active(&pdev->dev); | |
1464 | pm_runtime_enable(&pdev->dev); | |
1465 | ||
e0c9905e SS |
1466 | /* Register with the SPI framework */ |
1467 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1468 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1469 | if (status != 0) { |
1470 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1471 | goto out_error_clock_enabled; |
e0c9905e SS |
1472 | } |
1473 | ||
1474 | return status; | |
1475 | ||
e0c9905e | 1476 | out_error_clock_enabled: |
3343b7a6 | 1477 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1478 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1479 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1480 | |
1481 | out_error_master_alloc: | |
1482 | spi_master_put(master); | |
baffe169 | 1483 | pxa_ssp_free(ssp); |
e0c9905e SS |
1484 | return status; |
1485 | } | |
1486 | ||
1487 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1488 | { | |
1489 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1490 | struct ssp_device *ssp; |
e0c9905e SS |
1491 | |
1492 | if (!drv_data) | |
1493 | return 0; | |
51e911e2 | 1494 | ssp = drv_data->ssp; |
e0c9905e | 1495 | |
7d94a505 MW |
1496 | pm_runtime_get_sync(&pdev->dev); |
1497 | ||
e0c9905e | 1498 | /* Disable the SSP at the peripheral and SOC level */ |
c039dd27 | 1499 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
3343b7a6 | 1500 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1501 | |
1502 | /* Release DMA */ | |
cd7bed00 MW |
1503 | if (drv_data->master_info->enable_dma) |
1504 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1505 | |
7d94a505 MW |
1506 | pm_runtime_put_noidle(&pdev->dev); |
1507 | pm_runtime_disable(&pdev->dev); | |
1508 | ||
e0c9905e | 1509 | /* Release IRQ */ |
2f1a74e5 | 1510 | free_irq(ssp->irq, drv_data); |
1511 | ||
1512 | /* Release SSP */ | |
baffe169 | 1513 | pxa_ssp_free(ssp); |
e0c9905e | 1514 | |
e0c9905e SS |
1515 | return 0; |
1516 | } | |
1517 | ||
1518 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1519 | { | |
1520 | int status = 0; | |
1521 | ||
1522 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1523 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1524 | } | |
1525 | ||
382cebb0 | 1526 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1527 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1528 | { |
86d2593a | 1529 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1530 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1531 | int status = 0; |
1532 | ||
7f86bde9 | 1533 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1534 | if (status != 0) |
1535 | return status; | |
c039dd27 | 1536 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
2b9375b9 DES |
1537 | |
1538 | if (!pm_runtime_suspended(dev)) | |
1539 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1540 | |
1541 | return 0; | |
1542 | } | |
1543 | ||
86d2593a | 1544 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1545 | { |
86d2593a | 1546 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1547 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1548 | int status = 0; |
1549 | ||
cd7bed00 | 1550 | pxa2xx_spi_dma_resume(drv_data); |
148da331 | 1551 | |
e0c9905e | 1552 | /* Enable the SSP clock */ |
2b9375b9 DES |
1553 | if (!pm_runtime_suspended(dev)) |
1554 | clk_prepare_enable(ssp->clk); | |
e0c9905e | 1555 | |
c50325f7 | 1556 | /* Restore LPSS private register bits */ |
48421adf JN |
1557 | if (is_lpss_ssp(drv_data)) |
1558 | lpss_ssp_setup(drv_data); | |
c50325f7 | 1559 | |
e0c9905e | 1560 | /* Start the queue running */ |
7f86bde9 | 1561 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1562 | if (status != 0) { |
86d2593a | 1563 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1564 | return status; |
1565 | } | |
1566 | ||
1567 | return 0; | |
1568 | } | |
7d94a505 MW |
1569 | #endif |
1570 | ||
ec833050 | 1571 | #ifdef CONFIG_PM |
7d94a505 MW |
1572 | static int pxa2xx_spi_runtime_suspend(struct device *dev) |
1573 | { | |
1574 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1575 | ||
1576 | clk_disable_unprepare(drv_data->ssp->clk); | |
1577 | return 0; | |
1578 | } | |
1579 | ||
1580 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1581 | { | |
1582 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1583 | ||
1584 | clk_prepare_enable(drv_data->ssp->clk); | |
1585 | return 0; | |
1586 | } | |
1587 | #endif | |
86d2593a | 1588 | |
47145210 | 1589 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1590 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1591 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1592 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1593 | }; |
e0c9905e SS |
1594 | |
1595 | static struct platform_driver driver = { | |
1596 | .driver = { | |
86d2593a | 1597 | .name = "pxa2xx-spi", |
86d2593a | 1598 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1599 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1600 | }, |
fbd29a14 | 1601 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1602 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1603 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1604 | }; |
1605 | ||
1606 | static int __init pxa2xx_spi_init(void) | |
1607 | { | |
fbd29a14 | 1608 | return platform_driver_register(&driver); |
e0c9905e | 1609 | } |
5b61a749 | 1610 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1611 | |
1612 | static void __exit pxa2xx_spi_exit(void) | |
1613 | { | |
1614 | platform_driver_unregister(&driver); | |
1615 | } | |
1616 | module_exit(pxa2xx_spi_exit); |