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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/platform_device.h> | |
8348c259 | 26 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e SS |
27 | #include <linux/dma-mapping.h> |
28 | #include <linux/spi/spi.h> | |
29 | #include <linux/workqueue.h> | |
e0c9905e | 30 | #include <linux/delay.h> |
a7bb3909 | 31 | #include <linux/gpio.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e0c9905e SS |
33 | |
34 | #include <asm/io.h> | |
35 | #include <asm/irq.h> | |
e0c9905e | 36 | #include <asm/delay.h> |
e0c9905e | 37 | |
e0c9905e SS |
38 | |
39 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 40 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 41 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 42 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
43 | |
44 | #define MAX_BUSES 3 | |
45 | ||
f1f640a9 VS |
46 | #define TIMOUT_DFLT 1000 |
47 | ||
7e964455 NF |
48 | #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) |
49 | #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) | |
2b9b84f4 | 50 | #define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT) |
7e964455 | 51 | #define MAX_DMA_LEN 8191 |
7ad0ba91 | 52 | #define DMA_ALIGNMENT 8 |
e0c9905e | 53 | |
b97c74bd NF |
54 | /* |
55 | * for testing SSCR1 changes that require SSP restart, basically | |
56 | * everything except the service and interrupt enables, the pxa270 developer | |
57 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
58 | * list, but the PXA255 dev man says all bits without really meaning the | |
59 | * service and interrupt enables | |
60 | */ | |
61 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 62 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
63 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
64 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
65 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
66 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 67 | |
e0c9905e | 68 | #define DEFINE_SSP_REG(reg, off) \ |
cf43369d DB |
69 | static inline u32 read_##reg(void const __iomem *p) \ |
70 | { return __raw_readl(p + (off)); } \ | |
71 | \ | |
72 | static inline void write_##reg(u32 v, void __iomem *p) \ | |
73 | { __raw_writel(v, p + (off)); } | |
e0c9905e SS |
74 | |
75 | DEFINE_SSP_REG(SSCR0, 0x00) | |
76 | DEFINE_SSP_REG(SSCR1, 0x04) | |
77 | DEFINE_SSP_REG(SSSR, 0x08) | |
78 | DEFINE_SSP_REG(SSITR, 0x0c) | |
79 | DEFINE_SSP_REG(SSDR, 0x10) | |
80 | DEFINE_SSP_REG(SSTO, 0x28) | |
81 | DEFINE_SSP_REG(SSPSP, 0x2c) | |
82 | ||
83 | #define START_STATE ((void*)0) | |
84 | #define RUNNING_STATE ((void*)1) | |
85 | #define DONE_STATE ((void*)2) | |
86 | #define ERROR_STATE ((void*)-1) | |
87 | ||
e0c9905e SS |
88 | struct driver_data { |
89 | /* Driver model hookup */ | |
90 | struct platform_device *pdev; | |
91 | ||
2f1a74e5 | 92 | /* SSP Info */ |
93 | struct ssp_device *ssp; | |
94 | ||
e0c9905e SS |
95 | /* SPI framework hookup */ |
96 | enum pxa_ssp_type ssp_type; | |
97 | struct spi_master *master; | |
98 | ||
99 | /* PXA hookup */ | |
100 | struct pxa2xx_spi_master *master_info; | |
101 | ||
102 | /* DMA setup stuff */ | |
103 | int rx_channel; | |
104 | int tx_channel; | |
105 | u32 *null_dma_buf; | |
106 | ||
107 | /* SSP register addresses */ | |
cf43369d | 108 | void __iomem *ioaddr; |
e0c9905e SS |
109 | u32 ssdr_physical; |
110 | ||
111 | /* SSP masks*/ | |
112 | u32 dma_cr1; | |
113 | u32 int_cr1; | |
114 | u32 clear_sr; | |
115 | u32 mask_sr; | |
116 | ||
e0c9905e SS |
117 | /* Message Transfer pump */ |
118 | struct tasklet_struct pump_transfers; | |
119 | ||
120 | /* Current message transfer state info */ | |
121 | struct spi_message* cur_msg; | |
122 | struct spi_transfer* cur_transfer; | |
123 | struct chip_data *cur_chip; | |
124 | size_t len; | |
125 | void *tx; | |
126 | void *tx_end; | |
127 | void *rx; | |
128 | void *rx_end; | |
129 | int dma_mapped; | |
130 | dma_addr_t rx_dma; | |
131 | dma_addr_t tx_dma; | |
132 | size_t rx_map_len; | |
133 | size_t tx_map_len; | |
9708c121 SS |
134 | u8 n_bytes; |
135 | u32 dma_width; | |
8d94cc50 SS |
136 | int (*write)(struct driver_data *drv_data); |
137 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
138 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); |
139 | void (*cs_control)(u32 command); | |
140 | }; | |
141 | ||
142 | struct chip_data { | |
143 | u32 cr0; | |
144 | u32 cr1; | |
e0c9905e SS |
145 | u32 psp; |
146 | u32 timeout; | |
147 | u8 n_bytes; | |
148 | u32 dma_width; | |
149 | u32 dma_burst_size; | |
150 | u32 threshold; | |
151 | u32 dma_threshold; | |
152 | u8 enable_dma; | |
9708c121 SS |
153 | u8 bits_per_word; |
154 | u32 speed_hz; | |
2a8626a9 SAS |
155 | union { |
156 | int gpio_cs; | |
157 | unsigned int frm; | |
158 | }; | |
a7bb3909 | 159 | int gpio_cs_inverted; |
8d94cc50 SS |
160 | int (*write)(struct driver_data *drv_data); |
161 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
162 | void (*cs_control)(u32 command); |
163 | }; | |
164 | ||
a7bb3909 EM |
165 | static void cs_assert(struct driver_data *drv_data) |
166 | { | |
167 | struct chip_data *chip = drv_data->cur_chip; | |
168 | ||
2a8626a9 SAS |
169 | if (drv_data->ssp_type == CE4100_SSP) { |
170 | write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); | |
171 | return; | |
172 | } | |
173 | ||
a7bb3909 EM |
174 | if (chip->cs_control) { |
175 | chip->cs_control(PXA2XX_CS_ASSERT); | |
176 | return; | |
177 | } | |
178 | ||
179 | if (gpio_is_valid(chip->gpio_cs)) | |
180 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); | |
181 | } | |
182 | ||
183 | static void cs_deassert(struct driver_data *drv_data) | |
184 | { | |
185 | struct chip_data *chip = drv_data->cur_chip; | |
186 | ||
2a8626a9 SAS |
187 | if (drv_data->ssp_type == CE4100_SSP) |
188 | return; | |
189 | ||
a7bb3909 | 190 | if (chip->cs_control) { |
2b2562d3 | 191 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
192 | return; |
193 | } | |
194 | ||
195 | if (gpio_is_valid(chip->gpio_cs)) | |
196 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); | |
197 | } | |
198 | ||
2a8626a9 SAS |
199 | static void write_SSSR_CS(struct driver_data *drv_data, u32 val) |
200 | { | |
201 | void __iomem *reg = drv_data->ioaddr; | |
202 | ||
203 | if (drv_data->ssp_type == CE4100_SSP) | |
204 | val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK; | |
205 | ||
206 | write_SSSR(val, reg); | |
207 | } | |
208 | ||
209 | static int pxa25x_ssp_comp(struct driver_data *drv_data) | |
210 | { | |
211 | if (drv_data->ssp_type == PXA25x_SSP) | |
212 | return 1; | |
213 | if (drv_data->ssp_type == CE4100_SSP) | |
214 | return 1; | |
215 | return 0; | |
216 | } | |
217 | ||
e0c9905e SS |
218 | static int flush(struct driver_data *drv_data) |
219 | { | |
220 | unsigned long limit = loops_per_jiffy << 1; | |
221 | ||
cf43369d | 222 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
223 | |
224 | do { | |
225 | while (read_SSSR(reg) & SSSR_RNE) { | |
226 | read_SSDR(reg); | |
227 | } | |
306c68aa | 228 | } while ((read_SSSR(reg) & SSSR_BSY) && --limit); |
2a8626a9 | 229 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
230 | |
231 | return limit; | |
232 | } | |
233 | ||
8d94cc50 | 234 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 235 | { |
cf43369d | 236 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 237 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 238 | |
4a25605f | 239 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
240 | || (drv_data->tx == drv_data->tx_end)) |
241 | return 0; | |
242 | ||
243 | write_SSDR(0, reg); | |
244 | drv_data->tx += n_bytes; | |
245 | ||
246 | return 1; | |
e0c9905e SS |
247 | } |
248 | ||
8d94cc50 | 249 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 250 | { |
cf43369d | 251 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 252 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
253 | |
254 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 255 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
256 | read_SSDR(reg); |
257 | drv_data->rx += n_bytes; | |
258 | } | |
8d94cc50 SS |
259 | |
260 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
261 | } |
262 | ||
8d94cc50 | 263 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 264 | { |
cf43369d | 265 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 266 | |
4a25605f | 267 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
268 | || (drv_data->tx == drv_data->tx_end)) |
269 | return 0; | |
270 | ||
271 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
272 | ++drv_data->tx; | |
273 | ||
274 | return 1; | |
e0c9905e SS |
275 | } |
276 | ||
8d94cc50 | 277 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 278 | { |
cf43369d | 279 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
280 | |
281 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 282 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
283 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
284 | ++drv_data->rx; | |
285 | } | |
8d94cc50 SS |
286 | |
287 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
288 | } |
289 | ||
8d94cc50 | 290 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 291 | { |
cf43369d | 292 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 293 | |
4a25605f | 294 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
295 | || (drv_data->tx == drv_data->tx_end)) |
296 | return 0; | |
297 | ||
298 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
299 | drv_data->tx += 2; | |
300 | ||
301 | return 1; | |
e0c9905e SS |
302 | } |
303 | ||
8d94cc50 | 304 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 305 | { |
cf43369d | 306 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
307 | |
308 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 309 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
310 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
311 | drv_data->rx += 2; | |
312 | } | |
8d94cc50 SS |
313 | |
314 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 315 | } |
8d94cc50 SS |
316 | |
317 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 318 | { |
cf43369d | 319 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 320 | |
4a25605f | 321 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
322 | || (drv_data->tx == drv_data->tx_end)) |
323 | return 0; | |
324 | ||
325 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
326 | drv_data->tx += 4; | |
327 | ||
328 | return 1; | |
e0c9905e SS |
329 | } |
330 | ||
8d94cc50 | 331 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 332 | { |
cf43369d | 333 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
334 | |
335 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 336 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
337 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
338 | drv_data->rx += 4; | |
339 | } | |
8d94cc50 SS |
340 | |
341 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
342 | } |
343 | ||
344 | static void *next_transfer(struct driver_data *drv_data) | |
345 | { | |
346 | struct spi_message *msg = drv_data->cur_msg; | |
347 | struct spi_transfer *trans = drv_data->cur_transfer; | |
348 | ||
349 | /* Move to next transfer */ | |
350 | if (trans->transfer_list.next != &msg->transfers) { | |
351 | drv_data->cur_transfer = | |
352 | list_entry(trans->transfer_list.next, | |
353 | struct spi_transfer, | |
354 | transfer_list); | |
355 | return RUNNING_STATE; | |
356 | } else | |
357 | return DONE_STATE; | |
358 | } | |
359 | ||
360 | static int map_dma_buffers(struct driver_data *drv_data) | |
361 | { | |
362 | struct spi_message *msg = drv_data->cur_msg; | |
363 | struct device *dev = &msg->spi->dev; | |
364 | ||
365 | if (!drv_data->cur_chip->enable_dma) | |
366 | return 0; | |
367 | ||
368 | if (msg->is_dma_mapped) | |
369 | return drv_data->rx_dma && drv_data->tx_dma; | |
370 | ||
371 | if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) | |
372 | return 0; | |
373 | ||
374 | /* Modify setup if rx buffer is null */ | |
375 | if (drv_data->rx == NULL) { | |
376 | *drv_data->null_dma_buf = 0; | |
377 | drv_data->rx = drv_data->null_dma_buf; | |
378 | drv_data->rx_map_len = 4; | |
379 | } else | |
380 | drv_data->rx_map_len = drv_data->len; | |
381 | ||
382 | ||
383 | /* Modify setup if tx buffer is null */ | |
384 | if (drv_data->tx == NULL) { | |
385 | *drv_data->null_dma_buf = 0; | |
386 | drv_data->tx = drv_data->null_dma_buf; | |
387 | drv_data->tx_map_len = 4; | |
388 | } else | |
389 | drv_data->tx_map_len = drv_data->len; | |
390 | ||
393df744 NF |
391 | /* Stream map the tx buffer. Always do DMA_TO_DEVICE first |
392 | * so we flush the cache *before* invalidating it, in case | |
393 | * the tx and rx buffers overlap. | |
394 | */ | |
e0c9905e | 395 | drv_data->tx_dma = dma_map_single(dev, drv_data->tx, |
393df744 NF |
396 | drv_data->tx_map_len, DMA_TO_DEVICE); |
397 | if (dma_mapping_error(dev, drv_data->tx_dma)) | |
398 | return 0; | |
e0c9905e | 399 | |
393df744 NF |
400 | /* Stream map the rx buffer */ |
401 | drv_data->rx_dma = dma_map_single(dev, drv_data->rx, | |
e0c9905e | 402 | drv_data->rx_map_len, DMA_FROM_DEVICE); |
393df744 NF |
403 | if (dma_mapping_error(dev, drv_data->rx_dma)) { |
404 | dma_unmap_single(dev, drv_data->tx_dma, | |
405 | drv_data->tx_map_len, DMA_TO_DEVICE); | |
e0c9905e SS |
406 | return 0; |
407 | } | |
408 | ||
409 | return 1; | |
410 | } | |
411 | ||
412 | static void unmap_dma_buffers(struct driver_data *drv_data) | |
413 | { | |
414 | struct device *dev; | |
415 | ||
416 | if (!drv_data->dma_mapped) | |
417 | return; | |
418 | ||
419 | if (!drv_data->cur_msg->is_dma_mapped) { | |
420 | dev = &drv_data->cur_msg->spi->dev; | |
421 | dma_unmap_single(dev, drv_data->rx_dma, | |
422 | drv_data->rx_map_len, DMA_FROM_DEVICE); | |
423 | dma_unmap_single(dev, drv_data->tx_dma, | |
424 | drv_data->tx_map_len, DMA_TO_DEVICE); | |
425 | } | |
426 | ||
427 | drv_data->dma_mapped = 0; | |
428 | } | |
429 | ||
430 | /* caller already set message->status; dma and pio irqs are blocked */ | |
5daa3ba0 | 431 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
432 | { |
433 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 434 | struct spi_message *msg; |
e0c9905e | 435 | |
5daa3ba0 SS |
436 | msg = drv_data->cur_msg; |
437 | drv_data->cur_msg = NULL; | |
438 | drv_data->cur_transfer = NULL; | |
5daa3ba0 SS |
439 | |
440 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
441 | struct spi_transfer, |
442 | transfer_list); | |
443 | ||
8423597d NF |
444 | /* Delay if requested before any change in chip select */ |
445 | if (last_transfer->delay_usecs) | |
446 | udelay(last_transfer->delay_usecs); | |
447 | ||
448 | /* Drop chip select UNLESS cs_change is true or we are returning | |
449 | * a message with an error, or next message is for another chip | |
450 | */ | |
e0c9905e | 451 | if (!last_transfer->cs_change) |
a7bb3909 | 452 | cs_deassert(drv_data); |
8423597d NF |
453 | else { |
454 | struct spi_message *next_msg; | |
455 | ||
456 | /* Holding of cs was hinted, but we need to make sure | |
457 | * the next message is for the same chip. Don't waste | |
458 | * time with the following tests unless this was hinted. | |
459 | * | |
460 | * We cannot postpone this until pump_messages, because | |
461 | * after calling msg->complete (below) the driver that | |
462 | * sent the current message could be unloaded, which | |
463 | * could invalidate the cs_control() callback... | |
464 | */ | |
465 | ||
466 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 467 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
468 | |
469 | /* see if the next and current messages point | |
470 | * to the same chip | |
471 | */ | |
472 | if (next_msg && next_msg->spi != msg->spi) | |
473 | next_msg = NULL; | |
474 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 475 | cs_deassert(drv_data); |
8423597d | 476 | } |
e0c9905e | 477 | |
7f86bde9 | 478 | spi_finalize_current_message(drv_data->master); |
a7bb3909 | 479 | drv_data->cur_chip = NULL; |
e0c9905e SS |
480 | } |
481 | ||
cf43369d | 482 | static int wait_ssp_rx_stall(void const __iomem *ioaddr) |
e0c9905e SS |
483 | { |
484 | unsigned long limit = loops_per_jiffy << 1; | |
485 | ||
306c68aa | 486 | while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit) |
e0c9905e SS |
487 | cpu_relax(); |
488 | ||
489 | return limit; | |
490 | } | |
491 | ||
492 | static int wait_dma_channel_stop(int channel) | |
493 | { | |
494 | unsigned long limit = loops_per_jiffy << 1; | |
495 | ||
306c68aa | 496 | while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit) |
e0c9905e SS |
497 | cpu_relax(); |
498 | ||
499 | return limit; | |
500 | } | |
501 | ||
cf43369d | 502 | static void dma_error_stop(struct driver_data *drv_data, const char *msg) |
e0c9905e | 503 | { |
cf43369d | 504 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 505 | |
8d94cc50 SS |
506 | /* Stop and reset */ |
507 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
508 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
2a8626a9 | 509 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 | 510 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); |
2a8626a9 | 511 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 SS |
512 | write_SSTO(0, reg); |
513 | flush(drv_data); | |
514 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 515 | |
8d94cc50 | 516 | unmap_dma_buffers(drv_data); |
e0c9905e | 517 | |
8d94cc50 | 518 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 519 | |
8d94cc50 SS |
520 | drv_data->cur_msg->state = ERROR_STATE; |
521 | tasklet_schedule(&drv_data->pump_transfers); | |
522 | } | |
523 | ||
524 | static void dma_transfer_complete(struct driver_data *drv_data) | |
525 | { | |
cf43369d | 526 | void __iomem *reg = drv_data->ioaddr; |
8d94cc50 SS |
527 | struct spi_message *msg = drv_data->cur_msg; |
528 | ||
529 | /* Clear and disable interrupts on SSP and DMA channels*/ | |
530 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
2a8626a9 | 531 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
532 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; |
533 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
534 | ||
535 | if (wait_dma_channel_stop(drv_data->rx_channel) == 0) | |
536 | dev_err(&drv_data->pdev->dev, | |
537 | "dma_handler: dma rx channel stop failed\n"); | |
538 | ||
539 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
540 | dev_err(&drv_data->pdev->dev, | |
541 | "dma_transfer: ssp rx stall failed\n"); | |
542 | ||
543 | unmap_dma_buffers(drv_data); | |
544 | ||
545 | /* update the buffer pointer for the amount completed in dma */ | |
546 | drv_data->rx += drv_data->len - | |
547 | (DCMD(drv_data->rx_channel) & DCMD_LENGTH); | |
548 | ||
549 | /* read trailing data from fifo, it does not matter how many | |
550 | * bytes are in the fifo just read until buffer is full | |
551 | * or fifo is empty, which ever occurs first */ | |
552 | drv_data->read(drv_data); | |
553 | ||
554 | /* return count of what was actually read */ | |
555 | msg->actual_length += drv_data->len - | |
556 | (drv_data->rx_end - drv_data->rx); | |
557 | ||
8423597d NF |
558 | /* Transfer delays and chip select release are |
559 | * handled in pump_transfers or giveback | |
560 | */ | |
8d94cc50 SS |
561 | |
562 | /* Move to next transfer */ | |
563 | msg->state = next_transfer(drv_data); | |
564 | ||
565 | /* Schedule transfer tasklet */ | |
566 | tasklet_schedule(&drv_data->pump_transfers); | |
567 | } | |
568 | ||
569 | static void dma_handler(int channel, void *data) | |
570 | { | |
571 | struct driver_data *drv_data = data; | |
572 | u32 irq_status = DCSR(channel) & DMA_INT_MASK; | |
573 | ||
574 | if (irq_status & DCSR_BUSERR) { | |
e0c9905e SS |
575 | |
576 | if (channel == drv_data->tx_channel) | |
8d94cc50 SS |
577 | dma_error_stop(drv_data, |
578 | "dma_handler: " | |
579 | "bad bus address on tx channel"); | |
e0c9905e | 580 | else |
8d94cc50 SS |
581 | dma_error_stop(drv_data, |
582 | "dma_handler: " | |
583 | "bad bus address on rx channel"); | |
584 | return; | |
e0c9905e SS |
585 | } |
586 | ||
587 | /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */ | |
8d94cc50 SS |
588 | if ((channel == drv_data->tx_channel) |
589 | && (irq_status & DCSR_ENDINTR) | |
590 | && (drv_data->ssp_type == PXA25x_SSP)) { | |
e0c9905e SS |
591 | |
592 | /* Wait for rx to stall */ | |
593 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
594 | dev_err(&drv_data->pdev->dev, | |
595 | "dma_handler: ssp rx stall failed\n"); | |
596 | ||
8d94cc50 SS |
597 | /* finish this transfer, start the next */ |
598 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
599 | } |
600 | } | |
601 | ||
602 | static irqreturn_t dma_transfer(struct driver_data *drv_data) | |
603 | { | |
604 | u32 irq_status; | |
cf43369d | 605 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
606 | |
607 | irq_status = read_SSSR(reg) & drv_data->mask_sr; | |
608 | if (irq_status & SSSR_ROR) { | |
8d94cc50 | 609 | dma_error_stop(drv_data, "dma_transfer: fifo overrun"); |
e0c9905e SS |
610 | return IRQ_HANDLED; |
611 | } | |
612 | ||
613 | /* Check for false positive timeout */ | |
8d94cc50 SS |
614 | if ((irq_status & SSSR_TINT) |
615 | && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { | |
e0c9905e SS |
616 | write_SSSR(SSSR_TINT, reg); |
617 | return IRQ_HANDLED; | |
618 | } | |
619 | ||
620 | if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { | |
621 | ||
8d94cc50 SS |
622 | /* Clear and disable timeout interrupt, do the rest in |
623 | * dma_transfer_complete */ | |
2a8626a9 | 624 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e | 625 | write_SSTO(0, reg); |
e0c9905e | 626 | |
8d94cc50 SS |
627 | /* finish this transfer, start the next */ |
628 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
629 | |
630 | return IRQ_HANDLED; | |
631 | } | |
632 | ||
633 | /* Opps problem detected */ | |
634 | return IRQ_NONE; | |
635 | } | |
636 | ||
579d3bb2 SAS |
637 | static void reset_sccr1(struct driver_data *drv_data) |
638 | { | |
639 | void __iomem *reg = drv_data->ioaddr; | |
640 | struct chip_data *chip = drv_data->cur_chip; | |
641 | u32 sccr1_reg; | |
642 | ||
643 | sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; | |
644 | sccr1_reg &= ~SSCR1_RFT; | |
645 | sccr1_reg |= chip->threshold; | |
646 | write_SSCR1(sccr1_reg, reg); | |
647 | } | |
648 | ||
8d94cc50 | 649 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 650 | { |
cf43369d | 651 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 652 | |
8d94cc50 | 653 | /* Stop and reset SSP */ |
2a8626a9 | 654 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 655 | reset_sccr1(drv_data); |
2a8626a9 | 656 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 SS |
657 | write_SSTO(0, reg); |
658 | flush(drv_data); | |
659 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 660 | |
8d94cc50 | 661 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 662 | |
8d94cc50 SS |
663 | drv_data->cur_msg->state = ERROR_STATE; |
664 | tasklet_schedule(&drv_data->pump_transfers); | |
665 | } | |
5daa3ba0 | 666 | |
8d94cc50 SS |
667 | static void int_transfer_complete(struct driver_data *drv_data) |
668 | { | |
cf43369d | 669 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 670 | |
8d94cc50 | 671 | /* Stop SSP */ |
2a8626a9 | 672 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 673 | reset_sccr1(drv_data); |
2a8626a9 | 674 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 675 | write_SSTO(0, reg); |
e0c9905e | 676 | |
25985edc | 677 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
678 | drv_data->cur_msg->actual_length += drv_data->len - |
679 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 680 | |
8423597d NF |
681 | /* Transfer delays and chip select release are |
682 | * handled in pump_transfers or giveback | |
683 | */ | |
e0c9905e | 684 | |
8d94cc50 SS |
685 | /* Move to next transfer */ |
686 | drv_data->cur_msg->state = next_transfer(drv_data); | |
e0c9905e | 687 | |
8d94cc50 SS |
688 | /* Schedule transfer tasklet */ |
689 | tasklet_schedule(&drv_data->pump_transfers); | |
690 | } | |
e0c9905e | 691 | |
8d94cc50 SS |
692 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
693 | { | |
cf43369d | 694 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 695 | |
8d94cc50 SS |
696 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
697 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 698 | |
8d94cc50 | 699 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 700 | |
8d94cc50 SS |
701 | if (irq_status & SSSR_ROR) { |
702 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
703 | return IRQ_HANDLED; | |
704 | } | |
e0c9905e | 705 | |
8d94cc50 SS |
706 | if (irq_status & SSSR_TINT) { |
707 | write_SSSR(SSSR_TINT, reg); | |
708 | if (drv_data->read(drv_data)) { | |
709 | int_transfer_complete(drv_data); | |
710 | return IRQ_HANDLED; | |
711 | } | |
712 | } | |
e0c9905e | 713 | |
8d94cc50 SS |
714 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
715 | do { | |
716 | if (drv_data->read(drv_data)) { | |
717 | int_transfer_complete(drv_data); | |
718 | return IRQ_HANDLED; | |
719 | } | |
720 | } while (drv_data->write(drv_data)); | |
e0c9905e | 721 | |
8d94cc50 SS |
722 | if (drv_data->read(drv_data)) { |
723 | int_transfer_complete(drv_data); | |
724 | return IRQ_HANDLED; | |
725 | } | |
e0c9905e | 726 | |
8d94cc50 | 727 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
728 | u32 bytes_left; |
729 | u32 sccr1_reg; | |
730 | ||
731 | sccr1_reg = read_SSCR1(reg); | |
732 | sccr1_reg &= ~SSCR1_TIE; | |
733 | ||
734 | /* | |
735 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 736 | * remaining RX bytes. |
579d3bb2 | 737 | */ |
2a8626a9 | 738 | if (pxa25x_ssp_comp(drv_data)) { |
579d3bb2 SAS |
739 | |
740 | sccr1_reg &= ~SSCR1_RFT; | |
741 | ||
742 | bytes_left = drv_data->rx_end - drv_data->rx; | |
743 | switch (drv_data->n_bytes) { | |
744 | case 4: | |
745 | bytes_left >>= 1; | |
746 | case 2: | |
747 | bytes_left >>= 1; | |
8d94cc50 | 748 | } |
579d3bb2 SAS |
749 | |
750 | if (bytes_left > RX_THRESH_DFLT) | |
751 | bytes_left = RX_THRESH_DFLT; | |
752 | ||
753 | sccr1_reg |= SSCR1_RxTresh(bytes_left); | |
e0c9905e | 754 | } |
579d3bb2 | 755 | write_SSCR1(sccr1_reg, reg); |
e0c9905e SS |
756 | } |
757 | ||
5daa3ba0 SS |
758 | /* We did something */ |
759 | return IRQ_HANDLED; | |
e0c9905e SS |
760 | } |
761 | ||
7d12e780 | 762 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 763 | { |
c7bec5ab | 764 | struct driver_data *drv_data = dev_id; |
cf43369d | 765 | void __iomem *reg = drv_data->ioaddr; |
49cbb1e0 SAS |
766 | u32 sccr1_reg = read_SSCR1(reg); |
767 | u32 mask = drv_data->mask_sr; | |
768 | u32 status; | |
769 | ||
770 | status = read_SSSR(reg); | |
771 | ||
772 | /* Ignore possible writes if we don't need to write */ | |
773 | if (!(sccr1_reg & SSCR1_TIE)) | |
774 | mask &= ~SSSR_TFS; | |
775 | ||
776 | if (!(status & mask)) | |
777 | return IRQ_NONE; | |
e0c9905e SS |
778 | |
779 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
780 | |
781 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
782 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
2a8626a9 | 783 | if (!pxa25x_ssp_comp(drv_data)) |
5daa3ba0 | 784 | write_SSTO(0, reg); |
2a8626a9 | 785 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 786 | |
e0c9905e | 787 | dev_err(&drv_data->pdev->dev, "bad message state " |
8d94cc50 | 788 | "in interrupt handler\n"); |
5daa3ba0 | 789 | |
e0c9905e SS |
790 | /* Never fail */ |
791 | return IRQ_HANDLED; | |
792 | } | |
793 | ||
794 | return drv_data->transfer_handler(drv_data); | |
795 | } | |
796 | ||
cf43369d DB |
797 | static int set_dma_burst_and_threshold(struct chip_data *chip, |
798 | struct spi_device *spi, | |
8d94cc50 SS |
799 | u8 bits_per_word, u32 *burst_code, |
800 | u32 *threshold) | |
801 | { | |
802 | struct pxa2xx_spi_chip *chip_info = | |
803 | (struct pxa2xx_spi_chip *)spi->controller_data; | |
804 | int bytes_per_word; | |
805 | int burst_bytes; | |
806 | int thresh_words; | |
807 | int req_burst_size; | |
808 | int retval = 0; | |
809 | ||
810 | /* Set the threshold (in registers) to equal the same amount of data | |
811 | * as represented by burst size (in bytes). The computation below | |
812 | * is (burst_size rounded up to nearest 8 byte, word or long word) | |
813 | * divided by (bytes/register); the tx threshold is the inverse of | |
814 | * the rx, so that there will always be enough data in the rx fifo | |
815 | * to satisfy a burst, and there will always be enough space in the | |
816 | * tx fifo to accept a burst (a tx burst will overwrite the fifo if | |
817 | * there is not enough space), there must always remain enough empty | |
818 | * space in the rx fifo for any data loaded to the tx fifo. | |
819 | * Whenever burst_size (in bytes) equals bits/word, the fifo threshold | |
820 | * will be 8, or half the fifo; | |
821 | * The threshold can only be set to 2, 4 or 8, but not 16, because | |
822 | * to burst 16 to the tx fifo, the fifo would have to be empty; | |
823 | * however, the minimum fifo trigger level is 1, and the tx will | |
824 | * request service when the fifo is at this level, with only 15 spaces. | |
825 | */ | |
826 | ||
827 | /* find bytes/word */ | |
828 | if (bits_per_word <= 8) | |
829 | bytes_per_word = 1; | |
830 | else if (bits_per_word <= 16) | |
831 | bytes_per_word = 2; | |
832 | else | |
833 | bytes_per_word = 4; | |
834 | ||
835 | /* use struct pxa2xx_spi_chip->dma_burst_size if available */ | |
836 | if (chip_info) | |
837 | req_burst_size = chip_info->dma_burst_size; | |
838 | else { | |
839 | switch (chip->dma_burst_size) { | |
840 | default: | |
841 | /* if the default burst size is not set, | |
842 | * do it now */ | |
843 | chip->dma_burst_size = DCMD_BURST8; | |
844 | case DCMD_BURST8: | |
845 | req_burst_size = 8; | |
846 | break; | |
847 | case DCMD_BURST16: | |
848 | req_burst_size = 16; | |
849 | break; | |
850 | case DCMD_BURST32: | |
851 | req_burst_size = 32; | |
852 | break; | |
853 | } | |
854 | } | |
855 | if (req_burst_size <= 8) { | |
856 | *burst_code = DCMD_BURST8; | |
857 | burst_bytes = 8; | |
858 | } else if (req_burst_size <= 16) { | |
859 | if (bytes_per_word == 1) { | |
860 | /* don't burst more than 1/2 the fifo */ | |
861 | *burst_code = DCMD_BURST8; | |
862 | burst_bytes = 8; | |
863 | retval = 1; | |
864 | } else { | |
865 | *burst_code = DCMD_BURST16; | |
866 | burst_bytes = 16; | |
867 | } | |
868 | } else { | |
869 | if (bytes_per_word == 1) { | |
870 | /* don't burst more than 1/2 the fifo */ | |
871 | *burst_code = DCMD_BURST8; | |
872 | burst_bytes = 8; | |
873 | retval = 1; | |
874 | } else if (bytes_per_word == 2) { | |
875 | /* don't burst more than 1/2 the fifo */ | |
876 | *burst_code = DCMD_BURST16; | |
877 | burst_bytes = 16; | |
878 | retval = 1; | |
879 | } else { | |
880 | *burst_code = DCMD_BURST32; | |
881 | burst_bytes = 32; | |
882 | } | |
883 | } | |
884 | ||
885 | thresh_words = burst_bytes / bytes_per_word; | |
886 | ||
887 | /* thresh_words will be between 2 and 8 */ | |
888 | *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT) | |
889 | | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT); | |
890 | ||
891 | return retval; | |
892 | } | |
893 | ||
2f1a74e5 | 894 | static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate) |
895 | { | |
896 | unsigned long ssp_clk = clk_get_rate(ssp->clk); | |
897 | ||
2a8626a9 | 898 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
2f1a74e5 | 899 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; |
900 | else | |
901 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
902 | } | |
903 | ||
e0c9905e SS |
904 | static void pump_transfers(unsigned long data) |
905 | { | |
906 | struct driver_data *drv_data = (struct driver_data *)data; | |
907 | struct spi_message *message = NULL; | |
908 | struct spi_transfer *transfer = NULL; | |
909 | struct spi_transfer *previous = NULL; | |
910 | struct chip_data *chip = NULL; | |
2f1a74e5 | 911 | struct ssp_device *ssp = drv_data->ssp; |
cf43369d | 912 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
913 | u32 clk_div = 0; |
914 | u8 bits = 0; | |
915 | u32 speed = 0; | |
916 | u32 cr0; | |
8d94cc50 SS |
917 | u32 cr1; |
918 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
919 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
920 | |
921 | /* Get current state information */ | |
922 | message = drv_data->cur_msg; | |
923 | transfer = drv_data->cur_transfer; | |
924 | chip = drv_data->cur_chip; | |
925 | ||
926 | /* Handle for abort */ | |
927 | if (message->state == ERROR_STATE) { | |
928 | message->status = -EIO; | |
5daa3ba0 | 929 | giveback(drv_data); |
e0c9905e SS |
930 | return; |
931 | } | |
932 | ||
933 | /* Handle end of message */ | |
934 | if (message->state == DONE_STATE) { | |
935 | message->status = 0; | |
5daa3ba0 | 936 | giveback(drv_data); |
e0c9905e SS |
937 | return; |
938 | } | |
939 | ||
8423597d | 940 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
941 | if (message->state == RUNNING_STATE) { |
942 | previous = list_entry(transfer->transfer_list.prev, | |
943 | struct spi_transfer, | |
944 | transfer_list); | |
945 | if (previous->delay_usecs) | |
946 | udelay(previous->delay_usecs); | |
8423597d NF |
947 | |
948 | /* Drop chip select only if cs_change is requested */ | |
949 | if (previous->cs_change) | |
a7bb3909 | 950 | cs_deassert(drv_data); |
e0c9905e SS |
951 | } |
952 | ||
7e964455 NF |
953 | /* Check for transfers that need multiple DMA segments */ |
954 | if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { | |
955 | ||
956 | /* reject already-mapped transfers; PIO won't always work */ | |
957 | if (message->is_dma_mapped | |
958 | || transfer->rx_dma || transfer->tx_dma) { | |
959 | dev_err(&drv_data->pdev->dev, | |
960 | "pump_transfers: mapped transfer length " | |
20b918dc | 961 | "of %u is greater than %d\n", |
7e964455 NF |
962 | transfer->len, MAX_DMA_LEN); |
963 | message->status = -EINVAL; | |
964 | giveback(drv_data); | |
965 | return; | |
966 | } | |
967 | ||
968 | /* warn ... we force this to PIO mode */ | |
969 | if (printk_ratelimit()) | |
970 | dev_warn(&message->spi->dev, "pump_transfers: " | |
971 | "DMA disabled for transfer length %ld " | |
972 | "greater than %d\n", | |
973 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
974 | } |
975 | ||
e0c9905e SS |
976 | /* Setup the transfer state based on the type of transfer */ |
977 | if (flush(drv_data) == 0) { | |
978 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
979 | message->status = -EIO; | |
5daa3ba0 | 980 | giveback(drv_data); |
e0c9905e SS |
981 | return; |
982 | } | |
9708c121 SS |
983 | drv_data->n_bytes = chip->n_bytes; |
984 | drv_data->dma_width = chip->dma_width; | |
e0c9905e SS |
985 | drv_data->tx = (void *)transfer->tx_buf; |
986 | drv_data->tx_end = drv_data->tx + transfer->len; | |
987 | drv_data->rx = transfer->rx_buf; | |
988 | drv_data->rx_end = drv_data->rx + transfer->len; | |
989 | drv_data->rx_dma = transfer->rx_dma; | |
990 | drv_data->tx_dma = transfer->tx_dma; | |
8d94cc50 | 991 | drv_data->len = transfer->len & DCMD_LENGTH; |
e0c9905e SS |
992 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
993 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
994 | |
995 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 996 | cr0 = chip->cr0; |
9708c121 SS |
997 | if (transfer->speed_hz || transfer->bits_per_word) { |
998 | ||
9708c121 SS |
999 | bits = chip->bits_per_word; |
1000 | speed = chip->speed_hz; | |
1001 | ||
1002 | if (transfer->speed_hz) | |
1003 | speed = transfer->speed_hz; | |
1004 | ||
1005 | if (transfer->bits_per_word) | |
1006 | bits = transfer->bits_per_word; | |
1007 | ||
2f1a74e5 | 1008 | clk_div = ssp_get_clk_div(ssp, speed); |
9708c121 SS |
1009 | |
1010 | if (bits <= 8) { | |
1011 | drv_data->n_bytes = 1; | |
1012 | drv_data->dma_width = DCMD_WIDTH1; | |
1013 | drv_data->read = drv_data->read != null_reader ? | |
1014 | u8_reader : null_reader; | |
1015 | drv_data->write = drv_data->write != null_writer ? | |
1016 | u8_writer : null_writer; | |
1017 | } else if (bits <= 16) { | |
1018 | drv_data->n_bytes = 2; | |
1019 | drv_data->dma_width = DCMD_WIDTH2; | |
1020 | drv_data->read = drv_data->read != null_reader ? | |
1021 | u16_reader : null_reader; | |
1022 | drv_data->write = drv_data->write != null_writer ? | |
1023 | u16_writer : null_writer; | |
1024 | } else if (bits <= 32) { | |
1025 | drv_data->n_bytes = 4; | |
1026 | drv_data->dma_width = DCMD_WIDTH4; | |
1027 | drv_data->read = drv_data->read != null_reader ? | |
1028 | u32_reader : null_reader; | |
1029 | drv_data->write = drv_data->write != null_writer ? | |
1030 | u32_writer : null_writer; | |
1031 | } | |
8d94cc50 SS |
1032 | /* if bits/word is changed in dma mode, then must check the |
1033 | * thresholds and burst also */ | |
1034 | if (chip->enable_dma) { | |
1035 | if (set_dma_burst_and_threshold(chip, message->spi, | |
1036 | bits, &dma_burst, | |
1037 | &dma_thresh)) | |
1038 | if (printk_ratelimit()) | |
1039 | dev_warn(&message->spi->dev, | |
7e964455 | 1040 | "pump_transfers: " |
8d94cc50 SS |
1041 | "DMA burst size reduced to " |
1042 | "match bits_per_word\n"); | |
1043 | } | |
9708c121 SS |
1044 | |
1045 | cr0 = clk_div | |
1046 | | SSCR0_Motorola | |
5daa3ba0 | 1047 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
1048 | | SSCR0_SSE |
1049 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
1050 | } |
1051 | ||
e0c9905e SS |
1052 | message->state = RUNNING_STATE; |
1053 | ||
7e964455 NF |
1054 | /* Try to map dma buffer and do a dma transfer if successful, but |
1055 | * only if the length is non-zero and less than MAX_DMA_LEN. | |
1056 | * | |
1057 | * Zero-length non-descriptor DMA is illegal on PXA2xx; force use | |
1058 | * of PIO instead. Care is needed above because the transfer may | |
1059 | * have have been passed with buffers that are already dma mapped. | |
1060 | * A zero-length transfer in PIO mode will not try to write/read | |
1061 | * to/from the buffers | |
1062 | * | |
1063 | * REVISIT large transfers are exactly where we most want to be | |
1064 | * using DMA. If this happens much, split those transfers into | |
1065 | * multiple DMA segments rather than forcing PIO. | |
1066 | */ | |
1067 | drv_data->dma_mapped = 0; | |
1068 | if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN) | |
1069 | drv_data->dma_mapped = map_dma_buffers(drv_data); | |
1070 | if (drv_data->dma_mapped) { | |
e0c9905e SS |
1071 | |
1072 | /* Ensure we have the correct interrupt handler */ | |
1073 | drv_data->transfer_handler = dma_transfer; | |
1074 | ||
1075 | /* Setup rx DMA Channel */ | |
1076 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
1077 | DSADR(drv_data->rx_channel) = drv_data->ssdr_physical; | |
1078 | DTADR(drv_data->rx_channel) = drv_data->rx_dma; | |
1079 | if (drv_data->rx == drv_data->null_dma_buf) | |
1080 | /* No target address increment */ | |
1081 | DCMD(drv_data->rx_channel) = DCMD_FLOWSRC | |
9708c121 | 1082 | | drv_data->dma_width |
8d94cc50 | 1083 | | dma_burst |
e0c9905e SS |
1084 | | drv_data->len; |
1085 | else | |
1086 | DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR | |
1087 | | DCMD_FLOWSRC | |
9708c121 | 1088 | | drv_data->dma_width |
8d94cc50 | 1089 | | dma_burst |
e0c9905e SS |
1090 | | drv_data->len; |
1091 | ||
1092 | /* Setup tx DMA Channel */ | |
1093 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
1094 | DSADR(drv_data->tx_channel) = drv_data->tx_dma; | |
1095 | DTADR(drv_data->tx_channel) = drv_data->ssdr_physical; | |
1096 | if (drv_data->tx == drv_data->null_dma_buf) | |
1097 | /* No source address increment */ | |
1098 | DCMD(drv_data->tx_channel) = DCMD_FLOWTRG | |
9708c121 | 1099 | | drv_data->dma_width |
8d94cc50 | 1100 | | dma_burst |
e0c9905e SS |
1101 | | drv_data->len; |
1102 | else | |
1103 | DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR | |
1104 | | DCMD_FLOWTRG | |
9708c121 | 1105 | | drv_data->dma_width |
8d94cc50 | 1106 | | dma_burst |
e0c9905e SS |
1107 | | drv_data->len; |
1108 | ||
1109 | /* Enable dma end irqs on SSP to detect end of transfer */ | |
1110 | if (drv_data->ssp_type == PXA25x_SSP) | |
1111 | DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN; | |
1112 | ||
8d94cc50 SS |
1113 | /* Clear status and start DMA engine */ |
1114 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e SS |
1115 | write_SSSR(drv_data->clear_sr, reg); |
1116 | DCSR(drv_data->rx_channel) |= DCSR_RUN; | |
1117 | DCSR(drv_data->tx_channel) |= DCSR_RUN; | |
e0c9905e SS |
1118 | } else { |
1119 | /* Ensure we have the correct interrupt handler */ | |
1120 | drv_data->transfer_handler = interrupt_transfer; | |
1121 | ||
8d94cc50 SS |
1122 | /* Clear status */ |
1123 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 1124 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
1125 | } |
1126 | ||
1127 | /* see if we need to reload the config registers */ | |
1128 | if ((read_SSCR0(reg) != cr0) | |
1129 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
1130 | (cr1 & SSCR1_CHANGE_MASK)) { | |
1131 | ||
b97c74bd | 1132 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 1133 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
2a8626a9 | 1134 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e | 1135 | write_SSTO(chip->timeout, reg); |
b97c74bd NF |
1136 | /* first set CR1 without interrupt and service enables */ |
1137 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
1138 | /* restart the SSP */ | |
8d94cc50 | 1139 | write_SSCR0(cr0, reg); |
b97c74bd | 1140 | |
8d94cc50 | 1141 | } else { |
2a8626a9 | 1142 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 1143 | write_SSTO(chip->timeout, reg); |
e0c9905e | 1144 | } |
b97c74bd | 1145 | |
a7bb3909 | 1146 | cs_assert(drv_data); |
b97c74bd NF |
1147 | |
1148 | /* after chip select, release the data by enabling service | |
1149 | * requests and interrupts, without changing any mode bits */ | |
1150 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
1151 | } |
1152 | ||
7f86bde9 MW |
1153 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
1154 | struct spi_message *msg) | |
e0c9905e | 1155 | { |
7f86bde9 | 1156 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 1157 | |
7f86bde9 | 1158 | drv_data->cur_msg = msg; |
e0c9905e SS |
1159 | /* Initial message state*/ |
1160 | drv_data->cur_msg->state = START_STATE; | |
1161 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1162 | struct spi_transfer, | |
1163 | transfer_list); | |
1164 | ||
8d94cc50 SS |
1165 | /* prepare to setup the SSP, in pump_transfers, using the per |
1166 | * chip configuration */ | |
e0c9905e | 1167 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1168 | |
1169 | /* Mark as busy and launch transfers */ | |
1170 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
1171 | return 0; |
1172 | } | |
1173 | ||
a7bb3909 EM |
1174 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1175 | struct pxa2xx_spi_chip *chip_info) | |
1176 | { | |
1177 | int err = 0; | |
1178 | ||
1179 | if (chip == NULL || chip_info == NULL) | |
1180 | return 0; | |
1181 | ||
1182 | /* NOTE: setup() can be called multiple times, possibly with | |
1183 | * different chip_info, release previously requested GPIO | |
1184 | */ | |
1185 | if (gpio_is_valid(chip->gpio_cs)) | |
1186 | gpio_free(chip->gpio_cs); | |
1187 | ||
1188 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1189 | if (chip_info->cs_control) { | |
1190 | chip->cs_control = chip_info->cs_control; | |
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1195 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1196 | if (err) { | |
1197 | dev_err(&spi->dev, "failed to request chip select " | |
1198 | "GPIO%d\n", chip_info->gpio_cs); | |
1199 | return err; | |
1200 | } | |
1201 | ||
1202 | chip->gpio_cs = chip_info->gpio_cs; | |
1203 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1204 | ||
1205 | err = gpio_direction_output(chip->gpio_cs, | |
1206 | !chip->gpio_cs_inverted); | |
1207 | } | |
1208 | ||
1209 | return err; | |
1210 | } | |
1211 | ||
e0c9905e SS |
1212 | static int setup(struct spi_device *spi) |
1213 | { | |
1214 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1215 | struct chip_data *chip; | |
1216 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
2f1a74e5 | 1217 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e | 1218 | unsigned int clk_div; |
f1f640a9 VS |
1219 | uint tx_thres = TX_THRESH_DFLT; |
1220 | uint rx_thres = RX_THRESH_DFLT; | |
e0c9905e | 1221 | |
2a8626a9 | 1222 | if (!pxa25x_ssp_comp(drv_data) |
8d94cc50 SS |
1223 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
1224 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1225 | "b/w not 4-32 for type non-PXA25x_SSP\n", | |
1226 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1227 | return -EINVAL; |
2a8626a9 | 1228 | } else if (pxa25x_ssp_comp(drv_data) |
8d94cc50 SS |
1229 | && (spi->bits_per_word < 4 |
1230 | || spi->bits_per_word > 16)) { | |
1231 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1232 | "b/w not 4-16 for type PXA25x_SSP\n", | |
1233 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1234 | return -EINVAL; |
8d94cc50 | 1235 | } |
e0c9905e | 1236 | |
8d94cc50 | 1237 | /* Only alloc on first setup */ |
e0c9905e | 1238 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1239 | if (!chip) { |
e0c9905e | 1240 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
1241 | if (!chip) { |
1242 | dev_err(&spi->dev, | |
1243 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 1244 | return -ENOMEM; |
8d94cc50 | 1245 | } |
e0c9905e | 1246 | |
2a8626a9 SAS |
1247 | if (drv_data->ssp_type == CE4100_SSP) { |
1248 | if (spi->chip_select > 4) { | |
1249 | dev_err(&spi->dev, "failed setup: " | |
1250 | "cs number must not be > 4.\n"); | |
1251 | kfree(chip); | |
1252 | return -EINVAL; | |
1253 | } | |
1254 | ||
1255 | chip->frm = spi->chip_select; | |
1256 | } else | |
1257 | chip->gpio_cs = -1; | |
e0c9905e | 1258 | chip->enable_dma = 0; |
f1f640a9 | 1259 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1260 | chip->dma_burst_size = drv_data->master_info->enable_dma ? |
1261 | DCMD_BURST8 : 0; | |
e0c9905e SS |
1262 | } |
1263 | ||
8d94cc50 SS |
1264 | /* protocol drivers may change the chip settings, so... |
1265 | * if chip_info exists, use it */ | |
1266 | chip_info = spi->controller_data; | |
1267 | ||
e0c9905e | 1268 | /* chip_info isn't always needed */ |
8d94cc50 | 1269 | chip->cr1 = 0; |
e0c9905e | 1270 | if (chip_info) { |
f1f640a9 VS |
1271 | if (chip_info->timeout) |
1272 | chip->timeout = chip_info->timeout; | |
1273 | if (chip_info->tx_threshold) | |
1274 | tx_thres = chip_info->tx_threshold; | |
1275 | if (chip_info->rx_threshold) | |
1276 | rx_thres = chip_info->rx_threshold; | |
1277 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 1278 | chip->dma_threshold = 0; |
e0c9905e SS |
1279 | if (chip_info->enable_loopback) |
1280 | chip->cr1 = SSCR1_LBM; | |
1281 | } | |
1282 | ||
f1f640a9 VS |
1283 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
1284 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1285 | ||
8d94cc50 SS |
1286 | /* set dma burst and threshold outside of chip_info path so that if |
1287 | * chip_info goes away after setting chip->enable_dma, the | |
1288 | * burst and threshold can still respond to changes in bits_per_word */ | |
1289 | if (chip->enable_dma) { | |
1290 | /* set up legal burst and threshold for dma */ | |
1291 | if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word, | |
1292 | &chip->dma_burst_size, | |
1293 | &chip->dma_threshold)) { | |
1294 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | |
1295 | "to match bits_per_word\n"); | |
1296 | } | |
1297 | } | |
1298 | ||
2f1a74e5 | 1299 | clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz); |
9708c121 | 1300 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
1301 | |
1302 | chip->cr0 = clk_div | |
1303 | | SSCR0_Motorola | |
5daa3ba0 SS |
1304 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
1305 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
1306 | | SSCR0_SSE |
1307 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
1308 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1309 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1310 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e SS |
1311 | |
1312 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ | |
2a8626a9 | 1313 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 1314 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
c9840daa EM |
1315 | clk_get_rate(ssp->clk) |
1316 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), | |
1317 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 1318 | else |
7d077197 | 1319 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
c9840daa EM |
1320 | clk_get_rate(ssp->clk) / 2 |
1321 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), | |
1322 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
1323 | |
1324 | if (spi->bits_per_word <= 8) { | |
1325 | chip->n_bytes = 1; | |
1326 | chip->dma_width = DCMD_WIDTH1; | |
1327 | chip->read = u8_reader; | |
1328 | chip->write = u8_writer; | |
1329 | } else if (spi->bits_per_word <= 16) { | |
1330 | chip->n_bytes = 2; | |
1331 | chip->dma_width = DCMD_WIDTH2; | |
1332 | chip->read = u16_reader; | |
1333 | chip->write = u16_writer; | |
1334 | } else if (spi->bits_per_word <= 32) { | |
1335 | chip->cr0 |= SSCR0_EDSS; | |
1336 | chip->n_bytes = 4; | |
1337 | chip->dma_width = DCMD_WIDTH4; | |
1338 | chip->read = u32_reader; | |
1339 | chip->write = u32_writer; | |
1340 | } else { | |
1341 | dev_err(&spi->dev, "invalid wordsize\n"); | |
e0c9905e SS |
1342 | return -ENODEV; |
1343 | } | |
9708c121 | 1344 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1345 | |
1346 | spi_set_ctldata(spi, chip); | |
1347 | ||
2a8626a9 SAS |
1348 | if (drv_data->ssp_type == CE4100_SSP) |
1349 | return 0; | |
1350 | ||
a7bb3909 | 1351 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1352 | } |
1353 | ||
0ffa0285 | 1354 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1355 | { |
0ffa0285 | 1356 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1357 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1358 | |
7348d82a DR |
1359 | if (!chip) |
1360 | return; | |
1361 | ||
2a8626a9 | 1362 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1363 | gpio_free(chip->gpio_cs); |
1364 | ||
e0c9905e SS |
1365 | kfree(chip); |
1366 | } | |
1367 | ||
fd4a319b | 1368 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1369 | { |
1370 | struct device *dev = &pdev->dev; | |
1371 | struct pxa2xx_spi_master *platform_info; | |
1372 | struct spi_master *master; | |
65a00a20 | 1373 | struct driver_data *drv_data; |
2f1a74e5 | 1374 | struct ssp_device *ssp; |
65a00a20 | 1375 | int status; |
e0c9905e | 1376 | |
851bacf5 MW |
1377 | platform_info = dev_get_platdata(dev); |
1378 | if (!platform_info) { | |
1379 | dev_err(&pdev->dev, "missing platform data\n"); | |
1380 | return -ENODEV; | |
1381 | } | |
e0c9905e | 1382 | |
baffe169 | 1383 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1384 | if (!ssp) |
1385 | ssp = &platform_info->ssp; | |
1386 | ||
1387 | if (!ssp->mmio_base) { | |
1388 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1389 | return -ENODEV; |
1390 | } | |
1391 | ||
1392 | /* Allocate master with space for drv_data and null dma buffer */ | |
1393 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1394 | if (!master) { | |
65a00a20 | 1395 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1396 | pxa_ssp_free(ssp); |
e0c9905e SS |
1397 | return -ENOMEM; |
1398 | } | |
1399 | drv_data = spi_master_get_devdata(master); | |
1400 | drv_data->master = master; | |
1401 | drv_data->master_info = platform_info; | |
1402 | drv_data->pdev = pdev; | |
2f1a74e5 | 1403 | drv_data->ssp = ssp; |
e0c9905e | 1404 | |
21486af0 | 1405 | master->dev.parent = &pdev->dev; |
21486af0 | 1406 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1407 | /* the spi->mode bits understood by this driver: */ |
50e0a7bd | 1408 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
e7db06b5 | 1409 | |
851bacf5 | 1410 | master->bus_num = ssp->port_id; |
e0c9905e | 1411 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 1412 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1413 | master->cleanup = cleanup; |
1414 | master->setup = setup; | |
7f86bde9 | 1415 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
e0c9905e | 1416 | |
2f1a74e5 | 1417 | drv_data->ssp_type = ssp->type; |
2b9b84f4 | 1418 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
e0c9905e | 1419 | |
2f1a74e5 | 1420 | drv_data->ioaddr = ssp->mmio_base; |
1421 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1422 | if (pxa25x_ssp_comp(drv_data)) { |
e0c9905e SS |
1423 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1424 | drv_data->dma_cr1 = 0; | |
1425 | drv_data->clear_sr = SSSR_ROR; | |
1426 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1427 | } else { | |
1428 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | |
1429 | drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE; | |
1430 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; | |
1431 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1432 | } | |
1433 | ||
49cbb1e0 SAS |
1434 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1435 | drv_data); | |
e0c9905e | 1436 | if (status < 0) { |
65a00a20 | 1437 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1438 | goto out_error_master_alloc; |
1439 | } | |
1440 | ||
1441 | /* Setup DMA if requested */ | |
1442 | drv_data->tx_channel = -1; | |
1443 | drv_data->rx_channel = -1; | |
1444 | if (platform_info->enable_dma) { | |
1445 | ||
1446 | /* Get two DMA channels (rx and tx) */ | |
1447 | drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx", | |
1448 | DMA_PRIO_HIGH, | |
1449 | dma_handler, | |
1450 | drv_data); | |
1451 | if (drv_data->rx_channel < 0) { | |
1452 | dev_err(dev, "problem (%d) requesting rx channel\n", | |
1453 | drv_data->rx_channel); | |
1454 | status = -ENODEV; | |
1455 | goto out_error_irq_alloc; | |
1456 | } | |
1457 | drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx", | |
1458 | DMA_PRIO_MEDIUM, | |
1459 | dma_handler, | |
1460 | drv_data); | |
1461 | if (drv_data->tx_channel < 0) { | |
1462 | dev_err(dev, "problem (%d) requesting tx channel\n", | |
1463 | drv_data->tx_channel); | |
1464 | status = -ENODEV; | |
1465 | goto out_error_dma_alloc; | |
1466 | } | |
1467 | ||
2f1a74e5 | 1468 | DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; |
1469 | DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; | |
e0c9905e SS |
1470 | } |
1471 | ||
1472 | /* Enable SOC clock */ | |
2f1a74e5 | 1473 | clk_enable(ssp->clk); |
e0c9905e SS |
1474 | |
1475 | /* Load default SSP configuration */ | |
1476 | write_SSCR0(0, drv_data->ioaddr); | |
f1f640a9 VS |
1477 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | |
1478 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1479 | drv_data->ioaddr); | |
c9840daa | 1480 | write_SSCR0(SSCR0_SCR(2) |
e0c9905e SS |
1481 | | SSCR0_Motorola |
1482 | | SSCR0_DataSize(8), | |
1483 | drv_data->ioaddr); | |
2a8626a9 | 1484 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e SS |
1485 | write_SSTO(0, drv_data->ioaddr); |
1486 | write_SSPSP(0, drv_data->ioaddr); | |
1487 | ||
7f86bde9 MW |
1488 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1489 | (unsigned long)drv_data); | |
e0c9905e SS |
1490 | |
1491 | /* Register with the SPI framework */ | |
1492 | platform_set_drvdata(pdev, drv_data); | |
1493 | status = spi_register_master(master); | |
1494 | if (status != 0) { | |
1495 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1496 | goto out_error_clock_enabled; |
e0c9905e SS |
1497 | } |
1498 | ||
1499 | return status; | |
1500 | ||
e0c9905e | 1501 | out_error_clock_enabled: |
2f1a74e5 | 1502 | clk_disable(ssp->clk); |
e0c9905e SS |
1503 | |
1504 | out_error_dma_alloc: | |
1505 | if (drv_data->tx_channel != -1) | |
1506 | pxa_free_dma(drv_data->tx_channel); | |
1507 | if (drv_data->rx_channel != -1) | |
1508 | pxa_free_dma(drv_data->rx_channel); | |
1509 | ||
1510 | out_error_irq_alloc: | |
2f1a74e5 | 1511 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1512 | |
1513 | out_error_master_alloc: | |
1514 | spi_master_put(master); | |
baffe169 | 1515 | pxa_ssp_free(ssp); |
e0c9905e SS |
1516 | return status; |
1517 | } | |
1518 | ||
1519 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1520 | { | |
1521 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1522 | struct ssp_device *ssp; |
e0c9905e SS |
1523 | |
1524 | if (!drv_data) | |
1525 | return 0; | |
51e911e2 | 1526 | ssp = drv_data->ssp; |
e0c9905e | 1527 | |
e0c9905e SS |
1528 | /* Disable the SSP at the peripheral and SOC level */ |
1529 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1530 | clk_disable(ssp->clk); |
e0c9905e SS |
1531 | |
1532 | /* Release DMA */ | |
1533 | if (drv_data->master_info->enable_dma) { | |
2f1a74e5 | 1534 | DRCMR(ssp->drcmr_rx) = 0; |
1535 | DRCMR(ssp->drcmr_tx) = 0; | |
e0c9905e SS |
1536 | pxa_free_dma(drv_data->tx_channel); |
1537 | pxa_free_dma(drv_data->rx_channel); | |
1538 | } | |
1539 | ||
1540 | /* Release IRQ */ | |
2f1a74e5 | 1541 | free_irq(ssp->irq, drv_data); |
1542 | ||
1543 | /* Release SSP */ | |
baffe169 | 1544 | pxa_ssp_free(ssp); |
e0c9905e SS |
1545 | |
1546 | /* Disconnect from the SPI framework */ | |
1547 | spi_unregister_master(drv_data->master); | |
1548 | ||
1549 | /* Prevent double remove */ | |
1550 | platform_set_drvdata(pdev, NULL); | |
1551 | ||
1552 | return 0; | |
1553 | } | |
1554 | ||
1555 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1556 | { | |
1557 | int status = 0; | |
1558 | ||
1559 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1560 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1561 | } | |
1562 | ||
1563 | #ifdef CONFIG_PM | |
86d2593a | 1564 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1565 | { |
86d2593a | 1566 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1567 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1568 | int status = 0; |
1569 | ||
7f86bde9 | 1570 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1571 | if (status != 0) |
1572 | return status; | |
1573 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1574 | clk_disable(ssp->clk); |
e0c9905e SS |
1575 | |
1576 | return 0; | |
1577 | } | |
1578 | ||
86d2593a | 1579 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1580 | { |
86d2593a | 1581 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1582 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1583 | int status = 0; |
1584 | ||
148da331 DR |
1585 | if (drv_data->rx_channel != -1) |
1586 | DRCMR(drv_data->ssp->drcmr_rx) = | |
1587 | DRCMR_MAPVLD | drv_data->rx_channel; | |
1588 | if (drv_data->tx_channel != -1) | |
1589 | DRCMR(drv_data->ssp->drcmr_tx) = | |
1590 | DRCMR_MAPVLD | drv_data->tx_channel; | |
1591 | ||
e0c9905e | 1592 | /* Enable the SSP clock */ |
0cf942d7 | 1593 | clk_enable(ssp->clk); |
e0c9905e SS |
1594 | |
1595 | /* Start the queue running */ | |
7f86bde9 | 1596 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1597 | if (status != 0) { |
86d2593a | 1598 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1599 | return status; |
1600 | } | |
1601 | ||
1602 | return 0; | |
1603 | } | |
86d2593a | 1604 | |
47145210 | 1605 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
86d2593a MR |
1606 | .suspend = pxa2xx_spi_suspend, |
1607 | .resume = pxa2xx_spi_resume, | |
1608 | }; | |
1609 | #endif | |
e0c9905e SS |
1610 | |
1611 | static struct platform_driver driver = { | |
1612 | .driver = { | |
86d2593a MR |
1613 | .name = "pxa2xx-spi", |
1614 | .owner = THIS_MODULE, | |
1615 | #ifdef CONFIG_PM | |
1616 | .pm = &pxa2xx_spi_pm_ops, | |
1617 | #endif | |
e0c9905e | 1618 | }, |
fbd29a14 | 1619 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1620 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1621 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1622 | }; |
1623 | ||
1624 | static int __init pxa2xx_spi_init(void) | |
1625 | { | |
fbd29a14 | 1626 | return platform_driver_register(&driver); |
e0c9905e | 1627 | } |
5b61a749 | 1628 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1629 | |
1630 | static void __exit pxa2xx_spi_exit(void) | |
1631 | { | |
1632 | platform_driver_unregister(&driver); | |
1633 | } | |
1634 | module_exit(pxa2xx_spi_exit); |