]>
Commit | Line | Data |
---|---|---|
e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
e0c9905e SS |
14 | */ |
15 | ||
8b136baa | 16 | #include <linux/bitops.h> |
e0c9905e SS |
17 | #include <linux/init.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/errno.h> | |
cbfd6a21 | 22 | #include <linux/err.h> |
e0c9905e | 23 | #include <linux/interrupt.h> |
9df461ec | 24 | #include <linux/kernel.h> |
34cadd9c | 25 | #include <linux/pci.h> |
e0c9905e | 26 | #include <linux/platform_device.h> |
8348c259 | 27 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 28 | #include <linux/spi/spi.h> |
e0c9905e | 29 | #include <linux/delay.h> |
a7bb3909 | 30 | #include <linux/gpio.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
3343b7a6 | 32 | #include <linux/clk.h> |
7d94a505 | 33 | #include <linux/pm_runtime.h> |
a3496855 | 34 | #include <linux/acpi.h> |
e0c9905e | 35 | |
cd7bed00 | 36 | #include "spi-pxa2xx.h" |
e0c9905e SS |
37 | |
38 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 39 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 40 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 41 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e | 42 | |
f1f640a9 VS |
43 | #define TIMOUT_DFLT 1000 |
44 | ||
b97c74bd NF |
45 | /* |
46 | * for testing SSCR1 changes that require SSP restart, basically | |
47 | * everything except the service and interrupt enables, the pxa270 developer | |
48 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
49 | * list, but the PXA255 dev man says all bits without really meaning the | |
50 | * service and interrupt enables | |
51 | */ | |
52 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 53 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
54 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
55 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
56 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
57 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 58 | |
e5262d05 WC |
59 | #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ |
60 | | QUARK_X1000_SSCR1_EFWR \ | |
61 | | QUARK_X1000_SSCR1_RFT \ | |
62 | | QUARK_X1000_SSCR1_TFT \ | |
63 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
64 | ||
624ea72e JN |
65 | #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) |
66 | #define LPSS_CS_CONTROL_SW_MODE BIT(0) | |
67 | #define LPSS_CS_CONTROL_CS_HIGH BIT(1) | |
d0283eb2 JN |
68 | #define LPSS_CS_CONTROL_CS_SEL_SHIFT 8 |
69 | #define LPSS_CS_CONTROL_CS_SEL_MASK (3 << LPSS_CS_CONTROL_CS_SEL_SHIFT) | |
8b136baa JN |
70 | #define LPSS_CAPS_CS_EN_SHIFT 9 |
71 | #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) | |
a0d2642e | 72 | |
dccf7369 JN |
73 | struct lpss_config { |
74 | /* LPSS offset from drv_data->ioaddr */ | |
75 | unsigned offset; | |
76 | /* Register offsets from drv_data->lpss_base or -1 */ | |
77 | int reg_general; | |
78 | int reg_ssp; | |
79 | int reg_cs_ctrl; | |
8b136baa | 80 | int reg_capabilities; |
dccf7369 JN |
81 | /* FIFO thresholds */ |
82 | u32 rx_threshold; | |
83 | u32 tx_threshold_lo; | |
84 | u32 tx_threshold_hi; | |
85 | }; | |
86 | ||
87 | /* Keep these sorted with enum pxa_ssp_type */ | |
88 | static const struct lpss_config lpss_platforms[] = { | |
89 | { /* LPSS_LPT_SSP */ | |
90 | .offset = 0x800, | |
91 | .reg_general = 0x08, | |
92 | .reg_ssp = 0x0c, | |
93 | .reg_cs_ctrl = 0x18, | |
8b136baa | 94 | .reg_capabilities = -1, |
dccf7369 JN |
95 | .rx_threshold = 64, |
96 | .tx_threshold_lo = 160, | |
97 | .tx_threshold_hi = 224, | |
98 | }, | |
99 | { /* LPSS_BYT_SSP */ | |
100 | .offset = 0x400, | |
101 | .reg_general = 0x08, | |
102 | .reg_ssp = 0x0c, | |
103 | .reg_cs_ctrl = 0x18, | |
8b136baa | 104 | .reg_capabilities = -1, |
dccf7369 JN |
105 | .rx_threshold = 64, |
106 | .tx_threshold_lo = 160, | |
107 | .tx_threshold_hi = 224, | |
108 | }, | |
34cadd9c JN |
109 | { /* LPSS_SPT_SSP */ |
110 | .offset = 0x200, | |
111 | .reg_general = -1, | |
112 | .reg_ssp = 0x20, | |
113 | .reg_cs_ctrl = 0x24, | |
8b136baa | 114 | .reg_capabilities = 0xfc, |
34cadd9c JN |
115 | .rx_threshold = 1, |
116 | .tx_threshold_lo = 32, | |
117 | .tx_threshold_hi = 56, | |
118 | }, | |
dccf7369 JN |
119 | }; |
120 | ||
121 | static inline const struct lpss_config | |
122 | *lpss_get_config(const struct driver_data *drv_data) | |
123 | { | |
124 | return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; | |
125 | } | |
126 | ||
a0d2642e MW |
127 | static bool is_lpss_ssp(const struct driver_data *drv_data) |
128 | { | |
03fbf488 JN |
129 | switch (drv_data->ssp_type) { |
130 | case LPSS_LPT_SSP: | |
131 | case LPSS_BYT_SSP: | |
34cadd9c | 132 | case LPSS_SPT_SSP: |
03fbf488 JN |
133 | return true; |
134 | default: | |
135 | return false; | |
136 | } | |
a0d2642e MW |
137 | } |
138 | ||
e5262d05 WC |
139 | static bool is_quark_x1000_ssp(const struct driver_data *drv_data) |
140 | { | |
141 | return drv_data->ssp_type == QUARK_X1000_SSP; | |
142 | } | |
143 | ||
4fdb2424 WC |
144 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
145 | { | |
146 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
147 | case QUARK_X1000_SSP: |
148 | return QUARK_X1000_SSCR1_CHANGE_MASK; | |
4fdb2424 WC |
149 | default: |
150 | return SSCR1_CHANGE_MASK; | |
151 | } | |
152 | } | |
153 | ||
154 | static u32 | |
155 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
156 | { | |
157 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
158 | case QUARK_X1000_SSP: |
159 | return RX_THRESH_QUARK_X1000_DFLT; | |
4fdb2424 WC |
160 | default: |
161 | return RX_THRESH_DFLT; | |
162 | } | |
163 | } | |
164 | ||
165 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
166 | { | |
4fdb2424 WC |
167 | u32 mask; |
168 | ||
169 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
170 | case QUARK_X1000_SSP: |
171 | mask = QUARK_X1000_SSSR_TFL_MASK; | |
172 | break; | |
4fdb2424 WC |
173 | default: |
174 | mask = SSSR_TFL_MASK; | |
175 | break; | |
176 | } | |
177 | ||
c039dd27 | 178 | return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; |
4fdb2424 WC |
179 | } |
180 | ||
181 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
182 | u32 *sccr1_reg) | |
183 | { | |
184 | u32 mask; | |
185 | ||
186 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
187 | case QUARK_X1000_SSP: |
188 | mask = QUARK_X1000_SSCR1_RFT; | |
189 | break; | |
4fdb2424 WC |
190 | default: |
191 | mask = SSCR1_RFT; | |
192 | break; | |
193 | } | |
194 | *sccr1_reg &= ~mask; | |
195 | } | |
196 | ||
197 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
198 | u32 *sccr1_reg, u32 threshold) | |
199 | { | |
200 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
201 | case QUARK_X1000_SSP: |
202 | *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); | |
203 | break; | |
4fdb2424 WC |
204 | default: |
205 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
206 | break; | |
207 | } | |
208 | } | |
209 | ||
210 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
211 | u32 clk_div, u8 bits) | |
212 | { | |
213 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
214 | case QUARK_X1000_SSP: |
215 | return clk_div | |
216 | | QUARK_X1000_SSCR0_Motorola | |
217 | | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) | |
218 | | SSCR0_SSE; | |
4fdb2424 WC |
219 | default: |
220 | return clk_div | |
221 | | SSCR0_Motorola | |
222 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
223 | | SSCR0_SSE | |
224 | | (bits > 16 ? SSCR0_EDSS : 0); | |
225 | } | |
226 | } | |
227 | ||
a0d2642e MW |
228 | /* |
229 | * Read and write LPSS SSP private registers. Caller must first check that | |
230 | * is_lpss_ssp() returns true before these can be called. | |
231 | */ | |
232 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
233 | { | |
234 | WARN_ON(!drv_data->lpss_base); | |
235 | return readl(drv_data->lpss_base + offset); | |
236 | } | |
237 | ||
238 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
239 | unsigned offset, u32 value) | |
240 | { | |
241 | WARN_ON(!drv_data->lpss_base); | |
242 | writel(value, drv_data->lpss_base + offset); | |
243 | } | |
244 | ||
245 | /* | |
246 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
247 | * @drv_data: pointer to the driver private data | |
248 | * | |
249 | * Perform LPSS SSP specific setup. This function must be called first if | |
250 | * one is going to use LPSS SSP private registers. | |
251 | */ | |
252 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
253 | { | |
dccf7369 JN |
254 | const struct lpss_config *config; |
255 | u32 value; | |
a0d2642e | 256 | |
dccf7369 JN |
257 | config = lpss_get_config(drv_data); |
258 | drv_data->lpss_base = drv_data->ioaddr + config->offset; | |
a0d2642e MW |
259 | |
260 | /* Enable software chip select control */ | |
0e897218 | 261 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
624ea72e JN |
262 | value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); |
263 | value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; | |
dccf7369 | 264 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
0054e28d MW |
265 | |
266 | /* Enable multiblock DMA transfers */ | |
1de70612 | 267 | if (drv_data->master_info->enable_dma) { |
dccf7369 | 268 | __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); |
1de70612 | 269 | |
82ba2c2a JN |
270 | if (config->reg_general >= 0) { |
271 | value = __lpss_ssp_read_priv(drv_data, | |
272 | config->reg_general); | |
624ea72e | 273 | value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; |
82ba2c2a JN |
274 | __lpss_ssp_write_priv(drv_data, |
275 | config->reg_general, value); | |
276 | } | |
1de70612 | 277 | } |
a0d2642e MW |
278 | } |
279 | ||
280 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
281 | { | |
dccf7369 | 282 | const struct lpss_config *config; |
d0283eb2 | 283 | u32 value, cs; |
a0d2642e | 284 | |
dccf7369 JN |
285 | config = lpss_get_config(drv_data); |
286 | ||
287 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); | |
d0283eb2 JN |
288 | if (enable) { |
289 | cs = drv_data->cur_msg->spi->chip_select; | |
290 | cs <<= LPSS_CS_CONTROL_CS_SEL_SHIFT; | |
291 | if (cs != (value & LPSS_CS_CONTROL_CS_SEL_MASK)) { | |
292 | /* | |
293 | * When switching another chip select output active | |
294 | * the output must be selected first and wait 2 ssp_clk | |
295 | * cycles before changing state to active. Otherwise | |
296 | * a short glitch will occur on the previous chip | |
297 | * select since output select is latched but state | |
298 | * control is not. | |
299 | */ | |
300 | value &= ~LPSS_CS_CONTROL_CS_SEL_MASK; | |
301 | value |= cs; | |
302 | __lpss_ssp_write_priv(drv_data, | |
303 | config->reg_cs_ctrl, value); | |
304 | ndelay(1000000000 / | |
305 | (drv_data->master->max_speed_hz / 2)); | |
306 | } | |
624ea72e | 307 | value &= ~LPSS_CS_CONTROL_CS_HIGH; |
d0283eb2 | 308 | } else { |
624ea72e | 309 | value |= LPSS_CS_CONTROL_CS_HIGH; |
d0283eb2 | 310 | } |
dccf7369 | 311 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
a0d2642e MW |
312 | } |
313 | ||
a7bb3909 EM |
314 | static void cs_assert(struct driver_data *drv_data) |
315 | { | |
316 | struct chip_data *chip = drv_data->cur_chip; | |
317 | ||
2a8626a9 | 318 | if (drv_data->ssp_type == CE4100_SSP) { |
c039dd27 | 319 | pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm); |
2a8626a9 SAS |
320 | return; |
321 | } | |
322 | ||
a7bb3909 EM |
323 | if (chip->cs_control) { |
324 | chip->cs_control(PXA2XX_CS_ASSERT); | |
325 | return; | |
326 | } | |
327 | ||
a0d2642e | 328 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 329 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
330 | return; |
331 | } | |
332 | ||
7566bcc7 JN |
333 | if (is_lpss_ssp(drv_data)) |
334 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
335 | } |
336 | ||
337 | static void cs_deassert(struct driver_data *drv_data) | |
338 | { | |
339 | struct chip_data *chip = drv_data->cur_chip; | |
340 | ||
2a8626a9 SAS |
341 | if (drv_data->ssp_type == CE4100_SSP) |
342 | return; | |
343 | ||
a7bb3909 | 344 | if (chip->cs_control) { |
2b2562d3 | 345 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
346 | return; |
347 | } | |
348 | ||
a0d2642e | 349 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 350 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
351 | return; |
352 | } | |
353 | ||
7566bcc7 JN |
354 | if (is_lpss_ssp(drv_data)) |
355 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
356 | } |
357 | ||
cd7bed00 | 358 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
359 | { |
360 | unsigned long limit = loops_per_jiffy << 1; | |
361 | ||
e0c9905e | 362 | do { |
c039dd27 JN |
363 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
364 | pxa2xx_spi_read(drv_data, SSDR); | |
365 | } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); | |
2a8626a9 | 366 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
367 | |
368 | return limit; | |
369 | } | |
370 | ||
8d94cc50 | 371 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 372 | { |
9708c121 | 373 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 374 | |
4fdb2424 | 375 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
376 | || (drv_data->tx == drv_data->tx_end)) |
377 | return 0; | |
378 | ||
c039dd27 | 379 | pxa2xx_spi_write(drv_data, SSDR, 0); |
8d94cc50 SS |
380 | drv_data->tx += n_bytes; |
381 | ||
382 | return 1; | |
e0c9905e SS |
383 | } |
384 | ||
8d94cc50 | 385 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 386 | { |
9708c121 | 387 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 388 | |
c039dd27 JN |
389 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
390 | && (drv_data->rx < drv_data->rx_end)) { | |
391 | pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
392 | drv_data->rx += n_bytes; |
393 | } | |
8d94cc50 SS |
394 | |
395 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
396 | } |
397 | ||
8d94cc50 | 398 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 399 | { |
4fdb2424 | 400 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
401 | || (drv_data->tx == drv_data->tx_end)) |
402 | return 0; | |
403 | ||
c039dd27 | 404 | pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); |
8d94cc50 SS |
405 | ++drv_data->tx; |
406 | ||
407 | return 1; | |
e0c9905e SS |
408 | } |
409 | ||
8d94cc50 | 410 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 411 | { |
c039dd27 JN |
412 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
413 | && (drv_data->rx < drv_data->rx_end)) { | |
414 | *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
415 | ++drv_data->rx; |
416 | } | |
8d94cc50 SS |
417 | |
418 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
419 | } |
420 | ||
8d94cc50 | 421 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 422 | { |
4fdb2424 | 423 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
424 | || (drv_data->tx == drv_data->tx_end)) |
425 | return 0; | |
426 | ||
c039dd27 | 427 | pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); |
8d94cc50 SS |
428 | drv_data->tx += 2; |
429 | ||
430 | return 1; | |
e0c9905e SS |
431 | } |
432 | ||
8d94cc50 | 433 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 434 | { |
c039dd27 JN |
435 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
436 | && (drv_data->rx < drv_data->rx_end)) { | |
437 | *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
438 | drv_data->rx += 2; |
439 | } | |
8d94cc50 SS |
440 | |
441 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 442 | } |
8d94cc50 SS |
443 | |
444 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 445 | { |
4fdb2424 | 446 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
447 | || (drv_data->tx == drv_data->tx_end)) |
448 | return 0; | |
449 | ||
c039dd27 | 450 | pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); |
8d94cc50 SS |
451 | drv_data->tx += 4; |
452 | ||
453 | return 1; | |
e0c9905e SS |
454 | } |
455 | ||
8d94cc50 | 456 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 457 | { |
c039dd27 JN |
458 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
459 | && (drv_data->rx < drv_data->rx_end)) { | |
460 | *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
461 | drv_data->rx += 4; |
462 | } | |
8d94cc50 SS |
463 | |
464 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
465 | } |
466 | ||
cd7bed00 | 467 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
468 | { |
469 | struct spi_message *msg = drv_data->cur_msg; | |
470 | struct spi_transfer *trans = drv_data->cur_transfer; | |
471 | ||
472 | /* Move to next transfer */ | |
473 | if (trans->transfer_list.next != &msg->transfers) { | |
474 | drv_data->cur_transfer = | |
475 | list_entry(trans->transfer_list.next, | |
476 | struct spi_transfer, | |
477 | transfer_list); | |
478 | return RUNNING_STATE; | |
479 | } else | |
480 | return DONE_STATE; | |
481 | } | |
482 | ||
e0c9905e | 483 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 484 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
485 | { |
486 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 487 | struct spi_message *msg; |
e0c9905e | 488 | |
5daa3ba0 SS |
489 | msg = drv_data->cur_msg; |
490 | drv_data->cur_msg = NULL; | |
491 | drv_data->cur_transfer = NULL; | |
5daa3ba0 | 492 | |
23e2c2aa | 493 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e0c9905e SS |
494 | transfer_list); |
495 | ||
8423597d NF |
496 | /* Delay if requested before any change in chip select */ |
497 | if (last_transfer->delay_usecs) | |
498 | udelay(last_transfer->delay_usecs); | |
499 | ||
500 | /* Drop chip select UNLESS cs_change is true or we are returning | |
501 | * a message with an error, or next message is for another chip | |
502 | */ | |
e0c9905e | 503 | if (!last_transfer->cs_change) |
a7bb3909 | 504 | cs_deassert(drv_data); |
8423597d NF |
505 | else { |
506 | struct spi_message *next_msg; | |
507 | ||
508 | /* Holding of cs was hinted, but we need to make sure | |
509 | * the next message is for the same chip. Don't waste | |
510 | * time with the following tests unless this was hinted. | |
511 | * | |
512 | * We cannot postpone this until pump_messages, because | |
513 | * after calling msg->complete (below) the driver that | |
514 | * sent the current message could be unloaded, which | |
515 | * could invalidate the cs_control() callback... | |
516 | */ | |
517 | ||
518 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 519 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
520 | |
521 | /* see if the next and current messages point | |
522 | * to the same chip | |
523 | */ | |
524 | if (next_msg && next_msg->spi != msg->spi) | |
525 | next_msg = NULL; | |
526 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 527 | cs_deassert(drv_data); |
8423597d | 528 | } |
e0c9905e | 529 | |
a7bb3909 | 530 | drv_data->cur_chip = NULL; |
c957e8f0 | 531 | spi_finalize_current_message(drv_data->master); |
e0c9905e SS |
532 | } |
533 | ||
579d3bb2 SAS |
534 | static void reset_sccr1(struct driver_data *drv_data) |
535 | { | |
579d3bb2 SAS |
536 | struct chip_data *chip = drv_data->cur_chip; |
537 | u32 sccr1_reg; | |
538 | ||
c039dd27 | 539 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; |
579d3bb2 SAS |
540 | sccr1_reg &= ~SSCR1_RFT; |
541 | sccr1_reg |= chip->threshold; | |
c039dd27 | 542 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
579d3bb2 SAS |
543 | } |
544 | ||
8d94cc50 | 545 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 546 | { |
8d94cc50 | 547 | /* Stop and reset SSP */ |
2a8626a9 | 548 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 549 | reset_sccr1(drv_data); |
2a8626a9 | 550 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 551 | pxa2xx_spi_write(drv_data, SSTO, 0); |
cd7bed00 | 552 | pxa2xx_spi_flush(drv_data); |
c039dd27 JN |
553 | pxa2xx_spi_write(drv_data, SSCR0, |
554 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
e0c9905e | 555 | |
8d94cc50 | 556 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 557 | |
8d94cc50 SS |
558 | drv_data->cur_msg->state = ERROR_STATE; |
559 | tasklet_schedule(&drv_data->pump_transfers); | |
560 | } | |
5daa3ba0 | 561 | |
8d94cc50 SS |
562 | static void int_transfer_complete(struct driver_data *drv_data) |
563 | { | |
8d94cc50 | 564 | /* Stop SSP */ |
2a8626a9 | 565 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 566 | reset_sccr1(drv_data); |
2a8626a9 | 567 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 568 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e0c9905e | 569 | |
25985edc | 570 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
571 | drv_data->cur_msg->actual_length += drv_data->len - |
572 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 573 | |
8423597d NF |
574 | /* Transfer delays and chip select release are |
575 | * handled in pump_transfers or giveback | |
576 | */ | |
e0c9905e | 577 | |
8d94cc50 | 578 | /* Move to next transfer */ |
cd7bed00 | 579 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 580 | |
8d94cc50 SS |
581 | /* Schedule transfer tasklet */ |
582 | tasklet_schedule(&drv_data->pump_transfers); | |
583 | } | |
e0c9905e | 584 | |
8d94cc50 SS |
585 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
586 | { | |
c039dd27 JN |
587 | u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? |
588 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 589 | |
c039dd27 | 590 | u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; |
e0c9905e | 591 | |
8d94cc50 SS |
592 | if (irq_status & SSSR_ROR) { |
593 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
594 | return IRQ_HANDLED; | |
595 | } | |
e0c9905e | 596 | |
8d94cc50 | 597 | if (irq_status & SSSR_TINT) { |
c039dd27 | 598 | pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); |
8d94cc50 SS |
599 | if (drv_data->read(drv_data)) { |
600 | int_transfer_complete(drv_data); | |
601 | return IRQ_HANDLED; | |
602 | } | |
603 | } | |
e0c9905e | 604 | |
8d94cc50 SS |
605 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
606 | do { | |
607 | if (drv_data->read(drv_data)) { | |
608 | int_transfer_complete(drv_data); | |
609 | return IRQ_HANDLED; | |
610 | } | |
611 | } while (drv_data->write(drv_data)); | |
e0c9905e | 612 | |
8d94cc50 SS |
613 | if (drv_data->read(drv_data)) { |
614 | int_transfer_complete(drv_data); | |
615 | return IRQ_HANDLED; | |
616 | } | |
e0c9905e | 617 | |
8d94cc50 | 618 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
619 | u32 bytes_left; |
620 | u32 sccr1_reg; | |
621 | ||
c039dd27 | 622 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
579d3bb2 SAS |
623 | sccr1_reg &= ~SSCR1_TIE; |
624 | ||
625 | /* | |
626 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 627 | * remaining RX bytes. |
579d3bb2 | 628 | */ |
2a8626a9 | 629 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 630 | u32 rx_thre; |
579d3bb2 | 631 | |
4fdb2424 | 632 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
633 | |
634 | bytes_left = drv_data->rx_end - drv_data->rx; | |
635 | switch (drv_data->n_bytes) { | |
636 | case 4: | |
637 | bytes_left >>= 1; | |
638 | case 2: | |
639 | bytes_left >>= 1; | |
8d94cc50 | 640 | } |
579d3bb2 | 641 | |
4fdb2424 WC |
642 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
643 | if (rx_thre > bytes_left) | |
644 | rx_thre = bytes_left; | |
579d3bb2 | 645 | |
4fdb2424 | 646 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 647 | } |
c039dd27 | 648 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
e0c9905e SS |
649 | } |
650 | ||
5daa3ba0 SS |
651 | /* We did something */ |
652 | return IRQ_HANDLED; | |
e0c9905e SS |
653 | } |
654 | ||
7d12e780 | 655 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 656 | { |
c7bec5ab | 657 | struct driver_data *drv_data = dev_id; |
7d94a505 | 658 | u32 sccr1_reg; |
49cbb1e0 SAS |
659 | u32 mask = drv_data->mask_sr; |
660 | u32 status; | |
661 | ||
7d94a505 MW |
662 | /* |
663 | * The IRQ might be shared with other peripherals so we must first | |
664 | * check that are we RPM suspended or not. If we are we assume that | |
665 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
666 | * interrupt is enabled). | |
667 | */ | |
668 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
669 | return IRQ_NONE; | |
670 | ||
269e4a41 MW |
671 | /* |
672 | * If the device is not yet in RPM suspended state and we get an | |
673 | * interrupt that is meant for another device, check if status bits | |
674 | * are all set to one. That means that the device is already | |
675 | * powered off. | |
676 | */ | |
c039dd27 | 677 | status = pxa2xx_spi_read(drv_data, SSSR); |
269e4a41 MW |
678 | if (status == ~0) |
679 | return IRQ_NONE; | |
680 | ||
c039dd27 | 681 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
49cbb1e0 SAS |
682 | |
683 | /* Ignore possible writes if we don't need to write */ | |
684 | if (!(sccr1_reg & SSCR1_TIE)) | |
685 | mask &= ~SSSR_TFS; | |
686 | ||
687 | if (!(status & mask)) | |
688 | return IRQ_NONE; | |
e0c9905e SS |
689 | |
690 | if (!drv_data->cur_msg) { | |
5daa3ba0 | 691 | |
c039dd27 JN |
692 | pxa2xx_spi_write(drv_data, SSCR0, |
693 | pxa2xx_spi_read(drv_data, SSCR0) | |
694 | & ~SSCR0_SSE); | |
695 | pxa2xx_spi_write(drv_data, SSCR1, | |
696 | pxa2xx_spi_read(drv_data, SSCR1) | |
697 | & ~drv_data->int_cr1); | |
2a8626a9 | 698 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 699 | pxa2xx_spi_write(drv_data, SSTO, 0); |
2a8626a9 | 700 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 701 | |
f6bd03a7 JN |
702 | dev_err(&drv_data->pdev->dev, |
703 | "bad message state in interrupt handler\n"); | |
5daa3ba0 | 704 | |
e0c9905e SS |
705 | /* Never fail */ |
706 | return IRQ_HANDLED; | |
707 | } | |
708 | ||
709 | return drv_data->transfer_handler(drv_data); | |
710 | } | |
711 | ||
e5262d05 | 712 | /* |
9df461ec AS |
713 | * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply |
714 | * input frequency by fractions of 2^24. It also has a divider by 5. | |
715 | * | |
716 | * There are formulas to get baud rate value for given input frequency and | |
717 | * divider parameters, such as DDS_CLK_RATE and SCR: | |
718 | * | |
719 | * Fsys = 200MHz | |
720 | * | |
721 | * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) | |
722 | * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) | |
723 | * | |
724 | * DDS_CLK_RATE either 2^n or 2^n / 5. | |
725 | * SCR is in range 0 .. 255 | |
726 | * | |
727 | * Divisor = 5^i * 2^j * 2 * k | |
728 | * i = [0, 1] i = 1 iff j = 0 or j > 3 | |
729 | * j = [0, 23] j = 0 iff i = 1 | |
730 | * k = [1, 256] | |
731 | * Special case: j = 0, i = 1: Divisor = 2 / 5 | |
732 | * | |
733 | * Accordingly to the specification the recommended values for DDS_CLK_RATE | |
734 | * are: | |
735 | * Case 1: 2^n, n = [0, 23] | |
736 | * Case 2: 2^24 * 2 / 5 (0x666666) | |
737 | * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) | |
738 | * | |
739 | * In all cases the lowest possible value is better. | |
740 | * | |
741 | * The function calculates parameters for all cases and chooses the one closest | |
742 | * to the asked baud rate. | |
e5262d05 | 743 | */ |
9df461ec AS |
744 | static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) |
745 | { | |
746 | unsigned long xtal = 200000000; | |
747 | unsigned long fref = xtal / 2; /* mandatory division by 2, | |
748 | see (2) */ | |
749 | /* case 3 */ | |
750 | unsigned long fref1 = fref / 2; /* case 1 */ | |
751 | unsigned long fref2 = fref * 2 / 5; /* case 2 */ | |
752 | unsigned long scale; | |
753 | unsigned long q, q1, q2; | |
754 | long r, r1, r2; | |
755 | u32 mul; | |
756 | ||
757 | /* Case 1 */ | |
758 | ||
759 | /* Set initial value for DDS_CLK_RATE */ | |
760 | mul = (1 << 24) >> 1; | |
761 | ||
762 | /* Calculate initial quot */ | |
3ad48062 | 763 | q1 = DIV_ROUND_UP(fref1, rate); |
9df461ec AS |
764 | |
765 | /* Scale q1 if it's too big */ | |
766 | if (q1 > 256) { | |
767 | /* Scale q1 to range [1, 512] */ | |
768 | scale = fls_long(q1 - 1); | |
769 | if (scale > 9) { | |
770 | q1 >>= scale - 9; | |
771 | mul >>= scale - 9; | |
e5262d05 | 772 | } |
9df461ec AS |
773 | |
774 | /* Round the result if we have a remainder */ | |
775 | q1 += q1 & 1; | |
776 | } | |
777 | ||
778 | /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ | |
779 | scale = __ffs(q1); | |
780 | q1 >>= scale; | |
781 | mul >>= scale; | |
782 | ||
783 | /* Get the remainder */ | |
784 | r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); | |
785 | ||
786 | /* Case 2 */ | |
787 | ||
3ad48062 | 788 | q2 = DIV_ROUND_UP(fref2, rate); |
9df461ec AS |
789 | r2 = abs(fref2 / q2 - rate); |
790 | ||
791 | /* | |
792 | * Choose the best between two: less remainder we have the better. We | |
793 | * can't go case 2 if q2 is greater than 256 since SCR register can | |
794 | * hold only values 0 .. 255. | |
795 | */ | |
796 | if (r2 >= r1 || q2 > 256) { | |
797 | /* case 1 is better */ | |
798 | r = r1; | |
799 | q = q1; | |
800 | } else { | |
801 | /* case 2 is better */ | |
802 | r = r2; | |
803 | q = q2; | |
804 | mul = (1 << 24) * 2 / 5; | |
e5262d05 WC |
805 | } |
806 | ||
3ad48062 | 807 | /* Check case 3 only if the divisor is big enough */ |
9df461ec AS |
808 | if (fref / rate >= 80) { |
809 | u64 fssp; | |
810 | u32 m; | |
811 | ||
812 | /* Calculate initial quot */ | |
3ad48062 | 813 | q1 = DIV_ROUND_UP(fref, rate); |
9df461ec AS |
814 | m = (1 << 24) / q1; |
815 | ||
816 | /* Get the remainder */ | |
817 | fssp = (u64)fref * m; | |
818 | do_div(fssp, 1 << 24); | |
819 | r1 = abs(fssp - rate); | |
820 | ||
821 | /* Choose this one if it suits better */ | |
822 | if (r1 < r) { | |
823 | /* case 3 is better */ | |
824 | q = 1; | |
825 | mul = m; | |
826 | } | |
827 | } | |
e5262d05 | 828 | |
9df461ec AS |
829 | *dds = mul; |
830 | return q - 1; | |
e5262d05 WC |
831 | } |
832 | ||
3343b7a6 | 833 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 834 | { |
0eca7cf2 | 835 | unsigned long ssp_clk = drv_data->master->max_speed_hz; |
3343b7a6 MW |
836 | const struct ssp_device *ssp = drv_data->ssp; |
837 | ||
838 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 839 | |
2a8626a9 | 840 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
025ffe88 | 841 | return (ssp_clk / (2 * rate) - 1) & 0xff; |
2f1a74e5 | 842 | else |
025ffe88 | 843 | return (ssp_clk / rate - 1) & 0xfff; |
2f1a74e5 | 844 | } |
845 | ||
e5262d05 | 846 | static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, |
d2c2f6a4 | 847 | int rate) |
e5262d05 | 848 | { |
d2c2f6a4 | 849 | struct chip_data *chip = drv_data->cur_chip; |
025ffe88 | 850 | unsigned int clk_div; |
e5262d05 WC |
851 | |
852 | switch (drv_data->ssp_type) { | |
853 | case QUARK_X1000_SSP: | |
9df461ec | 854 | clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); |
eecacf73 | 855 | break; |
e5262d05 | 856 | default: |
025ffe88 | 857 | clk_div = ssp_get_clk_div(drv_data, rate); |
eecacf73 | 858 | break; |
e5262d05 | 859 | } |
025ffe88 | 860 | return clk_div << 8; |
e5262d05 WC |
861 | } |
862 | ||
e0c9905e SS |
863 | static void pump_transfers(unsigned long data) |
864 | { | |
865 | struct driver_data *drv_data = (struct driver_data *)data; | |
866 | struct spi_message *message = NULL; | |
867 | struct spi_transfer *transfer = NULL; | |
868 | struct spi_transfer *previous = NULL; | |
869 | struct chip_data *chip = NULL; | |
9708c121 SS |
870 | u32 clk_div = 0; |
871 | u8 bits = 0; | |
872 | u32 speed = 0; | |
873 | u32 cr0; | |
8d94cc50 SS |
874 | u32 cr1; |
875 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
876 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
4fdb2424 | 877 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); |
e0c9905e SS |
878 | |
879 | /* Get current state information */ | |
880 | message = drv_data->cur_msg; | |
881 | transfer = drv_data->cur_transfer; | |
882 | chip = drv_data->cur_chip; | |
883 | ||
884 | /* Handle for abort */ | |
885 | if (message->state == ERROR_STATE) { | |
886 | message->status = -EIO; | |
5daa3ba0 | 887 | giveback(drv_data); |
e0c9905e SS |
888 | return; |
889 | } | |
890 | ||
891 | /* Handle end of message */ | |
892 | if (message->state == DONE_STATE) { | |
893 | message->status = 0; | |
5daa3ba0 | 894 | giveback(drv_data); |
e0c9905e SS |
895 | return; |
896 | } | |
897 | ||
8423597d | 898 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
899 | if (message->state == RUNNING_STATE) { |
900 | previous = list_entry(transfer->transfer_list.prev, | |
901 | struct spi_transfer, | |
902 | transfer_list); | |
903 | if (previous->delay_usecs) | |
904 | udelay(previous->delay_usecs); | |
8423597d NF |
905 | |
906 | /* Drop chip select only if cs_change is requested */ | |
907 | if (previous->cs_change) | |
a7bb3909 | 908 | cs_deassert(drv_data); |
e0c9905e SS |
909 | } |
910 | ||
cd7bed00 MW |
911 | /* Check if we can DMA this transfer */ |
912 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
913 | |
914 | /* reject already-mapped transfers; PIO won't always work */ | |
915 | if (message->is_dma_mapped | |
916 | || transfer->rx_dma || transfer->tx_dma) { | |
917 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
918 | "pump_transfers: mapped transfer length of " |
919 | "%u is greater than %d\n", | |
7e964455 NF |
920 | transfer->len, MAX_DMA_LEN); |
921 | message->status = -EINVAL; | |
922 | giveback(drv_data); | |
923 | return; | |
924 | } | |
925 | ||
926 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
927 | dev_warn_ratelimited(&message->spi->dev, |
928 | "pump_transfers: DMA disabled for transfer length %ld " | |
929 | "greater than %d\n", | |
930 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
931 | } |
932 | ||
e0c9905e | 933 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 934 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
935 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
936 | message->status = -EIO; | |
5daa3ba0 | 937 | giveback(drv_data); |
e0c9905e SS |
938 | return; |
939 | } | |
9708c121 | 940 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
941 | drv_data->tx = (void *)transfer->tx_buf; |
942 | drv_data->tx_end = drv_data->tx + transfer->len; | |
943 | drv_data->rx = transfer->rx_buf; | |
944 | drv_data->rx_end = drv_data->rx + transfer->len; | |
945 | drv_data->rx_dma = transfer->rx_dma; | |
946 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 947 | drv_data->len = transfer->len; |
e0c9905e SS |
948 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
949 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
950 | |
951 | /* Change speed and bit per word on a per transfer */ | |
196b0e2c JN |
952 | bits = transfer->bits_per_word; |
953 | speed = transfer->speed_hz; | |
954 | ||
d2c2f6a4 | 955 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); |
196b0e2c JN |
956 | |
957 | if (bits <= 8) { | |
958 | drv_data->n_bytes = 1; | |
959 | drv_data->read = drv_data->read != null_reader ? | |
960 | u8_reader : null_reader; | |
961 | drv_data->write = drv_data->write != null_writer ? | |
962 | u8_writer : null_writer; | |
963 | } else if (bits <= 16) { | |
964 | drv_data->n_bytes = 2; | |
965 | drv_data->read = drv_data->read != null_reader ? | |
966 | u16_reader : null_reader; | |
967 | drv_data->write = drv_data->write != null_writer ? | |
968 | u16_writer : null_writer; | |
969 | } else if (bits <= 32) { | |
970 | drv_data->n_bytes = 4; | |
971 | drv_data->read = drv_data->read != null_reader ? | |
972 | u32_reader : null_reader; | |
973 | drv_data->write = drv_data->write != null_writer ? | |
974 | u32_writer : null_writer; | |
9708c121 | 975 | } |
196b0e2c JN |
976 | /* |
977 | * if bits/word is changed in dma mode, then must check the | |
978 | * thresholds and burst also | |
979 | */ | |
980 | if (chip->enable_dma) { | |
981 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, | |
982 | message->spi, | |
983 | bits, &dma_burst, | |
984 | &dma_thresh)) | |
985 | dev_warn_ratelimited(&message->spi->dev, | |
986 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
987 | } | |
988 | ||
d74c4b1c | 989 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
196b0e2c | 990 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); |
d74c4b1c AS |
991 | if (!pxa25x_ssp_comp(drv_data)) |
992 | dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", | |
993 | drv_data->master->max_speed_hz | |
994 | / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), | |
995 | chip->enable_dma ? "DMA" : "PIO"); | |
996 | else | |
997 | dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", | |
998 | drv_data->master->max_speed_hz / 2 | |
999 | / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), | |
1000 | chip->enable_dma ? "DMA" : "PIO"); | |
9708c121 | 1001 | |
e0c9905e SS |
1002 | message->state = RUNNING_STATE; |
1003 | ||
7e964455 | 1004 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
1005 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
1006 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 1007 | if (drv_data->dma_mapped) { |
e0c9905e SS |
1008 | |
1009 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
1010 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
1011 | ||
1012 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 1013 | |
8d94cc50 SS |
1014 | /* Clear status and start DMA engine */ |
1015 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
c039dd27 | 1016 | pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); |
cd7bed00 MW |
1017 | |
1018 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
1019 | } else { |
1020 | /* Ensure we have the correct interrupt handler */ | |
1021 | drv_data->transfer_handler = interrupt_transfer; | |
1022 | ||
8d94cc50 SS |
1023 | /* Clear status */ |
1024 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 1025 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
1026 | } |
1027 | ||
a0d2642e | 1028 | if (is_lpss_ssp(drv_data)) { |
c039dd27 JN |
1029 | if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) |
1030 | != chip->lpss_rx_threshold) | |
1031 | pxa2xx_spi_write(drv_data, SSIRF, | |
1032 | chip->lpss_rx_threshold); | |
1033 | if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) | |
1034 | != chip->lpss_tx_threshold) | |
1035 | pxa2xx_spi_write(drv_data, SSITF, | |
1036 | chip->lpss_tx_threshold); | |
a0d2642e MW |
1037 | } |
1038 | ||
e5262d05 | 1039 | if (is_quark_x1000_ssp(drv_data) && |
c039dd27 JN |
1040 | (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) |
1041 | pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); | |
e5262d05 | 1042 | |
8d94cc50 | 1043 | /* see if we need to reload the config registers */ |
c039dd27 JN |
1044 | if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) |
1045 | || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) | |
1046 | != (cr1 & change_mask)) { | |
b97c74bd | 1047 | /* stop the SSP, and update the other bits */ |
c039dd27 | 1048 | pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); |
2a8626a9 | 1049 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1050 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
b97c74bd | 1051 | /* first set CR1 without interrupt and service enables */ |
c039dd27 | 1052 | pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); |
b97c74bd | 1053 | /* restart the SSP */ |
c039dd27 | 1054 | pxa2xx_spi_write(drv_data, SSCR0, cr0); |
b97c74bd | 1055 | |
8d94cc50 | 1056 | } else { |
2a8626a9 | 1057 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1058 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
e0c9905e | 1059 | } |
b97c74bd | 1060 | |
a7bb3909 | 1061 | cs_assert(drv_data); |
b97c74bd NF |
1062 | |
1063 | /* after chip select, release the data by enabling service | |
1064 | * requests and interrupts, without changing any mode bits */ | |
c039dd27 | 1065 | pxa2xx_spi_write(drv_data, SSCR1, cr1); |
e0c9905e SS |
1066 | } |
1067 | ||
7f86bde9 MW |
1068 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
1069 | struct spi_message *msg) | |
e0c9905e | 1070 | { |
7f86bde9 | 1071 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 1072 | |
7f86bde9 | 1073 | drv_data->cur_msg = msg; |
e0c9905e SS |
1074 | /* Initial message state*/ |
1075 | drv_data->cur_msg->state = START_STATE; | |
1076 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1077 | struct spi_transfer, | |
1078 | transfer_list); | |
1079 | ||
8d94cc50 SS |
1080 | /* prepare to setup the SSP, in pump_transfers, using the per |
1081 | * chip configuration */ | |
e0c9905e | 1082 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1083 | |
1084 | /* Mark as busy and launch transfers */ | |
1085 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
1086 | return 0; |
1087 | } | |
1088 | ||
7d94a505 MW |
1089 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
1090 | { | |
1091 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1092 | ||
1093 | /* Disable the SSP now */ | |
c039dd27 JN |
1094 | pxa2xx_spi_write(drv_data, SSCR0, |
1095 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
7d94a505 | 1096 | |
7d94a505 MW |
1097 | return 0; |
1098 | } | |
1099 | ||
a7bb3909 EM |
1100 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1101 | struct pxa2xx_spi_chip *chip_info) | |
1102 | { | |
1103 | int err = 0; | |
1104 | ||
1105 | if (chip == NULL || chip_info == NULL) | |
1106 | return 0; | |
1107 | ||
1108 | /* NOTE: setup() can be called multiple times, possibly with | |
1109 | * different chip_info, release previously requested GPIO | |
1110 | */ | |
1111 | if (gpio_is_valid(chip->gpio_cs)) | |
1112 | gpio_free(chip->gpio_cs); | |
1113 | ||
1114 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1115 | if (chip_info->cs_control) { | |
1116 | chip->cs_control = chip_info->cs_control; | |
1117 | return 0; | |
1118 | } | |
1119 | ||
1120 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1121 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1122 | if (err) { | |
f6bd03a7 JN |
1123 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
1124 | chip_info->gpio_cs); | |
a7bb3909 EM |
1125 | return err; |
1126 | } | |
1127 | ||
1128 | chip->gpio_cs = chip_info->gpio_cs; | |
1129 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1130 | ||
1131 | err = gpio_direction_output(chip->gpio_cs, | |
1132 | !chip->gpio_cs_inverted); | |
1133 | } | |
1134 | ||
1135 | return err; | |
1136 | } | |
1137 | ||
e0c9905e SS |
1138 | static int setup(struct spi_device *spi) |
1139 | { | |
1140 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1141 | struct chip_data *chip; | |
dccf7369 | 1142 | const struct lpss_config *config; |
e0c9905e | 1143 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
a0d2642e MW |
1144 | uint tx_thres, tx_hi_thres, rx_thres; |
1145 | ||
e5262d05 WC |
1146 | switch (drv_data->ssp_type) { |
1147 | case QUARK_X1000_SSP: | |
1148 | tx_thres = TX_THRESH_QUARK_X1000_DFLT; | |
1149 | tx_hi_thres = 0; | |
1150 | rx_thres = RX_THRESH_QUARK_X1000_DFLT; | |
1151 | break; | |
03fbf488 JN |
1152 | case LPSS_LPT_SSP: |
1153 | case LPSS_BYT_SSP: | |
34cadd9c | 1154 | case LPSS_SPT_SSP: |
dccf7369 JN |
1155 | config = lpss_get_config(drv_data); |
1156 | tx_thres = config->tx_threshold_lo; | |
1157 | tx_hi_thres = config->tx_threshold_hi; | |
1158 | rx_thres = config->rx_threshold; | |
e5262d05 WC |
1159 | break; |
1160 | default: | |
a0d2642e MW |
1161 | tx_thres = TX_THRESH_DFLT; |
1162 | tx_hi_thres = 0; | |
1163 | rx_thres = RX_THRESH_DFLT; | |
e5262d05 | 1164 | break; |
a0d2642e | 1165 | } |
e0c9905e | 1166 | |
8d94cc50 | 1167 | /* Only alloc on first setup */ |
e0c9905e | 1168 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1169 | if (!chip) { |
e0c9905e | 1170 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 1171 | if (!chip) |
e0c9905e SS |
1172 | return -ENOMEM; |
1173 | ||
2a8626a9 SAS |
1174 | if (drv_data->ssp_type == CE4100_SSP) { |
1175 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
1176 | dev_err(&spi->dev, |
1177 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
1178 | kfree(chip); |
1179 | return -EINVAL; | |
1180 | } | |
1181 | ||
1182 | chip->frm = spi->chip_select; | |
1183 | } else | |
1184 | chip->gpio_cs = -1; | |
e0c9905e | 1185 | chip->enable_dma = 0; |
f1f640a9 | 1186 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1187 | } |
1188 | ||
8d94cc50 SS |
1189 | /* protocol drivers may change the chip settings, so... |
1190 | * if chip_info exists, use it */ | |
1191 | chip_info = spi->controller_data; | |
1192 | ||
e0c9905e | 1193 | /* chip_info isn't always needed */ |
8d94cc50 | 1194 | chip->cr1 = 0; |
e0c9905e | 1195 | if (chip_info) { |
f1f640a9 VS |
1196 | if (chip_info->timeout) |
1197 | chip->timeout = chip_info->timeout; | |
1198 | if (chip_info->tx_threshold) | |
1199 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
1200 | if (chip_info->tx_hi_threshold) |
1201 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
1202 | if (chip_info->rx_threshold) |
1203 | rx_thres = chip_info->rx_threshold; | |
1204 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 1205 | chip->dma_threshold = 0; |
e0c9905e SS |
1206 | if (chip_info->enable_loopback) |
1207 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
1208 | } else if (ACPI_HANDLE(&spi->dev)) { |
1209 | /* | |
1210 | * Slave devices enumerated from ACPI namespace don't | |
1211 | * usually have chip_info but we still might want to use | |
1212 | * DMA with them. | |
1213 | */ | |
1214 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
1215 | } |
1216 | ||
a0d2642e MW |
1217 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
1218 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
1219 | | SSITF_TxHiThresh(tx_hi_thres); | |
1220 | ||
8d94cc50 SS |
1221 | /* set dma burst and threshold outside of chip_info path so that if |
1222 | * chip_info goes away after setting chip->enable_dma, the | |
1223 | * burst and threshold can still respond to changes in bits_per_word */ | |
1224 | if (chip->enable_dma) { | |
1225 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
1226 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1227 | spi->bits_per_word, | |
8d94cc50 SS |
1228 | &chip->dma_burst_size, |
1229 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1230 | dev_warn(&spi->dev, |
1231 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
1232 | } |
1233 | } | |
1234 | ||
e5262d05 WC |
1235 | switch (drv_data->ssp_type) { |
1236 | case QUARK_X1000_SSP: | |
1237 | chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) | |
1238 | & QUARK_X1000_SSCR1_RFT) | |
1239 | | (QUARK_X1000_SSCR1_TxTresh(tx_thres) | |
1240 | & QUARK_X1000_SSCR1_TFT); | |
1241 | break; | |
1242 | default: | |
1243 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | |
1244 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1245 | break; | |
1246 | } | |
1247 | ||
7f6ee1ad JC |
1248 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1249 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1250 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 1251 | |
b833172f MW |
1252 | if (spi->mode & SPI_LOOP) |
1253 | chip->cr1 |= SSCR1_LBM; | |
1254 | ||
e0c9905e SS |
1255 | if (spi->bits_per_word <= 8) { |
1256 | chip->n_bytes = 1; | |
e0c9905e SS |
1257 | chip->read = u8_reader; |
1258 | chip->write = u8_writer; | |
1259 | } else if (spi->bits_per_word <= 16) { | |
1260 | chip->n_bytes = 2; | |
e0c9905e SS |
1261 | chip->read = u16_reader; |
1262 | chip->write = u16_writer; | |
1263 | } else if (spi->bits_per_word <= 32) { | |
e0c9905e | 1264 | chip->n_bytes = 4; |
e0c9905e SS |
1265 | chip->read = u32_reader; |
1266 | chip->write = u32_writer; | |
e0c9905e SS |
1267 | } |
1268 | ||
1269 | spi_set_ctldata(spi, chip); | |
1270 | ||
2a8626a9 SAS |
1271 | if (drv_data->ssp_type == CE4100_SSP) |
1272 | return 0; | |
1273 | ||
a7bb3909 | 1274 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1275 | } |
1276 | ||
0ffa0285 | 1277 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1278 | { |
0ffa0285 | 1279 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1280 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1281 | |
7348d82a DR |
1282 | if (!chip) |
1283 | return; | |
1284 | ||
2a8626a9 | 1285 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1286 | gpio_free(chip->gpio_cs); |
1287 | ||
e0c9905e SS |
1288 | kfree(chip); |
1289 | } | |
1290 | ||
a3496855 | 1291 | #ifdef CONFIG_ACPI |
03fbf488 | 1292 | |
8422ddf7 | 1293 | static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { |
03fbf488 JN |
1294 | { "INT33C0", LPSS_LPT_SSP }, |
1295 | { "INT33C1", LPSS_LPT_SSP }, | |
1296 | { "INT3430", LPSS_LPT_SSP }, | |
1297 | { "INT3431", LPSS_LPT_SSP }, | |
1298 | { "80860F0E", LPSS_BYT_SSP }, | |
1299 | { "8086228E", LPSS_BYT_SSP }, | |
1300 | { }, | |
1301 | }; | |
1302 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1303 | ||
34cadd9c JN |
1304 | /* |
1305 | * PCI IDs of compound devices that integrate both host controller and private | |
1306 | * integrated DMA engine. Please note these are not used in module | |
1307 | * autoloading and probing in this module but matching the LPSS SSP type. | |
1308 | */ | |
1309 | static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { | |
1310 | /* SPT-LP */ | |
1311 | { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, | |
1312 | { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, | |
1313 | /* SPT-H */ | |
1314 | { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, | |
1315 | { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, | |
94e5c23d | 1316 | { }, |
34cadd9c JN |
1317 | }; |
1318 | ||
1319 | static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) | |
1320 | { | |
1321 | struct device *dev = param; | |
1322 | ||
1323 | if (dev != chan->device->dev->parent) | |
1324 | return false; | |
1325 | ||
1326 | return true; | |
1327 | } | |
1328 | ||
a3496855 MW |
1329 | static struct pxa2xx_spi_master * |
1330 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1331 | { | |
1332 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1333 | struct acpi_device *adev; |
1334 | struct ssp_device *ssp; | |
1335 | struct resource *res; | |
34cadd9c JN |
1336 | const struct acpi_device_id *adev_id = NULL; |
1337 | const struct pci_device_id *pcidev_id = NULL; | |
3b8b6d05 JN |
1338 | unsigned int devid; |
1339 | int type; | |
a3496855 | 1340 | |
b9f6940a JN |
1341 | adev = ACPI_COMPANION(&pdev->dev); |
1342 | if (!adev) | |
a3496855 MW |
1343 | return NULL; |
1344 | ||
34cadd9c JN |
1345 | if (dev_is_pci(pdev->dev.parent)) |
1346 | pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, | |
1347 | to_pci_dev(pdev->dev.parent)); | |
1348 | else | |
1349 | adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, | |
1350 | &pdev->dev); | |
1351 | ||
1352 | if (adev_id) | |
1353 | type = (int)adev_id->driver_data; | |
1354 | else if (pcidev_id) | |
1355 | type = (int)pcidev_id->driver_data; | |
03fbf488 JN |
1356 | else |
1357 | return NULL; | |
1358 | ||
cc0ee987 | 1359 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1360 | if (!pdata) |
a3496855 | 1361 | return NULL; |
a3496855 MW |
1362 | |
1363 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1364 | if (!res) | |
1365 | return NULL; | |
1366 | ||
1367 | ssp = &pdata->ssp; | |
1368 | ||
1369 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1370 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1371 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1372 | return NULL; |
a3496855 | 1373 | |
34cadd9c JN |
1374 | if (pcidev_id) { |
1375 | pdata->tx_param = pdev->dev.parent; | |
1376 | pdata->rx_param = pdev->dev.parent; | |
1377 | pdata->dma_filter = pxa2xx_spi_idma_filter; | |
1378 | } | |
1379 | ||
a3496855 MW |
1380 | ssp->clk = devm_clk_get(&pdev->dev, NULL); |
1381 | ssp->irq = platform_get_irq(pdev, 0); | |
03fbf488 | 1382 | ssp->type = type; |
a3496855 MW |
1383 | ssp->pdev = pdev; |
1384 | ||
1385 | ssp->port_id = -1; | |
3b8b6d05 | 1386 | if (adev->pnp.unique_id && !kstrtouint(adev->pnp.unique_id, 0, &devid)) |
a3496855 MW |
1387 | ssp->port_id = devid; |
1388 | ||
1389 | pdata->num_chipselect = 1; | |
cddb339b | 1390 | pdata->enable_dma = true; |
a3496855 MW |
1391 | |
1392 | return pdata; | |
1393 | } | |
1394 | ||
a3496855 MW |
1395 | #else |
1396 | static inline struct pxa2xx_spi_master * | |
1397 | pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev) | |
1398 | { | |
1399 | return NULL; | |
1400 | } | |
1401 | #endif | |
1402 | ||
fd4a319b | 1403 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1404 | { |
1405 | struct device *dev = &pdev->dev; | |
1406 | struct pxa2xx_spi_master *platform_info; | |
1407 | struct spi_master *master; | |
65a00a20 | 1408 | struct driver_data *drv_data; |
2f1a74e5 | 1409 | struct ssp_device *ssp; |
8b136baa | 1410 | const struct lpss_config *config; |
65a00a20 | 1411 | int status; |
c039dd27 | 1412 | u32 tmp; |
e0c9905e | 1413 | |
851bacf5 MW |
1414 | platform_info = dev_get_platdata(dev); |
1415 | if (!platform_info) { | |
a3496855 MW |
1416 | platform_info = pxa2xx_spi_acpi_get_pdata(pdev); |
1417 | if (!platform_info) { | |
1418 | dev_err(&pdev->dev, "missing platform data\n"); | |
1419 | return -ENODEV; | |
1420 | } | |
851bacf5 | 1421 | } |
e0c9905e | 1422 | |
baffe169 | 1423 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1424 | if (!ssp) |
1425 | ssp = &platform_info->ssp; | |
1426 | ||
1427 | if (!ssp->mmio_base) { | |
1428 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1429 | return -ENODEV; |
1430 | } | |
1431 | ||
757fe8d5 | 1432 | master = spi_alloc_master(dev, sizeof(struct driver_data)); |
e0c9905e | 1433 | if (!master) { |
65a00a20 | 1434 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1435 | pxa_ssp_free(ssp); |
e0c9905e SS |
1436 | return -ENOMEM; |
1437 | } | |
1438 | drv_data = spi_master_get_devdata(master); | |
1439 | drv_data->master = master; | |
1440 | drv_data->master_info = platform_info; | |
1441 | drv_data->pdev = pdev; | |
2f1a74e5 | 1442 | drv_data->ssp = ssp; |
e0c9905e | 1443 | |
21486af0 | 1444 | master->dev.parent = &pdev->dev; |
21486af0 | 1445 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1446 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1447 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1448 | |
851bacf5 | 1449 | master->bus_num = ssp->port_id; |
7ad0ba91 | 1450 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1451 | master->cleanup = cleanup; |
1452 | master->setup = setup; | |
7f86bde9 | 1453 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1454 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
7dd62787 | 1455 | master->auto_runtime_pm = true; |
e0c9905e | 1456 | |
2f1a74e5 | 1457 | drv_data->ssp_type = ssp->type; |
e0c9905e | 1458 | |
2f1a74e5 | 1459 | drv_data->ioaddr = ssp->mmio_base; |
1460 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1461 | if (pxa25x_ssp_comp(drv_data)) { |
e5262d05 WC |
1462 | switch (drv_data->ssp_type) { |
1463 | case QUARK_X1000_SSP: | |
1464 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
1465 | break; | |
1466 | default: | |
1467 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
1468 | break; | |
1469 | } | |
1470 | ||
e0c9905e SS |
1471 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1472 | drv_data->dma_cr1 = 0; | |
1473 | drv_data->clear_sr = SSSR_ROR; | |
1474 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1475 | } else { | |
24778be2 | 1476 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1477 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1478 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1479 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1480 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1481 | } | |
1482 | ||
49cbb1e0 SAS |
1483 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1484 | drv_data); | |
e0c9905e | 1485 | if (status < 0) { |
65a00a20 | 1486 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1487 | goto out_error_master_alloc; |
1488 | } | |
1489 | ||
1490 | /* Setup DMA if requested */ | |
e0c9905e | 1491 | if (platform_info->enable_dma) { |
cd7bed00 MW |
1492 | status = pxa2xx_spi_dma_setup(drv_data); |
1493 | if (status) { | |
cddb339b | 1494 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1495 | platform_info->enable_dma = false; |
e0c9905e | 1496 | } |
e0c9905e SS |
1497 | } |
1498 | ||
1499 | /* Enable SOC clock */ | |
3343b7a6 MW |
1500 | clk_prepare_enable(ssp->clk); |
1501 | ||
0eca7cf2 | 1502 | master->max_speed_hz = clk_get_rate(ssp->clk); |
e0c9905e SS |
1503 | |
1504 | /* Load default SSP configuration */ | |
c039dd27 | 1505 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
e5262d05 WC |
1506 | switch (drv_data->ssp_type) { |
1507 | case QUARK_X1000_SSP: | |
c039dd27 JN |
1508 | tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1509 | | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); | |
1510 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
e5262d05 WC |
1511 | |
1512 | /* using the Motorola SPI protocol and use 8 bit frame */ | |
c039dd27 JN |
1513 | pxa2xx_spi_write(drv_data, SSCR0, |
1514 | QUARK_X1000_SSCR0_Motorola | |
1515 | | QUARK_X1000_SSCR0_DataSize(8)); | |
e5262d05 WC |
1516 | break; |
1517 | default: | |
c039dd27 JN |
1518 | tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | |
1519 | SSCR1_TxTresh(TX_THRESH_DFLT); | |
1520 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
1521 | tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); | |
1522 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
e5262d05 WC |
1523 | break; |
1524 | } | |
1525 | ||
2a8626a9 | 1526 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1527 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e5262d05 WC |
1528 | |
1529 | if (!is_quark_x1000_ssp(drv_data)) | |
c039dd27 | 1530 | pxa2xx_spi_write(drv_data, SSPSP, 0); |
e0c9905e | 1531 | |
7566bcc7 JN |
1532 | if (is_lpss_ssp(drv_data)) |
1533 | lpss_ssp_setup(drv_data); | |
a0d2642e | 1534 | |
8b136baa JN |
1535 | if (is_lpss_ssp(drv_data)) { |
1536 | lpss_ssp_setup(drv_data); | |
1537 | config = lpss_get_config(drv_data); | |
1538 | if (config->reg_capabilities >= 0) { | |
1539 | tmp = __lpss_ssp_read_priv(drv_data, | |
1540 | config->reg_capabilities); | |
1541 | tmp &= LPSS_CAPS_CS_EN_MASK; | |
1542 | tmp >>= LPSS_CAPS_CS_EN_SHIFT; | |
1543 | platform_info->num_chipselect = ffz(tmp); | |
1544 | } | |
1545 | } | |
1546 | master->num_chipselect = platform_info->num_chipselect; | |
1547 | ||
7f86bde9 MW |
1548 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1549 | (unsigned long)drv_data); | |
e0c9905e | 1550 | |
836d1a22 AO |
1551 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1552 | pm_runtime_use_autosuspend(&pdev->dev); | |
1553 | pm_runtime_set_active(&pdev->dev); | |
1554 | pm_runtime_enable(&pdev->dev); | |
1555 | ||
e0c9905e SS |
1556 | /* Register with the SPI framework */ |
1557 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1558 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1559 | if (status != 0) { |
1560 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1561 | goto out_error_clock_enabled; |
e0c9905e SS |
1562 | } |
1563 | ||
1564 | return status; | |
1565 | ||
e0c9905e | 1566 | out_error_clock_enabled: |
3343b7a6 | 1567 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1568 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1569 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1570 | |
1571 | out_error_master_alloc: | |
1572 | spi_master_put(master); | |
baffe169 | 1573 | pxa_ssp_free(ssp); |
e0c9905e SS |
1574 | return status; |
1575 | } | |
1576 | ||
1577 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1578 | { | |
1579 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1580 | struct ssp_device *ssp; |
e0c9905e SS |
1581 | |
1582 | if (!drv_data) | |
1583 | return 0; | |
51e911e2 | 1584 | ssp = drv_data->ssp; |
e0c9905e | 1585 | |
7d94a505 MW |
1586 | pm_runtime_get_sync(&pdev->dev); |
1587 | ||
e0c9905e | 1588 | /* Disable the SSP at the peripheral and SOC level */ |
c039dd27 | 1589 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
3343b7a6 | 1590 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1591 | |
1592 | /* Release DMA */ | |
cd7bed00 MW |
1593 | if (drv_data->master_info->enable_dma) |
1594 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1595 | |
7d94a505 MW |
1596 | pm_runtime_put_noidle(&pdev->dev); |
1597 | pm_runtime_disable(&pdev->dev); | |
1598 | ||
e0c9905e | 1599 | /* Release IRQ */ |
2f1a74e5 | 1600 | free_irq(ssp->irq, drv_data); |
1601 | ||
1602 | /* Release SSP */ | |
baffe169 | 1603 | pxa_ssp_free(ssp); |
e0c9905e | 1604 | |
e0c9905e SS |
1605 | return 0; |
1606 | } | |
1607 | ||
1608 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1609 | { | |
1610 | int status = 0; | |
1611 | ||
1612 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1613 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1614 | } | |
1615 | ||
382cebb0 | 1616 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1617 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1618 | { |
86d2593a | 1619 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1620 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1621 | int status = 0; |
1622 | ||
7f86bde9 | 1623 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1624 | if (status != 0) |
1625 | return status; | |
c039dd27 | 1626 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
2b9375b9 DES |
1627 | |
1628 | if (!pm_runtime_suspended(dev)) | |
1629 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1630 | |
1631 | return 0; | |
1632 | } | |
1633 | ||
86d2593a | 1634 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1635 | { |
86d2593a | 1636 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1637 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1638 | int status = 0; |
1639 | ||
1640 | /* Enable the SSP clock */ | |
2b9375b9 DES |
1641 | if (!pm_runtime_suspended(dev)) |
1642 | clk_prepare_enable(ssp->clk); | |
e0c9905e | 1643 | |
c50325f7 | 1644 | /* Restore LPSS private register bits */ |
48421adf JN |
1645 | if (is_lpss_ssp(drv_data)) |
1646 | lpss_ssp_setup(drv_data); | |
c50325f7 | 1647 | |
e0c9905e | 1648 | /* Start the queue running */ |
7f86bde9 | 1649 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1650 | if (status != 0) { |
86d2593a | 1651 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1652 | return status; |
1653 | } | |
1654 | ||
1655 | return 0; | |
1656 | } | |
7d94a505 MW |
1657 | #endif |
1658 | ||
ec833050 | 1659 | #ifdef CONFIG_PM |
7d94a505 MW |
1660 | static int pxa2xx_spi_runtime_suspend(struct device *dev) |
1661 | { | |
1662 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1663 | ||
1664 | clk_disable_unprepare(drv_data->ssp->clk); | |
1665 | return 0; | |
1666 | } | |
1667 | ||
1668 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1669 | { | |
1670 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1671 | ||
1672 | clk_prepare_enable(drv_data->ssp->clk); | |
1673 | return 0; | |
1674 | } | |
1675 | #endif | |
86d2593a | 1676 | |
47145210 | 1677 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1678 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1679 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1680 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1681 | }; |
e0c9905e SS |
1682 | |
1683 | static struct platform_driver driver = { | |
1684 | .driver = { | |
86d2593a | 1685 | .name = "pxa2xx-spi", |
86d2593a | 1686 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1687 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1688 | }, |
fbd29a14 | 1689 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1690 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1691 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1692 | }; |
1693 | ||
1694 | static int __init pxa2xx_spi_init(void) | |
1695 | { | |
fbd29a14 | 1696 | return platform_driver_register(&driver); |
e0c9905e | 1697 | } |
5b61a749 | 1698 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1699 | |
1700 | static void __exit pxa2xx_spi_exit(void) | |
1701 | { | |
1702 | platform_driver_unregister(&driver); | |
1703 | } | |
1704 | module_exit(pxa2xx_spi_exit); |