]>
Commit | Line | Data |
---|---|---|
e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/platform_device.h> | |
8348c259 | 27 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e SS |
28 | #include <linux/spi/spi.h> |
29 | #include <linux/workqueue.h> | |
e0c9905e | 30 | #include <linux/delay.h> |
a7bb3909 | 31 | #include <linux/gpio.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
3343b7a6 | 33 | #include <linux/clk.h> |
7d94a505 | 34 | #include <linux/pm_runtime.h> |
e0c9905e SS |
35 | |
36 | #include <asm/io.h> | |
37 | #include <asm/irq.h> | |
e0c9905e | 38 | #include <asm/delay.h> |
e0c9905e | 39 | |
cd7bed00 | 40 | #include "spi-pxa2xx.h" |
e0c9905e SS |
41 | |
42 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 43 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 44 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 45 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
46 | |
47 | #define MAX_BUSES 3 | |
48 | ||
f1f640a9 VS |
49 | #define TIMOUT_DFLT 1000 |
50 | ||
b97c74bd NF |
51 | /* |
52 | * for testing SSCR1 changes that require SSP restart, basically | |
53 | * everything except the service and interrupt enables, the pxa270 developer | |
54 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
55 | * list, but the PXA255 dev man says all bits without really meaning the | |
56 | * service and interrupt enables | |
57 | */ | |
58 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 59 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
60 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
61 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
62 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
63 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 64 | |
a0d2642e MW |
65 | #define LPSS_RX_THRESH_DFLT 64 |
66 | #define LPSS_TX_LOTHRESH_DFLT 160 | |
67 | #define LPSS_TX_HITHRESH_DFLT 224 | |
68 | ||
69 | /* Offset from drv_data->lpss_base */ | |
70 | #define SPI_CS_CONTROL 0x18 | |
71 | #define SPI_CS_CONTROL_SW_MODE BIT(0) | |
72 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | |
73 | ||
74 | static bool is_lpss_ssp(const struct driver_data *drv_data) | |
75 | { | |
76 | return drv_data->ssp_type == LPSS_SSP; | |
77 | } | |
78 | ||
79 | /* | |
80 | * Read and write LPSS SSP private registers. Caller must first check that | |
81 | * is_lpss_ssp() returns true before these can be called. | |
82 | */ | |
83 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
84 | { | |
85 | WARN_ON(!drv_data->lpss_base); | |
86 | return readl(drv_data->lpss_base + offset); | |
87 | } | |
88 | ||
89 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
90 | unsigned offset, u32 value) | |
91 | { | |
92 | WARN_ON(!drv_data->lpss_base); | |
93 | writel(value, drv_data->lpss_base + offset); | |
94 | } | |
95 | ||
96 | /* | |
97 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
98 | * @drv_data: pointer to the driver private data | |
99 | * | |
100 | * Perform LPSS SSP specific setup. This function must be called first if | |
101 | * one is going to use LPSS SSP private registers. | |
102 | */ | |
103 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
104 | { | |
105 | unsigned offset = 0x400; | |
106 | u32 value, orig; | |
107 | ||
108 | if (!is_lpss_ssp(drv_data)) | |
109 | return; | |
110 | ||
111 | /* | |
112 | * Perform auto-detection of the LPSS SSP private registers. They | |
113 | * can be either at 1k or 2k offset from the base address. | |
114 | */ | |
115 | orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
116 | ||
117 | value = orig | SPI_CS_CONTROL_SW_MODE; | |
118 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
119 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
120 | if (value != (orig | SPI_CS_CONTROL_SW_MODE)) { | |
121 | offset = 0x800; | |
122 | goto detection_done; | |
123 | } | |
124 | ||
125 | value &= ~SPI_CS_CONTROL_SW_MODE; | |
126 | writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
127 | value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); | |
128 | if (value != orig) { | |
129 | offset = 0x800; | |
130 | goto detection_done; | |
131 | } | |
132 | ||
133 | detection_done: | |
134 | /* Now set the LPSS base */ | |
135 | drv_data->lpss_base = drv_data->ioaddr + offset; | |
136 | ||
137 | /* Enable software chip select control */ | |
138 | value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | |
139 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
140 | } | |
141 | ||
142 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |
143 | { | |
144 | u32 value; | |
145 | ||
146 | if (!is_lpss_ssp(drv_data)) | |
147 | return; | |
148 | ||
149 | value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL); | |
150 | if (enable) | |
151 | value &= ~SPI_CS_CONTROL_CS_HIGH; | |
152 | else | |
153 | value |= SPI_CS_CONTROL_CS_HIGH; | |
154 | __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); | |
155 | } | |
156 | ||
a7bb3909 EM |
157 | static void cs_assert(struct driver_data *drv_data) |
158 | { | |
159 | struct chip_data *chip = drv_data->cur_chip; | |
160 | ||
2a8626a9 SAS |
161 | if (drv_data->ssp_type == CE4100_SSP) { |
162 | write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); | |
163 | return; | |
164 | } | |
165 | ||
a7bb3909 EM |
166 | if (chip->cs_control) { |
167 | chip->cs_control(PXA2XX_CS_ASSERT); | |
168 | return; | |
169 | } | |
170 | ||
a0d2642e | 171 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 172 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
173 | return; |
174 | } | |
175 | ||
176 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
177 | } |
178 | ||
179 | static void cs_deassert(struct driver_data *drv_data) | |
180 | { | |
181 | struct chip_data *chip = drv_data->cur_chip; | |
182 | ||
2a8626a9 SAS |
183 | if (drv_data->ssp_type == CE4100_SSP) |
184 | return; | |
185 | ||
a7bb3909 | 186 | if (chip->cs_control) { |
2b2562d3 | 187 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
188 | return; |
189 | } | |
190 | ||
a0d2642e | 191 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 192 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
193 | return; |
194 | } | |
195 | ||
196 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
197 | } |
198 | ||
cd7bed00 | 199 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
200 | { |
201 | unsigned long limit = loops_per_jiffy << 1; | |
202 | ||
cf43369d | 203 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
204 | |
205 | do { | |
206 | while (read_SSSR(reg) & SSSR_RNE) { | |
207 | read_SSDR(reg); | |
208 | } | |
306c68aa | 209 | } while ((read_SSSR(reg) & SSSR_BSY) && --limit); |
2a8626a9 | 210 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
211 | |
212 | return limit; | |
213 | } | |
214 | ||
8d94cc50 | 215 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 216 | { |
cf43369d | 217 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 218 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 219 | |
4a25605f | 220 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
221 | || (drv_data->tx == drv_data->tx_end)) |
222 | return 0; | |
223 | ||
224 | write_SSDR(0, reg); | |
225 | drv_data->tx += n_bytes; | |
226 | ||
227 | return 1; | |
e0c9905e SS |
228 | } |
229 | ||
8d94cc50 | 230 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 231 | { |
cf43369d | 232 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 233 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
234 | |
235 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 236 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
237 | read_SSDR(reg); |
238 | drv_data->rx += n_bytes; | |
239 | } | |
8d94cc50 SS |
240 | |
241 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
242 | } |
243 | ||
8d94cc50 | 244 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 245 | { |
cf43369d | 246 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 247 | |
4a25605f | 248 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
249 | || (drv_data->tx == drv_data->tx_end)) |
250 | return 0; | |
251 | ||
252 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
253 | ++drv_data->tx; | |
254 | ||
255 | return 1; | |
e0c9905e SS |
256 | } |
257 | ||
8d94cc50 | 258 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 259 | { |
cf43369d | 260 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
261 | |
262 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 263 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
264 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
265 | ++drv_data->rx; | |
266 | } | |
8d94cc50 SS |
267 | |
268 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
269 | } |
270 | ||
8d94cc50 | 271 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 272 | { |
cf43369d | 273 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 274 | |
4a25605f | 275 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
276 | || (drv_data->tx == drv_data->tx_end)) |
277 | return 0; | |
278 | ||
279 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
280 | drv_data->tx += 2; | |
281 | ||
282 | return 1; | |
e0c9905e SS |
283 | } |
284 | ||
8d94cc50 | 285 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 286 | { |
cf43369d | 287 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
288 | |
289 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 290 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
291 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
292 | drv_data->rx += 2; | |
293 | } | |
8d94cc50 SS |
294 | |
295 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 296 | } |
8d94cc50 SS |
297 | |
298 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 299 | { |
cf43369d | 300 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 301 | |
4a25605f | 302 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
303 | || (drv_data->tx == drv_data->tx_end)) |
304 | return 0; | |
305 | ||
306 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
307 | drv_data->tx += 4; | |
308 | ||
309 | return 1; | |
e0c9905e SS |
310 | } |
311 | ||
8d94cc50 | 312 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 313 | { |
cf43369d | 314 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
315 | |
316 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 317 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
318 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
319 | drv_data->rx += 4; | |
320 | } | |
8d94cc50 SS |
321 | |
322 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
323 | } |
324 | ||
cd7bed00 | 325 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
326 | { |
327 | struct spi_message *msg = drv_data->cur_msg; | |
328 | struct spi_transfer *trans = drv_data->cur_transfer; | |
329 | ||
330 | /* Move to next transfer */ | |
331 | if (trans->transfer_list.next != &msg->transfers) { | |
332 | drv_data->cur_transfer = | |
333 | list_entry(trans->transfer_list.next, | |
334 | struct spi_transfer, | |
335 | transfer_list); | |
336 | return RUNNING_STATE; | |
337 | } else | |
338 | return DONE_STATE; | |
339 | } | |
340 | ||
e0c9905e | 341 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 342 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
343 | { |
344 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 345 | struct spi_message *msg; |
e0c9905e | 346 | |
5daa3ba0 SS |
347 | msg = drv_data->cur_msg; |
348 | drv_data->cur_msg = NULL; | |
349 | drv_data->cur_transfer = NULL; | |
5daa3ba0 SS |
350 | |
351 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
352 | struct spi_transfer, |
353 | transfer_list); | |
354 | ||
8423597d NF |
355 | /* Delay if requested before any change in chip select */ |
356 | if (last_transfer->delay_usecs) | |
357 | udelay(last_transfer->delay_usecs); | |
358 | ||
359 | /* Drop chip select UNLESS cs_change is true or we are returning | |
360 | * a message with an error, or next message is for another chip | |
361 | */ | |
e0c9905e | 362 | if (!last_transfer->cs_change) |
a7bb3909 | 363 | cs_deassert(drv_data); |
8423597d NF |
364 | else { |
365 | struct spi_message *next_msg; | |
366 | ||
367 | /* Holding of cs was hinted, but we need to make sure | |
368 | * the next message is for the same chip. Don't waste | |
369 | * time with the following tests unless this was hinted. | |
370 | * | |
371 | * We cannot postpone this until pump_messages, because | |
372 | * after calling msg->complete (below) the driver that | |
373 | * sent the current message could be unloaded, which | |
374 | * could invalidate the cs_control() callback... | |
375 | */ | |
376 | ||
377 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 378 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
379 | |
380 | /* see if the next and current messages point | |
381 | * to the same chip | |
382 | */ | |
383 | if (next_msg && next_msg->spi != msg->spi) | |
384 | next_msg = NULL; | |
385 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 386 | cs_deassert(drv_data); |
8423597d | 387 | } |
e0c9905e | 388 | |
7f86bde9 | 389 | spi_finalize_current_message(drv_data->master); |
a7bb3909 | 390 | drv_data->cur_chip = NULL; |
e0c9905e SS |
391 | } |
392 | ||
579d3bb2 SAS |
393 | static void reset_sccr1(struct driver_data *drv_data) |
394 | { | |
395 | void __iomem *reg = drv_data->ioaddr; | |
396 | struct chip_data *chip = drv_data->cur_chip; | |
397 | u32 sccr1_reg; | |
398 | ||
399 | sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; | |
400 | sccr1_reg &= ~SSCR1_RFT; | |
401 | sccr1_reg |= chip->threshold; | |
402 | write_SSCR1(sccr1_reg, reg); | |
403 | } | |
404 | ||
8d94cc50 | 405 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 406 | { |
cf43369d | 407 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 408 | |
8d94cc50 | 409 | /* Stop and reset SSP */ |
2a8626a9 | 410 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 411 | reset_sccr1(drv_data); |
2a8626a9 | 412 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 413 | write_SSTO(0, reg); |
cd7bed00 | 414 | pxa2xx_spi_flush(drv_data); |
8d94cc50 | 415 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); |
e0c9905e | 416 | |
8d94cc50 | 417 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 418 | |
8d94cc50 SS |
419 | drv_data->cur_msg->state = ERROR_STATE; |
420 | tasklet_schedule(&drv_data->pump_transfers); | |
421 | } | |
5daa3ba0 | 422 | |
8d94cc50 SS |
423 | static void int_transfer_complete(struct driver_data *drv_data) |
424 | { | |
cf43369d | 425 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 426 | |
8d94cc50 | 427 | /* Stop SSP */ |
2a8626a9 | 428 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 429 | reset_sccr1(drv_data); |
2a8626a9 | 430 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 431 | write_SSTO(0, reg); |
e0c9905e | 432 | |
25985edc | 433 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
434 | drv_data->cur_msg->actual_length += drv_data->len - |
435 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 436 | |
8423597d NF |
437 | /* Transfer delays and chip select release are |
438 | * handled in pump_transfers or giveback | |
439 | */ | |
e0c9905e | 440 | |
8d94cc50 | 441 | /* Move to next transfer */ |
cd7bed00 | 442 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 443 | |
8d94cc50 SS |
444 | /* Schedule transfer tasklet */ |
445 | tasklet_schedule(&drv_data->pump_transfers); | |
446 | } | |
e0c9905e | 447 | |
8d94cc50 SS |
448 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
449 | { | |
cf43369d | 450 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 451 | |
8d94cc50 SS |
452 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
453 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 454 | |
8d94cc50 | 455 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 456 | |
8d94cc50 SS |
457 | if (irq_status & SSSR_ROR) { |
458 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
459 | return IRQ_HANDLED; | |
460 | } | |
e0c9905e | 461 | |
8d94cc50 SS |
462 | if (irq_status & SSSR_TINT) { |
463 | write_SSSR(SSSR_TINT, reg); | |
464 | if (drv_data->read(drv_data)) { | |
465 | int_transfer_complete(drv_data); | |
466 | return IRQ_HANDLED; | |
467 | } | |
468 | } | |
e0c9905e | 469 | |
8d94cc50 SS |
470 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
471 | do { | |
472 | if (drv_data->read(drv_data)) { | |
473 | int_transfer_complete(drv_data); | |
474 | return IRQ_HANDLED; | |
475 | } | |
476 | } while (drv_data->write(drv_data)); | |
e0c9905e | 477 | |
8d94cc50 SS |
478 | if (drv_data->read(drv_data)) { |
479 | int_transfer_complete(drv_data); | |
480 | return IRQ_HANDLED; | |
481 | } | |
e0c9905e | 482 | |
8d94cc50 | 483 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
484 | u32 bytes_left; |
485 | u32 sccr1_reg; | |
486 | ||
487 | sccr1_reg = read_SSCR1(reg); | |
488 | sccr1_reg &= ~SSCR1_TIE; | |
489 | ||
490 | /* | |
491 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 492 | * remaining RX bytes. |
579d3bb2 | 493 | */ |
2a8626a9 | 494 | if (pxa25x_ssp_comp(drv_data)) { |
579d3bb2 SAS |
495 | |
496 | sccr1_reg &= ~SSCR1_RFT; | |
497 | ||
498 | bytes_left = drv_data->rx_end - drv_data->rx; | |
499 | switch (drv_data->n_bytes) { | |
500 | case 4: | |
501 | bytes_left >>= 1; | |
502 | case 2: | |
503 | bytes_left >>= 1; | |
8d94cc50 | 504 | } |
579d3bb2 SAS |
505 | |
506 | if (bytes_left > RX_THRESH_DFLT) | |
507 | bytes_left = RX_THRESH_DFLT; | |
508 | ||
509 | sccr1_reg |= SSCR1_RxTresh(bytes_left); | |
e0c9905e | 510 | } |
579d3bb2 | 511 | write_SSCR1(sccr1_reg, reg); |
e0c9905e SS |
512 | } |
513 | ||
5daa3ba0 SS |
514 | /* We did something */ |
515 | return IRQ_HANDLED; | |
e0c9905e SS |
516 | } |
517 | ||
7d12e780 | 518 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 519 | { |
c7bec5ab | 520 | struct driver_data *drv_data = dev_id; |
cf43369d | 521 | void __iomem *reg = drv_data->ioaddr; |
7d94a505 | 522 | u32 sccr1_reg; |
49cbb1e0 SAS |
523 | u32 mask = drv_data->mask_sr; |
524 | u32 status; | |
525 | ||
7d94a505 MW |
526 | /* |
527 | * The IRQ might be shared with other peripherals so we must first | |
528 | * check that are we RPM suspended or not. If we are we assume that | |
529 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
530 | * interrupt is enabled). | |
531 | */ | |
532 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
533 | return IRQ_NONE; | |
534 | ||
535 | sccr1_reg = read_SSCR1(reg); | |
49cbb1e0 SAS |
536 | status = read_SSSR(reg); |
537 | ||
538 | /* Ignore possible writes if we don't need to write */ | |
539 | if (!(sccr1_reg & SSCR1_TIE)) | |
540 | mask &= ~SSSR_TFS; | |
541 | ||
542 | if (!(status & mask)) | |
543 | return IRQ_NONE; | |
e0c9905e SS |
544 | |
545 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
546 | |
547 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
548 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
2a8626a9 | 549 | if (!pxa25x_ssp_comp(drv_data)) |
5daa3ba0 | 550 | write_SSTO(0, reg); |
2a8626a9 | 551 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 552 | |
e0c9905e | 553 | dev_err(&drv_data->pdev->dev, "bad message state " |
8d94cc50 | 554 | "in interrupt handler\n"); |
5daa3ba0 | 555 | |
e0c9905e SS |
556 | /* Never fail */ |
557 | return IRQ_HANDLED; | |
558 | } | |
559 | ||
560 | return drv_data->transfer_handler(drv_data); | |
561 | } | |
562 | ||
3343b7a6 | 563 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 564 | { |
3343b7a6 MW |
565 | unsigned long ssp_clk = drv_data->max_clk_rate; |
566 | const struct ssp_device *ssp = drv_data->ssp; | |
567 | ||
568 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 569 | |
2a8626a9 | 570 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
2f1a74e5 | 571 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; |
572 | else | |
573 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
574 | } | |
575 | ||
e0c9905e SS |
576 | static void pump_transfers(unsigned long data) |
577 | { | |
578 | struct driver_data *drv_data = (struct driver_data *)data; | |
579 | struct spi_message *message = NULL; | |
580 | struct spi_transfer *transfer = NULL; | |
581 | struct spi_transfer *previous = NULL; | |
582 | struct chip_data *chip = NULL; | |
cf43369d | 583 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
584 | u32 clk_div = 0; |
585 | u8 bits = 0; | |
586 | u32 speed = 0; | |
587 | u32 cr0; | |
8d94cc50 SS |
588 | u32 cr1; |
589 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
590 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
591 | |
592 | /* Get current state information */ | |
593 | message = drv_data->cur_msg; | |
594 | transfer = drv_data->cur_transfer; | |
595 | chip = drv_data->cur_chip; | |
596 | ||
597 | /* Handle for abort */ | |
598 | if (message->state == ERROR_STATE) { | |
599 | message->status = -EIO; | |
5daa3ba0 | 600 | giveback(drv_data); |
e0c9905e SS |
601 | return; |
602 | } | |
603 | ||
604 | /* Handle end of message */ | |
605 | if (message->state == DONE_STATE) { | |
606 | message->status = 0; | |
5daa3ba0 | 607 | giveback(drv_data); |
e0c9905e SS |
608 | return; |
609 | } | |
610 | ||
8423597d | 611 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
612 | if (message->state == RUNNING_STATE) { |
613 | previous = list_entry(transfer->transfer_list.prev, | |
614 | struct spi_transfer, | |
615 | transfer_list); | |
616 | if (previous->delay_usecs) | |
617 | udelay(previous->delay_usecs); | |
8423597d NF |
618 | |
619 | /* Drop chip select only if cs_change is requested */ | |
620 | if (previous->cs_change) | |
a7bb3909 | 621 | cs_deassert(drv_data); |
e0c9905e SS |
622 | } |
623 | ||
cd7bed00 MW |
624 | /* Check if we can DMA this transfer */ |
625 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
626 | |
627 | /* reject already-mapped transfers; PIO won't always work */ | |
628 | if (message->is_dma_mapped | |
629 | || transfer->rx_dma || transfer->tx_dma) { | |
630 | dev_err(&drv_data->pdev->dev, | |
631 | "pump_transfers: mapped transfer length " | |
20b918dc | 632 | "of %u is greater than %d\n", |
7e964455 NF |
633 | transfer->len, MAX_DMA_LEN); |
634 | message->status = -EINVAL; | |
635 | giveback(drv_data); | |
636 | return; | |
637 | } | |
638 | ||
639 | /* warn ... we force this to PIO mode */ | |
640 | if (printk_ratelimit()) | |
641 | dev_warn(&message->spi->dev, "pump_transfers: " | |
642 | "DMA disabled for transfer length %ld " | |
643 | "greater than %d\n", | |
644 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
645 | } |
646 | ||
e0c9905e | 647 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 648 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
649 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
650 | message->status = -EIO; | |
5daa3ba0 | 651 | giveback(drv_data); |
e0c9905e SS |
652 | return; |
653 | } | |
9708c121 | 654 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
655 | drv_data->tx = (void *)transfer->tx_buf; |
656 | drv_data->tx_end = drv_data->tx + transfer->len; | |
657 | drv_data->rx = transfer->rx_buf; | |
658 | drv_data->rx_end = drv_data->rx + transfer->len; | |
659 | drv_data->rx_dma = transfer->rx_dma; | |
660 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 661 | drv_data->len = transfer->len; |
e0c9905e SS |
662 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
663 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
664 | |
665 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 666 | cr0 = chip->cr0; |
9708c121 SS |
667 | if (transfer->speed_hz || transfer->bits_per_word) { |
668 | ||
9708c121 SS |
669 | bits = chip->bits_per_word; |
670 | speed = chip->speed_hz; | |
671 | ||
672 | if (transfer->speed_hz) | |
673 | speed = transfer->speed_hz; | |
674 | ||
675 | if (transfer->bits_per_word) | |
676 | bits = transfer->bits_per_word; | |
677 | ||
3343b7a6 | 678 | clk_div = ssp_get_clk_div(drv_data, speed); |
9708c121 SS |
679 | |
680 | if (bits <= 8) { | |
681 | drv_data->n_bytes = 1; | |
9708c121 SS |
682 | drv_data->read = drv_data->read != null_reader ? |
683 | u8_reader : null_reader; | |
684 | drv_data->write = drv_data->write != null_writer ? | |
685 | u8_writer : null_writer; | |
686 | } else if (bits <= 16) { | |
687 | drv_data->n_bytes = 2; | |
9708c121 SS |
688 | drv_data->read = drv_data->read != null_reader ? |
689 | u16_reader : null_reader; | |
690 | drv_data->write = drv_data->write != null_writer ? | |
691 | u16_writer : null_writer; | |
692 | } else if (bits <= 32) { | |
693 | drv_data->n_bytes = 4; | |
9708c121 SS |
694 | drv_data->read = drv_data->read != null_reader ? |
695 | u32_reader : null_reader; | |
696 | drv_data->write = drv_data->write != null_writer ? | |
697 | u32_writer : null_writer; | |
698 | } | |
8d94cc50 SS |
699 | /* if bits/word is changed in dma mode, then must check the |
700 | * thresholds and burst also */ | |
701 | if (chip->enable_dma) { | |
cd7bed00 MW |
702 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
703 | message->spi, | |
8d94cc50 SS |
704 | bits, &dma_burst, |
705 | &dma_thresh)) | |
706 | if (printk_ratelimit()) | |
707 | dev_warn(&message->spi->dev, | |
7e964455 | 708 | "pump_transfers: " |
8d94cc50 SS |
709 | "DMA burst size reduced to " |
710 | "match bits_per_word\n"); | |
711 | } | |
9708c121 SS |
712 | |
713 | cr0 = clk_div | |
714 | | SSCR0_Motorola | |
5daa3ba0 | 715 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
716 | | SSCR0_SSE |
717 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
718 | } |
719 | ||
e0c9905e SS |
720 | message->state = RUNNING_STATE; |
721 | ||
7e964455 | 722 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
723 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
724 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 725 | if (drv_data->dma_mapped) { |
e0c9905e SS |
726 | |
727 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
728 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
729 | ||
730 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 731 | |
8d94cc50 SS |
732 | /* Clear status and start DMA engine */ |
733 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e | 734 | write_SSSR(drv_data->clear_sr, reg); |
cd7bed00 MW |
735 | |
736 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
737 | } else { |
738 | /* Ensure we have the correct interrupt handler */ | |
739 | drv_data->transfer_handler = interrupt_transfer; | |
740 | ||
8d94cc50 SS |
741 | /* Clear status */ |
742 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 743 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
744 | } |
745 | ||
a0d2642e MW |
746 | if (is_lpss_ssp(drv_data)) { |
747 | if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold) | |
748 | write_SSIRF(chip->lpss_rx_threshold, reg); | |
749 | if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold) | |
750 | write_SSITF(chip->lpss_tx_threshold, reg); | |
751 | } | |
752 | ||
8d94cc50 SS |
753 | /* see if we need to reload the config registers */ |
754 | if ((read_SSCR0(reg) != cr0) | |
755 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
756 | (cr1 & SSCR1_CHANGE_MASK)) { | |
757 | ||
b97c74bd | 758 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 759 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
2a8626a9 | 760 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e | 761 | write_SSTO(chip->timeout, reg); |
b97c74bd NF |
762 | /* first set CR1 without interrupt and service enables */ |
763 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
764 | /* restart the SSP */ | |
8d94cc50 | 765 | write_SSCR0(cr0, reg); |
b97c74bd | 766 | |
8d94cc50 | 767 | } else { |
2a8626a9 | 768 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 769 | write_SSTO(chip->timeout, reg); |
e0c9905e | 770 | } |
b97c74bd | 771 | |
a7bb3909 | 772 | cs_assert(drv_data); |
b97c74bd NF |
773 | |
774 | /* after chip select, release the data by enabling service | |
775 | * requests and interrupts, without changing any mode bits */ | |
776 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
777 | } |
778 | ||
7f86bde9 MW |
779 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
780 | struct spi_message *msg) | |
e0c9905e | 781 | { |
7f86bde9 | 782 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 783 | |
7f86bde9 | 784 | drv_data->cur_msg = msg; |
e0c9905e SS |
785 | /* Initial message state*/ |
786 | drv_data->cur_msg->state = START_STATE; | |
787 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
788 | struct spi_transfer, | |
789 | transfer_list); | |
790 | ||
8d94cc50 SS |
791 | /* prepare to setup the SSP, in pump_transfers, using the per |
792 | * chip configuration */ | |
e0c9905e | 793 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
794 | |
795 | /* Mark as busy and launch transfers */ | |
796 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
797 | return 0; |
798 | } | |
799 | ||
7d94a505 MW |
800 | static int pxa2xx_spi_prepare_transfer(struct spi_master *master) |
801 | { | |
802 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
803 | ||
804 | pm_runtime_get_sync(&drv_data->pdev->dev); | |
805 | return 0; | |
806 | } | |
807 | ||
808 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) | |
809 | { | |
810 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
811 | ||
812 | /* Disable the SSP now */ | |
813 | write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, | |
814 | drv_data->ioaddr); | |
815 | ||
816 | pm_runtime_mark_last_busy(&drv_data->pdev->dev); | |
817 | pm_runtime_put_autosuspend(&drv_data->pdev->dev); | |
818 | return 0; | |
819 | } | |
820 | ||
a7bb3909 EM |
821 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
822 | struct pxa2xx_spi_chip *chip_info) | |
823 | { | |
824 | int err = 0; | |
825 | ||
826 | if (chip == NULL || chip_info == NULL) | |
827 | return 0; | |
828 | ||
829 | /* NOTE: setup() can be called multiple times, possibly with | |
830 | * different chip_info, release previously requested GPIO | |
831 | */ | |
832 | if (gpio_is_valid(chip->gpio_cs)) | |
833 | gpio_free(chip->gpio_cs); | |
834 | ||
835 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
836 | if (chip_info->cs_control) { | |
837 | chip->cs_control = chip_info->cs_control; | |
838 | return 0; | |
839 | } | |
840 | ||
841 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
842 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
843 | if (err) { | |
844 | dev_err(&spi->dev, "failed to request chip select " | |
845 | "GPIO%d\n", chip_info->gpio_cs); | |
846 | return err; | |
847 | } | |
848 | ||
849 | chip->gpio_cs = chip_info->gpio_cs; | |
850 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
851 | ||
852 | err = gpio_direction_output(chip->gpio_cs, | |
853 | !chip->gpio_cs_inverted); | |
854 | } | |
855 | ||
856 | return err; | |
857 | } | |
858 | ||
e0c9905e SS |
859 | static int setup(struct spi_device *spi) |
860 | { | |
861 | struct pxa2xx_spi_chip *chip_info = NULL; | |
862 | struct chip_data *chip; | |
863 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
864 | unsigned int clk_div; | |
a0d2642e MW |
865 | uint tx_thres, tx_hi_thres, rx_thres; |
866 | ||
867 | if (is_lpss_ssp(drv_data)) { | |
868 | tx_thres = LPSS_TX_LOTHRESH_DFLT; | |
869 | tx_hi_thres = LPSS_TX_HITHRESH_DFLT; | |
870 | rx_thres = LPSS_RX_THRESH_DFLT; | |
871 | } else { | |
872 | tx_thres = TX_THRESH_DFLT; | |
873 | tx_hi_thres = 0; | |
874 | rx_thres = RX_THRESH_DFLT; | |
875 | } | |
e0c9905e | 876 | |
2a8626a9 | 877 | if (!pxa25x_ssp_comp(drv_data) |
8d94cc50 SS |
878 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
879 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
880 | "b/w not 4-32 for type non-PXA25x_SSP\n", | |
881 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 882 | return -EINVAL; |
2a8626a9 | 883 | } else if (pxa25x_ssp_comp(drv_data) |
8d94cc50 SS |
884 | && (spi->bits_per_word < 4 |
885 | || spi->bits_per_word > 16)) { | |
886 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
887 | "b/w not 4-16 for type PXA25x_SSP\n", | |
888 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 889 | return -EINVAL; |
8d94cc50 | 890 | } |
e0c9905e | 891 | |
8d94cc50 | 892 | /* Only alloc on first setup */ |
e0c9905e | 893 | chip = spi_get_ctldata(spi); |
8d94cc50 | 894 | if (!chip) { |
e0c9905e | 895 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
896 | if (!chip) { |
897 | dev_err(&spi->dev, | |
898 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 899 | return -ENOMEM; |
8d94cc50 | 900 | } |
e0c9905e | 901 | |
2a8626a9 SAS |
902 | if (drv_data->ssp_type == CE4100_SSP) { |
903 | if (spi->chip_select > 4) { | |
904 | dev_err(&spi->dev, "failed setup: " | |
905 | "cs number must not be > 4.\n"); | |
906 | kfree(chip); | |
907 | return -EINVAL; | |
908 | } | |
909 | ||
910 | chip->frm = spi->chip_select; | |
911 | } else | |
912 | chip->gpio_cs = -1; | |
e0c9905e | 913 | chip->enable_dma = 0; |
f1f640a9 | 914 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
915 | } |
916 | ||
8d94cc50 SS |
917 | /* protocol drivers may change the chip settings, so... |
918 | * if chip_info exists, use it */ | |
919 | chip_info = spi->controller_data; | |
920 | ||
e0c9905e | 921 | /* chip_info isn't always needed */ |
8d94cc50 | 922 | chip->cr1 = 0; |
e0c9905e | 923 | if (chip_info) { |
f1f640a9 VS |
924 | if (chip_info->timeout) |
925 | chip->timeout = chip_info->timeout; | |
926 | if (chip_info->tx_threshold) | |
927 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
928 | if (chip_info->tx_hi_threshold) |
929 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
930 | if (chip_info->rx_threshold) |
931 | rx_thres = chip_info->rx_threshold; | |
932 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 933 | chip->dma_threshold = 0; |
e0c9905e SS |
934 | if (chip_info->enable_loopback) |
935 | chip->cr1 = SSCR1_LBM; | |
936 | } | |
937 | ||
f1f640a9 VS |
938 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
939 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
940 | ||
a0d2642e MW |
941 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
942 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
943 | | SSITF_TxHiThresh(tx_hi_thres); | |
944 | ||
8d94cc50 SS |
945 | /* set dma burst and threshold outside of chip_info path so that if |
946 | * chip_info goes away after setting chip->enable_dma, the | |
947 | * burst and threshold can still respond to changes in bits_per_word */ | |
948 | if (chip->enable_dma) { | |
949 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
950 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
951 | spi->bits_per_word, | |
8d94cc50 SS |
952 | &chip->dma_burst_size, |
953 | &chip->dma_threshold)) { | |
954 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | |
955 | "to match bits_per_word\n"); | |
956 | } | |
957 | } | |
958 | ||
3343b7a6 | 959 | clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); |
9708c121 | 960 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
961 | |
962 | chip->cr0 = clk_div | |
963 | | SSCR0_Motorola | |
5daa3ba0 SS |
964 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
965 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
966 | | SSCR0_SSE |
967 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
968 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
969 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
970 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 971 | |
b833172f MW |
972 | if (spi->mode & SPI_LOOP) |
973 | chip->cr1 |= SSCR1_LBM; | |
974 | ||
e0c9905e | 975 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
2a8626a9 | 976 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 977 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 978 | drv_data->max_clk_rate |
c9840daa EM |
979 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
980 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 981 | else |
7d077197 | 982 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 983 | drv_data->max_clk_rate / 2 |
c9840daa EM |
984 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
985 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
986 | |
987 | if (spi->bits_per_word <= 8) { | |
988 | chip->n_bytes = 1; | |
e0c9905e SS |
989 | chip->read = u8_reader; |
990 | chip->write = u8_writer; | |
991 | } else if (spi->bits_per_word <= 16) { | |
992 | chip->n_bytes = 2; | |
e0c9905e SS |
993 | chip->read = u16_reader; |
994 | chip->write = u16_writer; | |
995 | } else if (spi->bits_per_word <= 32) { | |
996 | chip->cr0 |= SSCR0_EDSS; | |
997 | chip->n_bytes = 4; | |
e0c9905e SS |
998 | chip->read = u32_reader; |
999 | chip->write = u32_writer; | |
1000 | } else { | |
1001 | dev_err(&spi->dev, "invalid wordsize\n"); | |
e0c9905e SS |
1002 | return -ENODEV; |
1003 | } | |
9708c121 | 1004 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1005 | |
1006 | spi_set_ctldata(spi, chip); | |
1007 | ||
2a8626a9 SAS |
1008 | if (drv_data->ssp_type == CE4100_SSP) |
1009 | return 0; | |
1010 | ||
a7bb3909 | 1011 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1012 | } |
1013 | ||
0ffa0285 | 1014 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1015 | { |
0ffa0285 | 1016 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1017 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1018 | |
7348d82a DR |
1019 | if (!chip) |
1020 | return; | |
1021 | ||
2a8626a9 | 1022 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1023 | gpio_free(chip->gpio_cs); |
1024 | ||
e0c9905e SS |
1025 | kfree(chip); |
1026 | } | |
1027 | ||
fd4a319b | 1028 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1029 | { |
1030 | struct device *dev = &pdev->dev; | |
1031 | struct pxa2xx_spi_master *platform_info; | |
1032 | struct spi_master *master; | |
65a00a20 | 1033 | struct driver_data *drv_data; |
2f1a74e5 | 1034 | struct ssp_device *ssp; |
65a00a20 | 1035 | int status; |
e0c9905e | 1036 | |
851bacf5 MW |
1037 | platform_info = dev_get_platdata(dev); |
1038 | if (!platform_info) { | |
1039 | dev_err(&pdev->dev, "missing platform data\n"); | |
1040 | return -ENODEV; | |
1041 | } | |
e0c9905e | 1042 | |
baffe169 | 1043 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1044 | if (!ssp) |
1045 | ssp = &platform_info->ssp; | |
1046 | ||
1047 | if (!ssp->mmio_base) { | |
1048 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1049 | return -ENODEV; |
1050 | } | |
1051 | ||
1052 | /* Allocate master with space for drv_data and null dma buffer */ | |
1053 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1054 | if (!master) { | |
65a00a20 | 1055 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1056 | pxa_ssp_free(ssp); |
e0c9905e SS |
1057 | return -ENOMEM; |
1058 | } | |
1059 | drv_data = spi_master_get_devdata(master); | |
1060 | drv_data->master = master; | |
1061 | drv_data->master_info = platform_info; | |
1062 | drv_data->pdev = pdev; | |
2f1a74e5 | 1063 | drv_data->ssp = ssp; |
e0c9905e | 1064 | |
21486af0 | 1065 | master->dev.parent = &pdev->dev; |
21486af0 | 1066 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1067 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1068 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1069 | |
851bacf5 | 1070 | master->bus_num = ssp->port_id; |
e0c9905e | 1071 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 1072 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1073 | master->cleanup = cleanup; |
1074 | master->setup = setup; | |
7f86bde9 | 1075 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 MW |
1076 | master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer; |
1077 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; | |
e0c9905e | 1078 | |
2f1a74e5 | 1079 | drv_data->ssp_type = ssp->type; |
2b9b84f4 | 1080 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
e0c9905e | 1081 | |
2f1a74e5 | 1082 | drv_data->ioaddr = ssp->mmio_base; |
1083 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1084 | if (pxa25x_ssp_comp(drv_data)) { |
e0c9905e SS |
1085 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1086 | drv_data->dma_cr1 = 0; | |
1087 | drv_data->clear_sr = SSSR_ROR; | |
1088 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1089 | } else { | |
1090 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | |
5928808e | 1091 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1092 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1093 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1094 | } | |
1095 | ||
49cbb1e0 SAS |
1096 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1097 | drv_data); | |
e0c9905e | 1098 | if (status < 0) { |
65a00a20 | 1099 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1100 | goto out_error_master_alloc; |
1101 | } | |
1102 | ||
1103 | /* Setup DMA if requested */ | |
1104 | drv_data->tx_channel = -1; | |
1105 | drv_data->rx_channel = -1; | |
1106 | if (platform_info->enable_dma) { | |
cd7bed00 MW |
1107 | status = pxa2xx_spi_dma_setup(drv_data); |
1108 | if (status) { | |
1109 | dev_warn(dev, "failed to setup DMA, using PIO\n"); | |
1110 | platform_info->enable_dma = false; | |
e0c9905e | 1111 | } |
e0c9905e SS |
1112 | } |
1113 | ||
1114 | /* Enable SOC clock */ | |
3343b7a6 MW |
1115 | clk_prepare_enable(ssp->clk); |
1116 | ||
1117 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | |
e0c9905e SS |
1118 | |
1119 | /* Load default SSP configuration */ | |
1120 | write_SSCR0(0, drv_data->ioaddr); | |
f1f640a9 VS |
1121 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | |
1122 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1123 | drv_data->ioaddr); | |
c9840daa | 1124 | write_SSCR0(SSCR0_SCR(2) |
e0c9905e SS |
1125 | | SSCR0_Motorola |
1126 | | SSCR0_DataSize(8), | |
1127 | drv_data->ioaddr); | |
2a8626a9 | 1128 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e SS |
1129 | write_SSTO(0, drv_data->ioaddr); |
1130 | write_SSPSP(0, drv_data->ioaddr); | |
1131 | ||
a0d2642e MW |
1132 | lpss_ssp_setup(drv_data); |
1133 | ||
7f86bde9 MW |
1134 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1135 | (unsigned long)drv_data); | |
e0c9905e SS |
1136 | |
1137 | /* Register with the SPI framework */ | |
1138 | platform_set_drvdata(pdev, drv_data); | |
1139 | status = spi_register_master(master); | |
1140 | if (status != 0) { | |
1141 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1142 | goto out_error_clock_enabled; |
e0c9905e SS |
1143 | } |
1144 | ||
7d94a505 MW |
1145 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1146 | pm_runtime_use_autosuspend(&pdev->dev); | |
1147 | pm_runtime_set_active(&pdev->dev); | |
1148 | pm_runtime_enable(&pdev->dev); | |
1149 | ||
e0c9905e SS |
1150 | return status; |
1151 | ||
e0c9905e | 1152 | out_error_clock_enabled: |
3343b7a6 | 1153 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1154 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1155 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1156 | |
1157 | out_error_master_alloc: | |
1158 | spi_master_put(master); | |
baffe169 | 1159 | pxa_ssp_free(ssp); |
e0c9905e SS |
1160 | return status; |
1161 | } | |
1162 | ||
1163 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1164 | { | |
1165 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1166 | struct ssp_device *ssp; |
e0c9905e SS |
1167 | |
1168 | if (!drv_data) | |
1169 | return 0; | |
51e911e2 | 1170 | ssp = drv_data->ssp; |
e0c9905e | 1171 | |
7d94a505 MW |
1172 | pm_runtime_get_sync(&pdev->dev); |
1173 | ||
e0c9905e SS |
1174 | /* Disable the SSP at the peripheral and SOC level */ |
1175 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1176 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1177 | |
1178 | /* Release DMA */ | |
cd7bed00 MW |
1179 | if (drv_data->master_info->enable_dma) |
1180 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1181 | |
7d94a505 MW |
1182 | pm_runtime_put_noidle(&pdev->dev); |
1183 | pm_runtime_disable(&pdev->dev); | |
1184 | ||
e0c9905e | 1185 | /* Release IRQ */ |
2f1a74e5 | 1186 | free_irq(ssp->irq, drv_data); |
1187 | ||
1188 | /* Release SSP */ | |
baffe169 | 1189 | pxa_ssp_free(ssp); |
e0c9905e SS |
1190 | |
1191 | /* Disconnect from the SPI framework */ | |
1192 | spi_unregister_master(drv_data->master); | |
1193 | ||
1194 | /* Prevent double remove */ | |
1195 | platform_set_drvdata(pdev, NULL); | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1201 | { | |
1202 | int status = 0; | |
1203 | ||
1204 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1205 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1206 | } | |
1207 | ||
1208 | #ifdef CONFIG_PM | |
86d2593a | 1209 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1210 | { |
86d2593a | 1211 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1212 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1213 | int status = 0; |
1214 | ||
7f86bde9 | 1215 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1216 | if (status != 0) |
1217 | return status; | |
1218 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1219 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1220 | |
1221 | return 0; | |
1222 | } | |
1223 | ||
86d2593a | 1224 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1225 | { |
86d2593a | 1226 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1227 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1228 | int status = 0; |
1229 | ||
cd7bed00 | 1230 | pxa2xx_spi_dma_resume(drv_data); |
148da331 | 1231 | |
e0c9905e | 1232 | /* Enable the SSP clock */ |
3343b7a6 | 1233 | clk_prepare_enable(ssp->clk); |
e0c9905e SS |
1234 | |
1235 | /* Start the queue running */ | |
7f86bde9 | 1236 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1237 | if (status != 0) { |
86d2593a | 1238 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1239 | return status; |
1240 | } | |
1241 | ||
1242 | return 0; | |
1243 | } | |
7d94a505 MW |
1244 | #endif |
1245 | ||
1246 | #ifdef CONFIG_PM_RUNTIME | |
1247 | static int pxa2xx_spi_runtime_suspend(struct device *dev) | |
1248 | { | |
1249 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1250 | ||
1251 | clk_disable_unprepare(drv_data->ssp->clk); | |
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1256 | { | |
1257 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1258 | ||
1259 | clk_prepare_enable(drv_data->ssp->clk); | |
1260 | return 0; | |
1261 | } | |
1262 | #endif | |
86d2593a | 1263 | |
47145210 | 1264 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1265 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1266 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1267 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1268 | }; |
e0c9905e SS |
1269 | |
1270 | static struct platform_driver driver = { | |
1271 | .driver = { | |
86d2593a MR |
1272 | .name = "pxa2xx-spi", |
1273 | .owner = THIS_MODULE, | |
86d2593a | 1274 | .pm = &pxa2xx_spi_pm_ops, |
e0c9905e | 1275 | }, |
fbd29a14 | 1276 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1277 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1278 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1279 | }; |
1280 | ||
1281 | static int __init pxa2xx_spi_init(void) | |
1282 | { | |
fbd29a14 | 1283 | return platform_driver_register(&driver); |
e0c9905e | 1284 | } |
5b61a749 | 1285 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1286 | |
1287 | static void __exit pxa2xx_spi_exit(void) | |
1288 | { | |
1289 | platform_driver_unregister(&driver); | |
1290 | } | |
1291 | module_exit(pxa2xx_spi_exit); |