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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/platform_device.h> | |
8348c259 | 26 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e SS |
27 | #include <linux/spi/spi.h> |
28 | #include <linux/workqueue.h> | |
e0c9905e | 29 | #include <linux/delay.h> |
a7bb3909 | 30 | #include <linux/gpio.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
3343b7a6 | 32 | #include <linux/clk.h> |
7d94a505 | 33 | #include <linux/pm_runtime.h> |
e0c9905e SS |
34 | |
35 | #include <asm/io.h> | |
36 | #include <asm/irq.h> | |
e0c9905e | 37 | #include <asm/delay.h> |
e0c9905e | 38 | |
cd7bed00 | 39 | #include "spi-pxa2xx.h" |
e0c9905e SS |
40 | |
41 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 42 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 43 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 44 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
45 | |
46 | #define MAX_BUSES 3 | |
47 | ||
f1f640a9 VS |
48 | #define TIMOUT_DFLT 1000 |
49 | ||
b97c74bd NF |
50 | /* |
51 | * for testing SSCR1 changes that require SSP restart, basically | |
52 | * everything except the service and interrupt enables, the pxa270 developer | |
53 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
54 | * list, but the PXA255 dev man says all bits without really meaning the | |
55 | * service and interrupt enables | |
56 | */ | |
57 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 58 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
59 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
60 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
61 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
62 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 63 | |
a7bb3909 EM |
64 | static void cs_assert(struct driver_data *drv_data) |
65 | { | |
66 | struct chip_data *chip = drv_data->cur_chip; | |
67 | ||
2a8626a9 SAS |
68 | if (drv_data->ssp_type == CE4100_SSP) { |
69 | write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr); | |
70 | return; | |
71 | } | |
72 | ||
a7bb3909 EM |
73 | if (chip->cs_control) { |
74 | chip->cs_control(PXA2XX_CS_ASSERT); | |
75 | return; | |
76 | } | |
77 | ||
78 | if (gpio_is_valid(chip->gpio_cs)) | |
79 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); | |
80 | } | |
81 | ||
82 | static void cs_deassert(struct driver_data *drv_data) | |
83 | { | |
84 | struct chip_data *chip = drv_data->cur_chip; | |
85 | ||
2a8626a9 SAS |
86 | if (drv_data->ssp_type == CE4100_SSP) |
87 | return; | |
88 | ||
a7bb3909 | 89 | if (chip->cs_control) { |
2b2562d3 | 90 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
91 | return; |
92 | } | |
93 | ||
94 | if (gpio_is_valid(chip->gpio_cs)) | |
95 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); | |
96 | } | |
97 | ||
cd7bed00 | 98 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
99 | { |
100 | unsigned long limit = loops_per_jiffy << 1; | |
101 | ||
cf43369d | 102 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
103 | |
104 | do { | |
105 | while (read_SSSR(reg) & SSSR_RNE) { | |
106 | read_SSDR(reg); | |
107 | } | |
306c68aa | 108 | } while ((read_SSSR(reg) & SSSR_BSY) && --limit); |
2a8626a9 | 109 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
110 | |
111 | return limit; | |
112 | } | |
113 | ||
8d94cc50 | 114 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 115 | { |
cf43369d | 116 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 117 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 118 | |
4a25605f | 119 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
120 | || (drv_data->tx == drv_data->tx_end)) |
121 | return 0; | |
122 | ||
123 | write_SSDR(0, reg); | |
124 | drv_data->tx += n_bytes; | |
125 | ||
126 | return 1; | |
e0c9905e SS |
127 | } |
128 | ||
8d94cc50 | 129 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 130 | { |
cf43369d | 131 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 132 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
133 | |
134 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 135 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
136 | read_SSDR(reg); |
137 | drv_data->rx += n_bytes; | |
138 | } | |
8d94cc50 SS |
139 | |
140 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
141 | } |
142 | ||
8d94cc50 | 143 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 144 | { |
cf43369d | 145 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 146 | |
4a25605f | 147 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
148 | || (drv_data->tx == drv_data->tx_end)) |
149 | return 0; | |
150 | ||
151 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
152 | ++drv_data->tx; | |
153 | ||
154 | return 1; | |
e0c9905e SS |
155 | } |
156 | ||
8d94cc50 | 157 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 158 | { |
cf43369d | 159 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
160 | |
161 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 162 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
163 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
164 | ++drv_data->rx; | |
165 | } | |
8d94cc50 SS |
166 | |
167 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
168 | } |
169 | ||
8d94cc50 | 170 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 171 | { |
cf43369d | 172 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 173 | |
4a25605f | 174 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
175 | || (drv_data->tx == drv_data->tx_end)) |
176 | return 0; | |
177 | ||
178 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
179 | drv_data->tx += 2; | |
180 | ||
181 | return 1; | |
e0c9905e SS |
182 | } |
183 | ||
8d94cc50 | 184 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 185 | { |
cf43369d | 186 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
187 | |
188 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 189 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
190 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
191 | drv_data->rx += 2; | |
192 | } | |
8d94cc50 SS |
193 | |
194 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 195 | } |
8d94cc50 SS |
196 | |
197 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 198 | { |
cf43369d | 199 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 200 | |
4a25605f | 201 | if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK) |
8d94cc50 SS |
202 | || (drv_data->tx == drv_data->tx_end)) |
203 | return 0; | |
204 | ||
205 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
206 | drv_data->tx += 4; | |
207 | ||
208 | return 1; | |
e0c9905e SS |
209 | } |
210 | ||
8d94cc50 | 211 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 212 | { |
cf43369d | 213 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
214 | |
215 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 216 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
217 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
218 | drv_data->rx += 4; | |
219 | } | |
8d94cc50 SS |
220 | |
221 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
222 | } |
223 | ||
cd7bed00 | 224 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
225 | { |
226 | struct spi_message *msg = drv_data->cur_msg; | |
227 | struct spi_transfer *trans = drv_data->cur_transfer; | |
228 | ||
229 | /* Move to next transfer */ | |
230 | if (trans->transfer_list.next != &msg->transfers) { | |
231 | drv_data->cur_transfer = | |
232 | list_entry(trans->transfer_list.next, | |
233 | struct spi_transfer, | |
234 | transfer_list); | |
235 | return RUNNING_STATE; | |
236 | } else | |
237 | return DONE_STATE; | |
238 | } | |
239 | ||
e0c9905e | 240 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 241 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
242 | { |
243 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 244 | struct spi_message *msg; |
e0c9905e | 245 | |
5daa3ba0 SS |
246 | msg = drv_data->cur_msg; |
247 | drv_data->cur_msg = NULL; | |
248 | drv_data->cur_transfer = NULL; | |
5daa3ba0 SS |
249 | |
250 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
251 | struct spi_transfer, |
252 | transfer_list); | |
253 | ||
8423597d NF |
254 | /* Delay if requested before any change in chip select */ |
255 | if (last_transfer->delay_usecs) | |
256 | udelay(last_transfer->delay_usecs); | |
257 | ||
258 | /* Drop chip select UNLESS cs_change is true or we are returning | |
259 | * a message with an error, or next message is for another chip | |
260 | */ | |
e0c9905e | 261 | if (!last_transfer->cs_change) |
a7bb3909 | 262 | cs_deassert(drv_data); |
8423597d NF |
263 | else { |
264 | struct spi_message *next_msg; | |
265 | ||
266 | /* Holding of cs was hinted, but we need to make sure | |
267 | * the next message is for the same chip. Don't waste | |
268 | * time with the following tests unless this was hinted. | |
269 | * | |
270 | * We cannot postpone this until pump_messages, because | |
271 | * after calling msg->complete (below) the driver that | |
272 | * sent the current message could be unloaded, which | |
273 | * could invalidate the cs_control() callback... | |
274 | */ | |
275 | ||
276 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 277 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
278 | |
279 | /* see if the next and current messages point | |
280 | * to the same chip | |
281 | */ | |
282 | if (next_msg && next_msg->spi != msg->spi) | |
283 | next_msg = NULL; | |
284 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 285 | cs_deassert(drv_data); |
8423597d | 286 | } |
e0c9905e | 287 | |
7f86bde9 | 288 | spi_finalize_current_message(drv_data->master); |
a7bb3909 | 289 | drv_data->cur_chip = NULL; |
e0c9905e SS |
290 | } |
291 | ||
579d3bb2 SAS |
292 | static void reset_sccr1(struct driver_data *drv_data) |
293 | { | |
294 | void __iomem *reg = drv_data->ioaddr; | |
295 | struct chip_data *chip = drv_data->cur_chip; | |
296 | u32 sccr1_reg; | |
297 | ||
298 | sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1; | |
299 | sccr1_reg &= ~SSCR1_RFT; | |
300 | sccr1_reg |= chip->threshold; | |
301 | write_SSCR1(sccr1_reg, reg); | |
302 | } | |
303 | ||
8d94cc50 | 304 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 305 | { |
cf43369d | 306 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 307 | |
8d94cc50 | 308 | /* Stop and reset SSP */ |
2a8626a9 | 309 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 310 | reset_sccr1(drv_data); |
2a8626a9 | 311 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 312 | write_SSTO(0, reg); |
cd7bed00 | 313 | pxa2xx_spi_flush(drv_data); |
8d94cc50 | 314 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); |
e0c9905e | 315 | |
8d94cc50 | 316 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 317 | |
8d94cc50 SS |
318 | drv_data->cur_msg->state = ERROR_STATE; |
319 | tasklet_schedule(&drv_data->pump_transfers); | |
320 | } | |
5daa3ba0 | 321 | |
8d94cc50 SS |
322 | static void int_transfer_complete(struct driver_data *drv_data) |
323 | { | |
cf43369d | 324 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 325 | |
8d94cc50 | 326 | /* Stop SSP */ |
2a8626a9 | 327 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 328 | reset_sccr1(drv_data); |
2a8626a9 | 329 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 330 | write_SSTO(0, reg); |
e0c9905e | 331 | |
25985edc | 332 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
333 | drv_data->cur_msg->actual_length += drv_data->len - |
334 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 335 | |
8423597d NF |
336 | /* Transfer delays and chip select release are |
337 | * handled in pump_transfers or giveback | |
338 | */ | |
e0c9905e | 339 | |
8d94cc50 | 340 | /* Move to next transfer */ |
cd7bed00 | 341 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 342 | |
8d94cc50 SS |
343 | /* Schedule transfer tasklet */ |
344 | tasklet_schedule(&drv_data->pump_transfers); | |
345 | } | |
e0c9905e | 346 | |
8d94cc50 SS |
347 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
348 | { | |
cf43369d | 349 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 350 | |
8d94cc50 SS |
351 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
352 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 353 | |
8d94cc50 | 354 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 355 | |
8d94cc50 SS |
356 | if (irq_status & SSSR_ROR) { |
357 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
358 | return IRQ_HANDLED; | |
359 | } | |
e0c9905e | 360 | |
8d94cc50 SS |
361 | if (irq_status & SSSR_TINT) { |
362 | write_SSSR(SSSR_TINT, reg); | |
363 | if (drv_data->read(drv_data)) { | |
364 | int_transfer_complete(drv_data); | |
365 | return IRQ_HANDLED; | |
366 | } | |
367 | } | |
e0c9905e | 368 | |
8d94cc50 SS |
369 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
370 | do { | |
371 | if (drv_data->read(drv_data)) { | |
372 | int_transfer_complete(drv_data); | |
373 | return IRQ_HANDLED; | |
374 | } | |
375 | } while (drv_data->write(drv_data)); | |
e0c9905e | 376 | |
8d94cc50 SS |
377 | if (drv_data->read(drv_data)) { |
378 | int_transfer_complete(drv_data); | |
379 | return IRQ_HANDLED; | |
380 | } | |
e0c9905e | 381 | |
8d94cc50 | 382 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
383 | u32 bytes_left; |
384 | u32 sccr1_reg; | |
385 | ||
386 | sccr1_reg = read_SSCR1(reg); | |
387 | sccr1_reg &= ~SSCR1_TIE; | |
388 | ||
389 | /* | |
390 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 391 | * remaining RX bytes. |
579d3bb2 | 392 | */ |
2a8626a9 | 393 | if (pxa25x_ssp_comp(drv_data)) { |
579d3bb2 SAS |
394 | |
395 | sccr1_reg &= ~SSCR1_RFT; | |
396 | ||
397 | bytes_left = drv_data->rx_end - drv_data->rx; | |
398 | switch (drv_data->n_bytes) { | |
399 | case 4: | |
400 | bytes_left >>= 1; | |
401 | case 2: | |
402 | bytes_left >>= 1; | |
8d94cc50 | 403 | } |
579d3bb2 SAS |
404 | |
405 | if (bytes_left > RX_THRESH_DFLT) | |
406 | bytes_left = RX_THRESH_DFLT; | |
407 | ||
408 | sccr1_reg |= SSCR1_RxTresh(bytes_left); | |
e0c9905e | 409 | } |
579d3bb2 | 410 | write_SSCR1(sccr1_reg, reg); |
e0c9905e SS |
411 | } |
412 | ||
5daa3ba0 SS |
413 | /* We did something */ |
414 | return IRQ_HANDLED; | |
e0c9905e SS |
415 | } |
416 | ||
7d12e780 | 417 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 418 | { |
c7bec5ab | 419 | struct driver_data *drv_data = dev_id; |
cf43369d | 420 | void __iomem *reg = drv_data->ioaddr; |
7d94a505 | 421 | u32 sccr1_reg; |
49cbb1e0 SAS |
422 | u32 mask = drv_data->mask_sr; |
423 | u32 status; | |
424 | ||
7d94a505 MW |
425 | /* |
426 | * The IRQ might be shared with other peripherals so we must first | |
427 | * check that are we RPM suspended or not. If we are we assume that | |
428 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
429 | * interrupt is enabled). | |
430 | */ | |
431 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
432 | return IRQ_NONE; | |
433 | ||
434 | sccr1_reg = read_SSCR1(reg); | |
49cbb1e0 SAS |
435 | status = read_SSSR(reg); |
436 | ||
437 | /* Ignore possible writes if we don't need to write */ | |
438 | if (!(sccr1_reg & SSCR1_TIE)) | |
439 | mask &= ~SSSR_TFS; | |
440 | ||
441 | if (!(status & mask)) | |
442 | return IRQ_NONE; | |
e0c9905e SS |
443 | |
444 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
445 | |
446 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
447 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
2a8626a9 | 448 | if (!pxa25x_ssp_comp(drv_data)) |
5daa3ba0 | 449 | write_SSTO(0, reg); |
2a8626a9 | 450 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 451 | |
e0c9905e | 452 | dev_err(&drv_data->pdev->dev, "bad message state " |
8d94cc50 | 453 | "in interrupt handler\n"); |
5daa3ba0 | 454 | |
e0c9905e SS |
455 | /* Never fail */ |
456 | return IRQ_HANDLED; | |
457 | } | |
458 | ||
459 | return drv_data->transfer_handler(drv_data); | |
460 | } | |
461 | ||
3343b7a6 | 462 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 463 | { |
3343b7a6 MW |
464 | unsigned long ssp_clk = drv_data->max_clk_rate; |
465 | const struct ssp_device *ssp = drv_data->ssp; | |
466 | ||
467 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 468 | |
2a8626a9 | 469 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
2f1a74e5 | 470 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; |
471 | else | |
472 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
473 | } | |
474 | ||
e0c9905e SS |
475 | static void pump_transfers(unsigned long data) |
476 | { | |
477 | struct driver_data *drv_data = (struct driver_data *)data; | |
478 | struct spi_message *message = NULL; | |
479 | struct spi_transfer *transfer = NULL; | |
480 | struct spi_transfer *previous = NULL; | |
481 | struct chip_data *chip = NULL; | |
cf43369d | 482 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
483 | u32 clk_div = 0; |
484 | u8 bits = 0; | |
485 | u32 speed = 0; | |
486 | u32 cr0; | |
8d94cc50 SS |
487 | u32 cr1; |
488 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
489 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
490 | |
491 | /* Get current state information */ | |
492 | message = drv_data->cur_msg; | |
493 | transfer = drv_data->cur_transfer; | |
494 | chip = drv_data->cur_chip; | |
495 | ||
496 | /* Handle for abort */ | |
497 | if (message->state == ERROR_STATE) { | |
498 | message->status = -EIO; | |
5daa3ba0 | 499 | giveback(drv_data); |
e0c9905e SS |
500 | return; |
501 | } | |
502 | ||
503 | /* Handle end of message */ | |
504 | if (message->state == DONE_STATE) { | |
505 | message->status = 0; | |
5daa3ba0 | 506 | giveback(drv_data); |
e0c9905e SS |
507 | return; |
508 | } | |
509 | ||
8423597d | 510 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
511 | if (message->state == RUNNING_STATE) { |
512 | previous = list_entry(transfer->transfer_list.prev, | |
513 | struct spi_transfer, | |
514 | transfer_list); | |
515 | if (previous->delay_usecs) | |
516 | udelay(previous->delay_usecs); | |
8423597d NF |
517 | |
518 | /* Drop chip select only if cs_change is requested */ | |
519 | if (previous->cs_change) | |
a7bb3909 | 520 | cs_deassert(drv_data); |
e0c9905e SS |
521 | } |
522 | ||
cd7bed00 MW |
523 | /* Check if we can DMA this transfer */ |
524 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
525 | |
526 | /* reject already-mapped transfers; PIO won't always work */ | |
527 | if (message->is_dma_mapped | |
528 | || transfer->rx_dma || transfer->tx_dma) { | |
529 | dev_err(&drv_data->pdev->dev, | |
530 | "pump_transfers: mapped transfer length " | |
20b918dc | 531 | "of %u is greater than %d\n", |
7e964455 NF |
532 | transfer->len, MAX_DMA_LEN); |
533 | message->status = -EINVAL; | |
534 | giveback(drv_data); | |
535 | return; | |
536 | } | |
537 | ||
538 | /* warn ... we force this to PIO mode */ | |
539 | if (printk_ratelimit()) | |
540 | dev_warn(&message->spi->dev, "pump_transfers: " | |
541 | "DMA disabled for transfer length %ld " | |
542 | "greater than %d\n", | |
543 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
544 | } |
545 | ||
e0c9905e | 546 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 547 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
548 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
549 | message->status = -EIO; | |
5daa3ba0 | 550 | giveback(drv_data); |
e0c9905e SS |
551 | return; |
552 | } | |
9708c121 | 553 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
554 | drv_data->tx = (void *)transfer->tx_buf; |
555 | drv_data->tx_end = drv_data->tx + transfer->len; | |
556 | drv_data->rx = transfer->rx_buf; | |
557 | drv_data->rx_end = drv_data->rx + transfer->len; | |
558 | drv_data->rx_dma = transfer->rx_dma; | |
559 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 560 | drv_data->len = transfer->len; |
e0c9905e SS |
561 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
562 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
563 | |
564 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 565 | cr0 = chip->cr0; |
9708c121 SS |
566 | if (transfer->speed_hz || transfer->bits_per_word) { |
567 | ||
9708c121 SS |
568 | bits = chip->bits_per_word; |
569 | speed = chip->speed_hz; | |
570 | ||
571 | if (transfer->speed_hz) | |
572 | speed = transfer->speed_hz; | |
573 | ||
574 | if (transfer->bits_per_word) | |
575 | bits = transfer->bits_per_word; | |
576 | ||
3343b7a6 | 577 | clk_div = ssp_get_clk_div(drv_data, speed); |
9708c121 SS |
578 | |
579 | if (bits <= 8) { | |
580 | drv_data->n_bytes = 1; | |
9708c121 SS |
581 | drv_data->read = drv_data->read != null_reader ? |
582 | u8_reader : null_reader; | |
583 | drv_data->write = drv_data->write != null_writer ? | |
584 | u8_writer : null_writer; | |
585 | } else if (bits <= 16) { | |
586 | drv_data->n_bytes = 2; | |
9708c121 SS |
587 | drv_data->read = drv_data->read != null_reader ? |
588 | u16_reader : null_reader; | |
589 | drv_data->write = drv_data->write != null_writer ? | |
590 | u16_writer : null_writer; | |
591 | } else if (bits <= 32) { | |
592 | drv_data->n_bytes = 4; | |
9708c121 SS |
593 | drv_data->read = drv_data->read != null_reader ? |
594 | u32_reader : null_reader; | |
595 | drv_data->write = drv_data->write != null_writer ? | |
596 | u32_writer : null_writer; | |
597 | } | |
8d94cc50 SS |
598 | /* if bits/word is changed in dma mode, then must check the |
599 | * thresholds and burst also */ | |
600 | if (chip->enable_dma) { | |
cd7bed00 MW |
601 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, |
602 | message->spi, | |
8d94cc50 SS |
603 | bits, &dma_burst, |
604 | &dma_thresh)) | |
605 | if (printk_ratelimit()) | |
606 | dev_warn(&message->spi->dev, | |
7e964455 | 607 | "pump_transfers: " |
8d94cc50 SS |
608 | "DMA burst size reduced to " |
609 | "match bits_per_word\n"); | |
610 | } | |
9708c121 SS |
611 | |
612 | cr0 = clk_div | |
613 | | SSCR0_Motorola | |
5daa3ba0 | 614 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
615 | | SSCR0_SSE |
616 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
617 | } |
618 | ||
e0c9905e SS |
619 | message->state = RUNNING_STATE; |
620 | ||
7e964455 | 621 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
622 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
623 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 624 | if (drv_data->dma_mapped) { |
e0c9905e SS |
625 | |
626 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
627 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
628 | ||
629 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 630 | |
8d94cc50 SS |
631 | /* Clear status and start DMA engine */ |
632 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e | 633 | write_SSSR(drv_data->clear_sr, reg); |
cd7bed00 MW |
634 | |
635 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
636 | } else { |
637 | /* Ensure we have the correct interrupt handler */ | |
638 | drv_data->transfer_handler = interrupt_transfer; | |
639 | ||
8d94cc50 SS |
640 | /* Clear status */ |
641 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 642 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
643 | } |
644 | ||
645 | /* see if we need to reload the config registers */ | |
646 | if ((read_SSCR0(reg) != cr0) | |
647 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
648 | (cr1 & SSCR1_CHANGE_MASK)) { | |
649 | ||
b97c74bd | 650 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 651 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
2a8626a9 | 652 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e | 653 | write_SSTO(chip->timeout, reg); |
b97c74bd NF |
654 | /* first set CR1 without interrupt and service enables */ |
655 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
656 | /* restart the SSP */ | |
8d94cc50 | 657 | write_SSCR0(cr0, reg); |
b97c74bd | 658 | |
8d94cc50 | 659 | } else { |
2a8626a9 | 660 | if (!pxa25x_ssp_comp(drv_data)) |
8d94cc50 | 661 | write_SSTO(chip->timeout, reg); |
e0c9905e | 662 | } |
b97c74bd | 663 | |
a7bb3909 | 664 | cs_assert(drv_data); |
b97c74bd NF |
665 | |
666 | /* after chip select, release the data by enabling service | |
667 | * requests and interrupts, without changing any mode bits */ | |
668 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
669 | } |
670 | ||
7f86bde9 MW |
671 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
672 | struct spi_message *msg) | |
e0c9905e | 673 | { |
7f86bde9 | 674 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 675 | |
7f86bde9 | 676 | drv_data->cur_msg = msg; |
e0c9905e SS |
677 | /* Initial message state*/ |
678 | drv_data->cur_msg->state = START_STATE; | |
679 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
680 | struct spi_transfer, | |
681 | transfer_list); | |
682 | ||
8d94cc50 SS |
683 | /* prepare to setup the SSP, in pump_transfers, using the per |
684 | * chip configuration */ | |
e0c9905e | 685 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
686 | |
687 | /* Mark as busy and launch transfers */ | |
688 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
689 | return 0; |
690 | } | |
691 | ||
7d94a505 MW |
692 | static int pxa2xx_spi_prepare_transfer(struct spi_master *master) |
693 | { | |
694 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
695 | ||
696 | pm_runtime_get_sync(&drv_data->pdev->dev); | |
697 | return 0; | |
698 | } | |
699 | ||
700 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) | |
701 | { | |
702 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
703 | ||
704 | /* Disable the SSP now */ | |
705 | write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE, | |
706 | drv_data->ioaddr); | |
707 | ||
708 | pm_runtime_mark_last_busy(&drv_data->pdev->dev); | |
709 | pm_runtime_put_autosuspend(&drv_data->pdev->dev); | |
710 | return 0; | |
711 | } | |
712 | ||
a7bb3909 EM |
713 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
714 | struct pxa2xx_spi_chip *chip_info) | |
715 | { | |
716 | int err = 0; | |
717 | ||
718 | if (chip == NULL || chip_info == NULL) | |
719 | return 0; | |
720 | ||
721 | /* NOTE: setup() can be called multiple times, possibly with | |
722 | * different chip_info, release previously requested GPIO | |
723 | */ | |
724 | if (gpio_is_valid(chip->gpio_cs)) | |
725 | gpio_free(chip->gpio_cs); | |
726 | ||
727 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
728 | if (chip_info->cs_control) { | |
729 | chip->cs_control = chip_info->cs_control; | |
730 | return 0; | |
731 | } | |
732 | ||
733 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
734 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
735 | if (err) { | |
736 | dev_err(&spi->dev, "failed to request chip select " | |
737 | "GPIO%d\n", chip_info->gpio_cs); | |
738 | return err; | |
739 | } | |
740 | ||
741 | chip->gpio_cs = chip_info->gpio_cs; | |
742 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
743 | ||
744 | err = gpio_direction_output(chip->gpio_cs, | |
745 | !chip->gpio_cs_inverted); | |
746 | } | |
747 | ||
748 | return err; | |
749 | } | |
750 | ||
e0c9905e SS |
751 | static int setup(struct spi_device *spi) |
752 | { | |
753 | struct pxa2xx_spi_chip *chip_info = NULL; | |
754 | struct chip_data *chip; | |
755 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
756 | unsigned int clk_div; | |
f1f640a9 VS |
757 | uint tx_thres = TX_THRESH_DFLT; |
758 | uint rx_thres = RX_THRESH_DFLT; | |
e0c9905e | 759 | |
2a8626a9 | 760 | if (!pxa25x_ssp_comp(drv_data) |
8d94cc50 SS |
761 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
762 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
763 | "b/w not 4-32 for type non-PXA25x_SSP\n", | |
764 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 765 | return -EINVAL; |
2a8626a9 | 766 | } else if (pxa25x_ssp_comp(drv_data) |
8d94cc50 SS |
767 | && (spi->bits_per_word < 4 |
768 | || spi->bits_per_word > 16)) { | |
769 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
770 | "b/w not 4-16 for type PXA25x_SSP\n", | |
771 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 772 | return -EINVAL; |
8d94cc50 | 773 | } |
e0c9905e | 774 | |
8d94cc50 | 775 | /* Only alloc on first setup */ |
e0c9905e | 776 | chip = spi_get_ctldata(spi); |
8d94cc50 | 777 | if (!chip) { |
e0c9905e | 778 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
779 | if (!chip) { |
780 | dev_err(&spi->dev, | |
781 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 782 | return -ENOMEM; |
8d94cc50 | 783 | } |
e0c9905e | 784 | |
2a8626a9 SAS |
785 | if (drv_data->ssp_type == CE4100_SSP) { |
786 | if (spi->chip_select > 4) { | |
787 | dev_err(&spi->dev, "failed setup: " | |
788 | "cs number must not be > 4.\n"); | |
789 | kfree(chip); | |
790 | return -EINVAL; | |
791 | } | |
792 | ||
793 | chip->frm = spi->chip_select; | |
794 | } else | |
795 | chip->gpio_cs = -1; | |
e0c9905e | 796 | chip->enable_dma = 0; |
f1f640a9 | 797 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
798 | } |
799 | ||
8d94cc50 SS |
800 | /* protocol drivers may change the chip settings, so... |
801 | * if chip_info exists, use it */ | |
802 | chip_info = spi->controller_data; | |
803 | ||
e0c9905e | 804 | /* chip_info isn't always needed */ |
8d94cc50 | 805 | chip->cr1 = 0; |
e0c9905e | 806 | if (chip_info) { |
f1f640a9 VS |
807 | if (chip_info->timeout) |
808 | chip->timeout = chip_info->timeout; | |
809 | if (chip_info->tx_threshold) | |
810 | tx_thres = chip_info->tx_threshold; | |
811 | if (chip_info->rx_threshold) | |
812 | rx_thres = chip_info->rx_threshold; | |
813 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 814 | chip->dma_threshold = 0; |
e0c9905e SS |
815 | if (chip_info->enable_loopback) |
816 | chip->cr1 = SSCR1_LBM; | |
817 | } | |
818 | ||
f1f640a9 VS |
819 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
820 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
821 | ||
8d94cc50 SS |
822 | /* set dma burst and threshold outside of chip_info path so that if |
823 | * chip_info goes away after setting chip->enable_dma, the | |
824 | * burst and threshold can still respond to changes in bits_per_word */ | |
825 | if (chip->enable_dma) { | |
826 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
827 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
828 | spi->bits_per_word, | |
8d94cc50 SS |
829 | &chip->dma_burst_size, |
830 | &chip->dma_threshold)) { | |
831 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | |
832 | "to match bits_per_word\n"); | |
833 | } | |
834 | } | |
835 | ||
3343b7a6 | 836 | clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); |
9708c121 | 837 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
838 | |
839 | chip->cr0 = clk_div | |
840 | | SSCR0_Motorola | |
5daa3ba0 SS |
841 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
842 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
843 | | SSCR0_SSE |
844 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
845 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
846 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
847 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 848 | |
b833172f MW |
849 | if (spi->mode & SPI_LOOP) |
850 | chip->cr1 |= SSCR1_LBM; | |
851 | ||
e0c9905e | 852 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
2a8626a9 | 853 | if (!pxa25x_ssp_comp(drv_data)) |
7d077197 | 854 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 855 | drv_data->max_clk_rate |
c9840daa EM |
856 | / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)), |
857 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 858 | else |
7d077197 | 859 | dev_dbg(&spi->dev, "%ld Hz actual, %s\n", |
3343b7a6 | 860 | drv_data->max_clk_rate / 2 |
c9840daa EM |
861 | / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
862 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
863 | |
864 | if (spi->bits_per_word <= 8) { | |
865 | chip->n_bytes = 1; | |
e0c9905e SS |
866 | chip->read = u8_reader; |
867 | chip->write = u8_writer; | |
868 | } else if (spi->bits_per_word <= 16) { | |
869 | chip->n_bytes = 2; | |
e0c9905e SS |
870 | chip->read = u16_reader; |
871 | chip->write = u16_writer; | |
872 | } else if (spi->bits_per_word <= 32) { | |
873 | chip->cr0 |= SSCR0_EDSS; | |
874 | chip->n_bytes = 4; | |
e0c9905e SS |
875 | chip->read = u32_reader; |
876 | chip->write = u32_writer; | |
877 | } else { | |
878 | dev_err(&spi->dev, "invalid wordsize\n"); | |
e0c9905e SS |
879 | return -ENODEV; |
880 | } | |
9708c121 | 881 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
882 | |
883 | spi_set_ctldata(spi, chip); | |
884 | ||
2a8626a9 SAS |
885 | if (drv_data->ssp_type == CE4100_SSP) |
886 | return 0; | |
887 | ||
a7bb3909 | 888 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
889 | } |
890 | ||
0ffa0285 | 891 | static void cleanup(struct spi_device *spi) |
e0c9905e | 892 | { |
0ffa0285 | 893 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 894 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 895 | |
7348d82a DR |
896 | if (!chip) |
897 | return; | |
898 | ||
2a8626a9 | 899 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
900 | gpio_free(chip->gpio_cs); |
901 | ||
e0c9905e SS |
902 | kfree(chip); |
903 | } | |
904 | ||
fd4a319b | 905 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
906 | { |
907 | struct device *dev = &pdev->dev; | |
908 | struct pxa2xx_spi_master *platform_info; | |
909 | struct spi_master *master; | |
65a00a20 | 910 | struct driver_data *drv_data; |
2f1a74e5 | 911 | struct ssp_device *ssp; |
65a00a20 | 912 | int status; |
e0c9905e | 913 | |
851bacf5 MW |
914 | platform_info = dev_get_platdata(dev); |
915 | if (!platform_info) { | |
916 | dev_err(&pdev->dev, "missing platform data\n"); | |
917 | return -ENODEV; | |
918 | } | |
e0c9905e | 919 | |
baffe169 | 920 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
921 | if (!ssp) |
922 | ssp = &platform_info->ssp; | |
923 | ||
924 | if (!ssp->mmio_base) { | |
925 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
926 | return -ENODEV; |
927 | } | |
928 | ||
929 | /* Allocate master with space for drv_data and null dma buffer */ | |
930 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
931 | if (!master) { | |
65a00a20 | 932 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 933 | pxa_ssp_free(ssp); |
e0c9905e SS |
934 | return -ENOMEM; |
935 | } | |
936 | drv_data = spi_master_get_devdata(master); | |
937 | drv_data->master = master; | |
938 | drv_data->master_info = platform_info; | |
939 | drv_data->pdev = pdev; | |
2f1a74e5 | 940 | drv_data->ssp = ssp; |
e0c9905e | 941 | |
21486af0 | 942 | master->dev.parent = &pdev->dev; |
21486af0 | 943 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 944 | /* the spi->mode bits understood by this driver: */ |
b833172f | 945 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 946 | |
851bacf5 | 947 | master->bus_num = ssp->port_id; |
e0c9905e | 948 | master->num_chipselect = platform_info->num_chipselect; |
7ad0ba91 | 949 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
950 | master->cleanup = cleanup; |
951 | master->setup = setup; | |
7f86bde9 | 952 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 MW |
953 | master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer; |
954 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; | |
e0c9905e | 955 | |
2f1a74e5 | 956 | drv_data->ssp_type = ssp->type; |
2b9b84f4 | 957 | drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT); |
e0c9905e | 958 | |
2f1a74e5 | 959 | drv_data->ioaddr = ssp->mmio_base; |
960 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 961 | if (pxa25x_ssp_comp(drv_data)) { |
e0c9905e SS |
962 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
963 | drv_data->dma_cr1 = 0; | |
964 | drv_data->clear_sr = SSSR_ROR; | |
965 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
966 | } else { | |
967 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | |
5928808e | 968 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
969 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
970 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
971 | } | |
972 | ||
49cbb1e0 SAS |
973 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
974 | drv_data); | |
e0c9905e | 975 | if (status < 0) { |
65a00a20 | 976 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
977 | goto out_error_master_alloc; |
978 | } | |
979 | ||
980 | /* Setup DMA if requested */ | |
981 | drv_data->tx_channel = -1; | |
982 | drv_data->rx_channel = -1; | |
983 | if (platform_info->enable_dma) { | |
cd7bed00 MW |
984 | status = pxa2xx_spi_dma_setup(drv_data); |
985 | if (status) { | |
986 | dev_warn(dev, "failed to setup DMA, using PIO\n"); | |
987 | platform_info->enable_dma = false; | |
e0c9905e | 988 | } |
e0c9905e SS |
989 | } |
990 | ||
991 | /* Enable SOC clock */ | |
3343b7a6 MW |
992 | clk_prepare_enable(ssp->clk); |
993 | ||
994 | drv_data->max_clk_rate = clk_get_rate(ssp->clk); | |
e0c9905e SS |
995 | |
996 | /* Load default SSP configuration */ | |
997 | write_SSCR0(0, drv_data->ioaddr); | |
f1f640a9 VS |
998 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | |
999 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1000 | drv_data->ioaddr); | |
c9840daa | 1001 | write_SSCR0(SSCR0_SCR(2) |
e0c9905e SS |
1002 | | SSCR0_Motorola |
1003 | | SSCR0_DataSize(8), | |
1004 | drv_data->ioaddr); | |
2a8626a9 | 1005 | if (!pxa25x_ssp_comp(drv_data)) |
e0c9905e SS |
1006 | write_SSTO(0, drv_data->ioaddr); |
1007 | write_SSPSP(0, drv_data->ioaddr); | |
1008 | ||
7f86bde9 MW |
1009 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1010 | (unsigned long)drv_data); | |
e0c9905e SS |
1011 | |
1012 | /* Register with the SPI framework */ | |
1013 | platform_set_drvdata(pdev, drv_data); | |
1014 | status = spi_register_master(master); | |
1015 | if (status != 0) { | |
1016 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1017 | goto out_error_clock_enabled; |
e0c9905e SS |
1018 | } |
1019 | ||
7d94a505 MW |
1020 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1021 | pm_runtime_use_autosuspend(&pdev->dev); | |
1022 | pm_runtime_set_active(&pdev->dev); | |
1023 | pm_runtime_enable(&pdev->dev); | |
1024 | ||
e0c9905e SS |
1025 | return status; |
1026 | ||
e0c9905e | 1027 | out_error_clock_enabled: |
3343b7a6 | 1028 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1029 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1030 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1031 | |
1032 | out_error_master_alloc: | |
1033 | spi_master_put(master); | |
baffe169 | 1034 | pxa_ssp_free(ssp); |
e0c9905e SS |
1035 | return status; |
1036 | } | |
1037 | ||
1038 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1039 | { | |
1040 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1041 | struct ssp_device *ssp; |
e0c9905e SS |
1042 | |
1043 | if (!drv_data) | |
1044 | return 0; | |
51e911e2 | 1045 | ssp = drv_data->ssp; |
e0c9905e | 1046 | |
7d94a505 MW |
1047 | pm_runtime_get_sync(&pdev->dev); |
1048 | ||
e0c9905e SS |
1049 | /* Disable the SSP at the peripheral and SOC level */ |
1050 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1051 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1052 | |
1053 | /* Release DMA */ | |
cd7bed00 MW |
1054 | if (drv_data->master_info->enable_dma) |
1055 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1056 | |
7d94a505 MW |
1057 | pm_runtime_put_noidle(&pdev->dev); |
1058 | pm_runtime_disable(&pdev->dev); | |
1059 | ||
e0c9905e | 1060 | /* Release IRQ */ |
2f1a74e5 | 1061 | free_irq(ssp->irq, drv_data); |
1062 | ||
1063 | /* Release SSP */ | |
baffe169 | 1064 | pxa_ssp_free(ssp); |
e0c9905e SS |
1065 | |
1066 | /* Disconnect from the SPI framework */ | |
1067 | spi_unregister_master(drv_data->master); | |
1068 | ||
1069 | /* Prevent double remove */ | |
1070 | platform_set_drvdata(pdev, NULL); | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1076 | { | |
1077 | int status = 0; | |
1078 | ||
1079 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1080 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1081 | } | |
1082 | ||
1083 | #ifdef CONFIG_PM | |
86d2593a | 1084 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1085 | { |
86d2593a | 1086 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1087 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1088 | int status = 0; |
1089 | ||
7f86bde9 | 1090 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1091 | if (status != 0) |
1092 | return status; | |
1093 | write_SSCR0(0, drv_data->ioaddr); | |
3343b7a6 | 1094 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1095 | |
1096 | return 0; | |
1097 | } | |
1098 | ||
86d2593a | 1099 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1100 | { |
86d2593a | 1101 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1102 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1103 | int status = 0; |
1104 | ||
cd7bed00 | 1105 | pxa2xx_spi_dma_resume(drv_data); |
148da331 | 1106 | |
e0c9905e | 1107 | /* Enable the SSP clock */ |
3343b7a6 | 1108 | clk_prepare_enable(ssp->clk); |
e0c9905e SS |
1109 | |
1110 | /* Start the queue running */ | |
7f86bde9 | 1111 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1112 | if (status != 0) { |
86d2593a | 1113 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1114 | return status; |
1115 | } | |
1116 | ||
1117 | return 0; | |
1118 | } | |
7d94a505 MW |
1119 | #endif |
1120 | ||
1121 | #ifdef CONFIG_PM_RUNTIME | |
1122 | static int pxa2xx_spi_runtime_suspend(struct device *dev) | |
1123 | { | |
1124 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1125 | ||
1126 | clk_disable_unprepare(drv_data->ssp->clk); | |
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1131 | { | |
1132 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1133 | ||
1134 | clk_prepare_enable(drv_data->ssp->clk); | |
1135 | return 0; | |
1136 | } | |
1137 | #endif | |
86d2593a | 1138 | |
47145210 | 1139 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1140 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1141 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1142 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1143 | }; |
e0c9905e SS |
1144 | |
1145 | static struct platform_driver driver = { | |
1146 | .driver = { | |
86d2593a MR |
1147 | .name = "pxa2xx-spi", |
1148 | .owner = THIS_MODULE, | |
86d2593a | 1149 | .pm = &pxa2xx_spi_pm_ops, |
e0c9905e | 1150 | }, |
fbd29a14 | 1151 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1152 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1153 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1154 | }; |
1155 | ||
1156 | static int __init pxa2xx_spi_init(void) | |
1157 | { | |
fbd29a14 | 1158 | return platform_driver_register(&driver); |
e0c9905e | 1159 | } |
5b61a749 | 1160 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1161 | |
1162 | static void __exit pxa2xx_spi_exit(void) | |
1163 | { | |
1164 | platform_driver_unregister(&driver); | |
1165 | } | |
1166 | module_exit(pxa2xx_spi_exit); |