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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
e0c9905e SS |
14 | */ |
15 | ||
8b136baa | 16 | #include <linux/bitops.h> |
e0c9905e SS |
17 | #include <linux/init.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/errno.h> | |
cbfd6a21 | 22 | #include <linux/err.h> |
e0c9905e | 23 | #include <linux/interrupt.h> |
9df461ec | 24 | #include <linux/kernel.h> |
34cadd9c | 25 | #include <linux/pci.h> |
e0c9905e | 26 | #include <linux/platform_device.h> |
8348c259 | 27 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 28 | #include <linux/spi/spi.h> |
e0c9905e | 29 | #include <linux/delay.h> |
a7bb3909 | 30 | #include <linux/gpio.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
3343b7a6 | 32 | #include <linux/clk.h> |
7d94a505 | 33 | #include <linux/pm_runtime.h> |
a3496855 | 34 | #include <linux/acpi.h> |
e0c9905e | 35 | |
cd7bed00 | 36 | #include "spi-pxa2xx.h" |
e0c9905e SS |
37 | |
38 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 39 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 40 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 41 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e | 42 | |
f1f640a9 VS |
43 | #define TIMOUT_DFLT 1000 |
44 | ||
b97c74bd NF |
45 | /* |
46 | * for testing SSCR1 changes that require SSP restart, basically | |
47 | * everything except the service and interrupt enables, the pxa270 developer | |
48 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
49 | * list, but the PXA255 dev man says all bits without really meaning the | |
50 | * service and interrupt enables | |
51 | */ | |
52 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 53 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
54 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
55 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
56 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
57 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 58 | |
e5262d05 WC |
59 | #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ |
60 | | QUARK_X1000_SSCR1_EFWR \ | |
61 | | QUARK_X1000_SSCR1_RFT \ | |
62 | | QUARK_X1000_SSCR1_TFT \ | |
63 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
64 | ||
624ea72e JN |
65 | #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) |
66 | #define LPSS_CS_CONTROL_SW_MODE BIT(0) | |
67 | #define LPSS_CS_CONTROL_CS_HIGH BIT(1) | |
8b136baa JN |
68 | #define LPSS_CAPS_CS_EN_SHIFT 9 |
69 | #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) | |
a0d2642e | 70 | |
dccf7369 JN |
71 | struct lpss_config { |
72 | /* LPSS offset from drv_data->ioaddr */ | |
73 | unsigned offset; | |
74 | /* Register offsets from drv_data->lpss_base or -1 */ | |
75 | int reg_general; | |
76 | int reg_ssp; | |
77 | int reg_cs_ctrl; | |
8b136baa | 78 | int reg_capabilities; |
dccf7369 JN |
79 | /* FIFO thresholds */ |
80 | u32 rx_threshold; | |
81 | u32 tx_threshold_lo; | |
82 | u32 tx_threshold_hi; | |
c1e4a53c MW |
83 | /* Chip select control */ |
84 | unsigned cs_sel_shift; | |
85 | unsigned cs_sel_mask; | |
dccf7369 JN |
86 | }; |
87 | ||
88 | /* Keep these sorted with enum pxa_ssp_type */ | |
89 | static const struct lpss_config lpss_platforms[] = { | |
90 | { /* LPSS_LPT_SSP */ | |
91 | .offset = 0x800, | |
92 | .reg_general = 0x08, | |
93 | .reg_ssp = 0x0c, | |
94 | .reg_cs_ctrl = 0x18, | |
8b136baa | 95 | .reg_capabilities = -1, |
dccf7369 JN |
96 | .rx_threshold = 64, |
97 | .tx_threshold_lo = 160, | |
98 | .tx_threshold_hi = 224, | |
99 | }, | |
100 | { /* LPSS_BYT_SSP */ | |
101 | .offset = 0x400, | |
102 | .reg_general = 0x08, | |
103 | .reg_ssp = 0x0c, | |
104 | .reg_cs_ctrl = 0x18, | |
8b136baa | 105 | .reg_capabilities = -1, |
dccf7369 JN |
106 | .rx_threshold = 64, |
107 | .tx_threshold_lo = 160, | |
108 | .tx_threshold_hi = 224, | |
109 | }, | |
34cadd9c JN |
110 | { /* LPSS_SPT_SSP */ |
111 | .offset = 0x200, | |
112 | .reg_general = -1, | |
113 | .reg_ssp = 0x20, | |
114 | .reg_cs_ctrl = 0x24, | |
8b136baa | 115 | .reg_capabilities = 0xfc, |
34cadd9c JN |
116 | .rx_threshold = 1, |
117 | .tx_threshold_lo = 32, | |
118 | .tx_threshold_hi = 56, | |
119 | }, | |
b7c08cf8 JN |
120 | { /* LPSS_BXT_SSP */ |
121 | .offset = 0x200, | |
122 | .reg_general = -1, | |
123 | .reg_ssp = 0x20, | |
124 | .reg_cs_ctrl = 0x24, | |
125 | .reg_capabilities = 0xfc, | |
126 | .rx_threshold = 1, | |
127 | .tx_threshold_lo = 16, | |
128 | .tx_threshold_hi = 48, | |
c1e4a53c MW |
129 | .cs_sel_shift = 8, |
130 | .cs_sel_mask = 3 << 8, | |
b7c08cf8 | 131 | }, |
dccf7369 JN |
132 | }; |
133 | ||
134 | static inline const struct lpss_config | |
135 | *lpss_get_config(const struct driver_data *drv_data) | |
136 | { | |
137 | return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; | |
138 | } | |
139 | ||
a0d2642e MW |
140 | static bool is_lpss_ssp(const struct driver_data *drv_data) |
141 | { | |
03fbf488 JN |
142 | switch (drv_data->ssp_type) { |
143 | case LPSS_LPT_SSP: | |
144 | case LPSS_BYT_SSP: | |
34cadd9c | 145 | case LPSS_SPT_SSP: |
b7c08cf8 | 146 | case LPSS_BXT_SSP: |
03fbf488 JN |
147 | return true; |
148 | default: | |
149 | return false; | |
150 | } | |
a0d2642e MW |
151 | } |
152 | ||
e5262d05 WC |
153 | static bool is_quark_x1000_ssp(const struct driver_data *drv_data) |
154 | { | |
155 | return drv_data->ssp_type == QUARK_X1000_SSP; | |
156 | } | |
157 | ||
4fdb2424 WC |
158 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
159 | { | |
160 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
161 | case QUARK_X1000_SSP: |
162 | return QUARK_X1000_SSCR1_CHANGE_MASK; | |
4fdb2424 WC |
163 | default: |
164 | return SSCR1_CHANGE_MASK; | |
165 | } | |
166 | } | |
167 | ||
168 | static u32 | |
169 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
170 | { | |
171 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
172 | case QUARK_X1000_SSP: |
173 | return RX_THRESH_QUARK_X1000_DFLT; | |
4fdb2424 WC |
174 | default: |
175 | return RX_THRESH_DFLT; | |
176 | } | |
177 | } | |
178 | ||
179 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
180 | { | |
4fdb2424 WC |
181 | u32 mask; |
182 | ||
183 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
184 | case QUARK_X1000_SSP: |
185 | mask = QUARK_X1000_SSSR_TFL_MASK; | |
186 | break; | |
4fdb2424 WC |
187 | default: |
188 | mask = SSSR_TFL_MASK; | |
189 | break; | |
190 | } | |
191 | ||
c039dd27 | 192 | return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; |
4fdb2424 WC |
193 | } |
194 | ||
195 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
196 | u32 *sccr1_reg) | |
197 | { | |
198 | u32 mask; | |
199 | ||
200 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
201 | case QUARK_X1000_SSP: |
202 | mask = QUARK_X1000_SSCR1_RFT; | |
203 | break; | |
4fdb2424 WC |
204 | default: |
205 | mask = SSCR1_RFT; | |
206 | break; | |
207 | } | |
208 | *sccr1_reg &= ~mask; | |
209 | } | |
210 | ||
211 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
212 | u32 *sccr1_reg, u32 threshold) | |
213 | { | |
214 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
215 | case QUARK_X1000_SSP: |
216 | *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); | |
217 | break; | |
4fdb2424 WC |
218 | default: |
219 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
220 | break; | |
221 | } | |
222 | } | |
223 | ||
224 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
225 | u32 clk_div, u8 bits) | |
226 | { | |
227 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
228 | case QUARK_X1000_SSP: |
229 | return clk_div | |
230 | | QUARK_X1000_SSCR0_Motorola | |
231 | | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) | |
232 | | SSCR0_SSE; | |
4fdb2424 WC |
233 | default: |
234 | return clk_div | |
235 | | SSCR0_Motorola | |
236 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
237 | | SSCR0_SSE | |
238 | | (bits > 16 ? SSCR0_EDSS : 0); | |
239 | } | |
240 | } | |
241 | ||
a0d2642e MW |
242 | /* |
243 | * Read and write LPSS SSP private registers. Caller must first check that | |
244 | * is_lpss_ssp() returns true before these can be called. | |
245 | */ | |
246 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
247 | { | |
248 | WARN_ON(!drv_data->lpss_base); | |
249 | return readl(drv_data->lpss_base + offset); | |
250 | } | |
251 | ||
252 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
253 | unsigned offset, u32 value) | |
254 | { | |
255 | WARN_ON(!drv_data->lpss_base); | |
256 | writel(value, drv_data->lpss_base + offset); | |
257 | } | |
258 | ||
259 | /* | |
260 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
261 | * @drv_data: pointer to the driver private data | |
262 | * | |
263 | * Perform LPSS SSP specific setup. This function must be called first if | |
264 | * one is going to use LPSS SSP private registers. | |
265 | */ | |
266 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
267 | { | |
dccf7369 JN |
268 | const struct lpss_config *config; |
269 | u32 value; | |
a0d2642e | 270 | |
dccf7369 JN |
271 | config = lpss_get_config(drv_data); |
272 | drv_data->lpss_base = drv_data->ioaddr + config->offset; | |
a0d2642e MW |
273 | |
274 | /* Enable software chip select control */ | |
0e897218 | 275 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
624ea72e JN |
276 | value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); |
277 | value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; | |
dccf7369 | 278 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
0054e28d MW |
279 | |
280 | /* Enable multiblock DMA transfers */ | |
1de70612 | 281 | if (drv_data->master_info->enable_dma) { |
dccf7369 | 282 | __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); |
1de70612 | 283 | |
82ba2c2a JN |
284 | if (config->reg_general >= 0) { |
285 | value = __lpss_ssp_read_priv(drv_data, | |
286 | config->reg_general); | |
624ea72e | 287 | value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; |
82ba2c2a JN |
288 | __lpss_ssp_write_priv(drv_data, |
289 | config->reg_general, value); | |
290 | } | |
1de70612 | 291 | } |
a0d2642e MW |
292 | } |
293 | ||
c1e4a53c MW |
294 | static void lpss_ssp_select_cs(struct driver_data *drv_data, |
295 | const struct lpss_config *config) | |
296 | { | |
297 | u32 value, cs; | |
298 | ||
299 | if (!config->cs_sel_mask) | |
300 | return; | |
301 | ||
302 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); | |
303 | ||
304 | cs = drv_data->cur_msg->spi->chip_select; | |
305 | cs <<= config->cs_sel_shift; | |
306 | if (cs != (value & config->cs_sel_mask)) { | |
307 | /* | |
308 | * When switching another chip select output active the | |
309 | * output must be selected first and wait 2 ssp_clk cycles | |
310 | * before changing state to active. Otherwise a short | |
311 | * glitch will occur on the previous chip select since | |
312 | * output select is latched but state control is not. | |
313 | */ | |
314 | value &= ~config->cs_sel_mask; | |
315 | value |= cs; | |
316 | __lpss_ssp_write_priv(drv_data, | |
317 | config->reg_cs_ctrl, value); | |
318 | ndelay(1000000000 / | |
319 | (drv_data->master->max_speed_hz / 2)); | |
320 | } | |
321 | } | |
322 | ||
a0d2642e MW |
323 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) |
324 | { | |
dccf7369 | 325 | const struct lpss_config *config; |
c1e4a53c | 326 | u32 value; |
a0d2642e | 327 | |
dccf7369 JN |
328 | config = lpss_get_config(drv_data); |
329 | ||
c1e4a53c MW |
330 | if (enable) |
331 | lpss_ssp_select_cs(drv_data, config); | |
332 | ||
dccf7369 | 333 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
c1e4a53c | 334 | if (enable) |
624ea72e | 335 | value &= ~LPSS_CS_CONTROL_CS_HIGH; |
c1e4a53c | 336 | else |
624ea72e | 337 | value |= LPSS_CS_CONTROL_CS_HIGH; |
dccf7369 | 338 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
a0d2642e MW |
339 | } |
340 | ||
a7bb3909 EM |
341 | static void cs_assert(struct driver_data *drv_data) |
342 | { | |
343 | struct chip_data *chip = drv_data->cur_chip; | |
344 | ||
2a8626a9 | 345 | if (drv_data->ssp_type == CE4100_SSP) { |
c039dd27 | 346 | pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm); |
2a8626a9 SAS |
347 | return; |
348 | } | |
349 | ||
a7bb3909 EM |
350 | if (chip->cs_control) { |
351 | chip->cs_control(PXA2XX_CS_ASSERT); | |
352 | return; | |
353 | } | |
354 | ||
a0d2642e | 355 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 356 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
357 | return; |
358 | } | |
359 | ||
7566bcc7 JN |
360 | if (is_lpss_ssp(drv_data)) |
361 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
362 | } |
363 | ||
364 | static void cs_deassert(struct driver_data *drv_data) | |
365 | { | |
366 | struct chip_data *chip = drv_data->cur_chip; | |
367 | ||
2a8626a9 SAS |
368 | if (drv_data->ssp_type == CE4100_SSP) |
369 | return; | |
370 | ||
a7bb3909 | 371 | if (chip->cs_control) { |
2b2562d3 | 372 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
373 | return; |
374 | } | |
375 | ||
a0d2642e | 376 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 377 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
378 | return; |
379 | } | |
380 | ||
7566bcc7 JN |
381 | if (is_lpss_ssp(drv_data)) |
382 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
383 | } |
384 | ||
cd7bed00 | 385 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
386 | { |
387 | unsigned long limit = loops_per_jiffy << 1; | |
388 | ||
e0c9905e | 389 | do { |
c039dd27 JN |
390 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
391 | pxa2xx_spi_read(drv_data, SSDR); | |
392 | } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); | |
2a8626a9 | 393 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
394 | |
395 | return limit; | |
396 | } | |
397 | ||
8d94cc50 | 398 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 399 | { |
9708c121 | 400 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 401 | |
4fdb2424 | 402 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
403 | || (drv_data->tx == drv_data->tx_end)) |
404 | return 0; | |
405 | ||
c039dd27 | 406 | pxa2xx_spi_write(drv_data, SSDR, 0); |
8d94cc50 SS |
407 | drv_data->tx += n_bytes; |
408 | ||
409 | return 1; | |
e0c9905e SS |
410 | } |
411 | ||
8d94cc50 | 412 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 413 | { |
9708c121 | 414 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 415 | |
c039dd27 JN |
416 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
417 | && (drv_data->rx < drv_data->rx_end)) { | |
418 | pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
419 | drv_data->rx += n_bytes; |
420 | } | |
8d94cc50 SS |
421 | |
422 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
423 | } |
424 | ||
8d94cc50 | 425 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 426 | { |
4fdb2424 | 427 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
428 | || (drv_data->tx == drv_data->tx_end)) |
429 | return 0; | |
430 | ||
c039dd27 | 431 | pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); |
8d94cc50 SS |
432 | ++drv_data->tx; |
433 | ||
434 | return 1; | |
e0c9905e SS |
435 | } |
436 | ||
8d94cc50 | 437 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 438 | { |
c039dd27 JN |
439 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
440 | && (drv_data->rx < drv_data->rx_end)) { | |
441 | *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
442 | ++drv_data->rx; |
443 | } | |
8d94cc50 SS |
444 | |
445 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
446 | } |
447 | ||
8d94cc50 | 448 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 449 | { |
4fdb2424 | 450 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
451 | || (drv_data->tx == drv_data->tx_end)) |
452 | return 0; | |
453 | ||
c039dd27 | 454 | pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); |
8d94cc50 SS |
455 | drv_data->tx += 2; |
456 | ||
457 | return 1; | |
e0c9905e SS |
458 | } |
459 | ||
8d94cc50 | 460 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 461 | { |
c039dd27 JN |
462 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
463 | && (drv_data->rx < drv_data->rx_end)) { | |
464 | *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
465 | drv_data->rx += 2; |
466 | } | |
8d94cc50 SS |
467 | |
468 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 469 | } |
8d94cc50 SS |
470 | |
471 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 472 | { |
4fdb2424 | 473 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
474 | || (drv_data->tx == drv_data->tx_end)) |
475 | return 0; | |
476 | ||
c039dd27 | 477 | pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); |
8d94cc50 SS |
478 | drv_data->tx += 4; |
479 | ||
480 | return 1; | |
e0c9905e SS |
481 | } |
482 | ||
8d94cc50 | 483 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 484 | { |
c039dd27 JN |
485 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
486 | && (drv_data->rx < drv_data->rx_end)) { | |
487 | *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
488 | drv_data->rx += 4; |
489 | } | |
8d94cc50 SS |
490 | |
491 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
492 | } |
493 | ||
cd7bed00 | 494 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e SS |
495 | { |
496 | struct spi_message *msg = drv_data->cur_msg; | |
497 | struct spi_transfer *trans = drv_data->cur_transfer; | |
498 | ||
499 | /* Move to next transfer */ | |
500 | if (trans->transfer_list.next != &msg->transfers) { | |
501 | drv_data->cur_transfer = | |
502 | list_entry(trans->transfer_list.next, | |
503 | struct spi_transfer, | |
504 | transfer_list); | |
505 | return RUNNING_STATE; | |
506 | } else | |
507 | return DONE_STATE; | |
508 | } | |
509 | ||
e0c9905e | 510 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 511 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
512 | { |
513 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 514 | struct spi_message *msg; |
7a8d44bc | 515 | unsigned long timeout; |
e0c9905e | 516 | |
5daa3ba0 SS |
517 | msg = drv_data->cur_msg; |
518 | drv_data->cur_msg = NULL; | |
519 | drv_data->cur_transfer = NULL; | |
5daa3ba0 | 520 | |
23e2c2aa | 521 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e0c9905e SS |
522 | transfer_list); |
523 | ||
8423597d NF |
524 | /* Delay if requested before any change in chip select */ |
525 | if (last_transfer->delay_usecs) | |
526 | udelay(last_transfer->delay_usecs); | |
527 | ||
7a8d44bc JN |
528 | /* Wait until SSP becomes idle before deasserting the CS */ |
529 | timeout = jiffies + msecs_to_jiffies(10); | |
530 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && | |
531 | !time_after(jiffies, timeout)) | |
532 | cpu_relax(); | |
533 | ||
8423597d NF |
534 | /* Drop chip select UNLESS cs_change is true or we are returning |
535 | * a message with an error, or next message is for another chip | |
536 | */ | |
e0c9905e | 537 | if (!last_transfer->cs_change) |
a7bb3909 | 538 | cs_deassert(drv_data); |
8423597d NF |
539 | else { |
540 | struct spi_message *next_msg; | |
541 | ||
542 | /* Holding of cs was hinted, but we need to make sure | |
543 | * the next message is for the same chip. Don't waste | |
544 | * time with the following tests unless this was hinted. | |
545 | * | |
546 | * We cannot postpone this until pump_messages, because | |
547 | * after calling msg->complete (below) the driver that | |
548 | * sent the current message could be unloaded, which | |
549 | * could invalidate the cs_control() callback... | |
550 | */ | |
551 | ||
552 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 553 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
554 | |
555 | /* see if the next and current messages point | |
556 | * to the same chip | |
557 | */ | |
558 | if (next_msg && next_msg->spi != msg->spi) | |
559 | next_msg = NULL; | |
560 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 561 | cs_deassert(drv_data); |
8423597d | 562 | } |
e0c9905e | 563 | |
a7bb3909 | 564 | drv_data->cur_chip = NULL; |
c957e8f0 | 565 | spi_finalize_current_message(drv_data->master); |
e0c9905e SS |
566 | } |
567 | ||
579d3bb2 SAS |
568 | static void reset_sccr1(struct driver_data *drv_data) |
569 | { | |
579d3bb2 SAS |
570 | struct chip_data *chip = drv_data->cur_chip; |
571 | u32 sccr1_reg; | |
572 | ||
c039dd27 | 573 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; |
579d3bb2 SAS |
574 | sccr1_reg &= ~SSCR1_RFT; |
575 | sccr1_reg |= chip->threshold; | |
c039dd27 | 576 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
579d3bb2 SAS |
577 | } |
578 | ||
8d94cc50 | 579 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 580 | { |
8d94cc50 | 581 | /* Stop and reset SSP */ |
2a8626a9 | 582 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 583 | reset_sccr1(drv_data); |
2a8626a9 | 584 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 585 | pxa2xx_spi_write(drv_data, SSTO, 0); |
cd7bed00 | 586 | pxa2xx_spi_flush(drv_data); |
c039dd27 JN |
587 | pxa2xx_spi_write(drv_data, SSCR0, |
588 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
e0c9905e | 589 | |
8d94cc50 | 590 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 591 | |
8d94cc50 SS |
592 | drv_data->cur_msg->state = ERROR_STATE; |
593 | tasklet_schedule(&drv_data->pump_transfers); | |
594 | } | |
5daa3ba0 | 595 | |
8d94cc50 SS |
596 | static void int_transfer_complete(struct driver_data *drv_data) |
597 | { | |
07550df0 | 598 | /* Clear and disable interrupts */ |
2a8626a9 | 599 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 600 | reset_sccr1(drv_data); |
2a8626a9 | 601 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 602 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e0c9905e | 603 | |
25985edc | 604 | /* Update total byte transferred return count actual bytes read */ |
8d94cc50 SS |
605 | drv_data->cur_msg->actual_length += drv_data->len - |
606 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 607 | |
8423597d NF |
608 | /* Transfer delays and chip select release are |
609 | * handled in pump_transfers or giveback | |
610 | */ | |
e0c9905e | 611 | |
8d94cc50 | 612 | /* Move to next transfer */ |
cd7bed00 | 613 | drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 614 | |
8d94cc50 SS |
615 | /* Schedule transfer tasklet */ |
616 | tasklet_schedule(&drv_data->pump_transfers); | |
617 | } | |
e0c9905e | 618 | |
8d94cc50 SS |
619 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
620 | { | |
c039dd27 JN |
621 | u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? |
622 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 623 | |
c039dd27 | 624 | u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; |
e0c9905e | 625 | |
8d94cc50 SS |
626 | if (irq_status & SSSR_ROR) { |
627 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
628 | return IRQ_HANDLED; | |
629 | } | |
e0c9905e | 630 | |
8d94cc50 | 631 | if (irq_status & SSSR_TINT) { |
c039dd27 | 632 | pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); |
8d94cc50 SS |
633 | if (drv_data->read(drv_data)) { |
634 | int_transfer_complete(drv_data); | |
635 | return IRQ_HANDLED; | |
636 | } | |
637 | } | |
e0c9905e | 638 | |
8d94cc50 SS |
639 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
640 | do { | |
641 | if (drv_data->read(drv_data)) { | |
642 | int_transfer_complete(drv_data); | |
643 | return IRQ_HANDLED; | |
644 | } | |
645 | } while (drv_data->write(drv_data)); | |
e0c9905e | 646 | |
8d94cc50 SS |
647 | if (drv_data->read(drv_data)) { |
648 | int_transfer_complete(drv_data); | |
649 | return IRQ_HANDLED; | |
650 | } | |
e0c9905e | 651 | |
8d94cc50 | 652 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
653 | u32 bytes_left; |
654 | u32 sccr1_reg; | |
655 | ||
c039dd27 | 656 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
579d3bb2 SAS |
657 | sccr1_reg &= ~SSCR1_TIE; |
658 | ||
659 | /* | |
660 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 661 | * remaining RX bytes. |
579d3bb2 | 662 | */ |
2a8626a9 | 663 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 664 | u32 rx_thre; |
579d3bb2 | 665 | |
4fdb2424 | 666 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
667 | |
668 | bytes_left = drv_data->rx_end - drv_data->rx; | |
669 | switch (drv_data->n_bytes) { | |
670 | case 4: | |
671 | bytes_left >>= 1; | |
672 | case 2: | |
673 | bytes_left >>= 1; | |
8d94cc50 | 674 | } |
579d3bb2 | 675 | |
4fdb2424 WC |
676 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
677 | if (rx_thre > bytes_left) | |
678 | rx_thre = bytes_left; | |
579d3bb2 | 679 | |
4fdb2424 | 680 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 681 | } |
c039dd27 | 682 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
e0c9905e SS |
683 | } |
684 | ||
5daa3ba0 SS |
685 | /* We did something */ |
686 | return IRQ_HANDLED; | |
e0c9905e SS |
687 | } |
688 | ||
7d12e780 | 689 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 690 | { |
c7bec5ab | 691 | struct driver_data *drv_data = dev_id; |
7d94a505 | 692 | u32 sccr1_reg; |
49cbb1e0 SAS |
693 | u32 mask = drv_data->mask_sr; |
694 | u32 status; | |
695 | ||
7d94a505 MW |
696 | /* |
697 | * The IRQ might be shared with other peripherals so we must first | |
698 | * check that are we RPM suspended or not. If we are we assume that | |
699 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
700 | * interrupt is enabled). | |
701 | */ | |
702 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
703 | return IRQ_NONE; | |
704 | ||
269e4a41 MW |
705 | /* |
706 | * If the device is not yet in RPM suspended state and we get an | |
707 | * interrupt that is meant for another device, check if status bits | |
708 | * are all set to one. That means that the device is already | |
709 | * powered off. | |
710 | */ | |
c039dd27 | 711 | status = pxa2xx_spi_read(drv_data, SSSR); |
269e4a41 MW |
712 | if (status == ~0) |
713 | return IRQ_NONE; | |
714 | ||
c039dd27 | 715 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
49cbb1e0 SAS |
716 | |
717 | /* Ignore possible writes if we don't need to write */ | |
718 | if (!(sccr1_reg & SSCR1_TIE)) | |
719 | mask &= ~SSSR_TFS; | |
720 | ||
02bc933e TJN |
721 | /* Ignore RX timeout interrupt if it is disabled */ |
722 | if (!(sccr1_reg & SSCR1_TINTE)) | |
723 | mask &= ~SSSR_TINT; | |
724 | ||
49cbb1e0 SAS |
725 | if (!(status & mask)) |
726 | return IRQ_NONE; | |
e0c9905e SS |
727 | |
728 | if (!drv_data->cur_msg) { | |
5daa3ba0 | 729 | |
c039dd27 JN |
730 | pxa2xx_spi_write(drv_data, SSCR0, |
731 | pxa2xx_spi_read(drv_data, SSCR0) | |
732 | & ~SSCR0_SSE); | |
733 | pxa2xx_spi_write(drv_data, SSCR1, | |
734 | pxa2xx_spi_read(drv_data, SSCR1) | |
735 | & ~drv_data->int_cr1); | |
2a8626a9 | 736 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 737 | pxa2xx_spi_write(drv_data, SSTO, 0); |
2a8626a9 | 738 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
5daa3ba0 | 739 | |
f6bd03a7 JN |
740 | dev_err(&drv_data->pdev->dev, |
741 | "bad message state in interrupt handler\n"); | |
5daa3ba0 | 742 | |
e0c9905e SS |
743 | /* Never fail */ |
744 | return IRQ_HANDLED; | |
745 | } | |
746 | ||
747 | return drv_data->transfer_handler(drv_data); | |
748 | } | |
749 | ||
e5262d05 | 750 | /* |
9df461ec AS |
751 | * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply |
752 | * input frequency by fractions of 2^24. It also has a divider by 5. | |
753 | * | |
754 | * There are formulas to get baud rate value for given input frequency and | |
755 | * divider parameters, such as DDS_CLK_RATE and SCR: | |
756 | * | |
757 | * Fsys = 200MHz | |
758 | * | |
759 | * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) | |
760 | * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) | |
761 | * | |
762 | * DDS_CLK_RATE either 2^n or 2^n / 5. | |
763 | * SCR is in range 0 .. 255 | |
764 | * | |
765 | * Divisor = 5^i * 2^j * 2 * k | |
766 | * i = [0, 1] i = 1 iff j = 0 or j > 3 | |
767 | * j = [0, 23] j = 0 iff i = 1 | |
768 | * k = [1, 256] | |
769 | * Special case: j = 0, i = 1: Divisor = 2 / 5 | |
770 | * | |
771 | * Accordingly to the specification the recommended values for DDS_CLK_RATE | |
772 | * are: | |
773 | * Case 1: 2^n, n = [0, 23] | |
774 | * Case 2: 2^24 * 2 / 5 (0x666666) | |
775 | * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) | |
776 | * | |
777 | * In all cases the lowest possible value is better. | |
778 | * | |
779 | * The function calculates parameters for all cases and chooses the one closest | |
780 | * to the asked baud rate. | |
e5262d05 | 781 | */ |
9df461ec AS |
782 | static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) |
783 | { | |
784 | unsigned long xtal = 200000000; | |
785 | unsigned long fref = xtal / 2; /* mandatory division by 2, | |
786 | see (2) */ | |
787 | /* case 3 */ | |
788 | unsigned long fref1 = fref / 2; /* case 1 */ | |
789 | unsigned long fref2 = fref * 2 / 5; /* case 2 */ | |
790 | unsigned long scale; | |
791 | unsigned long q, q1, q2; | |
792 | long r, r1, r2; | |
793 | u32 mul; | |
794 | ||
795 | /* Case 1 */ | |
796 | ||
797 | /* Set initial value for DDS_CLK_RATE */ | |
798 | mul = (1 << 24) >> 1; | |
799 | ||
800 | /* Calculate initial quot */ | |
3ad48062 | 801 | q1 = DIV_ROUND_UP(fref1, rate); |
9df461ec AS |
802 | |
803 | /* Scale q1 if it's too big */ | |
804 | if (q1 > 256) { | |
805 | /* Scale q1 to range [1, 512] */ | |
806 | scale = fls_long(q1 - 1); | |
807 | if (scale > 9) { | |
808 | q1 >>= scale - 9; | |
809 | mul >>= scale - 9; | |
e5262d05 | 810 | } |
9df461ec AS |
811 | |
812 | /* Round the result if we have a remainder */ | |
813 | q1 += q1 & 1; | |
814 | } | |
815 | ||
816 | /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ | |
817 | scale = __ffs(q1); | |
818 | q1 >>= scale; | |
819 | mul >>= scale; | |
820 | ||
821 | /* Get the remainder */ | |
822 | r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); | |
823 | ||
824 | /* Case 2 */ | |
825 | ||
3ad48062 | 826 | q2 = DIV_ROUND_UP(fref2, rate); |
9df461ec AS |
827 | r2 = abs(fref2 / q2 - rate); |
828 | ||
829 | /* | |
830 | * Choose the best between two: less remainder we have the better. We | |
831 | * can't go case 2 if q2 is greater than 256 since SCR register can | |
832 | * hold only values 0 .. 255. | |
833 | */ | |
834 | if (r2 >= r1 || q2 > 256) { | |
835 | /* case 1 is better */ | |
836 | r = r1; | |
837 | q = q1; | |
838 | } else { | |
839 | /* case 2 is better */ | |
840 | r = r2; | |
841 | q = q2; | |
842 | mul = (1 << 24) * 2 / 5; | |
e5262d05 WC |
843 | } |
844 | ||
3ad48062 | 845 | /* Check case 3 only if the divisor is big enough */ |
9df461ec AS |
846 | if (fref / rate >= 80) { |
847 | u64 fssp; | |
848 | u32 m; | |
849 | ||
850 | /* Calculate initial quot */ | |
3ad48062 | 851 | q1 = DIV_ROUND_UP(fref, rate); |
9df461ec AS |
852 | m = (1 << 24) / q1; |
853 | ||
854 | /* Get the remainder */ | |
855 | fssp = (u64)fref * m; | |
856 | do_div(fssp, 1 << 24); | |
857 | r1 = abs(fssp - rate); | |
858 | ||
859 | /* Choose this one if it suits better */ | |
860 | if (r1 < r) { | |
861 | /* case 3 is better */ | |
862 | q = 1; | |
863 | mul = m; | |
864 | } | |
865 | } | |
e5262d05 | 866 | |
9df461ec AS |
867 | *dds = mul; |
868 | return q - 1; | |
e5262d05 WC |
869 | } |
870 | ||
3343b7a6 | 871 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 872 | { |
0eca7cf2 | 873 | unsigned long ssp_clk = drv_data->master->max_speed_hz; |
3343b7a6 MW |
874 | const struct ssp_device *ssp = drv_data->ssp; |
875 | ||
876 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 877 | |
2a8626a9 | 878 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
025ffe88 | 879 | return (ssp_clk / (2 * rate) - 1) & 0xff; |
2f1a74e5 | 880 | else |
025ffe88 | 881 | return (ssp_clk / rate - 1) & 0xfff; |
2f1a74e5 | 882 | } |
883 | ||
e5262d05 | 884 | static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, |
d2c2f6a4 | 885 | int rate) |
e5262d05 | 886 | { |
d2c2f6a4 | 887 | struct chip_data *chip = drv_data->cur_chip; |
025ffe88 | 888 | unsigned int clk_div; |
e5262d05 WC |
889 | |
890 | switch (drv_data->ssp_type) { | |
891 | case QUARK_X1000_SSP: | |
9df461ec | 892 | clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); |
eecacf73 | 893 | break; |
e5262d05 | 894 | default: |
025ffe88 | 895 | clk_div = ssp_get_clk_div(drv_data, rate); |
eecacf73 | 896 | break; |
e5262d05 | 897 | } |
025ffe88 | 898 | return clk_div << 8; |
e5262d05 WC |
899 | } |
900 | ||
e0c9905e SS |
901 | static void pump_transfers(unsigned long data) |
902 | { | |
903 | struct driver_data *drv_data = (struct driver_data *)data; | |
904 | struct spi_message *message = NULL; | |
905 | struct spi_transfer *transfer = NULL; | |
906 | struct spi_transfer *previous = NULL; | |
907 | struct chip_data *chip = NULL; | |
9708c121 SS |
908 | u32 clk_div = 0; |
909 | u8 bits = 0; | |
910 | u32 speed = 0; | |
911 | u32 cr0; | |
8d94cc50 SS |
912 | u32 cr1; |
913 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
914 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
4fdb2424 | 915 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); |
e0c9905e SS |
916 | |
917 | /* Get current state information */ | |
918 | message = drv_data->cur_msg; | |
919 | transfer = drv_data->cur_transfer; | |
920 | chip = drv_data->cur_chip; | |
921 | ||
922 | /* Handle for abort */ | |
923 | if (message->state == ERROR_STATE) { | |
924 | message->status = -EIO; | |
5daa3ba0 | 925 | giveback(drv_data); |
e0c9905e SS |
926 | return; |
927 | } | |
928 | ||
929 | /* Handle end of message */ | |
930 | if (message->state == DONE_STATE) { | |
931 | message->status = 0; | |
5daa3ba0 | 932 | giveback(drv_data); |
e0c9905e SS |
933 | return; |
934 | } | |
935 | ||
8423597d | 936 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
937 | if (message->state == RUNNING_STATE) { |
938 | previous = list_entry(transfer->transfer_list.prev, | |
939 | struct spi_transfer, | |
940 | transfer_list); | |
941 | if (previous->delay_usecs) | |
942 | udelay(previous->delay_usecs); | |
8423597d NF |
943 | |
944 | /* Drop chip select only if cs_change is requested */ | |
945 | if (previous->cs_change) | |
a7bb3909 | 946 | cs_deassert(drv_data); |
e0c9905e SS |
947 | } |
948 | ||
cd7bed00 MW |
949 | /* Check if we can DMA this transfer */ |
950 | if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) { | |
7e964455 NF |
951 | |
952 | /* reject already-mapped transfers; PIO won't always work */ | |
953 | if (message->is_dma_mapped | |
954 | || transfer->rx_dma || transfer->tx_dma) { | |
955 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
956 | "pump_transfers: mapped transfer length of " |
957 | "%u is greater than %d\n", | |
7e964455 NF |
958 | transfer->len, MAX_DMA_LEN); |
959 | message->status = -EINVAL; | |
960 | giveback(drv_data); | |
961 | return; | |
962 | } | |
963 | ||
964 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
965 | dev_warn_ratelimited(&message->spi->dev, |
966 | "pump_transfers: DMA disabled for transfer length %ld " | |
967 | "greater than %d\n", | |
968 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
969 | } |
970 | ||
e0c9905e | 971 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 972 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
973 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
974 | message->status = -EIO; | |
5daa3ba0 | 975 | giveback(drv_data); |
e0c9905e SS |
976 | return; |
977 | } | |
9708c121 | 978 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
979 | drv_data->tx = (void *)transfer->tx_buf; |
980 | drv_data->tx_end = drv_data->tx + transfer->len; | |
981 | drv_data->rx = transfer->rx_buf; | |
982 | drv_data->rx_end = drv_data->rx + transfer->len; | |
983 | drv_data->rx_dma = transfer->rx_dma; | |
984 | drv_data->tx_dma = transfer->tx_dma; | |
cd7bed00 | 985 | drv_data->len = transfer->len; |
e0c9905e SS |
986 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
987 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
988 | |
989 | /* Change speed and bit per word on a per transfer */ | |
196b0e2c JN |
990 | bits = transfer->bits_per_word; |
991 | speed = transfer->speed_hz; | |
992 | ||
d2c2f6a4 | 993 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); |
196b0e2c JN |
994 | |
995 | if (bits <= 8) { | |
996 | drv_data->n_bytes = 1; | |
997 | drv_data->read = drv_data->read != null_reader ? | |
998 | u8_reader : null_reader; | |
999 | drv_data->write = drv_data->write != null_writer ? | |
1000 | u8_writer : null_writer; | |
1001 | } else if (bits <= 16) { | |
1002 | drv_data->n_bytes = 2; | |
1003 | drv_data->read = drv_data->read != null_reader ? | |
1004 | u16_reader : null_reader; | |
1005 | drv_data->write = drv_data->write != null_writer ? | |
1006 | u16_writer : null_writer; | |
1007 | } else if (bits <= 32) { | |
1008 | drv_data->n_bytes = 4; | |
1009 | drv_data->read = drv_data->read != null_reader ? | |
1010 | u32_reader : null_reader; | |
1011 | drv_data->write = drv_data->write != null_writer ? | |
1012 | u32_writer : null_writer; | |
9708c121 | 1013 | } |
196b0e2c JN |
1014 | /* |
1015 | * if bits/word is changed in dma mode, then must check the | |
1016 | * thresholds and burst also | |
1017 | */ | |
1018 | if (chip->enable_dma) { | |
1019 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, | |
1020 | message->spi, | |
1021 | bits, &dma_burst, | |
1022 | &dma_thresh)) | |
1023 | dev_warn_ratelimited(&message->spi->dev, | |
1024 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
9708c121 SS |
1025 | } |
1026 | ||
e0c9905e SS |
1027 | message->state = RUNNING_STATE; |
1028 | ||
7e964455 | 1029 | drv_data->dma_mapped = 0; |
cd7bed00 MW |
1030 | if (pxa2xx_spi_dma_is_possible(drv_data->len)) |
1031 | drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data); | |
7e964455 | 1032 | if (drv_data->dma_mapped) { |
e0c9905e SS |
1033 | |
1034 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
1035 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
1036 | ||
1037 | pxa2xx_spi_dma_prepare(drv_data, dma_burst); | |
e0c9905e | 1038 | |
8d94cc50 SS |
1039 | /* Clear status and start DMA engine */ |
1040 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
c039dd27 | 1041 | pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); |
cd7bed00 MW |
1042 | |
1043 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
1044 | } else { |
1045 | /* Ensure we have the correct interrupt handler */ | |
1046 | drv_data->transfer_handler = interrupt_transfer; | |
1047 | ||
8d94cc50 SS |
1048 | /* Clear status */ |
1049 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 1050 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
1051 | } |
1052 | ||
ee03672d JN |
1053 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
1054 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); | |
1055 | if (!pxa25x_ssp_comp(drv_data)) | |
1056 | dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", | |
1057 | drv_data->master->max_speed_hz | |
1058 | / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), | |
1059 | drv_data->dma_mapped ? "DMA" : "PIO"); | |
1060 | else | |
1061 | dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", | |
1062 | drv_data->master->max_speed_hz / 2 | |
1063 | / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), | |
1064 | drv_data->dma_mapped ? "DMA" : "PIO"); | |
1065 | ||
a0d2642e | 1066 | if (is_lpss_ssp(drv_data)) { |
c039dd27 JN |
1067 | if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) |
1068 | != chip->lpss_rx_threshold) | |
1069 | pxa2xx_spi_write(drv_data, SSIRF, | |
1070 | chip->lpss_rx_threshold); | |
1071 | if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) | |
1072 | != chip->lpss_tx_threshold) | |
1073 | pxa2xx_spi_write(drv_data, SSITF, | |
1074 | chip->lpss_tx_threshold); | |
a0d2642e MW |
1075 | } |
1076 | ||
e5262d05 | 1077 | if (is_quark_x1000_ssp(drv_data) && |
c039dd27 JN |
1078 | (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) |
1079 | pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); | |
e5262d05 | 1080 | |
8d94cc50 | 1081 | /* see if we need to reload the config registers */ |
c039dd27 JN |
1082 | if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) |
1083 | || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) | |
1084 | != (cr1 & change_mask)) { | |
b97c74bd | 1085 | /* stop the SSP, and update the other bits */ |
c039dd27 | 1086 | pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); |
2a8626a9 | 1087 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1088 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
b97c74bd | 1089 | /* first set CR1 without interrupt and service enables */ |
c039dd27 | 1090 | pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); |
b97c74bd | 1091 | /* restart the SSP */ |
c039dd27 | 1092 | pxa2xx_spi_write(drv_data, SSCR0, cr0); |
b97c74bd | 1093 | |
8d94cc50 | 1094 | } else { |
2a8626a9 | 1095 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1096 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
e0c9905e | 1097 | } |
b97c74bd | 1098 | |
a7bb3909 | 1099 | cs_assert(drv_data); |
b97c74bd NF |
1100 | |
1101 | /* after chip select, release the data by enabling service | |
1102 | * requests and interrupts, without changing any mode bits */ | |
c039dd27 | 1103 | pxa2xx_spi_write(drv_data, SSCR1, cr1); |
e0c9905e SS |
1104 | } |
1105 | ||
7f86bde9 MW |
1106 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
1107 | struct spi_message *msg) | |
e0c9905e | 1108 | { |
7f86bde9 | 1109 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e | 1110 | |
7f86bde9 | 1111 | drv_data->cur_msg = msg; |
e0c9905e SS |
1112 | /* Initial message state*/ |
1113 | drv_data->cur_msg->state = START_STATE; | |
1114 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1115 | struct spi_transfer, | |
1116 | transfer_list); | |
1117 | ||
8d94cc50 SS |
1118 | /* prepare to setup the SSP, in pump_transfers, using the per |
1119 | * chip configuration */ | |
e0c9905e | 1120 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1121 | |
1122 | /* Mark as busy and launch transfers */ | |
1123 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
1124 | return 0; |
1125 | } | |
1126 | ||
7d94a505 MW |
1127 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
1128 | { | |
1129 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1130 | ||
1131 | /* Disable the SSP now */ | |
c039dd27 JN |
1132 | pxa2xx_spi_write(drv_data, SSCR0, |
1133 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
7d94a505 | 1134 | |
7d94a505 MW |
1135 | return 0; |
1136 | } | |
1137 | ||
a7bb3909 EM |
1138 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1139 | struct pxa2xx_spi_chip *chip_info) | |
1140 | { | |
1141 | int err = 0; | |
1142 | ||
1143 | if (chip == NULL || chip_info == NULL) | |
1144 | return 0; | |
1145 | ||
1146 | /* NOTE: setup() can be called multiple times, possibly with | |
1147 | * different chip_info, release previously requested GPIO | |
1148 | */ | |
1149 | if (gpio_is_valid(chip->gpio_cs)) | |
1150 | gpio_free(chip->gpio_cs); | |
1151 | ||
1152 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1153 | if (chip_info->cs_control) { | |
1154 | chip->cs_control = chip_info->cs_control; | |
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1159 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1160 | if (err) { | |
f6bd03a7 JN |
1161 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
1162 | chip_info->gpio_cs); | |
a7bb3909 EM |
1163 | return err; |
1164 | } | |
1165 | ||
1166 | chip->gpio_cs = chip_info->gpio_cs; | |
1167 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1168 | ||
1169 | err = gpio_direction_output(chip->gpio_cs, | |
1170 | !chip->gpio_cs_inverted); | |
1171 | } | |
1172 | ||
1173 | return err; | |
1174 | } | |
1175 | ||
e0c9905e SS |
1176 | static int setup(struct spi_device *spi) |
1177 | { | |
1178 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1179 | struct chip_data *chip; | |
dccf7369 | 1180 | const struct lpss_config *config; |
e0c9905e | 1181 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
a0d2642e MW |
1182 | uint tx_thres, tx_hi_thres, rx_thres; |
1183 | ||
e5262d05 WC |
1184 | switch (drv_data->ssp_type) { |
1185 | case QUARK_X1000_SSP: | |
1186 | tx_thres = TX_THRESH_QUARK_X1000_DFLT; | |
1187 | tx_hi_thres = 0; | |
1188 | rx_thres = RX_THRESH_QUARK_X1000_DFLT; | |
1189 | break; | |
03fbf488 JN |
1190 | case LPSS_LPT_SSP: |
1191 | case LPSS_BYT_SSP: | |
34cadd9c | 1192 | case LPSS_SPT_SSP: |
b7c08cf8 | 1193 | case LPSS_BXT_SSP: |
dccf7369 JN |
1194 | config = lpss_get_config(drv_data); |
1195 | tx_thres = config->tx_threshold_lo; | |
1196 | tx_hi_thres = config->tx_threshold_hi; | |
1197 | rx_thres = config->rx_threshold; | |
e5262d05 WC |
1198 | break; |
1199 | default: | |
a0d2642e MW |
1200 | tx_thres = TX_THRESH_DFLT; |
1201 | tx_hi_thres = 0; | |
1202 | rx_thres = RX_THRESH_DFLT; | |
e5262d05 | 1203 | break; |
a0d2642e | 1204 | } |
e0c9905e | 1205 | |
8d94cc50 | 1206 | /* Only alloc on first setup */ |
e0c9905e | 1207 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1208 | if (!chip) { |
e0c9905e | 1209 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 1210 | if (!chip) |
e0c9905e SS |
1211 | return -ENOMEM; |
1212 | ||
2a8626a9 SAS |
1213 | if (drv_data->ssp_type == CE4100_SSP) { |
1214 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
1215 | dev_err(&spi->dev, |
1216 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
1217 | kfree(chip); |
1218 | return -EINVAL; | |
1219 | } | |
1220 | ||
1221 | chip->frm = spi->chip_select; | |
1222 | } else | |
1223 | chip->gpio_cs = -1; | |
e0c9905e | 1224 | chip->enable_dma = 0; |
f1f640a9 | 1225 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1226 | } |
1227 | ||
8d94cc50 SS |
1228 | /* protocol drivers may change the chip settings, so... |
1229 | * if chip_info exists, use it */ | |
1230 | chip_info = spi->controller_data; | |
1231 | ||
e0c9905e | 1232 | /* chip_info isn't always needed */ |
8d94cc50 | 1233 | chip->cr1 = 0; |
e0c9905e | 1234 | if (chip_info) { |
f1f640a9 VS |
1235 | if (chip_info->timeout) |
1236 | chip->timeout = chip_info->timeout; | |
1237 | if (chip_info->tx_threshold) | |
1238 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
1239 | if (chip_info->tx_hi_threshold) |
1240 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
1241 | if (chip_info->rx_threshold) |
1242 | rx_thres = chip_info->rx_threshold; | |
1243 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 1244 | chip->dma_threshold = 0; |
e0c9905e SS |
1245 | if (chip_info->enable_loopback) |
1246 | chip->cr1 = SSCR1_LBM; | |
a3496855 MW |
1247 | } else if (ACPI_HANDLE(&spi->dev)) { |
1248 | /* | |
1249 | * Slave devices enumerated from ACPI namespace don't | |
1250 | * usually have chip_info but we still might want to use | |
1251 | * DMA with them. | |
1252 | */ | |
1253 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e SS |
1254 | } |
1255 | ||
a0d2642e MW |
1256 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
1257 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
1258 | | SSITF_TxHiThresh(tx_hi_thres); | |
1259 | ||
8d94cc50 SS |
1260 | /* set dma burst and threshold outside of chip_info path so that if |
1261 | * chip_info goes away after setting chip->enable_dma, the | |
1262 | * burst and threshold can still respond to changes in bits_per_word */ | |
1263 | if (chip->enable_dma) { | |
1264 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
1265 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1266 | spi->bits_per_word, | |
8d94cc50 SS |
1267 | &chip->dma_burst_size, |
1268 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1269 | dev_warn(&spi->dev, |
1270 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
1271 | } |
1272 | } | |
1273 | ||
e5262d05 WC |
1274 | switch (drv_data->ssp_type) { |
1275 | case QUARK_X1000_SSP: | |
1276 | chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) | |
1277 | & QUARK_X1000_SSCR1_RFT) | |
1278 | | (QUARK_X1000_SSCR1_TxTresh(tx_thres) | |
1279 | & QUARK_X1000_SSCR1_TFT); | |
1280 | break; | |
1281 | default: | |
1282 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | |
1283 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1284 | break; | |
1285 | } | |
1286 | ||
7f6ee1ad JC |
1287 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1288 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1289 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 1290 | |
b833172f MW |
1291 | if (spi->mode & SPI_LOOP) |
1292 | chip->cr1 |= SSCR1_LBM; | |
1293 | ||
e0c9905e SS |
1294 | if (spi->bits_per_word <= 8) { |
1295 | chip->n_bytes = 1; | |
e0c9905e SS |
1296 | chip->read = u8_reader; |
1297 | chip->write = u8_writer; | |
1298 | } else if (spi->bits_per_word <= 16) { | |
1299 | chip->n_bytes = 2; | |
e0c9905e SS |
1300 | chip->read = u16_reader; |
1301 | chip->write = u16_writer; | |
1302 | } else if (spi->bits_per_word <= 32) { | |
e0c9905e | 1303 | chip->n_bytes = 4; |
e0c9905e SS |
1304 | chip->read = u32_reader; |
1305 | chip->write = u32_writer; | |
e0c9905e SS |
1306 | } |
1307 | ||
1308 | spi_set_ctldata(spi, chip); | |
1309 | ||
2a8626a9 SAS |
1310 | if (drv_data->ssp_type == CE4100_SSP) |
1311 | return 0; | |
1312 | ||
a7bb3909 | 1313 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1314 | } |
1315 | ||
0ffa0285 | 1316 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1317 | { |
0ffa0285 | 1318 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1319 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1320 | |
7348d82a DR |
1321 | if (!chip) |
1322 | return; | |
1323 | ||
2a8626a9 | 1324 | if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs)) |
a7bb3909 EM |
1325 | gpio_free(chip->gpio_cs); |
1326 | ||
e0c9905e SS |
1327 | kfree(chip); |
1328 | } | |
1329 | ||
0db64215 | 1330 | #ifdef CONFIG_PCI |
a3496855 | 1331 | #ifdef CONFIG_ACPI |
03fbf488 | 1332 | |
8422ddf7 | 1333 | static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { |
03fbf488 JN |
1334 | { "INT33C0", LPSS_LPT_SSP }, |
1335 | { "INT33C1", LPSS_LPT_SSP }, | |
1336 | { "INT3430", LPSS_LPT_SSP }, | |
1337 | { "INT3431", LPSS_LPT_SSP }, | |
1338 | { "80860F0E", LPSS_BYT_SSP }, | |
1339 | { "8086228E", LPSS_BYT_SSP }, | |
1340 | { }, | |
1341 | }; | |
1342 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1343 | ||
0db64215 JN |
1344 | static int pxa2xx_spi_get_port_id(struct acpi_device *adev) |
1345 | { | |
1346 | unsigned int devid; | |
1347 | int port_id = -1; | |
1348 | ||
1349 | if (adev && adev->pnp.unique_id && | |
1350 | !kstrtouint(adev->pnp.unique_id, 0, &devid)) | |
1351 | port_id = devid; | |
1352 | return port_id; | |
1353 | } | |
1354 | #else /* !CONFIG_ACPI */ | |
1355 | static int pxa2xx_spi_get_port_id(struct acpi_device *adev) | |
1356 | { | |
1357 | return -1; | |
1358 | } | |
1359 | #endif | |
1360 | ||
34cadd9c JN |
1361 | /* |
1362 | * PCI IDs of compound devices that integrate both host controller and private | |
1363 | * integrated DMA engine. Please note these are not used in module | |
1364 | * autoloading and probing in this module but matching the LPSS SSP type. | |
1365 | */ | |
1366 | static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { | |
1367 | /* SPT-LP */ | |
1368 | { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, | |
1369 | { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, | |
1370 | /* SPT-H */ | |
1371 | { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, | |
1372 | { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, | |
b7c08cf8 JN |
1373 | /* BXT */ |
1374 | { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, | |
1375 | { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, | |
1376 | { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, | |
1377 | /* APL */ | |
1378 | { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, | |
1379 | { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, | |
1380 | { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, | |
94e5c23d | 1381 | { }, |
34cadd9c JN |
1382 | }; |
1383 | ||
1384 | static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) | |
1385 | { | |
1386 | struct device *dev = param; | |
1387 | ||
1388 | if (dev != chan->device->dev->parent) | |
1389 | return false; | |
1390 | ||
1391 | return true; | |
1392 | } | |
1393 | ||
a3496855 | 1394 | static struct pxa2xx_spi_master * |
0db64215 | 1395 | pxa2xx_spi_init_pdata(struct platform_device *pdev) |
a3496855 MW |
1396 | { |
1397 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1398 | struct acpi_device *adev; |
1399 | struct ssp_device *ssp; | |
1400 | struct resource *res; | |
34cadd9c JN |
1401 | const struct acpi_device_id *adev_id = NULL; |
1402 | const struct pci_device_id *pcidev_id = NULL; | |
3b8b6d05 | 1403 | int type; |
a3496855 | 1404 | |
b9f6940a | 1405 | adev = ACPI_COMPANION(&pdev->dev); |
a3496855 | 1406 | |
34cadd9c JN |
1407 | if (dev_is_pci(pdev->dev.parent)) |
1408 | pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, | |
1409 | to_pci_dev(pdev->dev.parent)); | |
0db64215 | 1410 | else if (adev) |
34cadd9c JN |
1411 | adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, |
1412 | &pdev->dev); | |
0db64215 JN |
1413 | else |
1414 | return NULL; | |
34cadd9c JN |
1415 | |
1416 | if (adev_id) | |
1417 | type = (int)adev_id->driver_data; | |
1418 | else if (pcidev_id) | |
1419 | type = (int)pcidev_id->driver_data; | |
03fbf488 JN |
1420 | else |
1421 | return NULL; | |
1422 | ||
cc0ee987 | 1423 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1424 | if (!pdata) |
a3496855 | 1425 | return NULL; |
a3496855 MW |
1426 | |
1427 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1428 | if (!res) | |
1429 | return NULL; | |
1430 | ||
1431 | ssp = &pdata->ssp; | |
1432 | ||
1433 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1434 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1435 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1436 | return NULL; |
a3496855 | 1437 | |
34cadd9c JN |
1438 | if (pcidev_id) { |
1439 | pdata->tx_param = pdev->dev.parent; | |
1440 | pdata->rx_param = pdev->dev.parent; | |
1441 | pdata->dma_filter = pxa2xx_spi_idma_filter; | |
1442 | } | |
1443 | ||
a3496855 MW |
1444 | ssp->clk = devm_clk_get(&pdev->dev, NULL); |
1445 | ssp->irq = platform_get_irq(pdev, 0); | |
03fbf488 | 1446 | ssp->type = type; |
a3496855 | 1447 | ssp->pdev = pdev; |
0db64215 | 1448 | ssp->port_id = pxa2xx_spi_get_port_id(adev); |
a3496855 MW |
1449 | |
1450 | pdata->num_chipselect = 1; | |
cddb339b | 1451 | pdata->enable_dma = true; |
a3496855 MW |
1452 | |
1453 | return pdata; | |
1454 | } | |
1455 | ||
0db64215 | 1456 | #else /* !CONFIG_PCI */ |
a3496855 | 1457 | static inline struct pxa2xx_spi_master * |
0db64215 | 1458 | pxa2xx_spi_init_pdata(struct platform_device *pdev) |
a3496855 MW |
1459 | { |
1460 | return NULL; | |
1461 | } | |
1462 | #endif | |
1463 | ||
0c27d9cf MW |
1464 | static int pxa2xx_spi_fw_translate_cs(struct spi_master *master, unsigned cs) |
1465 | { | |
1466 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1467 | ||
1468 | if (has_acpi_companion(&drv_data->pdev->dev)) { | |
1469 | switch (drv_data->ssp_type) { | |
1470 | /* | |
1471 | * For Atoms the ACPI DeviceSelection used by the Windows | |
1472 | * driver starts from 1 instead of 0 so translate it here | |
1473 | * to match what Linux expects. | |
1474 | */ | |
1475 | case LPSS_BYT_SSP: | |
1476 | return cs - 1; | |
1477 | ||
1478 | default: | |
1479 | break; | |
1480 | } | |
1481 | } | |
1482 | ||
1483 | return cs; | |
1484 | } | |
1485 | ||
fd4a319b | 1486 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1487 | { |
1488 | struct device *dev = &pdev->dev; | |
1489 | struct pxa2xx_spi_master *platform_info; | |
1490 | struct spi_master *master; | |
65a00a20 | 1491 | struct driver_data *drv_data; |
2f1a74e5 | 1492 | struct ssp_device *ssp; |
8b136baa | 1493 | const struct lpss_config *config; |
65a00a20 | 1494 | int status; |
c039dd27 | 1495 | u32 tmp; |
e0c9905e | 1496 | |
851bacf5 MW |
1497 | platform_info = dev_get_platdata(dev); |
1498 | if (!platform_info) { | |
0db64215 | 1499 | platform_info = pxa2xx_spi_init_pdata(pdev); |
a3496855 MW |
1500 | if (!platform_info) { |
1501 | dev_err(&pdev->dev, "missing platform data\n"); | |
1502 | return -ENODEV; | |
1503 | } | |
851bacf5 | 1504 | } |
e0c9905e | 1505 | |
baffe169 | 1506 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1507 | if (!ssp) |
1508 | ssp = &platform_info->ssp; | |
1509 | ||
1510 | if (!ssp->mmio_base) { | |
1511 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1512 | return -ENODEV; |
1513 | } | |
1514 | ||
757fe8d5 | 1515 | master = spi_alloc_master(dev, sizeof(struct driver_data)); |
e0c9905e | 1516 | if (!master) { |
65a00a20 | 1517 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1518 | pxa_ssp_free(ssp); |
e0c9905e SS |
1519 | return -ENOMEM; |
1520 | } | |
1521 | drv_data = spi_master_get_devdata(master); | |
1522 | drv_data->master = master; | |
1523 | drv_data->master_info = platform_info; | |
1524 | drv_data->pdev = pdev; | |
2f1a74e5 | 1525 | drv_data->ssp = ssp; |
e0c9905e | 1526 | |
21486af0 | 1527 | master->dev.parent = &pdev->dev; |
21486af0 | 1528 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1529 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1530 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1531 | |
851bacf5 | 1532 | master->bus_num = ssp->port_id; |
7ad0ba91 | 1533 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1534 | master->cleanup = cleanup; |
1535 | master->setup = setup; | |
7f86bde9 | 1536 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1537 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
0c27d9cf | 1538 | master->fw_translate_cs = pxa2xx_spi_fw_translate_cs; |
7dd62787 | 1539 | master->auto_runtime_pm = true; |
e0c9905e | 1540 | |
2f1a74e5 | 1541 | drv_data->ssp_type = ssp->type; |
e0c9905e | 1542 | |
2f1a74e5 | 1543 | drv_data->ioaddr = ssp->mmio_base; |
1544 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1545 | if (pxa25x_ssp_comp(drv_data)) { |
e5262d05 WC |
1546 | switch (drv_data->ssp_type) { |
1547 | case QUARK_X1000_SSP: | |
1548 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
1549 | break; | |
1550 | default: | |
1551 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
1552 | break; | |
1553 | } | |
1554 | ||
e0c9905e SS |
1555 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1556 | drv_data->dma_cr1 = 0; | |
1557 | drv_data->clear_sr = SSSR_ROR; | |
1558 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1559 | } else { | |
24778be2 | 1560 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1561 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1562 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1563 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1564 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1565 | } | |
1566 | ||
49cbb1e0 SAS |
1567 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1568 | drv_data); | |
e0c9905e | 1569 | if (status < 0) { |
65a00a20 | 1570 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1571 | goto out_error_master_alloc; |
1572 | } | |
1573 | ||
1574 | /* Setup DMA if requested */ | |
e0c9905e | 1575 | if (platform_info->enable_dma) { |
cd7bed00 MW |
1576 | status = pxa2xx_spi_dma_setup(drv_data); |
1577 | if (status) { | |
cddb339b | 1578 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1579 | platform_info->enable_dma = false; |
e0c9905e | 1580 | } |
e0c9905e SS |
1581 | } |
1582 | ||
1583 | /* Enable SOC clock */ | |
3343b7a6 MW |
1584 | clk_prepare_enable(ssp->clk); |
1585 | ||
0eca7cf2 | 1586 | master->max_speed_hz = clk_get_rate(ssp->clk); |
e0c9905e SS |
1587 | |
1588 | /* Load default SSP configuration */ | |
c039dd27 | 1589 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
e5262d05 WC |
1590 | switch (drv_data->ssp_type) { |
1591 | case QUARK_X1000_SSP: | |
c039dd27 JN |
1592 | tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1593 | | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); | |
1594 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
e5262d05 WC |
1595 | |
1596 | /* using the Motorola SPI protocol and use 8 bit frame */ | |
c039dd27 JN |
1597 | pxa2xx_spi_write(drv_data, SSCR0, |
1598 | QUARK_X1000_SSCR0_Motorola | |
1599 | | QUARK_X1000_SSCR0_DataSize(8)); | |
e5262d05 WC |
1600 | break; |
1601 | default: | |
c039dd27 JN |
1602 | tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | |
1603 | SSCR1_TxTresh(TX_THRESH_DFLT); | |
1604 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
1605 | tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); | |
1606 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
e5262d05 WC |
1607 | break; |
1608 | } | |
1609 | ||
2a8626a9 | 1610 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1611 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e5262d05 WC |
1612 | |
1613 | if (!is_quark_x1000_ssp(drv_data)) | |
c039dd27 | 1614 | pxa2xx_spi_write(drv_data, SSPSP, 0); |
e0c9905e | 1615 | |
8b136baa JN |
1616 | if (is_lpss_ssp(drv_data)) { |
1617 | lpss_ssp_setup(drv_data); | |
1618 | config = lpss_get_config(drv_data); | |
1619 | if (config->reg_capabilities >= 0) { | |
1620 | tmp = __lpss_ssp_read_priv(drv_data, | |
1621 | config->reg_capabilities); | |
1622 | tmp &= LPSS_CAPS_CS_EN_MASK; | |
1623 | tmp >>= LPSS_CAPS_CS_EN_SHIFT; | |
1624 | platform_info->num_chipselect = ffz(tmp); | |
1625 | } | |
1626 | } | |
1627 | master->num_chipselect = platform_info->num_chipselect; | |
1628 | ||
7f86bde9 MW |
1629 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1630 | (unsigned long)drv_data); | |
e0c9905e | 1631 | |
836d1a22 AO |
1632 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1633 | pm_runtime_use_autosuspend(&pdev->dev); | |
1634 | pm_runtime_set_active(&pdev->dev); | |
1635 | pm_runtime_enable(&pdev->dev); | |
1636 | ||
e0c9905e SS |
1637 | /* Register with the SPI framework */ |
1638 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1639 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1640 | if (status != 0) { |
1641 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1642 | goto out_error_clock_enabled; |
e0c9905e SS |
1643 | } |
1644 | ||
1645 | return status; | |
1646 | ||
e0c9905e | 1647 | out_error_clock_enabled: |
3343b7a6 | 1648 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1649 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1650 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1651 | |
1652 | out_error_master_alloc: | |
1653 | spi_master_put(master); | |
baffe169 | 1654 | pxa_ssp_free(ssp); |
e0c9905e SS |
1655 | return status; |
1656 | } | |
1657 | ||
1658 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1659 | { | |
1660 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1661 | struct ssp_device *ssp; |
e0c9905e SS |
1662 | |
1663 | if (!drv_data) | |
1664 | return 0; | |
51e911e2 | 1665 | ssp = drv_data->ssp; |
e0c9905e | 1666 | |
7d94a505 MW |
1667 | pm_runtime_get_sync(&pdev->dev); |
1668 | ||
e0c9905e | 1669 | /* Disable the SSP at the peripheral and SOC level */ |
c039dd27 | 1670 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
3343b7a6 | 1671 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1672 | |
1673 | /* Release DMA */ | |
cd7bed00 MW |
1674 | if (drv_data->master_info->enable_dma) |
1675 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1676 | |
7d94a505 MW |
1677 | pm_runtime_put_noidle(&pdev->dev); |
1678 | pm_runtime_disable(&pdev->dev); | |
1679 | ||
e0c9905e | 1680 | /* Release IRQ */ |
2f1a74e5 | 1681 | free_irq(ssp->irq, drv_data); |
1682 | ||
1683 | /* Release SSP */ | |
baffe169 | 1684 | pxa_ssp_free(ssp); |
e0c9905e | 1685 | |
e0c9905e SS |
1686 | return 0; |
1687 | } | |
1688 | ||
1689 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1690 | { | |
1691 | int status = 0; | |
1692 | ||
1693 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1694 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1695 | } | |
1696 | ||
382cebb0 | 1697 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1698 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1699 | { |
86d2593a | 1700 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1701 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1702 | int status = 0; |
1703 | ||
7f86bde9 | 1704 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1705 | if (status != 0) |
1706 | return status; | |
c039dd27 | 1707 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
2b9375b9 DES |
1708 | |
1709 | if (!pm_runtime_suspended(dev)) | |
1710 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1711 | |
1712 | return 0; | |
1713 | } | |
1714 | ||
86d2593a | 1715 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1716 | { |
86d2593a | 1717 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1718 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1719 | int status = 0; |
1720 | ||
1721 | /* Enable the SSP clock */ | |
2b9375b9 DES |
1722 | if (!pm_runtime_suspended(dev)) |
1723 | clk_prepare_enable(ssp->clk); | |
e0c9905e | 1724 | |
c50325f7 | 1725 | /* Restore LPSS private register bits */ |
48421adf JN |
1726 | if (is_lpss_ssp(drv_data)) |
1727 | lpss_ssp_setup(drv_data); | |
c50325f7 | 1728 | |
e0c9905e | 1729 | /* Start the queue running */ |
7f86bde9 | 1730 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1731 | if (status != 0) { |
86d2593a | 1732 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1733 | return status; |
1734 | } | |
1735 | ||
1736 | return 0; | |
1737 | } | |
7d94a505 MW |
1738 | #endif |
1739 | ||
ec833050 | 1740 | #ifdef CONFIG_PM |
7d94a505 MW |
1741 | static int pxa2xx_spi_runtime_suspend(struct device *dev) |
1742 | { | |
1743 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1744 | ||
1745 | clk_disable_unprepare(drv_data->ssp->clk); | |
1746 | return 0; | |
1747 | } | |
1748 | ||
1749 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1750 | { | |
1751 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1752 | ||
1753 | clk_prepare_enable(drv_data->ssp->clk); | |
1754 | return 0; | |
1755 | } | |
1756 | #endif | |
86d2593a | 1757 | |
47145210 | 1758 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1759 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1760 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1761 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1762 | }; |
e0c9905e SS |
1763 | |
1764 | static struct platform_driver driver = { | |
1765 | .driver = { | |
86d2593a | 1766 | .name = "pxa2xx-spi", |
86d2593a | 1767 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1768 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1769 | }, |
fbd29a14 | 1770 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1771 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1772 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1773 | }; |
1774 | ||
1775 | static int __init pxa2xx_spi_init(void) | |
1776 | { | |
fbd29a14 | 1777 | return platform_driver_register(&driver); |
e0c9905e | 1778 | } |
5b61a749 | 1779 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1780 | |
1781 | static void __exit pxa2xx_spi_exit(void) | |
1782 | { | |
1783 | platform_driver_unregister(&driver); | |
1784 | } | |
1785 | module_exit(pxa2xx_spi_exit); |