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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
a0d2642e | 3 | * Copyright (C) 2013, Intel Corporation |
e0c9905e SS |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
e0c9905e SS |
14 | */ |
15 | ||
8b136baa | 16 | #include <linux/bitops.h> |
e0c9905e SS |
17 | #include <linux/init.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/errno.h> | |
cbfd6a21 | 22 | #include <linux/err.h> |
e0c9905e | 23 | #include <linux/interrupt.h> |
9df461ec | 24 | #include <linux/kernel.h> |
34cadd9c | 25 | #include <linux/pci.h> |
e0c9905e | 26 | #include <linux/platform_device.h> |
8348c259 | 27 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 28 | #include <linux/spi/spi.h> |
e0c9905e | 29 | #include <linux/delay.h> |
a7bb3909 | 30 | #include <linux/gpio.h> |
089bd46d | 31 | #include <linux/gpio/consumer.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
3343b7a6 | 33 | #include <linux/clk.h> |
7d94a505 | 34 | #include <linux/pm_runtime.h> |
a3496855 | 35 | #include <linux/acpi.h> |
e0c9905e | 36 | |
cd7bed00 | 37 | #include "spi-pxa2xx.h" |
e0c9905e SS |
38 | |
39 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 40 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 41 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 42 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e | 43 | |
f1f640a9 VS |
44 | #define TIMOUT_DFLT 1000 |
45 | ||
b97c74bd NF |
46 | /* |
47 | * for testing SSCR1 changes that require SSP restart, basically | |
48 | * everything except the service and interrupt enables, the pxa270 developer | |
49 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
50 | * list, but the PXA255 dev man says all bits without really meaning the | |
51 | * service and interrupt enables | |
52 | */ | |
53 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 54 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
55 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
56 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
57 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
58 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 59 | |
e5262d05 WC |
60 | #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ |
61 | | QUARK_X1000_SSCR1_EFWR \ | |
62 | | QUARK_X1000_SSCR1_RFT \ | |
63 | | QUARK_X1000_SSCR1_TFT \ | |
64 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
65 | ||
7c7289a4 AS |
66 | #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ |
67 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ | |
68 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ | |
69 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
70 | | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \ | |
71 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
72 | ||
624ea72e JN |
73 | #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) |
74 | #define LPSS_CS_CONTROL_SW_MODE BIT(0) | |
75 | #define LPSS_CS_CONTROL_CS_HIGH BIT(1) | |
8b136baa JN |
76 | #define LPSS_CAPS_CS_EN_SHIFT 9 |
77 | #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) | |
a0d2642e | 78 | |
dccf7369 JN |
79 | struct lpss_config { |
80 | /* LPSS offset from drv_data->ioaddr */ | |
81 | unsigned offset; | |
82 | /* Register offsets from drv_data->lpss_base or -1 */ | |
83 | int reg_general; | |
84 | int reg_ssp; | |
85 | int reg_cs_ctrl; | |
8b136baa | 86 | int reg_capabilities; |
dccf7369 JN |
87 | /* FIFO thresholds */ |
88 | u32 rx_threshold; | |
89 | u32 tx_threshold_lo; | |
90 | u32 tx_threshold_hi; | |
c1e4a53c MW |
91 | /* Chip select control */ |
92 | unsigned cs_sel_shift; | |
93 | unsigned cs_sel_mask; | |
30f3a6ab | 94 | unsigned cs_num; |
dccf7369 JN |
95 | }; |
96 | ||
97 | /* Keep these sorted with enum pxa_ssp_type */ | |
98 | static const struct lpss_config lpss_platforms[] = { | |
99 | { /* LPSS_LPT_SSP */ | |
100 | .offset = 0x800, | |
101 | .reg_general = 0x08, | |
102 | .reg_ssp = 0x0c, | |
103 | .reg_cs_ctrl = 0x18, | |
8b136baa | 104 | .reg_capabilities = -1, |
dccf7369 JN |
105 | .rx_threshold = 64, |
106 | .tx_threshold_lo = 160, | |
107 | .tx_threshold_hi = 224, | |
108 | }, | |
109 | { /* LPSS_BYT_SSP */ | |
110 | .offset = 0x400, | |
111 | .reg_general = 0x08, | |
112 | .reg_ssp = 0x0c, | |
113 | .reg_cs_ctrl = 0x18, | |
8b136baa | 114 | .reg_capabilities = -1, |
dccf7369 JN |
115 | .rx_threshold = 64, |
116 | .tx_threshold_lo = 160, | |
117 | .tx_threshold_hi = 224, | |
118 | }, | |
30f3a6ab MW |
119 | { /* LPSS_BSW_SSP */ |
120 | .offset = 0x400, | |
121 | .reg_general = 0x08, | |
122 | .reg_ssp = 0x0c, | |
123 | .reg_cs_ctrl = 0x18, | |
124 | .reg_capabilities = -1, | |
125 | .rx_threshold = 64, | |
126 | .tx_threshold_lo = 160, | |
127 | .tx_threshold_hi = 224, | |
128 | .cs_sel_shift = 2, | |
129 | .cs_sel_mask = 1 << 2, | |
130 | .cs_num = 2, | |
131 | }, | |
34cadd9c JN |
132 | { /* LPSS_SPT_SSP */ |
133 | .offset = 0x200, | |
134 | .reg_general = -1, | |
135 | .reg_ssp = 0x20, | |
136 | .reg_cs_ctrl = 0x24, | |
66ec246e | 137 | .reg_capabilities = -1, |
34cadd9c JN |
138 | .rx_threshold = 1, |
139 | .tx_threshold_lo = 32, | |
140 | .tx_threshold_hi = 56, | |
141 | }, | |
b7c08cf8 JN |
142 | { /* LPSS_BXT_SSP */ |
143 | .offset = 0x200, | |
144 | .reg_general = -1, | |
145 | .reg_ssp = 0x20, | |
146 | .reg_cs_ctrl = 0x24, | |
147 | .reg_capabilities = 0xfc, | |
148 | .rx_threshold = 1, | |
149 | .tx_threshold_lo = 16, | |
150 | .tx_threshold_hi = 48, | |
c1e4a53c MW |
151 | .cs_sel_shift = 8, |
152 | .cs_sel_mask = 3 << 8, | |
b7c08cf8 | 153 | }, |
dccf7369 JN |
154 | }; |
155 | ||
156 | static inline const struct lpss_config | |
157 | *lpss_get_config(const struct driver_data *drv_data) | |
158 | { | |
159 | return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; | |
160 | } | |
161 | ||
a0d2642e MW |
162 | static bool is_lpss_ssp(const struct driver_data *drv_data) |
163 | { | |
03fbf488 JN |
164 | switch (drv_data->ssp_type) { |
165 | case LPSS_LPT_SSP: | |
166 | case LPSS_BYT_SSP: | |
30f3a6ab | 167 | case LPSS_BSW_SSP: |
34cadd9c | 168 | case LPSS_SPT_SSP: |
b7c08cf8 | 169 | case LPSS_BXT_SSP: |
03fbf488 JN |
170 | return true; |
171 | default: | |
172 | return false; | |
173 | } | |
a0d2642e MW |
174 | } |
175 | ||
e5262d05 WC |
176 | static bool is_quark_x1000_ssp(const struct driver_data *drv_data) |
177 | { | |
178 | return drv_data->ssp_type == QUARK_X1000_SSP; | |
179 | } | |
180 | ||
4fdb2424 WC |
181 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
182 | { | |
183 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
184 | case QUARK_X1000_SSP: |
185 | return QUARK_X1000_SSCR1_CHANGE_MASK; | |
7c7289a4 AS |
186 | case CE4100_SSP: |
187 | return CE4100_SSCR1_CHANGE_MASK; | |
4fdb2424 WC |
188 | default: |
189 | return SSCR1_CHANGE_MASK; | |
190 | } | |
191 | } | |
192 | ||
193 | static u32 | |
194 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
195 | { | |
196 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
197 | case QUARK_X1000_SSP: |
198 | return RX_THRESH_QUARK_X1000_DFLT; | |
7c7289a4 AS |
199 | case CE4100_SSP: |
200 | return RX_THRESH_CE4100_DFLT; | |
4fdb2424 WC |
201 | default: |
202 | return RX_THRESH_DFLT; | |
203 | } | |
204 | } | |
205 | ||
206 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
207 | { | |
4fdb2424 WC |
208 | u32 mask; |
209 | ||
210 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
211 | case QUARK_X1000_SSP: |
212 | mask = QUARK_X1000_SSSR_TFL_MASK; | |
213 | break; | |
7c7289a4 AS |
214 | case CE4100_SSP: |
215 | mask = CE4100_SSSR_TFL_MASK; | |
216 | break; | |
4fdb2424 WC |
217 | default: |
218 | mask = SSSR_TFL_MASK; | |
219 | break; | |
220 | } | |
221 | ||
c039dd27 | 222 | return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; |
4fdb2424 WC |
223 | } |
224 | ||
225 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
226 | u32 *sccr1_reg) | |
227 | { | |
228 | u32 mask; | |
229 | ||
230 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
231 | case QUARK_X1000_SSP: |
232 | mask = QUARK_X1000_SSCR1_RFT; | |
233 | break; | |
7c7289a4 AS |
234 | case CE4100_SSP: |
235 | mask = CE4100_SSCR1_RFT; | |
236 | break; | |
4fdb2424 WC |
237 | default: |
238 | mask = SSCR1_RFT; | |
239 | break; | |
240 | } | |
241 | *sccr1_reg &= ~mask; | |
242 | } | |
243 | ||
244 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
245 | u32 *sccr1_reg, u32 threshold) | |
246 | { | |
247 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
248 | case QUARK_X1000_SSP: |
249 | *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); | |
250 | break; | |
7c7289a4 AS |
251 | case CE4100_SSP: |
252 | *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); | |
253 | break; | |
4fdb2424 WC |
254 | default: |
255 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
256 | break; | |
257 | } | |
258 | } | |
259 | ||
260 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
261 | u32 clk_div, u8 bits) | |
262 | { | |
263 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
264 | case QUARK_X1000_SSP: |
265 | return clk_div | |
266 | | QUARK_X1000_SSCR0_Motorola | |
267 | | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) | |
268 | | SSCR0_SSE; | |
4fdb2424 WC |
269 | default: |
270 | return clk_div | |
271 | | SSCR0_Motorola | |
272 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
273 | | SSCR0_SSE | |
274 | | (bits > 16 ? SSCR0_EDSS : 0); | |
275 | } | |
276 | } | |
277 | ||
a0d2642e MW |
278 | /* |
279 | * Read and write LPSS SSP private registers. Caller must first check that | |
280 | * is_lpss_ssp() returns true before these can be called. | |
281 | */ | |
282 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
283 | { | |
284 | WARN_ON(!drv_data->lpss_base); | |
285 | return readl(drv_data->lpss_base + offset); | |
286 | } | |
287 | ||
288 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
289 | unsigned offset, u32 value) | |
290 | { | |
291 | WARN_ON(!drv_data->lpss_base); | |
292 | writel(value, drv_data->lpss_base + offset); | |
293 | } | |
294 | ||
295 | /* | |
296 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
297 | * @drv_data: pointer to the driver private data | |
298 | * | |
299 | * Perform LPSS SSP specific setup. This function must be called first if | |
300 | * one is going to use LPSS SSP private registers. | |
301 | */ | |
302 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
303 | { | |
dccf7369 JN |
304 | const struct lpss_config *config; |
305 | u32 value; | |
a0d2642e | 306 | |
dccf7369 JN |
307 | config = lpss_get_config(drv_data); |
308 | drv_data->lpss_base = drv_data->ioaddr + config->offset; | |
a0d2642e MW |
309 | |
310 | /* Enable software chip select control */ | |
0e897218 | 311 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
624ea72e JN |
312 | value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); |
313 | value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; | |
dccf7369 | 314 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
0054e28d MW |
315 | |
316 | /* Enable multiblock DMA transfers */ | |
1de70612 | 317 | if (drv_data->master_info->enable_dma) { |
dccf7369 | 318 | __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); |
1de70612 | 319 | |
82ba2c2a JN |
320 | if (config->reg_general >= 0) { |
321 | value = __lpss_ssp_read_priv(drv_data, | |
322 | config->reg_general); | |
624ea72e | 323 | value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; |
82ba2c2a JN |
324 | __lpss_ssp_write_priv(drv_data, |
325 | config->reg_general, value); | |
326 | } | |
1de70612 | 327 | } |
a0d2642e MW |
328 | } |
329 | ||
c1e4a53c MW |
330 | static void lpss_ssp_select_cs(struct driver_data *drv_data, |
331 | const struct lpss_config *config) | |
332 | { | |
333 | u32 value, cs; | |
334 | ||
335 | if (!config->cs_sel_mask) | |
336 | return; | |
337 | ||
338 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); | |
339 | ||
4fc0caac | 340 | cs = drv_data->master->cur_msg->spi->chip_select; |
c1e4a53c MW |
341 | cs <<= config->cs_sel_shift; |
342 | if (cs != (value & config->cs_sel_mask)) { | |
343 | /* | |
344 | * When switching another chip select output active the | |
345 | * output must be selected first and wait 2 ssp_clk cycles | |
346 | * before changing state to active. Otherwise a short | |
347 | * glitch will occur on the previous chip select since | |
348 | * output select is latched but state control is not. | |
349 | */ | |
350 | value &= ~config->cs_sel_mask; | |
351 | value |= cs; | |
352 | __lpss_ssp_write_priv(drv_data, | |
353 | config->reg_cs_ctrl, value); | |
354 | ndelay(1000000000 / | |
355 | (drv_data->master->max_speed_hz / 2)); | |
356 | } | |
357 | } | |
358 | ||
a0d2642e MW |
359 | static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) |
360 | { | |
dccf7369 | 361 | const struct lpss_config *config; |
c1e4a53c | 362 | u32 value; |
a0d2642e | 363 | |
dccf7369 JN |
364 | config = lpss_get_config(drv_data); |
365 | ||
c1e4a53c MW |
366 | if (enable) |
367 | lpss_ssp_select_cs(drv_data, config); | |
368 | ||
dccf7369 | 369 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
c1e4a53c | 370 | if (enable) |
624ea72e | 371 | value &= ~LPSS_CS_CONTROL_CS_HIGH; |
c1e4a53c | 372 | else |
624ea72e | 373 | value |= LPSS_CS_CONTROL_CS_HIGH; |
dccf7369 | 374 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
a0d2642e MW |
375 | } |
376 | ||
a7bb3909 EM |
377 | static void cs_assert(struct driver_data *drv_data) |
378 | { | |
96579a4e JN |
379 | struct chip_data *chip = |
380 | spi_get_ctldata(drv_data->master->cur_msg->spi); | |
a7bb3909 | 381 | |
2a8626a9 | 382 | if (drv_data->ssp_type == CE4100_SSP) { |
96579a4e | 383 | pxa2xx_spi_write(drv_data, SSSR, chip->frm); |
2a8626a9 SAS |
384 | return; |
385 | } | |
386 | ||
a7bb3909 EM |
387 | if (chip->cs_control) { |
388 | chip->cs_control(PXA2XX_CS_ASSERT); | |
389 | return; | |
390 | } | |
391 | ||
a0d2642e | 392 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 393 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); |
a0d2642e MW |
394 | return; |
395 | } | |
396 | ||
7566bcc7 JN |
397 | if (is_lpss_ssp(drv_data)) |
398 | lpss_ssp_cs_control(drv_data, true); | |
a7bb3909 EM |
399 | } |
400 | ||
401 | static void cs_deassert(struct driver_data *drv_data) | |
402 | { | |
96579a4e JN |
403 | struct chip_data *chip = |
404 | spi_get_ctldata(drv_data->master->cur_msg->spi); | |
a7bb3909 | 405 | |
2a8626a9 SAS |
406 | if (drv_data->ssp_type == CE4100_SSP) |
407 | return; | |
408 | ||
a7bb3909 | 409 | if (chip->cs_control) { |
2b2562d3 | 410 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
411 | return; |
412 | } | |
413 | ||
a0d2642e | 414 | if (gpio_is_valid(chip->gpio_cs)) { |
a7bb3909 | 415 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); |
a0d2642e MW |
416 | return; |
417 | } | |
418 | ||
7566bcc7 JN |
419 | if (is_lpss_ssp(drv_data)) |
420 | lpss_ssp_cs_control(drv_data, false); | |
a7bb3909 EM |
421 | } |
422 | ||
cd7bed00 | 423 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
424 | { |
425 | unsigned long limit = loops_per_jiffy << 1; | |
426 | ||
e0c9905e | 427 | do { |
c039dd27 JN |
428 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
429 | pxa2xx_spi_read(drv_data, SSDR); | |
430 | } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); | |
2a8626a9 | 431 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
432 | |
433 | return limit; | |
434 | } | |
435 | ||
8d94cc50 | 436 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 437 | { |
9708c121 | 438 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 439 | |
4fdb2424 | 440 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
441 | || (drv_data->tx == drv_data->tx_end)) |
442 | return 0; | |
443 | ||
c039dd27 | 444 | pxa2xx_spi_write(drv_data, SSDR, 0); |
8d94cc50 SS |
445 | drv_data->tx += n_bytes; |
446 | ||
447 | return 1; | |
e0c9905e SS |
448 | } |
449 | ||
8d94cc50 | 450 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 451 | { |
9708c121 | 452 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 453 | |
c039dd27 JN |
454 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
455 | && (drv_data->rx < drv_data->rx_end)) { | |
456 | pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
457 | drv_data->rx += n_bytes; |
458 | } | |
8d94cc50 SS |
459 | |
460 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
461 | } |
462 | ||
8d94cc50 | 463 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 464 | { |
4fdb2424 | 465 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
466 | || (drv_data->tx == drv_data->tx_end)) |
467 | return 0; | |
468 | ||
c039dd27 | 469 | pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); |
8d94cc50 SS |
470 | ++drv_data->tx; |
471 | ||
472 | return 1; | |
e0c9905e SS |
473 | } |
474 | ||
8d94cc50 | 475 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 476 | { |
c039dd27 JN |
477 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
478 | && (drv_data->rx < drv_data->rx_end)) { | |
479 | *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
480 | ++drv_data->rx; |
481 | } | |
8d94cc50 SS |
482 | |
483 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
484 | } |
485 | ||
8d94cc50 | 486 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 487 | { |
4fdb2424 | 488 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
489 | || (drv_data->tx == drv_data->tx_end)) |
490 | return 0; | |
491 | ||
c039dd27 | 492 | pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); |
8d94cc50 SS |
493 | drv_data->tx += 2; |
494 | ||
495 | return 1; | |
e0c9905e SS |
496 | } |
497 | ||
8d94cc50 | 498 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 499 | { |
c039dd27 JN |
500 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
501 | && (drv_data->rx < drv_data->rx_end)) { | |
502 | *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
503 | drv_data->rx += 2; |
504 | } | |
8d94cc50 SS |
505 | |
506 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 507 | } |
8d94cc50 SS |
508 | |
509 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 510 | { |
4fdb2424 | 511 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
512 | || (drv_data->tx == drv_data->tx_end)) |
513 | return 0; | |
514 | ||
c039dd27 | 515 | pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); |
8d94cc50 SS |
516 | drv_data->tx += 4; |
517 | ||
518 | return 1; | |
e0c9905e SS |
519 | } |
520 | ||
8d94cc50 | 521 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 522 | { |
c039dd27 JN |
523 | while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) |
524 | && (drv_data->rx < drv_data->rx_end)) { | |
525 | *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); | |
e0c9905e SS |
526 | drv_data->rx += 4; |
527 | } | |
8d94cc50 SS |
528 | |
529 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
530 | } |
531 | ||
cd7bed00 | 532 | void *pxa2xx_spi_next_transfer(struct driver_data *drv_data) |
e0c9905e | 533 | { |
4fc0caac | 534 | struct spi_message *msg = drv_data->master->cur_msg; |
e0c9905e SS |
535 | struct spi_transfer *trans = drv_data->cur_transfer; |
536 | ||
537 | /* Move to next transfer */ | |
538 | if (trans->transfer_list.next != &msg->transfers) { | |
539 | drv_data->cur_transfer = | |
540 | list_entry(trans->transfer_list.next, | |
541 | struct spi_transfer, | |
542 | transfer_list); | |
543 | return RUNNING_STATE; | |
544 | } else | |
545 | return DONE_STATE; | |
546 | } | |
547 | ||
e0c9905e | 548 | /* caller already set message->status; dma and pio irqs are blocked */ |
5daa3ba0 | 549 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
550 | { |
551 | struct spi_transfer* last_transfer; | |
5daa3ba0 | 552 | struct spi_message *msg; |
7a8d44bc | 553 | unsigned long timeout; |
e0c9905e | 554 | |
4fc0caac | 555 | msg = drv_data->master->cur_msg; |
5daa3ba0 | 556 | drv_data->cur_transfer = NULL; |
5daa3ba0 | 557 | |
23e2c2aa | 558 | last_transfer = list_last_entry(&msg->transfers, struct spi_transfer, |
e0c9905e SS |
559 | transfer_list); |
560 | ||
8423597d NF |
561 | /* Delay if requested before any change in chip select */ |
562 | if (last_transfer->delay_usecs) | |
563 | udelay(last_transfer->delay_usecs); | |
564 | ||
7a8d44bc JN |
565 | /* Wait until SSP becomes idle before deasserting the CS */ |
566 | timeout = jiffies + msecs_to_jiffies(10); | |
567 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && | |
568 | !time_after(jiffies, timeout)) | |
569 | cpu_relax(); | |
570 | ||
8423597d NF |
571 | /* Drop chip select UNLESS cs_change is true or we are returning |
572 | * a message with an error, or next message is for another chip | |
573 | */ | |
e0c9905e | 574 | if (!last_transfer->cs_change) |
a7bb3909 | 575 | cs_deassert(drv_data); |
8423597d NF |
576 | else { |
577 | struct spi_message *next_msg; | |
578 | ||
579 | /* Holding of cs was hinted, but we need to make sure | |
580 | * the next message is for the same chip. Don't waste | |
581 | * time with the following tests unless this was hinted. | |
582 | * | |
583 | * We cannot postpone this until pump_messages, because | |
584 | * after calling msg->complete (below) the driver that | |
585 | * sent the current message could be unloaded, which | |
586 | * could invalidate the cs_control() callback... | |
587 | */ | |
588 | ||
589 | /* get a pointer to the next message, if any */ | |
7f86bde9 | 590 | next_msg = spi_get_next_queued_message(drv_data->master); |
8423597d NF |
591 | |
592 | /* see if the next and current messages point | |
593 | * to the same chip | |
594 | */ | |
a52db659 CR |
595 | if ((next_msg && next_msg->spi != msg->spi) || |
596 | msg->state == ERROR_STATE) | |
a7bb3909 | 597 | cs_deassert(drv_data); |
8423597d | 598 | } |
e0c9905e | 599 | |
c957e8f0 | 600 | spi_finalize_current_message(drv_data->master); |
e0c9905e SS |
601 | } |
602 | ||
579d3bb2 SAS |
603 | static void reset_sccr1(struct driver_data *drv_data) |
604 | { | |
96579a4e JN |
605 | struct chip_data *chip = |
606 | spi_get_ctldata(drv_data->master->cur_msg->spi); | |
579d3bb2 SAS |
607 | u32 sccr1_reg; |
608 | ||
c039dd27 | 609 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; |
152bc19e AS |
610 | switch (drv_data->ssp_type) { |
611 | case QUARK_X1000_SSP: | |
612 | sccr1_reg &= ~QUARK_X1000_SSCR1_RFT; | |
613 | break; | |
7c7289a4 AS |
614 | case CE4100_SSP: |
615 | sccr1_reg &= ~CE4100_SSCR1_RFT; | |
616 | break; | |
152bc19e AS |
617 | default: |
618 | sccr1_reg &= ~SSCR1_RFT; | |
619 | break; | |
620 | } | |
579d3bb2 | 621 | sccr1_reg |= chip->threshold; |
c039dd27 | 622 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
579d3bb2 SAS |
623 | } |
624 | ||
8d94cc50 | 625 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 626 | { |
8d94cc50 | 627 | /* Stop and reset SSP */ |
2a8626a9 | 628 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 629 | reset_sccr1(drv_data); |
2a8626a9 | 630 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 631 | pxa2xx_spi_write(drv_data, SSTO, 0); |
cd7bed00 | 632 | pxa2xx_spi_flush(drv_data); |
c039dd27 JN |
633 | pxa2xx_spi_write(drv_data, SSCR0, |
634 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
e0c9905e | 635 | |
8d94cc50 | 636 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 637 | |
4fc0caac | 638 | drv_data->master->cur_msg->state = ERROR_STATE; |
8d94cc50 SS |
639 | tasklet_schedule(&drv_data->pump_transfers); |
640 | } | |
5daa3ba0 | 641 | |
8d94cc50 SS |
642 | static void int_transfer_complete(struct driver_data *drv_data) |
643 | { | |
07550df0 | 644 | /* Clear and disable interrupts */ |
2a8626a9 | 645 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 646 | reset_sccr1(drv_data); |
2a8626a9 | 647 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 648 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e0c9905e | 649 | |
25985edc | 650 | /* Update total byte transferred return count actual bytes read */ |
4fc0caac | 651 | drv_data->master->cur_msg->actual_length += drv_data->len - |
8d94cc50 | 652 | (drv_data->rx_end - drv_data->rx); |
e0c9905e | 653 | |
8423597d NF |
654 | /* Transfer delays and chip select release are |
655 | * handled in pump_transfers or giveback | |
656 | */ | |
e0c9905e | 657 | |
8d94cc50 | 658 | /* Move to next transfer */ |
4fc0caac | 659 | drv_data->master->cur_msg->state = pxa2xx_spi_next_transfer(drv_data); |
e0c9905e | 660 | |
8d94cc50 SS |
661 | /* Schedule transfer tasklet */ |
662 | tasklet_schedule(&drv_data->pump_transfers); | |
663 | } | |
e0c9905e | 664 | |
8d94cc50 SS |
665 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
666 | { | |
c039dd27 JN |
667 | u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? |
668 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 669 | |
c039dd27 | 670 | u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; |
e0c9905e | 671 | |
8d94cc50 SS |
672 | if (irq_status & SSSR_ROR) { |
673 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
674 | return IRQ_HANDLED; | |
675 | } | |
e0c9905e | 676 | |
8d94cc50 | 677 | if (irq_status & SSSR_TINT) { |
c039dd27 | 678 | pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); |
8d94cc50 SS |
679 | if (drv_data->read(drv_data)) { |
680 | int_transfer_complete(drv_data); | |
681 | return IRQ_HANDLED; | |
682 | } | |
683 | } | |
e0c9905e | 684 | |
8d94cc50 SS |
685 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
686 | do { | |
687 | if (drv_data->read(drv_data)) { | |
688 | int_transfer_complete(drv_data); | |
689 | return IRQ_HANDLED; | |
690 | } | |
691 | } while (drv_data->write(drv_data)); | |
e0c9905e | 692 | |
8d94cc50 SS |
693 | if (drv_data->read(drv_data)) { |
694 | int_transfer_complete(drv_data); | |
695 | return IRQ_HANDLED; | |
696 | } | |
e0c9905e | 697 | |
8d94cc50 | 698 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
699 | u32 bytes_left; |
700 | u32 sccr1_reg; | |
701 | ||
c039dd27 | 702 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
579d3bb2 SAS |
703 | sccr1_reg &= ~SSCR1_TIE; |
704 | ||
705 | /* | |
706 | * PXA25x_SSP has no timeout, set up rx threshould for the | |
25985edc | 707 | * remaining RX bytes. |
579d3bb2 | 708 | */ |
2a8626a9 | 709 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 710 | u32 rx_thre; |
579d3bb2 | 711 | |
4fdb2424 | 712 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
713 | |
714 | bytes_left = drv_data->rx_end - drv_data->rx; | |
715 | switch (drv_data->n_bytes) { | |
716 | case 4: | |
717 | bytes_left >>= 1; | |
718 | case 2: | |
719 | bytes_left >>= 1; | |
8d94cc50 | 720 | } |
579d3bb2 | 721 | |
4fdb2424 WC |
722 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
723 | if (rx_thre > bytes_left) | |
724 | rx_thre = bytes_left; | |
579d3bb2 | 725 | |
4fdb2424 | 726 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 727 | } |
c039dd27 | 728 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
e0c9905e SS |
729 | } |
730 | ||
5daa3ba0 SS |
731 | /* We did something */ |
732 | return IRQ_HANDLED; | |
e0c9905e SS |
733 | } |
734 | ||
b0312482 JK |
735 | static void handle_bad_msg(struct driver_data *drv_data) |
736 | { | |
737 | pxa2xx_spi_write(drv_data, SSCR0, | |
738 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
739 | pxa2xx_spi_write(drv_data, SSCR1, | |
740 | pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1); | |
741 | if (!pxa25x_ssp_comp(drv_data)) | |
742 | pxa2xx_spi_write(drv_data, SSTO, 0); | |
743 | write_SSSR_CS(drv_data, drv_data->clear_sr); | |
744 | ||
745 | dev_err(&drv_data->pdev->dev, | |
746 | "bad message state in interrupt handler\n"); | |
747 | } | |
748 | ||
7d12e780 | 749 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 750 | { |
c7bec5ab | 751 | struct driver_data *drv_data = dev_id; |
7d94a505 | 752 | u32 sccr1_reg; |
49cbb1e0 SAS |
753 | u32 mask = drv_data->mask_sr; |
754 | u32 status; | |
755 | ||
7d94a505 MW |
756 | /* |
757 | * The IRQ might be shared with other peripherals so we must first | |
758 | * check that are we RPM suspended or not. If we are we assume that | |
759 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
760 | * interrupt is enabled). | |
761 | */ | |
762 | if (pm_runtime_suspended(&drv_data->pdev->dev)) | |
763 | return IRQ_NONE; | |
764 | ||
269e4a41 MW |
765 | /* |
766 | * If the device is not yet in RPM suspended state and we get an | |
767 | * interrupt that is meant for another device, check if status bits | |
768 | * are all set to one. That means that the device is already | |
769 | * powered off. | |
770 | */ | |
c039dd27 | 771 | status = pxa2xx_spi_read(drv_data, SSSR); |
269e4a41 MW |
772 | if (status == ~0) |
773 | return IRQ_NONE; | |
774 | ||
c039dd27 | 775 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
49cbb1e0 SAS |
776 | |
777 | /* Ignore possible writes if we don't need to write */ | |
778 | if (!(sccr1_reg & SSCR1_TIE)) | |
779 | mask &= ~SSSR_TFS; | |
780 | ||
02bc933e TJN |
781 | /* Ignore RX timeout interrupt if it is disabled */ |
782 | if (!(sccr1_reg & SSCR1_TINTE)) | |
783 | mask &= ~SSSR_TINT; | |
784 | ||
49cbb1e0 SAS |
785 | if (!(status & mask)) |
786 | return IRQ_NONE; | |
e0c9905e | 787 | |
e51e9b93 JK |
788 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); |
789 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); | |
5daa3ba0 | 790 | |
4fc0caac | 791 | if (!drv_data->master->cur_msg) { |
b0312482 | 792 | handle_bad_msg(drv_data); |
e0c9905e SS |
793 | /* Never fail */ |
794 | return IRQ_HANDLED; | |
795 | } | |
796 | ||
797 | return drv_data->transfer_handler(drv_data); | |
798 | } | |
799 | ||
e5262d05 | 800 | /* |
9df461ec AS |
801 | * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply |
802 | * input frequency by fractions of 2^24. It also has a divider by 5. | |
803 | * | |
804 | * There are formulas to get baud rate value for given input frequency and | |
805 | * divider parameters, such as DDS_CLK_RATE and SCR: | |
806 | * | |
807 | * Fsys = 200MHz | |
808 | * | |
809 | * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) | |
810 | * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) | |
811 | * | |
812 | * DDS_CLK_RATE either 2^n or 2^n / 5. | |
813 | * SCR is in range 0 .. 255 | |
814 | * | |
815 | * Divisor = 5^i * 2^j * 2 * k | |
816 | * i = [0, 1] i = 1 iff j = 0 or j > 3 | |
817 | * j = [0, 23] j = 0 iff i = 1 | |
818 | * k = [1, 256] | |
819 | * Special case: j = 0, i = 1: Divisor = 2 / 5 | |
820 | * | |
821 | * Accordingly to the specification the recommended values for DDS_CLK_RATE | |
822 | * are: | |
823 | * Case 1: 2^n, n = [0, 23] | |
824 | * Case 2: 2^24 * 2 / 5 (0x666666) | |
825 | * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) | |
826 | * | |
827 | * In all cases the lowest possible value is better. | |
828 | * | |
829 | * The function calculates parameters for all cases and chooses the one closest | |
830 | * to the asked baud rate. | |
e5262d05 | 831 | */ |
9df461ec AS |
832 | static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) |
833 | { | |
834 | unsigned long xtal = 200000000; | |
835 | unsigned long fref = xtal / 2; /* mandatory division by 2, | |
836 | see (2) */ | |
837 | /* case 3 */ | |
838 | unsigned long fref1 = fref / 2; /* case 1 */ | |
839 | unsigned long fref2 = fref * 2 / 5; /* case 2 */ | |
840 | unsigned long scale; | |
841 | unsigned long q, q1, q2; | |
842 | long r, r1, r2; | |
843 | u32 mul; | |
844 | ||
845 | /* Case 1 */ | |
846 | ||
847 | /* Set initial value for DDS_CLK_RATE */ | |
848 | mul = (1 << 24) >> 1; | |
849 | ||
850 | /* Calculate initial quot */ | |
3ad48062 | 851 | q1 = DIV_ROUND_UP(fref1, rate); |
9df461ec AS |
852 | |
853 | /* Scale q1 if it's too big */ | |
854 | if (q1 > 256) { | |
855 | /* Scale q1 to range [1, 512] */ | |
856 | scale = fls_long(q1 - 1); | |
857 | if (scale > 9) { | |
858 | q1 >>= scale - 9; | |
859 | mul >>= scale - 9; | |
e5262d05 | 860 | } |
9df461ec AS |
861 | |
862 | /* Round the result if we have a remainder */ | |
863 | q1 += q1 & 1; | |
864 | } | |
865 | ||
866 | /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ | |
867 | scale = __ffs(q1); | |
868 | q1 >>= scale; | |
869 | mul >>= scale; | |
870 | ||
871 | /* Get the remainder */ | |
872 | r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); | |
873 | ||
874 | /* Case 2 */ | |
875 | ||
3ad48062 | 876 | q2 = DIV_ROUND_UP(fref2, rate); |
9df461ec AS |
877 | r2 = abs(fref2 / q2 - rate); |
878 | ||
879 | /* | |
880 | * Choose the best between two: less remainder we have the better. We | |
881 | * can't go case 2 if q2 is greater than 256 since SCR register can | |
882 | * hold only values 0 .. 255. | |
883 | */ | |
884 | if (r2 >= r1 || q2 > 256) { | |
885 | /* case 1 is better */ | |
886 | r = r1; | |
887 | q = q1; | |
888 | } else { | |
889 | /* case 2 is better */ | |
890 | r = r2; | |
891 | q = q2; | |
892 | mul = (1 << 24) * 2 / 5; | |
e5262d05 WC |
893 | } |
894 | ||
3ad48062 | 895 | /* Check case 3 only if the divisor is big enough */ |
9df461ec AS |
896 | if (fref / rate >= 80) { |
897 | u64 fssp; | |
898 | u32 m; | |
899 | ||
900 | /* Calculate initial quot */ | |
3ad48062 | 901 | q1 = DIV_ROUND_UP(fref, rate); |
9df461ec AS |
902 | m = (1 << 24) / q1; |
903 | ||
904 | /* Get the remainder */ | |
905 | fssp = (u64)fref * m; | |
906 | do_div(fssp, 1 << 24); | |
907 | r1 = abs(fssp - rate); | |
908 | ||
909 | /* Choose this one if it suits better */ | |
910 | if (r1 < r) { | |
911 | /* case 3 is better */ | |
912 | q = 1; | |
913 | mul = m; | |
914 | } | |
915 | } | |
e5262d05 | 916 | |
9df461ec AS |
917 | *dds = mul; |
918 | return q - 1; | |
e5262d05 WC |
919 | } |
920 | ||
3343b7a6 | 921 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 922 | { |
0eca7cf2 | 923 | unsigned long ssp_clk = drv_data->master->max_speed_hz; |
3343b7a6 MW |
924 | const struct ssp_device *ssp = drv_data->ssp; |
925 | ||
926 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 927 | |
2a8626a9 | 928 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
025ffe88 | 929 | return (ssp_clk / (2 * rate) - 1) & 0xff; |
2f1a74e5 | 930 | else |
025ffe88 | 931 | return (ssp_clk / rate - 1) & 0xfff; |
2f1a74e5 | 932 | } |
933 | ||
e5262d05 | 934 | static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, |
d2c2f6a4 | 935 | int rate) |
e5262d05 | 936 | { |
96579a4e JN |
937 | struct chip_data *chip = |
938 | spi_get_ctldata(drv_data->master->cur_msg->spi); | |
025ffe88 | 939 | unsigned int clk_div; |
e5262d05 WC |
940 | |
941 | switch (drv_data->ssp_type) { | |
942 | case QUARK_X1000_SSP: | |
9df461ec | 943 | clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); |
eecacf73 | 944 | break; |
e5262d05 | 945 | default: |
025ffe88 | 946 | clk_div = ssp_get_clk_div(drv_data, rate); |
eecacf73 | 947 | break; |
e5262d05 | 948 | } |
025ffe88 | 949 | return clk_div << 8; |
e5262d05 WC |
950 | } |
951 | ||
b6ced294 JN |
952 | static bool pxa2xx_spi_can_dma(struct spi_master *master, |
953 | struct spi_device *spi, | |
954 | struct spi_transfer *xfer) | |
955 | { | |
956 | struct chip_data *chip = spi_get_ctldata(spi); | |
957 | ||
958 | return chip->enable_dma && | |
959 | xfer->len <= MAX_DMA_LEN && | |
960 | xfer->len >= chip->dma_burst_size; | |
961 | } | |
962 | ||
e0c9905e SS |
963 | static void pump_transfers(unsigned long data) |
964 | { | |
965 | struct driver_data *drv_data = (struct driver_data *)data; | |
2d7537d8 | 966 | struct spi_master *master = drv_data->master; |
4fc0caac | 967 | struct spi_message *message = master->cur_msg; |
96579a4e JN |
968 | struct chip_data *chip = spi_get_ctldata(message->spi); |
969 | u32 dma_thresh = chip->dma_threshold; | |
970 | u32 dma_burst = chip->dma_burst_size; | |
971 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); | |
bffc967e JN |
972 | struct spi_transfer *transfer; |
973 | struct spi_transfer *previous; | |
bffc967e JN |
974 | u32 clk_div; |
975 | u8 bits; | |
976 | u32 speed; | |
9708c121 | 977 | u32 cr0; |
8d94cc50 | 978 | u32 cr1; |
7d1f1bf6 | 979 | int err; |
b6ced294 | 980 | int dma_mapped; |
e0c9905e SS |
981 | |
982 | /* Get current state information */ | |
e0c9905e | 983 | transfer = drv_data->cur_transfer; |
e0c9905e SS |
984 | |
985 | /* Handle for abort */ | |
986 | if (message->state == ERROR_STATE) { | |
987 | message->status = -EIO; | |
5daa3ba0 | 988 | giveback(drv_data); |
e0c9905e SS |
989 | return; |
990 | } | |
991 | ||
992 | /* Handle end of message */ | |
993 | if (message->state == DONE_STATE) { | |
994 | message->status = 0; | |
5daa3ba0 | 995 | giveback(drv_data); |
e0c9905e SS |
996 | return; |
997 | } | |
998 | ||
8423597d | 999 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
1000 | if (message->state == RUNNING_STATE) { |
1001 | previous = list_entry(transfer->transfer_list.prev, | |
1002 | struct spi_transfer, | |
1003 | transfer_list); | |
1004 | if (previous->delay_usecs) | |
1005 | udelay(previous->delay_usecs); | |
8423597d NF |
1006 | |
1007 | /* Drop chip select only if cs_change is requested */ | |
1008 | if (previous->cs_change) | |
a7bb3909 | 1009 | cs_deassert(drv_data); |
e0c9905e SS |
1010 | } |
1011 | ||
cd7bed00 | 1012 | /* Check if we can DMA this transfer */ |
b6ced294 | 1013 | if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { |
7e964455 NF |
1014 | |
1015 | /* reject already-mapped transfers; PIO won't always work */ | |
1016 | if (message->is_dma_mapped | |
1017 | || transfer->rx_dma || transfer->tx_dma) { | |
1018 | dev_err(&drv_data->pdev->dev, | |
f6bd03a7 JN |
1019 | "pump_transfers: mapped transfer length of " |
1020 | "%u is greater than %d\n", | |
7e964455 NF |
1021 | transfer->len, MAX_DMA_LEN); |
1022 | message->status = -EINVAL; | |
1023 | giveback(drv_data); | |
1024 | return; | |
1025 | } | |
1026 | ||
1027 | /* warn ... we force this to PIO mode */ | |
f6bd03a7 JN |
1028 | dev_warn_ratelimited(&message->spi->dev, |
1029 | "pump_transfers: DMA disabled for transfer length %ld " | |
1030 | "greater than %d\n", | |
1031 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
1032 | } |
1033 | ||
e0c9905e | 1034 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 1035 | if (pxa2xx_spi_flush(drv_data) == 0) { |
e0c9905e SS |
1036 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
1037 | message->status = -EIO; | |
5daa3ba0 | 1038 | giveback(drv_data); |
e0c9905e SS |
1039 | return; |
1040 | } | |
9708c121 | 1041 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
1042 | drv_data->tx = (void *)transfer->tx_buf; |
1043 | drv_data->tx_end = drv_data->tx + transfer->len; | |
1044 | drv_data->rx = transfer->rx_buf; | |
1045 | drv_data->rx_end = drv_data->rx + transfer->len; | |
cd7bed00 | 1046 | drv_data->len = transfer->len; |
e0c9905e SS |
1047 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
1048 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
1049 | |
1050 | /* Change speed and bit per word on a per transfer */ | |
196b0e2c JN |
1051 | bits = transfer->bits_per_word; |
1052 | speed = transfer->speed_hz; | |
1053 | ||
d2c2f6a4 | 1054 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); |
196b0e2c JN |
1055 | |
1056 | if (bits <= 8) { | |
1057 | drv_data->n_bytes = 1; | |
1058 | drv_data->read = drv_data->read != null_reader ? | |
1059 | u8_reader : null_reader; | |
1060 | drv_data->write = drv_data->write != null_writer ? | |
1061 | u8_writer : null_writer; | |
1062 | } else if (bits <= 16) { | |
1063 | drv_data->n_bytes = 2; | |
1064 | drv_data->read = drv_data->read != null_reader ? | |
1065 | u16_reader : null_reader; | |
1066 | drv_data->write = drv_data->write != null_writer ? | |
1067 | u16_writer : null_writer; | |
1068 | } else if (bits <= 32) { | |
1069 | drv_data->n_bytes = 4; | |
1070 | drv_data->read = drv_data->read != null_reader ? | |
1071 | u32_reader : null_reader; | |
1072 | drv_data->write = drv_data->write != null_writer ? | |
1073 | u32_writer : null_writer; | |
9708c121 | 1074 | } |
196b0e2c JN |
1075 | /* |
1076 | * if bits/word is changed in dma mode, then must check the | |
1077 | * thresholds and burst also | |
1078 | */ | |
1079 | if (chip->enable_dma) { | |
1080 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, | |
1081 | message->spi, | |
1082 | bits, &dma_burst, | |
1083 | &dma_thresh)) | |
1084 | dev_warn_ratelimited(&message->spi->dev, | |
1085 | "pump_transfers: DMA burst size reduced to match bits_per_word\n"); | |
9708c121 SS |
1086 | } |
1087 | ||
e0c9905e SS |
1088 | message->state = RUNNING_STATE; |
1089 | ||
b6ced294 JN |
1090 | dma_mapped = master->can_dma && |
1091 | master->can_dma(master, message->spi, transfer) && | |
1092 | master->cur_msg_mapped; | |
1093 | if (dma_mapped) { | |
e0c9905e SS |
1094 | |
1095 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
1096 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
1097 | ||
7d1f1bf6 AS |
1098 | err = pxa2xx_spi_dma_prepare(drv_data, dma_burst); |
1099 | if (err) { | |
1100 | message->status = err; | |
1101 | giveback(drv_data); | |
1102 | return; | |
1103 | } | |
e0c9905e | 1104 | |
8d94cc50 SS |
1105 | /* Clear status and start DMA engine */ |
1106 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
c039dd27 | 1107 | pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); |
cd7bed00 MW |
1108 | |
1109 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
1110 | } else { |
1111 | /* Ensure we have the correct interrupt handler */ | |
1112 | drv_data->transfer_handler = interrupt_transfer; | |
1113 | ||
8d94cc50 SS |
1114 | /* Clear status */ |
1115 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 1116 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
1117 | } |
1118 | ||
ee03672d JN |
1119 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
1120 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); | |
1121 | if (!pxa25x_ssp_comp(drv_data)) | |
1122 | dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", | |
2d7537d8 | 1123 | master->max_speed_hz |
ee03672d | 1124 | / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), |
b6ced294 | 1125 | dma_mapped ? "DMA" : "PIO"); |
ee03672d JN |
1126 | else |
1127 | dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", | |
2d7537d8 | 1128 | master->max_speed_hz / 2 |
ee03672d | 1129 | / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
b6ced294 | 1130 | dma_mapped ? "DMA" : "PIO"); |
ee03672d | 1131 | |
a0d2642e | 1132 | if (is_lpss_ssp(drv_data)) { |
c039dd27 JN |
1133 | if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) |
1134 | != chip->lpss_rx_threshold) | |
1135 | pxa2xx_spi_write(drv_data, SSIRF, | |
1136 | chip->lpss_rx_threshold); | |
1137 | if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) | |
1138 | != chip->lpss_tx_threshold) | |
1139 | pxa2xx_spi_write(drv_data, SSITF, | |
1140 | chip->lpss_tx_threshold); | |
a0d2642e MW |
1141 | } |
1142 | ||
e5262d05 | 1143 | if (is_quark_x1000_ssp(drv_data) && |
c039dd27 JN |
1144 | (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) |
1145 | pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); | |
e5262d05 | 1146 | |
8d94cc50 | 1147 | /* see if we need to reload the config registers */ |
c039dd27 JN |
1148 | if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) |
1149 | || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) | |
1150 | != (cr1 & change_mask)) { | |
b97c74bd | 1151 | /* stop the SSP, and update the other bits */ |
c039dd27 | 1152 | pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); |
2a8626a9 | 1153 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1154 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
b97c74bd | 1155 | /* first set CR1 without interrupt and service enables */ |
c039dd27 | 1156 | pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); |
b97c74bd | 1157 | /* restart the SSP */ |
c039dd27 | 1158 | pxa2xx_spi_write(drv_data, SSCR0, cr0); |
b97c74bd | 1159 | |
8d94cc50 | 1160 | } else { |
2a8626a9 | 1161 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1162 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); |
e0c9905e | 1163 | } |
b97c74bd | 1164 | |
a7bb3909 | 1165 | cs_assert(drv_data); |
b97c74bd NF |
1166 | |
1167 | /* after chip select, release the data by enabling service | |
1168 | * requests and interrupts, without changing any mode bits */ | |
c039dd27 | 1169 | pxa2xx_spi_write(drv_data, SSCR1, cr1); |
e0c9905e SS |
1170 | } |
1171 | ||
7f86bde9 MW |
1172 | static int pxa2xx_spi_transfer_one_message(struct spi_master *master, |
1173 | struct spi_message *msg) | |
e0c9905e | 1174 | { |
7f86bde9 | 1175 | struct driver_data *drv_data = spi_master_get_devdata(master); |
e0c9905e SS |
1176 | |
1177 | /* Initial message state*/ | |
4fc0caac JN |
1178 | msg->state = START_STATE; |
1179 | drv_data->cur_transfer = list_entry(msg->transfers.next, | |
e0c9905e SS |
1180 | struct spi_transfer, |
1181 | transfer_list); | |
1182 | ||
e0c9905e SS |
1183 | /* Mark as busy and launch transfers */ |
1184 | tasklet_schedule(&drv_data->pump_transfers); | |
e0c9905e SS |
1185 | return 0; |
1186 | } | |
1187 | ||
7d94a505 MW |
1188 | static int pxa2xx_spi_unprepare_transfer(struct spi_master *master) |
1189 | { | |
1190 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1191 | ||
1192 | /* Disable the SSP now */ | |
c039dd27 JN |
1193 | pxa2xx_spi_write(drv_data, SSCR0, |
1194 | pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); | |
7d94a505 | 1195 | |
7d94a505 MW |
1196 | return 0; |
1197 | } | |
1198 | ||
a7bb3909 EM |
1199 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1200 | struct pxa2xx_spi_chip *chip_info) | |
1201 | { | |
99f499cd | 1202 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
a7bb3909 EM |
1203 | int err = 0; |
1204 | ||
99f499cd MW |
1205 | if (chip == NULL) |
1206 | return 0; | |
1207 | ||
1208 | if (drv_data->cs_gpiods) { | |
1209 | struct gpio_desc *gpiod; | |
1210 | ||
1211 | gpiod = drv_data->cs_gpiods[spi->chip_select]; | |
1212 | if (gpiod) { | |
1213 | chip->gpio_cs = desc_to_gpio(gpiod); | |
1214 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1215 | gpiod_set_value(gpiod, chip->gpio_cs_inverted); | |
1216 | } | |
1217 | ||
1218 | return 0; | |
1219 | } | |
1220 | ||
1221 | if (chip_info == NULL) | |
a7bb3909 EM |
1222 | return 0; |
1223 | ||
1224 | /* NOTE: setup() can be called multiple times, possibly with | |
1225 | * different chip_info, release previously requested GPIO | |
1226 | */ | |
1227 | if (gpio_is_valid(chip->gpio_cs)) | |
1228 | gpio_free(chip->gpio_cs); | |
1229 | ||
1230 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1231 | if (chip_info->cs_control) { | |
1232 | chip->cs_control = chip_info->cs_control; | |
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1237 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1238 | if (err) { | |
f6bd03a7 JN |
1239 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", |
1240 | chip_info->gpio_cs); | |
a7bb3909 EM |
1241 | return err; |
1242 | } | |
1243 | ||
1244 | chip->gpio_cs = chip_info->gpio_cs; | |
1245 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1246 | ||
1247 | err = gpio_direction_output(chip->gpio_cs, | |
1248 | !chip->gpio_cs_inverted); | |
1249 | } | |
1250 | ||
1251 | return err; | |
1252 | } | |
1253 | ||
e0c9905e SS |
1254 | static int setup(struct spi_device *spi) |
1255 | { | |
bffc967e | 1256 | struct pxa2xx_spi_chip *chip_info; |
e0c9905e | 1257 | struct chip_data *chip; |
dccf7369 | 1258 | const struct lpss_config *config; |
e0c9905e | 1259 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
a0d2642e MW |
1260 | uint tx_thres, tx_hi_thres, rx_thres; |
1261 | ||
e5262d05 WC |
1262 | switch (drv_data->ssp_type) { |
1263 | case QUARK_X1000_SSP: | |
1264 | tx_thres = TX_THRESH_QUARK_X1000_DFLT; | |
1265 | tx_hi_thres = 0; | |
1266 | rx_thres = RX_THRESH_QUARK_X1000_DFLT; | |
1267 | break; | |
7c7289a4 AS |
1268 | case CE4100_SSP: |
1269 | tx_thres = TX_THRESH_CE4100_DFLT; | |
1270 | tx_hi_thres = 0; | |
1271 | rx_thres = RX_THRESH_CE4100_DFLT; | |
1272 | break; | |
03fbf488 JN |
1273 | case LPSS_LPT_SSP: |
1274 | case LPSS_BYT_SSP: | |
30f3a6ab | 1275 | case LPSS_BSW_SSP: |
34cadd9c | 1276 | case LPSS_SPT_SSP: |
b7c08cf8 | 1277 | case LPSS_BXT_SSP: |
dccf7369 JN |
1278 | config = lpss_get_config(drv_data); |
1279 | tx_thres = config->tx_threshold_lo; | |
1280 | tx_hi_thres = config->tx_threshold_hi; | |
1281 | rx_thres = config->rx_threshold; | |
e5262d05 WC |
1282 | break; |
1283 | default: | |
a0d2642e MW |
1284 | tx_thres = TX_THRESH_DFLT; |
1285 | tx_hi_thres = 0; | |
1286 | rx_thres = RX_THRESH_DFLT; | |
e5262d05 | 1287 | break; |
a0d2642e | 1288 | } |
e0c9905e | 1289 | |
8d94cc50 | 1290 | /* Only alloc on first setup */ |
e0c9905e | 1291 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1292 | if (!chip) { |
e0c9905e | 1293 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 1294 | if (!chip) |
e0c9905e SS |
1295 | return -ENOMEM; |
1296 | ||
2a8626a9 SAS |
1297 | if (drv_data->ssp_type == CE4100_SSP) { |
1298 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
1299 | dev_err(&spi->dev, |
1300 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
1301 | kfree(chip); |
1302 | return -EINVAL; | |
1303 | } | |
1304 | ||
1305 | chip->frm = spi->chip_select; | |
1306 | } else | |
1307 | chip->gpio_cs = -1; | |
c64e1265 | 1308 | chip->enable_dma = drv_data->master_info->enable_dma; |
f1f640a9 | 1309 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1310 | } |
1311 | ||
8d94cc50 SS |
1312 | /* protocol drivers may change the chip settings, so... |
1313 | * if chip_info exists, use it */ | |
1314 | chip_info = spi->controller_data; | |
1315 | ||
e0c9905e | 1316 | /* chip_info isn't always needed */ |
8d94cc50 | 1317 | chip->cr1 = 0; |
e0c9905e | 1318 | if (chip_info) { |
f1f640a9 VS |
1319 | if (chip_info->timeout) |
1320 | chip->timeout = chip_info->timeout; | |
1321 | if (chip_info->tx_threshold) | |
1322 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
1323 | if (chip_info->tx_hi_threshold) |
1324 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
1325 | if (chip_info->rx_threshold) |
1326 | rx_thres = chip_info->rx_threshold; | |
e0c9905e | 1327 | chip->dma_threshold = 0; |
e0c9905e SS |
1328 | if (chip_info->enable_loopback) |
1329 | chip->cr1 = SSCR1_LBM; | |
1330 | } | |
1331 | ||
a0d2642e MW |
1332 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); |
1333 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | |
1334 | | SSITF_TxHiThresh(tx_hi_thres); | |
1335 | ||
8d94cc50 SS |
1336 | /* set dma burst and threshold outside of chip_info path so that if |
1337 | * chip_info goes away after setting chip->enable_dma, the | |
1338 | * burst and threshold can still respond to changes in bits_per_word */ | |
1339 | if (chip->enable_dma) { | |
1340 | /* set up legal burst and threshold for dma */ | |
cd7bed00 MW |
1341 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1342 | spi->bits_per_word, | |
8d94cc50 SS |
1343 | &chip->dma_burst_size, |
1344 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1345 | dev_warn(&spi->dev, |
1346 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 SS |
1347 | } |
1348 | } | |
1349 | ||
e5262d05 WC |
1350 | switch (drv_data->ssp_type) { |
1351 | case QUARK_X1000_SSP: | |
1352 | chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) | |
1353 | & QUARK_X1000_SSCR1_RFT) | |
1354 | | (QUARK_X1000_SSCR1_TxTresh(tx_thres) | |
1355 | & QUARK_X1000_SSCR1_TFT); | |
1356 | break; | |
7c7289a4 AS |
1357 | case CE4100_SSP: |
1358 | chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | | |
1359 | (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT); | |
1360 | break; | |
e5262d05 WC |
1361 | default: |
1362 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | |
1363 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1364 | break; | |
1365 | } | |
1366 | ||
7f6ee1ad JC |
1367 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1368 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1369 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e | 1370 | |
b833172f MW |
1371 | if (spi->mode & SPI_LOOP) |
1372 | chip->cr1 |= SSCR1_LBM; | |
1373 | ||
e0c9905e SS |
1374 | if (spi->bits_per_word <= 8) { |
1375 | chip->n_bytes = 1; | |
e0c9905e SS |
1376 | chip->read = u8_reader; |
1377 | chip->write = u8_writer; | |
1378 | } else if (spi->bits_per_word <= 16) { | |
1379 | chip->n_bytes = 2; | |
e0c9905e SS |
1380 | chip->read = u16_reader; |
1381 | chip->write = u16_writer; | |
1382 | } else if (spi->bits_per_word <= 32) { | |
e0c9905e | 1383 | chip->n_bytes = 4; |
e0c9905e SS |
1384 | chip->read = u32_reader; |
1385 | chip->write = u32_writer; | |
e0c9905e SS |
1386 | } |
1387 | ||
1388 | spi_set_ctldata(spi, chip); | |
1389 | ||
2a8626a9 SAS |
1390 | if (drv_data->ssp_type == CE4100_SSP) |
1391 | return 0; | |
1392 | ||
a7bb3909 | 1393 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1394 | } |
1395 | ||
0ffa0285 | 1396 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1397 | { |
0ffa0285 | 1398 | struct chip_data *chip = spi_get_ctldata(spi); |
2a8626a9 | 1399 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
e0c9905e | 1400 | |
7348d82a DR |
1401 | if (!chip) |
1402 | return; | |
1403 | ||
99f499cd MW |
1404 | if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods && |
1405 | gpio_is_valid(chip->gpio_cs)) | |
a7bb3909 EM |
1406 | gpio_free(chip->gpio_cs); |
1407 | ||
e0c9905e SS |
1408 | kfree(chip); |
1409 | } | |
1410 | ||
0db64215 | 1411 | #ifdef CONFIG_PCI |
a3496855 | 1412 | #ifdef CONFIG_ACPI |
03fbf488 | 1413 | |
8422ddf7 | 1414 | static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { |
03fbf488 JN |
1415 | { "INT33C0", LPSS_LPT_SSP }, |
1416 | { "INT33C1", LPSS_LPT_SSP }, | |
1417 | { "INT3430", LPSS_LPT_SSP }, | |
1418 | { "INT3431", LPSS_LPT_SSP }, | |
1419 | { "80860F0E", LPSS_BYT_SSP }, | |
30f3a6ab | 1420 | { "8086228E", LPSS_BSW_SSP }, |
03fbf488 JN |
1421 | { }, |
1422 | }; | |
1423 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
1424 | ||
0db64215 JN |
1425 | static int pxa2xx_spi_get_port_id(struct acpi_device *adev) |
1426 | { | |
1427 | unsigned int devid; | |
1428 | int port_id = -1; | |
1429 | ||
1430 | if (adev && adev->pnp.unique_id && | |
1431 | !kstrtouint(adev->pnp.unique_id, 0, &devid)) | |
1432 | port_id = devid; | |
1433 | return port_id; | |
1434 | } | |
1435 | #else /* !CONFIG_ACPI */ | |
1436 | static int pxa2xx_spi_get_port_id(struct acpi_device *adev) | |
1437 | { | |
1438 | return -1; | |
1439 | } | |
1440 | #endif | |
1441 | ||
34cadd9c JN |
1442 | /* |
1443 | * PCI IDs of compound devices that integrate both host controller and private | |
1444 | * integrated DMA engine. Please note these are not used in module | |
1445 | * autoloading and probing in this module but matching the LPSS SSP type. | |
1446 | */ | |
1447 | static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { | |
1448 | /* SPT-LP */ | |
1449 | { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, | |
1450 | { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, | |
1451 | /* SPT-H */ | |
1452 | { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, | |
1453 | { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, | |
704d2b07 MW |
1454 | /* KBL-H */ |
1455 | { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP }, | |
1456 | { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP }, | |
c1b03f11 | 1457 | /* BXT A-Step */ |
b7c08cf8 JN |
1458 | { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, |
1459 | { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, | |
1460 | { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, | |
c1b03f11 JN |
1461 | /* BXT B-Step */ |
1462 | { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, | |
1463 | { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, | |
1464 | { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, | |
e18a80ac DB |
1465 | /* GLK */ |
1466 | { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP }, | |
1467 | { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP }, | |
1468 | { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP }, | |
b7c08cf8 JN |
1469 | /* APL */ |
1470 | { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, | |
1471 | { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, | |
1472 | { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, | |
94e5c23d | 1473 | { }, |
34cadd9c JN |
1474 | }; |
1475 | ||
1476 | static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) | |
1477 | { | |
1478 | struct device *dev = param; | |
1479 | ||
1480 | if (dev != chan->device->dev->parent) | |
1481 | return false; | |
1482 | ||
1483 | return true; | |
1484 | } | |
1485 | ||
a3496855 | 1486 | static struct pxa2xx_spi_master * |
0db64215 | 1487 | pxa2xx_spi_init_pdata(struct platform_device *pdev) |
a3496855 MW |
1488 | { |
1489 | struct pxa2xx_spi_master *pdata; | |
a3496855 MW |
1490 | struct acpi_device *adev; |
1491 | struct ssp_device *ssp; | |
1492 | struct resource *res; | |
34cadd9c JN |
1493 | const struct acpi_device_id *adev_id = NULL; |
1494 | const struct pci_device_id *pcidev_id = NULL; | |
3b8b6d05 | 1495 | int type; |
a3496855 | 1496 | |
b9f6940a | 1497 | adev = ACPI_COMPANION(&pdev->dev); |
a3496855 | 1498 | |
34cadd9c JN |
1499 | if (dev_is_pci(pdev->dev.parent)) |
1500 | pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, | |
1501 | to_pci_dev(pdev->dev.parent)); | |
0db64215 | 1502 | else if (adev) |
34cadd9c JN |
1503 | adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, |
1504 | &pdev->dev); | |
0db64215 JN |
1505 | else |
1506 | return NULL; | |
34cadd9c JN |
1507 | |
1508 | if (adev_id) | |
1509 | type = (int)adev_id->driver_data; | |
1510 | else if (pcidev_id) | |
1511 | type = (int)pcidev_id->driver_data; | |
03fbf488 JN |
1512 | else |
1513 | return NULL; | |
1514 | ||
cc0ee987 | 1515 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1516 | if (!pdata) |
a3496855 | 1517 | return NULL; |
a3496855 MW |
1518 | |
1519 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1520 | if (!res) | |
1521 | return NULL; | |
1522 | ||
1523 | ssp = &pdata->ssp; | |
1524 | ||
1525 | ssp->phys_base = res->start; | |
cbfd6a21 SK |
1526 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1527 | if (IS_ERR(ssp->mmio_base)) | |
6dc81f6f | 1528 | return NULL; |
a3496855 | 1529 | |
34cadd9c JN |
1530 | if (pcidev_id) { |
1531 | pdata->tx_param = pdev->dev.parent; | |
1532 | pdata->rx_param = pdev->dev.parent; | |
1533 | pdata->dma_filter = pxa2xx_spi_idma_filter; | |
1534 | } | |
1535 | ||
a3496855 MW |
1536 | ssp->clk = devm_clk_get(&pdev->dev, NULL); |
1537 | ssp->irq = platform_get_irq(pdev, 0); | |
03fbf488 | 1538 | ssp->type = type; |
a3496855 | 1539 | ssp->pdev = pdev; |
0db64215 | 1540 | ssp->port_id = pxa2xx_spi_get_port_id(adev); |
a3496855 MW |
1541 | |
1542 | pdata->num_chipselect = 1; | |
cddb339b | 1543 | pdata->enable_dma = true; |
a3496855 MW |
1544 | |
1545 | return pdata; | |
1546 | } | |
1547 | ||
0db64215 | 1548 | #else /* !CONFIG_PCI */ |
a3496855 | 1549 | static inline struct pxa2xx_spi_master * |
0db64215 | 1550 | pxa2xx_spi_init_pdata(struct platform_device *pdev) |
a3496855 MW |
1551 | { |
1552 | return NULL; | |
1553 | } | |
1554 | #endif | |
1555 | ||
0c27d9cf MW |
1556 | static int pxa2xx_spi_fw_translate_cs(struct spi_master *master, unsigned cs) |
1557 | { | |
1558 | struct driver_data *drv_data = spi_master_get_devdata(master); | |
1559 | ||
1560 | if (has_acpi_companion(&drv_data->pdev->dev)) { | |
1561 | switch (drv_data->ssp_type) { | |
1562 | /* | |
1563 | * For Atoms the ACPI DeviceSelection used by the Windows | |
1564 | * driver starts from 1 instead of 0 so translate it here | |
1565 | * to match what Linux expects. | |
1566 | */ | |
1567 | case LPSS_BYT_SSP: | |
30f3a6ab | 1568 | case LPSS_BSW_SSP: |
0c27d9cf MW |
1569 | return cs - 1; |
1570 | ||
1571 | default: | |
1572 | break; | |
1573 | } | |
1574 | } | |
1575 | ||
1576 | return cs; | |
1577 | } | |
1578 | ||
fd4a319b | 1579 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1580 | { |
1581 | struct device *dev = &pdev->dev; | |
1582 | struct pxa2xx_spi_master *platform_info; | |
1583 | struct spi_master *master; | |
65a00a20 | 1584 | struct driver_data *drv_data; |
2f1a74e5 | 1585 | struct ssp_device *ssp; |
8b136baa | 1586 | const struct lpss_config *config; |
99f499cd | 1587 | int status, count; |
c039dd27 | 1588 | u32 tmp; |
e0c9905e | 1589 | |
851bacf5 MW |
1590 | platform_info = dev_get_platdata(dev); |
1591 | if (!platform_info) { | |
0db64215 | 1592 | platform_info = pxa2xx_spi_init_pdata(pdev); |
a3496855 MW |
1593 | if (!platform_info) { |
1594 | dev_err(&pdev->dev, "missing platform data\n"); | |
1595 | return -ENODEV; | |
1596 | } | |
851bacf5 | 1597 | } |
e0c9905e | 1598 | |
baffe169 | 1599 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1600 | if (!ssp) |
1601 | ssp = &platform_info->ssp; | |
1602 | ||
1603 | if (!ssp->mmio_base) { | |
1604 | dev_err(&pdev->dev, "failed to get ssp\n"); | |
e0c9905e SS |
1605 | return -ENODEV; |
1606 | } | |
1607 | ||
757fe8d5 | 1608 | master = spi_alloc_master(dev, sizeof(struct driver_data)); |
e0c9905e | 1609 | if (!master) { |
65a00a20 | 1610 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
baffe169 | 1611 | pxa_ssp_free(ssp); |
e0c9905e SS |
1612 | return -ENOMEM; |
1613 | } | |
1614 | drv_data = spi_master_get_devdata(master); | |
1615 | drv_data->master = master; | |
1616 | drv_data->master_info = platform_info; | |
1617 | drv_data->pdev = pdev; | |
2f1a74e5 | 1618 | drv_data->ssp = ssp; |
e0c9905e | 1619 | |
21486af0 | 1620 | master->dev.of_node = pdev->dev.of_node; |
e7db06b5 | 1621 | /* the spi->mode bits understood by this driver: */ |
b833172f | 1622 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
e7db06b5 | 1623 | |
851bacf5 | 1624 | master->bus_num = ssp->port_id; |
7ad0ba91 | 1625 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1626 | master->cleanup = cleanup; |
1627 | master->setup = setup; | |
7f86bde9 | 1628 | master->transfer_one_message = pxa2xx_spi_transfer_one_message; |
7d94a505 | 1629 | master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; |
0c27d9cf | 1630 | master->fw_translate_cs = pxa2xx_spi_fw_translate_cs; |
7dd62787 | 1631 | master->auto_runtime_pm = true; |
8c3ad488 | 1632 | master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; |
e0c9905e | 1633 | |
2f1a74e5 | 1634 | drv_data->ssp_type = ssp->type; |
e0c9905e | 1635 | |
2f1a74e5 | 1636 | drv_data->ioaddr = ssp->mmio_base; |
1637 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
2a8626a9 | 1638 | if (pxa25x_ssp_comp(drv_data)) { |
e5262d05 WC |
1639 | switch (drv_data->ssp_type) { |
1640 | case QUARK_X1000_SSP: | |
1641 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); | |
1642 | break; | |
1643 | default: | |
1644 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); | |
1645 | break; | |
1646 | } | |
1647 | ||
e0c9905e SS |
1648 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1649 | drv_data->dma_cr1 = 0; | |
1650 | drv_data->clear_sr = SSSR_ROR; | |
1651 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1652 | } else { | |
24778be2 | 1653 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1654 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1655 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e SS |
1656 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
1657 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1658 | } | |
1659 | ||
49cbb1e0 SAS |
1660 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1661 | drv_data); | |
e0c9905e | 1662 | if (status < 0) { |
65a00a20 | 1663 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1664 | goto out_error_master_alloc; |
1665 | } | |
1666 | ||
1667 | /* Setup DMA if requested */ | |
e0c9905e | 1668 | if (platform_info->enable_dma) { |
cd7bed00 MW |
1669 | status = pxa2xx_spi_dma_setup(drv_data); |
1670 | if (status) { | |
cddb339b | 1671 | dev_dbg(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1672 | platform_info->enable_dma = false; |
b6ced294 JN |
1673 | } else { |
1674 | master->can_dma = pxa2xx_spi_can_dma; | |
e0c9905e | 1675 | } |
e0c9905e SS |
1676 | } |
1677 | ||
1678 | /* Enable SOC clock */ | |
3343b7a6 MW |
1679 | clk_prepare_enable(ssp->clk); |
1680 | ||
0eca7cf2 | 1681 | master->max_speed_hz = clk_get_rate(ssp->clk); |
e0c9905e SS |
1682 | |
1683 | /* Load default SSP configuration */ | |
c039dd27 | 1684 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
e5262d05 WC |
1685 | switch (drv_data->ssp_type) { |
1686 | case QUARK_X1000_SSP: | |
7c7289a4 AS |
1687 | tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) | |
1688 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); | |
c039dd27 | 1689 | pxa2xx_spi_write(drv_data, SSCR1, tmp); |
e5262d05 WC |
1690 | |
1691 | /* using the Motorola SPI protocol and use 8 bit frame */ | |
7c7289a4 AS |
1692 | tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8); |
1693 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
e5262d05 | 1694 | break; |
7c7289a4 AS |
1695 | case CE4100_SSP: |
1696 | tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) | | |
1697 | CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT); | |
1698 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
1699 | tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); | |
1700 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
a2dd8af0 | 1701 | break; |
e5262d05 | 1702 | default: |
c039dd27 JN |
1703 | tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | |
1704 | SSCR1_TxTresh(TX_THRESH_DFLT); | |
1705 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
1706 | tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); | |
1707 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
e5262d05 WC |
1708 | break; |
1709 | } | |
1710 | ||
2a8626a9 | 1711 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1712 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e5262d05 WC |
1713 | |
1714 | if (!is_quark_x1000_ssp(drv_data)) | |
c039dd27 | 1715 | pxa2xx_spi_write(drv_data, SSPSP, 0); |
e0c9905e | 1716 | |
8b136baa JN |
1717 | if (is_lpss_ssp(drv_data)) { |
1718 | lpss_ssp_setup(drv_data); | |
1719 | config = lpss_get_config(drv_data); | |
1720 | if (config->reg_capabilities >= 0) { | |
1721 | tmp = __lpss_ssp_read_priv(drv_data, | |
1722 | config->reg_capabilities); | |
1723 | tmp &= LPSS_CAPS_CS_EN_MASK; | |
1724 | tmp >>= LPSS_CAPS_CS_EN_SHIFT; | |
1725 | platform_info->num_chipselect = ffz(tmp); | |
30f3a6ab MW |
1726 | } else if (config->cs_num) { |
1727 | platform_info->num_chipselect = config->cs_num; | |
8b136baa JN |
1728 | } |
1729 | } | |
1730 | master->num_chipselect = platform_info->num_chipselect; | |
1731 | ||
99f499cd MW |
1732 | count = gpiod_count(&pdev->dev, "cs"); |
1733 | if (count > 0) { | |
1734 | int i; | |
1735 | ||
1736 | master->num_chipselect = max_t(int, count, | |
1737 | master->num_chipselect); | |
1738 | ||
1739 | drv_data->cs_gpiods = devm_kcalloc(&pdev->dev, | |
1740 | master->num_chipselect, sizeof(struct gpio_desc *), | |
1741 | GFP_KERNEL); | |
1742 | if (!drv_data->cs_gpiods) { | |
1743 | status = -ENOMEM; | |
1744 | goto out_error_clock_enabled; | |
1745 | } | |
1746 | ||
1747 | for (i = 0; i < master->num_chipselect; i++) { | |
1748 | struct gpio_desc *gpiod; | |
1749 | ||
1750 | gpiod = devm_gpiod_get_index(dev, "cs", i, | |
1751 | GPIOD_OUT_HIGH); | |
1752 | if (IS_ERR(gpiod)) { | |
1753 | /* Means use native chip select */ | |
1754 | if (PTR_ERR(gpiod) == -ENOENT) | |
1755 | continue; | |
1756 | ||
1757 | status = (int)PTR_ERR(gpiod); | |
1758 | goto out_error_clock_enabled; | |
1759 | } else { | |
1760 | drv_data->cs_gpiods[i] = gpiod; | |
1761 | } | |
1762 | } | |
1763 | } | |
1764 | ||
7f86bde9 MW |
1765 | tasklet_init(&drv_data->pump_transfers, pump_transfers, |
1766 | (unsigned long)drv_data); | |
e0c9905e | 1767 | |
836d1a22 AO |
1768 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1769 | pm_runtime_use_autosuspend(&pdev->dev); | |
1770 | pm_runtime_set_active(&pdev->dev); | |
1771 | pm_runtime_enable(&pdev->dev); | |
1772 | ||
e0c9905e SS |
1773 | /* Register with the SPI framework */ |
1774 | platform_set_drvdata(pdev, drv_data); | |
a807fcd0 | 1775 | status = devm_spi_register_master(&pdev->dev, master); |
e0c9905e SS |
1776 | if (status != 0) { |
1777 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
7f86bde9 | 1778 | goto out_error_clock_enabled; |
e0c9905e SS |
1779 | } |
1780 | ||
1781 | return status; | |
1782 | ||
e0c9905e | 1783 | out_error_clock_enabled: |
3343b7a6 | 1784 | clk_disable_unprepare(ssp->clk); |
cd7bed00 | 1785 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1786 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1787 | |
1788 | out_error_master_alloc: | |
1789 | spi_master_put(master); | |
baffe169 | 1790 | pxa_ssp_free(ssp); |
e0c9905e SS |
1791 | return status; |
1792 | } | |
1793 | ||
1794 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1795 | { | |
1796 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1797 | struct ssp_device *ssp; |
e0c9905e SS |
1798 | |
1799 | if (!drv_data) | |
1800 | return 0; | |
51e911e2 | 1801 | ssp = drv_data->ssp; |
e0c9905e | 1802 | |
7d94a505 MW |
1803 | pm_runtime_get_sync(&pdev->dev); |
1804 | ||
e0c9905e | 1805 | /* Disable the SSP at the peripheral and SOC level */ |
c039dd27 | 1806 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
3343b7a6 | 1807 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1808 | |
1809 | /* Release DMA */ | |
cd7bed00 MW |
1810 | if (drv_data->master_info->enable_dma) |
1811 | pxa2xx_spi_dma_release(drv_data); | |
e0c9905e | 1812 | |
7d94a505 MW |
1813 | pm_runtime_put_noidle(&pdev->dev); |
1814 | pm_runtime_disable(&pdev->dev); | |
1815 | ||
e0c9905e | 1816 | /* Release IRQ */ |
2f1a74e5 | 1817 | free_irq(ssp->irq, drv_data); |
1818 | ||
1819 | /* Release SSP */ | |
baffe169 | 1820 | pxa_ssp_free(ssp); |
e0c9905e | 1821 | |
e0c9905e SS |
1822 | return 0; |
1823 | } | |
1824 | ||
1825 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1826 | { | |
1827 | int status = 0; | |
1828 | ||
1829 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1830 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1831 | } | |
1832 | ||
382cebb0 | 1833 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1834 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1835 | { |
86d2593a | 1836 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1837 | struct ssp_device *ssp = drv_data->ssp; |
bffc967e | 1838 | int status; |
e0c9905e | 1839 | |
7f86bde9 | 1840 | status = spi_master_suspend(drv_data->master); |
e0c9905e SS |
1841 | if (status != 0) |
1842 | return status; | |
c039dd27 | 1843 | pxa2xx_spi_write(drv_data, SSCR0, 0); |
2b9375b9 DB |
1844 | |
1845 | if (!pm_runtime_suspended(dev)) | |
1846 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1847 | |
1848 | return 0; | |
1849 | } | |
1850 | ||
86d2593a | 1851 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1852 | { |
86d2593a | 1853 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1854 | struct ssp_device *ssp = drv_data->ssp; |
bffc967e | 1855 | int status; |
e0c9905e SS |
1856 | |
1857 | /* Enable the SSP clock */ | |
2b9375b9 DB |
1858 | if (!pm_runtime_suspended(dev)) |
1859 | clk_prepare_enable(ssp->clk); | |
e0c9905e | 1860 | |
c50325f7 | 1861 | /* Restore LPSS private register bits */ |
48421adf JN |
1862 | if (is_lpss_ssp(drv_data)) |
1863 | lpss_ssp_setup(drv_data); | |
c50325f7 | 1864 | |
e0c9905e | 1865 | /* Start the queue running */ |
7f86bde9 | 1866 | status = spi_master_resume(drv_data->master); |
e0c9905e | 1867 | if (status != 0) { |
86d2593a | 1868 | dev_err(dev, "problem starting queue (%d)\n", status); |
e0c9905e SS |
1869 | return status; |
1870 | } | |
1871 | ||
1872 | return 0; | |
1873 | } | |
7d94a505 MW |
1874 | #endif |
1875 | ||
ec833050 | 1876 | #ifdef CONFIG_PM |
7d94a505 MW |
1877 | static int pxa2xx_spi_runtime_suspend(struct device *dev) |
1878 | { | |
1879 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1880 | ||
1881 | clk_disable_unprepare(drv_data->ssp->clk); | |
1882 | return 0; | |
1883 | } | |
1884 | ||
1885 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1886 | { | |
1887 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1888 | ||
1889 | clk_prepare_enable(drv_data->ssp->clk); | |
1890 | return 0; | |
1891 | } | |
1892 | #endif | |
86d2593a | 1893 | |
47145210 | 1894 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1895 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1896 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1897 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1898 | }; |
e0c9905e SS |
1899 | |
1900 | static struct platform_driver driver = { | |
1901 | .driver = { | |
86d2593a | 1902 | .name = "pxa2xx-spi", |
86d2593a | 1903 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1904 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
e0c9905e | 1905 | }, |
fbd29a14 | 1906 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1907 | .remove = pxa2xx_spi_remove, |
e0c9905e | 1908 | .shutdown = pxa2xx_spi_shutdown, |
e0c9905e SS |
1909 | }; |
1910 | ||
1911 | static int __init pxa2xx_spi_init(void) | |
1912 | { | |
fbd29a14 | 1913 | return platform_driver_register(&driver); |
e0c9905e | 1914 | } |
5b61a749 | 1915 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
1916 | |
1917 | static void __exit pxa2xx_spi_exit(void) | |
1918 | { | |
1919 | platform_driver_unregister(&driver); | |
1920 | } | |
1921 | module_exit(pxa2xx_spi_exit); |