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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e0c9905e SS |
2 | /* |
3 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
8083d6b8 | 4 | * Copyright (C) 2013, 2021 Intel Corporation |
e0c9905e SS |
5 | */ |
6 | ||
5ce25705 | 7 | #include <linux/acpi.h> |
8b136baa | 8 | #include <linux/bitops.h> |
5ce25705 AS |
9 | #include <linux/clk.h> |
10 | #include <linux/delay.h> | |
e0c9905e | 11 | #include <linux/device.h> |
0e476871 | 12 | #include <linux/dmaengine.h> |
cbfd6a21 | 13 | #include <linux/err.h> |
5ce25705 AS |
14 | #include <linux/errno.h> |
15 | #include <linux/gpio/consumer.h> | |
16 | #include <linux/gpio.h> | |
17 | #include <linux/init.h> | |
e0c9905e | 18 | #include <linux/interrupt.h> |
5ce25705 | 19 | #include <linux/ioport.h> |
9df461ec | 20 | #include <linux/kernel.h> |
5ce25705 | 21 | #include <linux/module.h> |
ae8fbf1d AS |
22 | #include <linux/mod_devicetable.h> |
23 | #include <linux/of.h> | |
34cadd9c | 24 | #include <linux/pci.h> |
e0c9905e | 25 | #include <linux/platform_device.h> |
5ce25705 | 26 | #include <linux/pm_runtime.h> |
f2faa3ec | 27 | #include <linux/property.h> |
5ce25705 | 28 | #include <linux/slab.h> |
0e476871 | 29 | |
8348c259 | 30 | #include <linux/spi/pxa2xx_spi.h> |
e0c9905e | 31 | #include <linux/spi/spi.h> |
e0c9905e | 32 | |
cd7bed00 | 33 | #include "spi-pxa2xx.h" |
e0c9905e SS |
34 | |
35 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 36 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 37 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 38 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e | 39 | |
f1f640a9 VS |
40 | #define TIMOUT_DFLT 1000 |
41 | ||
b97c74bd | 42 | /* |
8083d6b8 AS |
43 | * For testing SSCR1 changes that require SSP restart, basically |
44 | * everything except the service and interrupt enables, the PXA270 developer | |
b97c74bd | 45 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this |
8083d6b8 AS |
46 | * list, but the PXA255 developer manual says all bits without really meaning |
47 | * the service and interrupt enables. | |
b97c74bd NF |
48 | */ |
49 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 50 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
51 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
52 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
53 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
54 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 55 | |
e5262d05 WC |
56 | #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ |
57 | | QUARK_X1000_SSCR1_EFWR \ | |
58 | | QUARK_X1000_SSCR1_RFT \ | |
59 | | QUARK_X1000_SSCR1_TFT \ | |
60 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
61 | ||
7c7289a4 AS |
62 | #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ |
63 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ | |
64 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ | |
65 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
66 | | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \ | |
67 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
68 | ||
624ea72e JN |
69 | #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) |
70 | #define LPSS_CS_CONTROL_SW_MODE BIT(0) | |
71 | #define LPSS_CS_CONTROL_CS_HIGH BIT(1) | |
8b136baa JN |
72 | #define LPSS_CAPS_CS_EN_SHIFT 9 |
73 | #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) | |
a0d2642e | 74 | |
683f65de EG |
75 | #define LPSS_PRIV_CLOCK_GATE 0x38 |
76 | #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3 | |
77 | #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3 | |
78 | ||
dccf7369 JN |
79 | struct lpss_config { |
80 | /* LPSS offset from drv_data->ioaddr */ | |
81 | unsigned offset; | |
82 | /* Register offsets from drv_data->lpss_base or -1 */ | |
83 | int reg_general; | |
84 | int reg_ssp; | |
85 | int reg_cs_ctrl; | |
8b136baa | 86 | int reg_capabilities; |
dccf7369 JN |
87 | /* FIFO thresholds */ |
88 | u32 rx_threshold; | |
89 | u32 tx_threshold_lo; | |
90 | u32 tx_threshold_hi; | |
c1e4a53c MW |
91 | /* Chip select control */ |
92 | unsigned cs_sel_shift; | |
93 | unsigned cs_sel_mask; | |
30f3a6ab | 94 | unsigned cs_num; |
683f65de EG |
95 | /* Quirks */ |
96 | unsigned cs_clk_stays_gated : 1; | |
dccf7369 JN |
97 | }; |
98 | ||
99 | /* Keep these sorted with enum pxa_ssp_type */ | |
100 | static const struct lpss_config lpss_platforms[] = { | |
101 | { /* LPSS_LPT_SSP */ | |
102 | .offset = 0x800, | |
103 | .reg_general = 0x08, | |
104 | .reg_ssp = 0x0c, | |
105 | .reg_cs_ctrl = 0x18, | |
8b136baa | 106 | .reg_capabilities = -1, |
dccf7369 JN |
107 | .rx_threshold = 64, |
108 | .tx_threshold_lo = 160, | |
109 | .tx_threshold_hi = 224, | |
110 | }, | |
111 | { /* LPSS_BYT_SSP */ | |
112 | .offset = 0x400, | |
113 | .reg_general = 0x08, | |
114 | .reg_ssp = 0x0c, | |
115 | .reg_cs_ctrl = 0x18, | |
8b136baa | 116 | .reg_capabilities = -1, |
dccf7369 JN |
117 | .rx_threshold = 64, |
118 | .tx_threshold_lo = 160, | |
119 | .tx_threshold_hi = 224, | |
120 | }, | |
30f3a6ab MW |
121 | { /* LPSS_BSW_SSP */ |
122 | .offset = 0x400, | |
123 | .reg_general = 0x08, | |
124 | .reg_ssp = 0x0c, | |
125 | .reg_cs_ctrl = 0x18, | |
126 | .reg_capabilities = -1, | |
127 | .rx_threshold = 64, | |
128 | .tx_threshold_lo = 160, | |
129 | .tx_threshold_hi = 224, | |
130 | .cs_sel_shift = 2, | |
131 | .cs_sel_mask = 1 << 2, | |
132 | .cs_num = 2, | |
133 | }, | |
34cadd9c JN |
134 | { /* LPSS_SPT_SSP */ |
135 | .offset = 0x200, | |
136 | .reg_general = -1, | |
137 | .reg_ssp = 0x20, | |
138 | .reg_cs_ctrl = 0x24, | |
66ec246e | 139 | .reg_capabilities = -1, |
34cadd9c JN |
140 | .rx_threshold = 1, |
141 | .tx_threshold_lo = 32, | |
142 | .tx_threshold_hi = 56, | |
143 | }, | |
b7c08cf8 JN |
144 | { /* LPSS_BXT_SSP */ |
145 | .offset = 0x200, | |
146 | .reg_general = -1, | |
147 | .reg_ssp = 0x20, | |
148 | .reg_cs_ctrl = 0x24, | |
149 | .reg_capabilities = 0xfc, | |
150 | .rx_threshold = 1, | |
151 | .tx_threshold_lo = 16, | |
152 | .tx_threshold_hi = 48, | |
c1e4a53c MW |
153 | .cs_sel_shift = 8, |
154 | .cs_sel_mask = 3 << 8, | |
6eefaee4 | 155 | .cs_clk_stays_gated = true, |
b7c08cf8 | 156 | }, |
fc0b2acc JN |
157 | { /* LPSS_CNL_SSP */ |
158 | .offset = 0x200, | |
159 | .reg_general = -1, | |
160 | .reg_ssp = 0x20, | |
161 | .reg_cs_ctrl = 0x24, | |
162 | .reg_capabilities = 0xfc, | |
163 | .rx_threshold = 1, | |
164 | .tx_threshold_lo = 32, | |
165 | .tx_threshold_hi = 56, | |
166 | .cs_sel_shift = 8, | |
167 | .cs_sel_mask = 3 << 8, | |
683f65de | 168 | .cs_clk_stays_gated = true, |
fc0b2acc | 169 | }, |
dccf7369 JN |
170 | }; |
171 | ||
172 | static inline const struct lpss_config | |
173 | *lpss_get_config(const struct driver_data *drv_data) | |
174 | { | |
175 | return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; | |
176 | } | |
177 | ||
a0d2642e MW |
178 | static bool is_lpss_ssp(const struct driver_data *drv_data) |
179 | { | |
03fbf488 JN |
180 | switch (drv_data->ssp_type) { |
181 | case LPSS_LPT_SSP: | |
182 | case LPSS_BYT_SSP: | |
30f3a6ab | 183 | case LPSS_BSW_SSP: |
34cadd9c | 184 | case LPSS_SPT_SSP: |
b7c08cf8 | 185 | case LPSS_BXT_SSP: |
fc0b2acc | 186 | case LPSS_CNL_SSP: |
03fbf488 JN |
187 | return true; |
188 | default: | |
189 | return false; | |
190 | } | |
a0d2642e MW |
191 | } |
192 | ||
e5262d05 WC |
193 | static bool is_quark_x1000_ssp(const struct driver_data *drv_data) |
194 | { | |
195 | return drv_data->ssp_type == QUARK_X1000_SSP; | |
196 | } | |
197 | ||
41c98841 AS |
198 | static bool is_mmp2_ssp(const struct driver_data *drv_data) |
199 | { | |
200 | return drv_data->ssp_type == MMP2_SSP; | |
201 | } | |
202 | ||
3fdb59cf AS |
203 | static bool is_mrfld_ssp(const struct driver_data *drv_data) |
204 | { | |
205 | return drv_data->ssp_type == MRFLD_SSP; | |
206 | } | |
207 | ||
1bed378c AS |
208 | static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value) |
209 | { | |
210 | if ((pxa2xx_spi_read(drv_data, reg) & mask) != value) | |
211 | pxa2xx_spi_write(drv_data, reg, value & mask); | |
212 | } | |
213 | ||
4fdb2424 WC |
214 | static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) |
215 | { | |
216 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
217 | case QUARK_X1000_SSP: |
218 | return QUARK_X1000_SSCR1_CHANGE_MASK; | |
7c7289a4 AS |
219 | case CE4100_SSP: |
220 | return CE4100_SSCR1_CHANGE_MASK; | |
4fdb2424 WC |
221 | default: |
222 | return SSCR1_CHANGE_MASK; | |
223 | } | |
224 | } | |
225 | ||
226 | static u32 | |
227 | pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) | |
228 | { | |
229 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
230 | case QUARK_X1000_SSP: |
231 | return RX_THRESH_QUARK_X1000_DFLT; | |
7c7289a4 AS |
232 | case CE4100_SSP: |
233 | return RX_THRESH_CE4100_DFLT; | |
4fdb2424 WC |
234 | default: |
235 | return RX_THRESH_DFLT; | |
236 | } | |
237 | } | |
238 | ||
239 | static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) | |
240 | { | |
4fdb2424 WC |
241 | u32 mask; |
242 | ||
243 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
244 | case QUARK_X1000_SSP: |
245 | mask = QUARK_X1000_SSSR_TFL_MASK; | |
246 | break; | |
7c7289a4 AS |
247 | case CE4100_SSP: |
248 | mask = CE4100_SSSR_TFL_MASK; | |
249 | break; | |
4fdb2424 WC |
250 | default: |
251 | mask = SSSR_TFL_MASK; | |
252 | break; | |
253 | } | |
254 | ||
6d380132 | 255 | return read_SSSR_bits(drv_data, mask) == mask; |
4fdb2424 WC |
256 | } |
257 | ||
258 | static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, | |
259 | u32 *sccr1_reg) | |
260 | { | |
261 | u32 mask; | |
262 | ||
263 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
264 | case QUARK_X1000_SSP: |
265 | mask = QUARK_X1000_SSCR1_RFT; | |
266 | break; | |
7c7289a4 AS |
267 | case CE4100_SSP: |
268 | mask = CE4100_SSCR1_RFT; | |
269 | break; | |
4fdb2424 WC |
270 | default: |
271 | mask = SSCR1_RFT; | |
272 | break; | |
273 | } | |
274 | *sccr1_reg &= ~mask; | |
275 | } | |
276 | ||
277 | static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, | |
278 | u32 *sccr1_reg, u32 threshold) | |
279 | { | |
280 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
281 | case QUARK_X1000_SSP: |
282 | *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); | |
283 | break; | |
7c7289a4 AS |
284 | case CE4100_SSP: |
285 | *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); | |
286 | break; | |
4fdb2424 WC |
287 | default: |
288 | *sccr1_reg |= SSCR1_RxTresh(threshold); | |
289 | break; | |
290 | } | |
291 | } | |
292 | ||
293 | static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, | |
294 | u32 clk_div, u8 bits) | |
295 | { | |
296 | switch (drv_data->ssp_type) { | |
e5262d05 WC |
297 | case QUARK_X1000_SSP: |
298 | return clk_div | |
299 | | QUARK_X1000_SSCR0_Motorola | |
0c8ccd8b | 300 | | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits); |
4fdb2424 WC |
301 | default: |
302 | return clk_div | |
303 | | SSCR0_Motorola | |
304 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | |
4fdb2424 WC |
305 | | (bits > 16 ? SSCR0_EDSS : 0); |
306 | } | |
307 | } | |
308 | ||
a0d2642e MW |
309 | /* |
310 | * Read and write LPSS SSP private registers. Caller must first check that | |
311 | * is_lpss_ssp() returns true before these can be called. | |
312 | */ | |
313 | static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) | |
314 | { | |
315 | WARN_ON(!drv_data->lpss_base); | |
316 | return readl(drv_data->lpss_base + offset); | |
317 | } | |
318 | ||
319 | static void __lpss_ssp_write_priv(struct driver_data *drv_data, | |
320 | unsigned offset, u32 value) | |
321 | { | |
322 | WARN_ON(!drv_data->lpss_base); | |
323 | writel(value, drv_data->lpss_base + offset); | |
324 | } | |
325 | ||
326 | /* | |
327 | * lpss_ssp_setup - perform LPSS SSP specific setup | |
328 | * @drv_data: pointer to the driver private data | |
329 | * | |
330 | * Perform LPSS SSP specific setup. This function must be called first if | |
331 | * one is going to use LPSS SSP private registers. | |
332 | */ | |
333 | static void lpss_ssp_setup(struct driver_data *drv_data) | |
334 | { | |
dccf7369 JN |
335 | const struct lpss_config *config; |
336 | u32 value; | |
a0d2642e | 337 | |
dccf7369 | 338 | config = lpss_get_config(drv_data); |
9e43c9a8 | 339 | drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset; |
a0d2642e MW |
340 | |
341 | /* Enable software chip select control */ | |
0e897218 | 342 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
624ea72e JN |
343 | value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); |
344 | value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; | |
dccf7369 | 345 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
0054e28d MW |
346 | |
347 | /* Enable multiblock DMA transfers */ | |
51eea52d | 348 | if (drv_data->controller_info->enable_dma) { |
dccf7369 | 349 | __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); |
1de70612 | 350 | |
82ba2c2a JN |
351 | if (config->reg_general >= 0) { |
352 | value = __lpss_ssp_read_priv(drv_data, | |
353 | config->reg_general); | |
624ea72e | 354 | value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; |
82ba2c2a JN |
355 | __lpss_ssp_write_priv(drv_data, |
356 | config->reg_general, value); | |
357 | } | |
1de70612 | 358 | } |
a0d2642e MW |
359 | } |
360 | ||
d5898e19 | 361 | static void lpss_ssp_select_cs(struct spi_device *spi, |
c1e4a53c MW |
362 | const struct lpss_config *config) |
363 | { | |
d5898e19 JN |
364 | struct driver_data *drv_data = |
365 | spi_controller_get_devdata(spi->controller); | |
c1e4a53c MW |
366 | u32 value, cs; |
367 | ||
368 | if (!config->cs_sel_mask) | |
369 | return; | |
370 | ||
371 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); | |
372 | ||
d5898e19 | 373 | cs = spi->chip_select; |
c1e4a53c MW |
374 | cs <<= config->cs_sel_shift; |
375 | if (cs != (value & config->cs_sel_mask)) { | |
376 | /* | |
377 | * When switching another chip select output active the | |
378 | * output must be selected first and wait 2 ssp_clk cycles | |
379 | * before changing state to active. Otherwise a short | |
380 | * glitch will occur on the previous chip select since | |
381 | * output select is latched but state control is not. | |
382 | */ | |
383 | value &= ~config->cs_sel_mask; | |
384 | value |= cs; | |
385 | __lpss_ssp_write_priv(drv_data, | |
386 | config->reg_cs_ctrl, value); | |
387 | ndelay(1000000000 / | |
51eea52d | 388 | (drv_data->controller->max_speed_hz / 2)); |
c1e4a53c MW |
389 | } |
390 | } | |
391 | ||
d5898e19 | 392 | static void lpss_ssp_cs_control(struct spi_device *spi, bool enable) |
a0d2642e | 393 | { |
d5898e19 JN |
394 | struct driver_data *drv_data = |
395 | spi_controller_get_devdata(spi->controller); | |
dccf7369 | 396 | const struct lpss_config *config; |
c1e4a53c | 397 | u32 value; |
a0d2642e | 398 | |
dccf7369 JN |
399 | config = lpss_get_config(drv_data); |
400 | ||
c1e4a53c | 401 | if (enable) |
d5898e19 | 402 | lpss_ssp_select_cs(spi, config); |
c1e4a53c | 403 | |
dccf7369 | 404 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
c1e4a53c | 405 | if (enable) |
624ea72e | 406 | value &= ~LPSS_CS_CONTROL_CS_HIGH; |
c1e4a53c | 407 | else |
624ea72e | 408 | value |= LPSS_CS_CONTROL_CS_HIGH; |
dccf7369 | 409 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
683f65de EG |
410 | if (config->cs_clk_stays_gated) { |
411 | u32 clkgate; | |
412 | ||
413 | /* | |
414 | * Changing CS alone when dynamic clock gating is on won't | |
415 | * actually flip CS at that time. This ruins SPI transfers | |
416 | * that specify delays, or have no data. Toggle the clock mode | |
417 | * to force on briefly to poke the CS pin to move. | |
418 | */ | |
419 | clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE); | |
420 | value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) | | |
421 | LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON; | |
422 | ||
423 | __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value); | |
424 | __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate); | |
425 | } | |
a0d2642e MW |
426 | } |
427 | ||
d5898e19 | 428 | static void cs_assert(struct spi_device *spi) |
a7bb3909 | 429 | { |
d5898e19 JN |
430 | struct chip_data *chip = spi_get_ctldata(spi); |
431 | struct driver_data *drv_data = | |
432 | spi_controller_get_devdata(spi->controller); | |
a7bb3909 | 433 | |
2a8626a9 | 434 | if (drv_data->ssp_type == CE4100_SSP) { |
ccd60b20 | 435 | pxa2xx_spi_write(drv_data, SSSR, spi->chip_select); |
2a8626a9 SAS |
436 | return; |
437 | } | |
438 | ||
a7bb3909 EM |
439 | if (chip->cs_control) { |
440 | chip->cs_control(PXA2XX_CS_ASSERT); | |
441 | return; | |
442 | } | |
443 | ||
7566bcc7 | 444 | if (is_lpss_ssp(drv_data)) |
d5898e19 | 445 | lpss_ssp_cs_control(spi, true); |
a7bb3909 EM |
446 | } |
447 | ||
d5898e19 | 448 | static void cs_deassert(struct spi_device *spi) |
a7bb3909 | 449 | { |
d5898e19 JN |
450 | struct chip_data *chip = spi_get_ctldata(spi); |
451 | struct driver_data *drv_data = | |
452 | spi_controller_get_devdata(spi->controller); | |
104e51af | 453 | unsigned long timeout; |
a7bb3909 | 454 | |
2a8626a9 SAS |
455 | if (drv_data->ssp_type == CE4100_SSP) |
456 | return; | |
457 | ||
104e51af JN |
458 | /* Wait until SSP becomes idle before deasserting the CS */ |
459 | timeout = jiffies + msecs_to_jiffies(10); | |
460 | while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && | |
461 | !time_after(jiffies, timeout)) | |
462 | cpu_relax(); | |
463 | ||
a7bb3909 | 464 | if (chip->cs_control) { |
2b2562d3 | 465 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
466 | return; |
467 | } | |
468 | ||
7566bcc7 | 469 | if (is_lpss_ssp(drv_data)) |
d5898e19 JN |
470 | lpss_ssp_cs_control(spi, false); |
471 | } | |
472 | ||
473 | static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level) | |
474 | { | |
475 | if (level) | |
476 | cs_deassert(spi); | |
477 | else | |
478 | cs_assert(spi); | |
a7bb3909 EM |
479 | } |
480 | ||
cd7bed00 | 481 | int pxa2xx_spi_flush(struct driver_data *drv_data) |
e0c9905e SS |
482 | { |
483 | unsigned long limit = loops_per_jiffy << 1; | |
484 | ||
e0c9905e | 485 | do { |
6d380132 | 486 | while (read_SSSR_bits(drv_data, SSSR_RNE)) |
c039dd27 JN |
487 | pxa2xx_spi_read(drv_data, SSDR); |
488 | } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); | |
2a8626a9 | 489 | write_SSSR_CS(drv_data, SSSR_ROR); |
e0c9905e SS |
490 | |
491 | return limit; | |
492 | } | |
493 | ||
29d7e05c LR |
494 | static void pxa2xx_spi_off(struct driver_data *drv_data) |
495 | { | |
41c98841 AS |
496 | /* On MMP, disabling SSE seems to corrupt the Rx FIFO */ |
497 | if (is_mmp2_ssp(drv_data)) | |
29d7e05c LR |
498 | return; |
499 | ||
0c8ccd8b | 500 | pxa_ssp_disable(drv_data->ssp); |
29d7e05c LR |
501 | } |
502 | ||
8d94cc50 | 503 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 504 | { |
9708c121 | 505 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 506 | |
4fdb2424 | 507 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
508 | || (drv_data->tx == drv_data->tx_end)) |
509 | return 0; | |
510 | ||
c039dd27 | 511 | pxa2xx_spi_write(drv_data, SSDR, 0); |
8d94cc50 SS |
512 | drv_data->tx += n_bytes; |
513 | ||
514 | return 1; | |
e0c9905e SS |
515 | } |
516 | ||
8d94cc50 | 517 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 518 | { |
9708c121 | 519 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 520 | |
6d380132 | 521 | while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { |
c039dd27 | 522 | pxa2xx_spi_read(drv_data, SSDR); |
e0c9905e SS |
523 | drv_data->rx += n_bytes; |
524 | } | |
8d94cc50 SS |
525 | |
526 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
527 | } |
528 | ||
8d94cc50 | 529 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 530 | { |
4fdb2424 | 531 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
532 | || (drv_data->tx == drv_data->tx_end)) |
533 | return 0; | |
534 | ||
c039dd27 | 535 | pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); |
8d94cc50 SS |
536 | ++drv_data->tx; |
537 | ||
538 | return 1; | |
e0c9905e SS |
539 | } |
540 | ||
8d94cc50 | 541 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 542 | { |
6d380132 | 543 | while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { |
c039dd27 | 544 | *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); |
e0c9905e SS |
545 | ++drv_data->rx; |
546 | } | |
8d94cc50 SS |
547 | |
548 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
549 | } |
550 | ||
8d94cc50 | 551 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 552 | { |
4fdb2424 | 553 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
554 | || (drv_data->tx == drv_data->tx_end)) |
555 | return 0; | |
556 | ||
c039dd27 | 557 | pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); |
8d94cc50 SS |
558 | drv_data->tx += 2; |
559 | ||
560 | return 1; | |
e0c9905e SS |
561 | } |
562 | ||
8d94cc50 | 563 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 564 | { |
6d380132 | 565 | while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { |
c039dd27 | 566 | *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); |
e0c9905e SS |
567 | drv_data->rx += 2; |
568 | } | |
8d94cc50 SS |
569 | |
570 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 571 | } |
8d94cc50 SS |
572 | |
573 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 574 | { |
4fdb2424 | 575 | if (pxa2xx_spi_txfifo_full(drv_data) |
8d94cc50 SS |
576 | || (drv_data->tx == drv_data->tx_end)) |
577 | return 0; | |
578 | ||
c039dd27 | 579 | pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); |
8d94cc50 SS |
580 | drv_data->tx += 4; |
581 | ||
582 | return 1; | |
e0c9905e SS |
583 | } |
584 | ||
8d94cc50 | 585 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 586 | { |
6d380132 | 587 | while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { |
c039dd27 | 588 | *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); |
e0c9905e SS |
589 | drv_data->rx += 4; |
590 | } | |
8d94cc50 SS |
591 | |
592 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
593 | } |
594 | ||
579d3bb2 SAS |
595 | static void reset_sccr1(struct driver_data *drv_data) |
596 | { | |
e3aa9acc AS |
597 | u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold; |
598 | struct chip_data *chip; | |
599 | ||
600 | if (drv_data->controller->cur_msg) { | |
601 | chip = spi_get_ctldata(drv_data->controller->cur_msg->spi); | |
602 | threshold = chip->threshold; | |
603 | } else { | |
604 | threshold = 0; | |
605 | } | |
579d3bb2 | 606 | |
152bc19e AS |
607 | switch (drv_data->ssp_type) { |
608 | case QUARK_X1000_SSP: | |
e0a6512d | 609 | mask |= QUARK_X1000_SSCR1_RFT; |
152bc19e | 610 | break; |
7c7289a4 | 611 | case CE4100_SSP: |
e0a6512d | 612 | mask |= CE4100_SSCR1_RFT; |
7c7289a4 | 613 | break; |
152bc19e | 614 | default: |
e0a6512d | 615 | mask |= SSCR1_RFT; |
152bc19e AS |
616 | break; |
617 | } | |
e0a6512d | 618 | |
e3aa9acc | 619 | pxa2xx_spi_update(drv_data, SSCR1, mask, threshold); |
579d3bb2 SAS |
620 | } |
621 | ||
ab77fe89 | 622 | static void int_stop_and_reset(struct driver_data *drv_data) |
e0c9905e | 623 | { |
ab77fe89 | 624 | /* Clear and disable interrupts */ |
2a8626a9 | 625 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
579d3bb2 | 626 | reset_sccr1(drv_data); |
ab77fe89 AS |
627 | if (pxa25x_ssp_comp(drv_data)) |
628 | return; | |
629 | ||
630 | pxa2xx_spi_write(drv_data, SSTO, 0); | |
631 | } | |
632 | ||
4761d2e7 | 633 | static void int_error_stop(struct driver_data *drv_data, const char *msg, int err) |
ab77fe89 AS |
634 | { |
635 | int_stop_and_reset(drv_data); | |
cd7bed00 | 636 | pxa2xx_spi_flush(drv_data); |
29d7e05c | 637 | pxa2xx_spi_off(drv_data); |
e0c9905e | 638 | |
c3dce24c | 639 | dev_err(drv_data->ssp->dev, "%s\n", msg); |
e0c9905e | 640 | |
4761d2e7 | 641 | drv_data->controller->cur_msg->status = err; |
51eea52d | 642 | spi_finalize_current_transfer(drv_data->controller); |
8d94cc50 | 643 | } |
5daa3ba0 | 644 | |
8d94cc50 SS |
645 | static void int_transfer_complete(struct driver_data *drv_data) |
646 | { | |
ab77fe89 | 647 | int_stop_and_reset(drv_data); |
e0c9905e | 648 | |
51eea52d | 649 | spi_finalize_current_transfer(drv_data->controller); |
8d94cc50 | 650 | } |
e0c9905e | 651 | |
8d94cc50 SS |
652 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
653 | { | |
6d380132 | 654 | u32 irq_status; |
e0c9905e | 655 | |
6d380132 AS |
656 | irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr); |
657 | if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE)) | |
658 | irq_status &= ~SSSR_TFS; | |
e0c9905e | 659 | |
8d94cc50 | 660 | if (irq_status & SSSR_ROR) { |
8083d6b8 | 661 | int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO); |
8d94cc50 SS |
662 | return IRQ_HANDLED; |
663 | } | |
e0c9905e | 664 | |
ec93cb6f | 665 | if (irq_status & SSSR_TUR) { |
8083d6b8 | 666 | int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO); |
ec93cb6f LR |
667 | return IRQ_HANDLED; |
668 | } | |
669 | ||
8d94cc50 | 670 | if (irq_status & SSSR_TINT) { |
c039dd27 | 671 | pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); |
8d94cc50 SS |
672 | if (drv_data->read(drv_data)) { |
673 | int_transfer_complete(drv_data); | |
674 | return IRQ_HANDLED; | |
675 | } | |
676 | } | |
e0c9905e | 677 | |
8083d6b8 | 678 | /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */ |
8d94cc50 SS |
679 | do { |
680 | if (drv_data->read(drv_data)) { | |
681 | int_transfer_complete(drv_data); | |
682 | return IRQ_HANDLED; | |
683 | } | |
684 | } while (drv_data->write(drv_data)); | |
e0c9905e | 685 | |
8d94cc50 SS |
686 | if (drv_data->read(drv_data)) { |
687 | int_transfer_complete(drv_data); | |
688 | return IRQ_HANDLED; | |
689 | } | |
e0c9905e | 690 | |
8d94cc50 | 691 | if (drv_data->tx == drv_data->tx_end) { |
579d3bb2 SAS |
692 | u32 bytes_left; |
693 | u32 sccr1_reg; | |
694 | ||
c039dd27 | 695 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
579d3bb2 SAS |
696 | sccr1_reg &= ~SSCR1_TIE; |
697 | ||
698 | /* | |
8083d6b8 AS |
699 | * PXA25x_SSP has no timeout, set up Rx threshold for |
700 | * the remaining Rx bytes. | |
579d3bb2 | 701 | */ |
2a8626a9 | 702 | if (pxa25x_ssp_comp(drv_data)) { |
4fdb2424 | 703 | u32 rx_thre; |
579d3bb2 | 704 | |
4fdb2424 | 705 | pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); |
579d3bb2 SAS |
706 | |
707 | bytes_left = drv_data->rx_end - drv_data->rx; | |
708 | switch (drv_data->n_bytes) { | |
709 | case 4: | |
2c183376 GS |
710 | bytes_left >>= 2; |
711 | break; | |
579d3bb2 SAS |
712 | case 2: |
713 | bytes_left >>= 1; | |
2c183376 | 714 | break; |
8d94cc50 | 715 | } |
579d3bb2 | 716 | |
4fdb2424 WC |
717 | rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); |
718 | if (rx_thre > bytes_left) | |
719 | rx_thre = bytes_left; | |
579d3bb2 | 720 | |
4fdb2424 | 721 | pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); |
e0c9905e | 722 | } |
c039dd27 | 723 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); |
e0c9905e SS |
724 | } |
725 | ||
5daa3ba0 SS |
726 | /* We did something */ |
727 | return IRQ_HANDLED; | |
e0c9905e SS |
728 | } |
729 | ||
b0312482 JK |
730 | static void handle_bad_msg(struct driver_data *drv_data) |
731 | { | |
3bbdc083 | 732 | int_stop_and_reset(drv_data); |
29d7e05c | 733 | pxa2xx_spi_off(drv_data); |
b0312482 | 734 | |
c3dce24c | 735 | dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n"); |
b0312482 JK |
736 | } |
737 | ||
7d12e780 | 738 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 739 | { |
c7bec5ab | 740 | struct driver_data *drv_data = dev_id; |
7d94a505 | 741 | u32 sccr1_reg; |
49cbb1e0 SAS |
742 | u32 mask = drv_data->mask_sr; |
743 | u32 status; | |
744 | ||
7d94a505 MW |
745 | /* |
746 | * The IRQ might be shared with other peripherals so we must first | |
747 | * check that are we RPM suspended or not. If we are we assume that | |
748 | * the IRQ was not for us (we shouldn't be RPM suspended when the | |
749 | * interrupt is enabled). | |
750 | */ | |
c3dce24c | 751 | if (pm_runtime_suspended(drv_data->ssp->dev)) |
7d94a505 MW |
752 | return IRQ_NONE; |
753 | ||
269e4a41 MW |
754 | /* |
755 | * If the device is not yet in RPM suspended state and we get an | |
756 | * interrupt that is meant for another device, check if status bits | |
757 | * are all set to one. That means that the device is already | |
758 | * powered off. | |
759 | */ | |
c039dd27 | 760 | status = pxa2xx_spi_read(drv_data, SSSR); |
269e4a41 MW |
761 | if (status == ~0) |
762 | return IRQ_NONE; | |
763 | ||
c039dd27 | 764 | sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); |
49cbb1e0 SAS |
765 | |
766 | /* Ignore possible writes if we don't need to write */ | |
767 | if (!(sccr1_reg & SSCR1_TIE)) | |
768 | mask &= ~SSSR_TFS; | |
769 | ||
02bc933e TJN |
770 | /* Ignore RX timeout interrupt if it is disabled */ |
771 | if (!(sccr1_reg & SSCR1_TINTE)) | |
772 | mask &= ~SSSR_TINT; | |
773 | ||
49cbb1e0 SAS |
774 | if (!(status & mask)) |
775 | return IRQ_NONE; | |
e0c9905e | 776 | |
e51e9b93 JK |
777 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); |
778 | pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); | |
5daa3ba0 | 779 | |
51eea52d | 780 | if (!drv_data->controller->cur_msg) { |
b0312482 | 781 | handle_bad_msg(drv_data); |
e0c9905e SS |
782 | /* Never fail */ |
783 | return IRQ_HANDLED; | |
784 | } | |
785 | ||
786 | return drv_data->transfer_handler(drv_data); | |
787 | } | |
788 | ||
e5262d05 | 789 | /* |
9df461ec AS |
790 | * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply |
791 | * input frequency by fractions of 2^24. It also has a divider by 5. | |
792 | * | |
793 | * There are formulas to get baud rate value for given input frequency and | |
794 | * divider parameters, such as DDS_CLK_RATE and SCR: | |
795 | * | |
796 | * Fsys = 200MHz | |
797 | * | |
798 | * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) | |
799 | * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) | |
800 | * | |
801 | * DDS_CLK_RATE either 2^n or 2^n / 5. | |
802 | * SCR is in range 0 .. 255 | |
803 | * | |
804 | * Divisor = 5^i * 2^j * 2 * k | |
805 | * i = [0, 1] i = 1 iff j = 0 or j > 3 | |
806 | * j = [0, 23] j = 0 iff i = 1 | |
807 | * k = [1, 256] | |
808 | * Special case: j = 0, i = 1: Divisor = 2 / 5 | |
809 | * | |
810 | * Accordingly to the specification the recommended values for DDS_CLK_RATE | |
811 | * are: | |
812 | * Case 1: 2^n, n = [0, 23] | |
813 | * Case 2: 2^24 * 2 / 5 (0x666666) | |
814 | * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) | |
815 | * | |
816 | * In all cases the lowest possible value is better. | |
817 | * | |
818 | * The function calculates parameters for all cases and chooses the one closest | |
819 | * to the asked baud rate. | |
e5262d05 | 820 | */ |
9df461ec AS |
821 | static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) |
822 | { | |
823 | unsigned long xtal = 200000000; | |
824 | unsigned long fref = xtal / 2; /* mandatory division by 2, | |
825 | see (2) */ | |
826 | /* case 3 */ | |
827 | unsigned long fref1 = fref / 2; /* case 1 */ | |
828 | unsigned long fref2 = fref * 2 / 5; /* case 2 */ | |
829 | unsigned long scale; | |
830 | unsigned long q, q1, q2; | |
831 | long r, r1, r2; | |
832 | u32 mul; | |
833 | ||
834 | /* Case 1 */ | |
835 | ||
836 | /* Set initial value for DDS_CLK_RATE */ | |
837 | mul = (1 << 24) >> 1; | |
838 | ||
839 | /* Calculate initial quot */ | |
3ad48062 | 840 | q1 = DIV_ROUND_UP(fref1, rate); |
9df461ec AS |
841 | |
842 | /* Scale q1 if it's too big */ | |
843 | if (q1 > 256) { | |
844 | /* Scale q1 to range [1, 512] */ | |
845 | scale = fls_long(q1 - 1); | |
846 | if (scale > 9) { | |
847 | q1 >>= scale - 9; | |
848 | mul >>= scale - 9; | |
e5262d05 | 849 | } |
9df461ec AS |
850 | |
851 | /* Round the result if we have a remainder */ | |
852 | q1 += q1 & 1; | |
853 | } | |
854 | ||
855 | /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ | |
856 | scale = __ffs(q1); | |
857 | q1 >>= scale; | |
858 | mul >>= scale; | |
859 | ||
860 | /* Get the remainder */ | |
861 | r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); | |
862 | ||
863 | /* Case 2 */ | |
864 | ||
3ad48062 | 865 | q2 = DIV_ROUND_UP(fref2, rate); |
9df461ec AS |
866 | r2 = abs(fref2 / q2 - rate); |
867 | ||
868 | /* | |
869 | * Choose the best between two: less remainder we have the better. We | |
870 | * can't go case 2 if q2 is greater than 256 since SCR register can | |
871 | * hold only values 0 .. 255. | |
872 | */ | |
873 | if (r2 >= r1 || q2 > 256) { | |
874 | /* case 1 is better */ | |
875 | r = r1; | |
876 | q = q1; | |
877 | } else { | |
878 | /* case 2 is better */ | |
879 | r = r2; | |
880 | q = q2; | |
881 | mul = (1 << 24) * 2 / 5; | |
e5262d05 WC |
882 | } |
883 | ||
3ad48062 | 884 | /* Check case 3 only if the divisor is big enough */ |
9df461ec AS |
885 | if (fref / rate >= 80) { |
886 | u64 fssp; | |
887 | u32 m; | |
888 | ||
889 | /* Calculate initial quot */ | |
3ad48062 | 890 | q1 = DIV_ROUND_UP(fref, rate); |
9df461ec AS |
891 | m = (1 << 24) / q1; |
892 | ||
893 | /* Get the remainder */ | |
894 | fssp = (u64)fref * m; | |
895 | do_div(fssp, 1 << 24); | |
896 | r1 = abs(fssp - rate); | |
897 | ||
898 | /* Choose this one if it suits better */ | |
899 | if (r1 < r) { | |
900 | /* case 3 is better */ | |
901 | q = 1; | |
902 | mul = m; | |
903 | } | |
904 | } | |
e5262d05 | 905 | |
9df461ec AS |
906 | *dds = mul; |
907 | return q - 1; | |
e5262d05 WC |
908 | } |
909 | ||
3343b7a6 | 910 | static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) |
2f1a74e5 | 911 | { |
51eea52d | 912 | unsigned long ssp_clk = drv_data->controller->max_speed_hz; |
3343b7a6 MW |
913 | const struct ssp_device *ssp = drv_data->ssp; |
914 | ||
915 | rate = min_t(int, ssp_clk, rate); | |
2f1a74e5 | 916 | |
29f21337 FS |
917 | /* |
918 | * Calculate the divisor for the SCR (Serial Clock Rate), avoiding | |
8083d6b8 | 919 | * that the SSP transmission rate can be greater than the device rate. |
29f21337 | 920 | */ |
2a8626a9 | 921 | if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) |
29f21337 | 922 | return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff; |
2f1a74e5 | 923 | else |
29f21337 | 924 | return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff; |
2f1a74e5 | 925 | } |
926 | ||
e5262d05 | 927 | static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, |
d2c2f6a4 | 928 | int rate) |
e5262d05 | 929 | { |
96579a4e | 930 | struct chip_data *chip = |
51eea52d | 931 | spi_get_ctldata(drv_data->controller->cur_msg->spi); |
025ffe88 | 932 | unsigned int clk_div; |
e5262d05 WC |
933 | |
934 | switch (drv_data->ssp_type) { | |
935 | case QUARK_X1000_SSP: | |
9df461ec | 936 | clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); |
eecacf73 | 937 | break; |
e5262d05 | 938 | default: |
025ffe88 | 939 | clk_div = ssp_get_clk_div(drv_data, rate); |
eecacf73 | 940 | break; |
e5262d05 | 941 | } |
025ffe88 | 942 | return clk_div << 8; |
e5262d05 WC |
943 | } |
944 | ||
51eea52d | 945 | static bool pxa2xx_spi_can_dma(struct spi_controller *controller, |
b6ced294 JN |
946 | struct spi_device *spi, |
947 | struct spi_transfer *xfer) | |
948 | { | |
949 | struct chip_data *chip = spi_get_ctldata(spi); | |
950 | ||
951 | return chip->enable_dma && | |
952 | xfer->len <= MAX_DMA_LEN && | |
953 | xfer->len >= chip->dma_burst_size; | |
954 | } | |
955 | ||
51eea52d | 956 | static int pxa2xx_spi_transfer_one(struct spi_controller *controller, |
71293a60 | 957 | struct spi_device *spi, |
958 | struct spi_transfer *transfer) | |
e0c9905e | 959 | { |
51eea52d LR |
960 | struct driver_data *drv_data = spi_controller_get_devdata(controller); |
961 | struct spi_message *message = controller->cur_msg; | |
20f4c379 | 962 | struct chip_data *chip = spi_get_ctldata(spi); |
96579a4e JN |
963 | u32 dma_thresh = chip->dma_threshold; |
964 | u32 dma_burst = chip->dma_burst_size; | |
965 | u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); | |
bffc967e JN |
966 | u32 clk_div; |
967 | u8 bits; | |
968 | u32 speed; | |
9708c121 | 969 | u32 cr0; |
8d94cc50 | 970 | u32 cr1; |
7d1f1bf6 | 971 | int err; |
b6ced294 | 972 | int dma_mapped; |
e0c9905e | 973 | |
cd7bed00 | 974 | /* Check if we can DMA this transfer */ |
b6ced294 | 975 | if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { |
7e964455 | 976 | |
8083d6b8 | 977 | /* Reject already-mapped transfers; PIO won't always work */ |
7e964455 NF |
978 | if (message->is_dma_mapped |
979 | || transfer->rx_dma || transfer->tx_dma) { | |
748fbadf | 980 | dev_err(&spi->dev, |
8ae55af3 | 981 | "Mapped transfer length of %u is greater than %d\n", |
7e964455 | 982 | transfer->len, MAX_DMA_LEN); |
d5898e19 | 983 | return -EINVAL; |
7e964455 NF |
984 | } |
985 | ||
8083d6b8 | 986 | /* Warn ... we force this to PIO mode */ |
20f4c379 | 987 | dev_warn_ratelimited(&spi->dev, |
684a3ac7 AS |
988 | "DMA disabled for transfer length %u greater than %d\n", |
989 | transfer->len, MAX_DMA_LEN); | |
8d94cc50 SS |
990 | } |
991 | ||
e0c9905e | 992 | /* Setup the transfer state based on the type of transfer */ |
cd7bed00 | 993 | if (pxa2xx_spi_flush(drv_data) == 0) { |
748fbadf | 994 | dev_err(&spi->dev, "Flush failed\n"); |
d5898e19 | 995 | return -EIO; |
e0c9905e | 996 | } |
9708c121 | 997 | drv_data->n_bytes = chip->n_bytes; |
e0c9905e SS |
998 | drv_data->tx = (void *)transfer->tx_buf; |
999 | drv_data->tx_end = drv_data->tx + transfer->len; | |
1000 | drv_data->rx = transfer->rx_buf; | |
1001 | drv_data->rx_end = drv_data->rx + transfer->len; | |
e0c9905e SS |
1002 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
1003 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
1004 | |
1005 | /* Change speed and bit per word on a per transfer */ | |
196b0e2c JN |
1006 | bits = transfer->bits_per_word; |
1007 | speed = transfer->speed_hz; | |
1008 | ||
d2c2f6a4 | 1009 | clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); |
196b0e2c JN |
1010 | |
1011 | if (bits <= 8) { | |
1012 | drv_data->n_bytes = 1; | |
1013 | drv_data->read = drv_data->read != null_reader ? | |
1014 | u8_reader : null_reader; | |
1015 | drv_data->write = drv_data->write != null_writer ? | |
1016 | u8_writer : null_writer; | |
1017 | } else if (bits <= 16) { | |
1018 | drv_data->n_bytes = 2; | |
1019 | drv_data->read = drv_data->read != null_reader ? | |
1020 | u16_reader : null_reader; | |
1021 | drv_data->write = drv_data->write != null_writer ? | |
1022 | u16_writer : null_writer; | |
1023 | } else if (bits <= 32) { | |
1024 | drv_data->n_bytes = 4; | |
1025 | drv_data->read = drv_data->read != null_reader ? | |
1026 | u32_reader : null_reader; | |
1027 | drv_data->write = drv_data->write != null_writer ? | |
1028 | u32_writer : null_writer; | |
9708c121 | 1029 | } |
196b0e2c | 1030 | /* |
8083d6b8 AS |
1031 | * If bits per word is changed in DMA mode, then must check |
1032 | * the thresholds and burst also. | |
196b0e2c JN |
1033 | */ |
1034 | if (chip->enable_dma) { | |
1035 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, | |
20f4c379 | 1036 | spi, |
196b0e2c JN |
1037 | bits, &dma_burst, |
1038 | &dma_thresh)) | |
20f4c379 | 1039 | dev_warn_ratelimited(&spi->dev, |
8ae55af3 | 1040 | "DMA burst size reduced to match bits_per_word\n"); |
9708c121 SS |
1041 | } |
1042 | ||
51eea52d | 1043 | dma_mapped = controller->can_dma && |
20f4c379 | 1044 | controller->can_dma(controller, spi, transfer) && |
51eea52d | 1045 | controller->cur_msg_mapped; |
b6ced294 | 1046 | if (dma_mapped) { |
e0c9905e SS |
1047 | |
1048 | /* Ensure we have the correct interrupt handler */ | |
cd7bed00 MW |
1049 | drv_data->transfer_handler = pxa2xx_spi_dma_transfer; |
1050 | ||
d5898e19 JN |
1051 | err = pxa2xx_spi_dma_prepare(drv_data, transfer); |
1052 | if (err) | |
1053 | return err; | |
e0c9905e | 1054 | |
8d94cc50 SS |
1055 | /* Clear status and start DMA engine */ |
1056 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
c039dd27 | 1057 | pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); |
cd7bed00 MW |
1058 | |
1059 | pxa2xx_spi_dma_start(drv_data); | |
e0c9905e SS |
1060 | } else { |
1061 | /* Ensure we have the correct interrupt handler */ | |
1062 | drv_data->transfer_handler = interrupt_transfer; | |
1063 | ||
8d94cc50 SS |
1064 | /* Clear status */ |
1065 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
2a8626a9 | 1066 | write_SSSR_CS(drv_data, drv_data->clear_sr); |
8d94cc50 SS |
1067 | } |
1068 | ||
ee03672d JN |
1069 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ |
1070 | cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); | |
1071 | if (!pxa25x_ssp_comp(drv_data)) | |
20f4c379 | 1072 | dev_dbg(&spi->dev, "%u Hz actual, %s\n", |
51eea52d | 1073 | controller->max_speed_hz |
ee03672d | 1074 | / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), |
b6ced294 | 1075 | dma_mapped ? "DMA" : "PIO"); |
ee03672d | 1076 | else |
20f4c379 | 1077 | dev_dbg(&spi->dev, "%u Hz actual, %s\n", |
51eea52d | 1078 | controller->max_speed_hz / 2 |
ee03672d | 1079 | / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), |
b6ced294 | 1080 | dma_mapped ? "DMA" : "PIO"); |
ee03672d | 1081 | |
a0d2642e | 1082 | if (is_lpss_ssp(drv_data)) { |
1bed378c AS |
1083 | pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold); |
1084 | pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold); | |
a0d2642e MW |
1085 | } |
1086 | ||
3fdb59cf | 1087 | if (is_mrfld_ssp(drv_data)) { |
70252440 | 1088 | u32 mask = SFIFOTT_RFT | SFIFOTT_TFT; |
3fdb59cf AS |
1089 | u32 thresh = 0; |
1090 | ||
1091 | thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold); | |
1092 | thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold); | |
1093 | ||
70252440 | 1094 | pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh); |
3fdb59cf AS |
1095 | } |
1096 | ||
1bed378c AS |
1097 | if (is_quark_x1000_ssp(drv_data)) |
1098 | pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate); | |
e5262d05 | 1099 | |
0c8ccd8b AS |
1100 | /* Stop the SSP */ |
1101 | if (!is_mmp2_ssp(drv_data)) | |
1102 | pxa_ssp_disable(drv_data->ssp); | |
1103 | ||
1104 | if (!pxa25x_ssp_comp(drv_data)) | |
1105 | pxa2xx_spi_write(drv_data, SSTO, chip->timeout); | |
1106 | ||
8083d6b8 | 1107 | /* First set CR1 without interrupt and service enables */ |
1bed378c AS |
1108 | pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1); |
1109 | ||
8083d6b8 | 1110 | /* See if we need to reload the configuration registers */ |
1bed378c | 1111 | pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0); |
b97c74bd | 1112 | |
0c8ccd8b AS |
1113 | /* Restart the SSP */ |
1114 | pxa_ssp_enable(drv_data->ssp); | |
1115 | ||
41c98841 | 1116 | if (is_mmp2_ssp(drv_data)) { |
6d380132 | 1117 | u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8; |
82391856 LR |
1118 | |
1119 | if (tx_level) { | |
8083d6b8 | 1120 | /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */ |
684a3ac7 | 1121 | dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level); |
82391856 LR |
1122 | if (tx_level > transfer->len) |
1123 | tx_level = transfer->len; | |
1124 | drv_data->tx += tx_level; | |
1125 | } | |
1126 | } | |
1127 | ||
51eea52d | 1128 | if (spi_controller_is_slave(controller)) { |
ec93cb6f LR |
1129 | while (drv_data->write(drv_data)) |
1130 | ; | |
77d33897 LR |
1131 | if (drv_data->gpiod_ready) { |
1132 | gpiod_set_value(drv_data->gpiod_ready, 1); | |
1133 | udelay(1); | |
1134 | gpiod_set_value(drv_data->gpiod_ready, 0); | |
1135 | } | |
ec93cb6f LR |
1136 | } |
1137 | ||
d5898e19 JN |
1138 | /* |
1139 | * Release the data by enabling service requests and interrupts, | |
8083d6b8 | 1140 | * without changing any mode bits. |
d5898e19 | 1141 | */ |
c039dd27 | 1142 | pxa2xx_spi_write(drv_data, SSCR1, cr1); |
d5898e19 JN |
1143 | |
1144 | return 1; | |
e0c9905e SS |
1145 | } |
1146 | ||
51eea52d | 1147 | static int pxa2xx_spi_slave_abort(struct spi_controller *controller) |
ec93cb6f | 1148 | { |
51eea52d | 1149 | struct driver_data *drv_data = spi_controller_get_devdata(controller); |
ec93cb6f | 1150 | |
4761d2e7 | 1151 | int_error_stop(drv_data, "transfer aborted", -EINTR); |
ec93cb6f LR |
1152 | |
1153 | return 0; | |
1154 | } | |
1155 | ||
51eea52d | 1156 | static void pxa2xx_spi_handle_err(struct spi_controller *controller, |
d5898e19 | 1157 | struct spi_message *msg) |
e0c9905e | 1158 | { |
51eea52d | 1159 | struct driver_data *drv_data = spi_controller_get_devdata(controller); |
e0c9905e | 1160 | |
3bbdc083 AS |
1161 | int_stop_and_reset(drv_data); |
1162 | ||
d5898e19 | 1163 | /* Disable the SSP */ |
29d7e05c | 1164 | pxa2xx_spi_off(drv_data); |
e0c9905e | 1165 | |
d5898e19 JN |
1166 | /* |
1167 | * Stop the DMA if running. Note DMA callback handler may have unset | |
1168 | * the dma_running already, which is fine as stopping is not needed | |
1169 | * then but we shouldn't rely this flag for anything else than | |
1170 | * stopping. For instance to differentiate between PIO and DMA | |
1171 | * transfers. | |
1172 | */ | |
1173 | if (atomic_read(&drv_data->dma_running)) | |
1174 | pxa2xx_spi_dma_stop(drv_data); | |
e0c9905e SS |
1175 | } |
1176 | ||
51eea52d | 1177 | static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller) |
7d94a505 | 1178 | { |
51eea52d | 1179 | struct driver_data *drv_data = spi_controller_get_devdata(controller); |
7d94a505 MW |
1180 | |
1181 | /* Disable the SSP now */ | |
29d7e05c | 1182 | pxa2xx_spi_off(drv_data); |
7d94a505 | 1183 | |
7d94a505 MW |
1184 | return 0; |
1185 | } | |
1186 | ||
de6926f3 AS |
1187 | static void cleanup_cs(struct spi_device *spi) |
1188 | { | |
1189 | if (!gpio_is_valid(spi->cs_gpio)) | |
1190 | return; | |
1191 | ||
1192 | gpio_free(spi->cs_gpio); | |
1193 | spi->cs_gpio = -ENOENT; | |
1194 | } | |
1195 | ||
a7bb3909 EM |
1196 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1197 | struct pxa2xx_spi_chip *chip_info) | |
1198 | { | |
de6926f3 | 1199 | struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); |
a7bb3909 | 1200 | |
99f499cd MW |
1201 | if (chip == NULL) |
1202 | return 0; | |
1203 | ||
99f499cd | 1204 | if (chip_info == NULL) |
a7bb3909 EM |
1205 | return 0; |
1206 | ||
de6926f3 AS |
1207 | if (drv_data->ssp_type == CE4100_SSP) |
1208 | return 0; | |
1209 | ||
8083d6b8 AS |
1210 | /* |
1211 | * NOTE: setup() can be called multiple times, possibly with | |
1212 | * different chip_info, release previously requested GPIO. | |
a7bb3909 | 1213 | */ |
de6926f3 | 1214 | cleanup_cs(spi); |
a7bb3909 | 1215 | |
8083d6b8 | 1216 | /* If ->cs_control() is provided, ignore GPIO chip select */ |
a7bb3909 EM |
1217 | if (chip_info->cs_control) { |
1218 | chip->cs_control = chip_info->cs_control; | |
1219 | return 0; | |
1220 | } | |
1221 | ||
1222 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
de6926f3 AS |
1223 | int gpio = chip_info->gpio_cs; |
1224 | int err; | |
1225 | ||
1226 | err = gpio_request(gpio, "SPI_CS"); | |
a7bb3909 | 1227 | if (err) { |
de6926f3 | 1228 | dev_err(&spi->dev, "failed to request chip select GPIO%d\n", gpio); |
a7bb3909 EM |
1229 | return err; |
1230 | } | |
1231 | ||
de6926f3 AS |
1232 | err = gpio_direction_output(gpio, !(spi->mode & SPI_CS_HIGH)); |
1233 | if (err) { | |
1234 | gpio_free(gpio); | |
1235 | return err; | |
1236 | } | |
a7bb3909 | 1237 | |
de6926f3 | 1238 | spi->cs_gpio = gpio; |
a7bb3909 EM |
1239 | } |
1240 | ||
de6926f3 | 1241 | return 0; |
a7bb3909 EM |
1242 | } |
1243 | ||
e0c9905e SS |
1244 | static int setup(struct spi_device *spi) |
1245 | { | |
bffc967e | 1246 | struct pxa2xx_spi_chip *chip_info; |
e0c9905e | 1247 | struct chip_data *chip; |
dccf7369 | 1248 | const struct lpss_config *config; |
3cc7b0e3 JN |
1249 | struct driver_data *drv_data = |
1250 | spi_controller_get_devdata(spi->controller); | |
a0d2642e | 1251 | uint tx_thres, tx_hi_thres, rx_thres; |
2ec6f20b | 1252 | int err; |
a0d2642e | 1253 | |
e5262d05 WC |
1254 | switch (drv_data->ssp_type) { |
1255 | case QUARK_X1000_SSP: | |
1256 | tx_thres = TX_THRESH_QUARK_X1000_DFLT; | |
1257 | tx_hi_thres = 0; | |
1258 | rx_thres = RX_THRESH_QUARK_X1000_DFLT; | |
1259 | break; | |
3fdb59cf AS |
1260 | case MRFLD_SSP: |
1261 | tx_thres = TX_THRESH_MRFLD_DFLT; | |
1262 | tx_hi_thres = 0; | |
1263 | rx_thres = RX_THRESH_MRFLD_DFLT; | |
1264 | break; | |
7c7289a4 AS |
1265 | case CE4100_SSP: |
1266 | tx_thres = TX_THRESH_CE4100_DFLT; | |
1267 | tx_hi_thres = 0; | |
1268 | rx_thres = RX_THRESH_CE4100_DFLT; | |
1269 | break; | |
03fbf488 JN |
1270 | case LPSS_LPT_SSP: |
1271 | case LPSS_BYT_SSP: | |
30f3a6ab | 1272 | case LPSS_BSW_SSP: |
34cadd9c | 1273 | case LPSS_SPT_SSP: |
b7c08cf8 | 1274 | case LPSS_BXT_SSP: |
fc0b2acc | 1275 | case LPSS_CNL_SSP: |
dccf7369 JN |
1276 | config = lpss_get_config(drv_data); |
1277 | tx_thres = config->tx_threshold_lo; | |
1278 | tx_hi_thres = config->tx_threshold_hi; | |
1279 | rx_thres = config->rx_threshold; | |
e5262d05 WC |
1280 | break; |
1281 | default: | |
a0d2642e | 1282 | tx_hi_thres = 0; |
51eea52d | 1283 | if (spi_controller_is_slave(drv_data->controller)) { |
ec93cb6f LR |
1284 | tx_thres = 1; |
1285 | rx_thres = 2; | |
1286 | } else { | |
1287 | tx_thres = TX_THRESH_DFLT; | |
1288 | rx_thres = RX_THRESH_DFLT; | |
1289 | } | |
e5262d05 | 1290 | break; |
a0d2642e | 1291 | } |
e0c9905e | 1292 | |
8083d6b8 | 1293 | /* Only allocate on the first setup */ |
e0c9905e | 1294 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1295 | if (!chip) { |
e0c9905e | 1296 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
9deae459 | 1297 | if (!chip) |
e0c9905e SS |
1298 | return -ENOMEM; |
1299 | ||
2a8626a9 SAS |
1300 | if (drv_data->ssp_type == CE4100_SSP) { |
1301 | if (spi->chip_select > 4) { | |
f6bd03a7 JN |
1302 | dev_err(&spi->dev, |
1303 | "failed setup: cs number must not be > 4.\n"); | |
2a8626a9 SAS |
1304 | kfree(chip); |
1305 | return -EINVAL; | |
1306 | } | |
c18d925f | 1307 | } |
51eea52d | 1308 | chip->enable_dma = drv_data->controller_info->enable_dma; |
f1f640a9 | 1309 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1310 | } |
1311 | ||
8083d6b8 AS |
1312 | /* |
1313 | * Protocol drivers may change the chip settings, so... | |
1314 | * if chip_info exists, use it. | |
1315 | */ | |
8d94cc50 SS |
1316 | chip_info = spi->controller_data; |
1317 | ||
e0c9905e | 1318 | /* chip_info isn't always needed */ |
8d94cc50 | 1319 | chip->cr1 = 0; |
e0c9905e | 1320 | if (chip_info) { |
f1f640a9 VS |
1321 | if (chip_info->timeout) |
1322 | chip->timeout = chip_info->timeout; | |
1323 | if (chip_info->tx_threshold) | |
1324 | tx_thres = chip_info->tx_threshold; | |
a0d2642e MW |
1325 | if (chip_info->tx_hi_threshold) |
1326 | tx_hi_thres = chip_info->tx_hi_threshold; | |
f1f640a9 VS |
1327 | if (chip_info->rx_threshold) |
1328 | rx_thres = chip_info->rx_threshold; | |
e0c9905e | 1329 | chip->dma_threshold = 0; |
e0c9905e SS |
1330 | if (chip_info->enable_loopback) |
1331 | chip->cr1 = SSCR1_LBM; | |
1332 | } | |
51eea52d | 1333 | if (spi_controller_is_slave(drv_data->controller)) { |
ec93cb6f LR |
1334 | chip->cr1 |= SSCR1_SCFR; |
1335 | chip->cr1 |= SSCR1_SCLKDIR; | |
1336 | chip->cr1 |= SSCR1_SFRMDIR; | |
1337 | chip->cr1 |= SSCR1_SPH; | |
1338 | } | |
e0c9905e | 1339 | |
3fdb59cf AS |
1340 | if (is_lpss_ssp(drv_data)) { |
1341 | chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); | |
1342 | chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | | |
1343 | SSITF_TxHiThresh(tx_hi_thres); | |
1344 | } | |
1345 | ||
1346 | if (is_mrfld_ssp(drv_data)) { | |
1347 | chip->lpss_rx_threshold = rx_thres; | |
1348 | chip->lpss_tx_threshold = tx_thres; | |
1349 | } | |
a0d2642e | 1350 | |
8083d6b8 AS |
1351 | /* |
1352 | * Set DMA burst and threshold outside of chip_info path so that if | |
1353 | * chip_info goes away after setting chip->enable_dma, the burst and | |
1354 | * threshold can still respond to changes in bits_per_word. | |
1355 | */ | |
8d94cc50 | 1356 | if (chip->enable_dma) { |
8083d6b8 | 1357 | /* Set up legal burst and threshold for DMA */ |
cd7bed00 MW |
1358 | if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, |
1359 | spi->bits_per_word, | |
8d94cc50 SS |
1360 | &chip->dma_burst_size, |
1361 | &chip->dma_threshold)) { | |
f6bd03a7 JN |
1362 | dev_warn(&spi->dev, |
1363 | "in setup: DMA burst size reduced to match bits_per_word\n"); | |
8d94cc50 | 1364 | } |
000c6af4 AS |
1365 | dev_dbg(&spi->dev, |
1366 | "in setup: DMA burst size set to %u\n", | |
1367 | chip->dma_burst_size); | |
8d94cc50 SS |
1368 | } |
1369 | ||
e5262d05 WC |
1370 | switch (drv_data->ssp_type) { |
1371 | case QUARK_X1000_SSP: | |
1372 | chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) | |
1373 | & QUARK_X1000_SSCR1_RFT) | |
1374 | | (QUARK_X1000_SSCR1_TxTresh(tx_thres) | |
1375 | & QUARK_X1000_SSCR1_TFT); | |
1376 | break; | |
7c7289a4 AS |
1377 | case CE4100_SSP: |
1378 | chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | | |
1379 | (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT); | |
1380 | break; | |
e5262d05 WC |
1381 | default: |
1382 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | | |
1383 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1384 | break; | |
1385 | } | |
1386 | ||
7f6ee1ad | 1387 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
eb743ec6 AS |
1388 | chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) | |
1389 | ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0); | |
e0c9905e | 1390 | |
b833172f MW |
1391 | if (spi->mode & SPI_LOOP) |
1392 | chip->cr1 |= SSCR1_LBM; | |
1393 | ||
e0c9905e SS |
1394 | if (spi->bits_per_word <= 8) { |
1395 | chip->n_bytes = 1; | |
e0c9905e SS |
1396 | chip->read = u8_reader; |
1397 | chip->write = u8_writer; | |
1398 | } else if (spi->bits_per_word <= 16) { | |
1399 | chip->n_bytes = 2; | |
e0c9905e SS |
1400 | chip->read = u16_reader; |
1401 | chip->write = u16_writer; | |
1402 | } else if (spi->bits_per_word <= 32) { | |
e0c9905e | 1403 | chip->n_bytes = 4; |
e0c9905e SS |
1404 | chip->read = u32_reader; |
1405 | chip->write = u32_writer; | |
e0c9905e SS |
1406 | } |
1407 | ||
1408 | spi_set_ctldata(spi, chip); | |
1409 | ||
2a8626a9 SAS |
1410 | if (drv_data->ssp_type == CE4100_SSP) |
1411 | return 0; | |
1412 | ||
2ec6f20b LW |
1413 | err = setup_cs(spi, chip, chip_info); |
1414 | if (err) | |
1415 | kfree(chip); | |
1416 | ||
1417 | return err; | |
e0c9905e SS |
1418 | } |
1419 | ||
0ffa0285 | 1420 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1421 | { |
0ffa0285 | 1422 | struct chip_data *chip = spi_get_ctldata(spi); |
a7bb3909 | 1423 | |
de6926f3 | 1424 | cleanup_cs(spi); |
e0c9905e SS |
1425 | kfree(chip); |
1426 | } | |
1427 | ||
9b2d6119 | 1428 | #ifdef CONFIG_ACPI |
8422ddf7 | 1429 | static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { |
03fbf488 JN |
1430 | { "INT33C0", LPSS_LPT_SSP }, |
1431 | { "INT33C1", LPSS_LPT_SSP }, | |
1432 | { "INT3430", LPSS_LPT_SSP }, | |
1433 | { "INT3431", LPSS_LPT_SSP }, | |
1434 | { "80860F0E", LPSS_BYT_SSP }, | |
30f3a6ab | 1435 | { "8086228E", LPSS_BSW_SSP }, |
03fbf488 JN |
1436 | { }, |
1437 | }; | |
1438 | MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); | |
9b2d6119 | 1439 | #endif |
03fbf488 | 1440 | |
34cadd9c JN |
1441 | /* |
1442 | * PCI IDs of compound devices that integrate both host controller and private | |
1443 | * integrated DMA engine. Please note these are not used in module | |
1444 | * autoloading and probing in this module but matching the LPSS SSP type. | |
1445 | */ | |
1446 | static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { | |
1447 | /* SPT-LP */ | |
1448 | { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, | |
1449 | { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, | |
1450 | /* SPT-H */ | |
1451 | { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, | |
1452 | { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, | |
704d2b07 MW |
1453 | /* KBL-H */ |
1454 | { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP }, | |
1455 | { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP }, | |
6157d4c2 JN |
1456 | /* CML-V */ |
1457 | { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP }, | |
1458 | { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP }, | |
c1b03f11 | 1459 | /* BXT A-Step */ |
b7c08cf8 JN |
1460 | { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, |
1461 | { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, | |
1462 | { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, | |
c1b03f11 JN |
1463 | /* BXT B-Step */ |
1464 | { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, | |
1465 | { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, | |
1466 | { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, | |
e18a80ac DB |
1467 | /* GLK */ |
1468 | { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP }, | |
1469 | { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP }, | |
1470 | { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP }, | |
22d71a50 MW |
1471 | /* ICL-LP */ |
1472 | { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP }, | |
1473 | { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP }, | |
1474 | { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP }, | |
8cc77204 JN |
1475 | /* EHL */ |
1476 | { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP }, | |
1477 | { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP }, | |
1478 | { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP }, | |
9c7315c9 JN |
1479 | /* JSL */ |
1480 | { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP }, | |
1481 | { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP }, | |
1482 | { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP }, | |
cf961fce JN |
1483 | /* TGL-H */ |
1484 | { PCI_VDEVICE(INTEL, 0x43aa), LPSS_CNL_SSP }, | |
1485 | { PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP }, | |
1486 | { PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP }, | |
1487 | { PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP }, | |
a402e397 JN |
1488 | /* ADL-P */ |
1489 | { PCI_VDEVICE(INTEL, 0x51aa), LPSS_CNL_SSP }, | |
1490 | { PCI_VDEVICE(INTEL, 0x51ab), LPSS_CNL_SSP }, | |
1491 | { PCI_VDEVICE(INTEL, 0x51fb), LPSS_CNL_SSP }, | |
8c4ffe4d JN |
1492 | /* ADL-M */ |
1493 | { PCI_VDEVICE(INTEL, 0x54aa), LPSS_CNL_SSP }, | |
1494 | { PCI_VDEVICE(INTEL, 0x54ab), LPSS_CNL_SSP }, | |
1495 | { PCI_VDEVICE(INTEL, 0x54fb), LPSS_CNL_SSP }, | |
b7c08cf8 JN |
1496 | /* APL */ |
1497 | { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, | |
1498 | { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, | |
1499 | { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, | |
b8450e01 JN |
1500 | /* ADL-S */ |
1501 | { PCI_VDEVICE(INTEL, 0x7aaa), LPSS_CNL_SSP }, | |
1502 | { PCI_VDEVICE(INTEL, 0x7aab), LPSS_CNL_SSP }, | |
1503 | { PCI_VDEVICE(INTEL, 0x7af9), LPSS_CNL_SSP }, | |
1504 | { PCI_VDEVICE(INTEL, 0x7afb), LPSS_CNL_SSP }, | |
fc0b2acc JN |
1505 | /* CNL-LP */ |
1506 | { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP }, | |
1507 | { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP }, | |
1508 | { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP }, | |
1509 | /* CNL-H */ | |
1510 | { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP }, | |
1511 | { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP }, | |
1512 | { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP }, | |
41a91802 EG |
1513 | /* CML-LP */ |
1514 | { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP }, | |
1515 | { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP }, | |
1516 | { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP }, | |
f0cf17ed JN |
1517 | /* CML-H */ |
1518 | { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP }, | |
1519 | { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP }, | |
1520 | { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP }, | |
a4127952 JN |
1521 | /* TGL-LP */ |
1522 | { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP }, | |
1523 | { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP }, | |
1524 | { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP }, | |
1525 | { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP }, | |
1526 | { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP }, | |
1527 | { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP }, | |
1528 | { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP }, | |
94e5c23d | 1529 | { }, |
34cadd9c JN |
1530 | }; |
1531 | ||
87ae1d2d LR |
1532 | static const struct of_device_id pxa2xx_spi_of_match[] = { |
1533 | { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP }, | |
1534 | {}, | |
1535 | }; | |
1536 | MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match); | |
1537 | ||
1538 | #ifdef CONFIG_ACPI | |
1539 | ||
365e856e | 1540 | static int pxa2xx_spi_get_port_id(struct device *dev) |
87ae1d2d | 1541 | { |
365e856e | 1542 | struct acpi_device *adev; |
87ae1d2d LR |
1543 | unsigned int devid; |
1544 | int port_id = -1; | |
1545 | ||
365e856e | 1546 | adev = ACPI_COMPANION(dev); |
87ae1d2d LR |
1547 | if (adev && adev->pnp.unique_id && |
1548 | !kstrtouint(adev->pnp.unique_id, 0, &devid)) | |
1549 | port_id = devid; | |
1550 | return port_id; | |
1551 | } | |
1552 | ||
1553 | #else /* !CONFIG_ACPI */ | |
1554 | ||
365e856e | 1555 | static int pxa2xx_spi_get_port_id(struct device *dev) |
87ae1d2d LR |
1556 | { |
1557 | return -1; | |
1558 | } | |
1559 | ||
1560 | #endif /* CONFIG_ACPI */ | |
1561 | ||
1562 | ||
1563 | #ifdef CONFIG_PCI | |
1564 | ||
34cadd9c JN |
1565 | static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) |
1566 | { | |
5ba846b1 | 1567 | return param == chan->device->dev; |
34cadd9c JN |
1568 | } |
1569 | ||
87ae1d2d LR |
1570 | #endif /* CONFIG_PCI */ |
1571 | ||
51eea52d | 1572 | static struct pxa2xx_spi_controller * |
0db64215 | 1573 | pxa2xx_spi_init_pdata(struct platform_device *pdev) |
a3496855 | 1574 | { |
51eea52d | 1575 | struct pxa2xx_spi_controller *pdata; |
a3496855 MW |
1576 | struct ssp_device *ssp; |
1577 | struct resource *res; | |
6fb7427d AS |
1578 | struct device *parent = pdev->dev.parent; |
1579 | struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL; | |
34cadd9c | 1580 | const struct pci_device_id *pcidev_id = NULL; |
55ef8262 | 1581 | enum pxa_ssp_type type; |
f2faa3ec | 1582 | const void *match; |
a3496855 | 1583 | |
6fb7427d AS |
1584 | if (pcidev) |
1585 | pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev); | |
34cadd9c | 1586 | |
f2faa3ec AS |
1587 | match = device_get_match_data(&pdev->dev); |
1588 | if (match) | |
1589 | type = (enum pxa_ssp_type)match; | |
34cadd9c | 1590 | else if (pcidev_id) |
55ef8262 | 1591 | type = (enum pxa_ssp_type)pcidev_id->driver_data; |
03fbf488 | 1592 | else |
14af1df3 | 1593 | return ERR_PTR(-EINVAL); |
03fbf488 | 1594 | |
cc0ee987 | 1595 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
9deae459 | 1596 | if (!pdata) |
14af1df3 | 1597 | return ERR_PTR(-ENOMEM); |
a3496855 | 1598 | |
a3496855 MW |
1599 | ssp = &pdata->ssp; |
1600 | ||
77c544d2 | 1601 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
cbfd6a21 SK |
1602 | ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); |
1603 | if (IS_ERR(ssp->mmio_base)) | |
14af1df3 | 1604 | return ERR_CAST(ssp->mmio_base); |
a3496855 | 1605 | |
77c544d2 AS |
1606 | ssp->phys_base = res->start; |
1607 | ||
87ae1d2d | 1608 | #ifdef CONFIG_PCI |
34cadd9c | 1609 | if (pcidev_id) { |
6fb7427d AS |
1610 | pdata->tx_param = parent; |
1611 | pdata->rx_param = parent; | |
34cadd9c JN |
1612 | pdata->dma_filter = pxa2xx_spi_idma_filter; |
1613 | } | |
87ae1d2d | 1614 | #endif |
34cadd9c | 1615 | |
a3496855 | 1616 | ssp->clk = devm_clk_get(&pdev->dev, NULL); |
5eb263ef | 1617 | if (IS_ERR(ssp->clk)) |
14af1df3 | 1618 | return ERR_CAST(ssp->clk); |
5eb263ef | 1619 | |
a3496855 | 1620 | ssp->irq = platform_get_irq(pdev, 0); |
5eb263ef | 1621 | if (ssp->irq < 0) |
14af1df3 | 1622 | return ERR_PTR(ssp->irq); |
5eb263ef | 1623 | |
03fbf488 | 1624 | ssp->type = type; |
4f3d9577 | 1625 | ssp->dev = &pdev->dev; |
365e856e | 1626 | ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev); |
a3496855 | 1627 | |
f2faa3ec | 1628 | pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave"); |
a3496855 | 1629 | pdata->num_chipselect = 1; |
cddb339b | 1630 | pdata->enable_dma = true; |
37821a82 | 1631 | pdata->dma_burst_size = 1; |
a3496855 MW |
1632 | |
1633 | return pdata; | |
1634 | } | |
1635 | ||
51eea52d | 1636 | static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller, |
3cc7b0e3 | 1637 | unsigned int cs) |
0c27d9cf | 1638 | { |
51eea52d | 1639 | struct driver_data *drv_data = spi_controller_get_devdata(controller); |
0c27d9cf | 1640 | |
c3dce24c | 1641 | if (has_acpi_companion(drv_data->ssp->dev)) { |
0c27d9cf MW |
1642 | switch (drv_data->ssp_type) { |
1643 | /* | |
1644 | * For Atoms the ACPI DeviceSelection used by the Windows | |
1645 | * driver starts from 1 instead of 0 so translate it here | |
1646 | * to match what Linux expects. | |
1647 | */ | |
1648 | case LPSS_BYT_SSP: | |
30f3a6ab | 1649 | case LPSS_BSW_SSP: |
0c27d9cf MW |
1650 | return cs - 1; |
1651 | ||
1652 | default: | |
1653 | break; | |
1654 | } | |
1655 | } | |
1656 | ||
1657 | return cs; | |
1658 | } | |
1659 | ||
b2662a16 DV |
1660 | static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi) |
1661 | { | |
1662 | return MAX_DMA_LEN; | |
1663 | } | |
1664 | ||
fd4a319b | 1665 | static int pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1666 | { |
1667 | struct device *dev = &pdev->dev; | |
51eea52d LR |
1668 | struct pxa2xx_spi_controller *platform_info; |
1669 | struct spi_controller *controller; | |
65a00a20 | 1670 | struct driver_data *drv_data; |
2f1a74e5 | 1671 | struct ssp_device *ssp; |
8b136baa | 1672 | const struct lpss_config *config; |
778c12e6 | 1673 | int status; |
c039dd27 | 1674 | u32 tmp; |
e0c9905e | 1675 | |
851bacf5 MW |
1676 | platform_info = dev_get_platdata(dev); |
1677 | if (!platform_info) { | |
0db64215 | 1678 | platform_info = pxa2xx_spi_init_pdata(pdev); |
14af1df3 | 1679 | if (IS_ERR(platform_info)) { |
a3496855 | 1680 | dev_err(&pdev->dev, "missing platform data\n"); |
14af1df3 | 1681 | return PTR_ERR(platform_info); |
a3496855 | 1682 | } |
851bacf5 | 1683 | } |
e0c9905e | 1684 | |
baffe169 | 1685 | ssp = pxa_ssp_request(pdev->id, pdev->name); |
851bacf5 MW |
1686 | if (!ssp) |
1687 | ssp = &platform_info->ssp; | |
1688 | ||
1689 | if (!ssp->mmio_base) { | |
8083d6b8 | 1690 | dev_err(&pdev->dev, "failed to get SSP\n"); |
e0c9905e SS |
1691 | return -ENODEV; |
1692 | } | |
1693 | ||
ec93cb6f | 1694 | if (platform_info->is_slave) |
5626308b | 1695 | controller = devm_spi_alloc_slave(dev, sizeof(*drv_data)); |
ec93cb6f | 1696 | else |
5626308b | 1697 | controller = devm_spi_alloc_master(dev, sizeof(*drv_data)); |
ec93cb6f | 1698 | |
51eea52d LR |
1699 | if (!controller) { |
1700 | dev_err(&pdev->dev, "cannot alloc spi_controller\n"); | |
f2eed8ca AS |
1701 | status = -ENOMEM; |
1702 | goto out_error_controller_alloc; | |
e0c9905e | 1703 | } |
51eea52d LR |
1704 | drv_data = spi_controller_get_devdata(controller); |
1705 | drv_data->controller = controller; | |
1706 | drv_data->controller_info = platform_info; | |
2f1a74e5 | 1707 | drv_data->ssp = ssp; |
e0c9905e | 1708 | |
94acf807 AS |
1709 | controller->dev.of_node = dev->of_node; |
1710 | controller->dev.fwnode = dev->fwnode; | |
1711 | ||
8083d6b8 | 1712 | /* The spi->mode bits understood by this driver: */ |
51eea52d LR |
1713 | controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
1714 | ||
1715 | controller->bus_num = ssp->port_id; | |
1716 | controller->dma_alignment = DMA_ALIGNMENT; | |
1717 | controller->cleanup = cleanup; | |
1718 | controller->setup = setup; | |
1719 | controller->set_cs = pxa2xx_spi_set_cs; | |
1720 | controller->transfer_one = pxa2xx_spi_transfer_one; | |
1721 | controller->slave_abort = pxa2xx_spi_slave_abort; | |
1722 | controller->handle_err = pxa2xx_spi_handle_err; | |
1723 | controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; | |
1724 | controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs; | |
1725 | controller->auto_runtime_pm = true; | |
1726 | controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; | |
e0c9905e | 1727 | |
2f1a74e5 | 1728 | drv_data->ssp_type = ssp->type; |
e0c9905e | 1729 | |
2a8626a9 | 1730 | if (pxa25x_ssp_comp(drv_data)) { |
e5262d05 WC |
1731 | switch (drv_data->ssp_type) { |
1732 | case QUARK_X1000_SSP: | |
51eea52d | 1733 | controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e5262d05 WC |
1734 | break; |
1735 | default: | |
51eea52d | 1736 | controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
e5262d05 WC |
1737 | break; |
1738 | } | |
1739 | ||
e0c9905e SS |
1740 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1741 | drv_data->dma_cr1 = 0; | |
1742 | drv_data->clear_sr = SSSR_ROR; | |
1743 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1744 | } else { | |
51eea52d | 1745 | controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
e0c9905e | 1746 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; |
5928808e | 1747 | drv_data->dma_cr1 = DEFAULT_DMA_CR1; |
e0c9905e | 1748 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; |
ec93cb6f LR |
1749 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS |
1750 | | SSSR_ROR | SSSR_TUR; | |
e0c9905e SS |
1751 | } |
1752 | ||
49cbb1e0 SAS |
1753 | status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), |
1754 | drv_data); | |
e0c9905e | 1755 | if (status < 0) { |
65a00a20 | 1756 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
51eea52d | 1757 | goto out_error_controller_alloc; |
e0c9905e SS |
1758 | } |
1759 | ||
1760 | /* Setup DMA if requested */ | |
e0c9905e | 1761 | if (platform_info->enable_dma) { |
cd7bed00 MW |
1762 | status = pxa2xx_spi_dma_setup(drv_data); |
1763 | if (status) { | |
8b57b11b | 1764 | dev_warn(dev, "no DMA channels available, using PIO\n"); |
cd7bed00 | 1765 | platform_info->enable_dma = false; |
b6ced294 | 1766 | } else { |
51eea52d | 1767 | controller->can_dma = pxa2xx_spi_can_dma; |
bf9f742c | 1768 | controller->max_dma_len = MAX_DMA_LEN; |
b2662a16 DV |
1769 | controller->max_transfer_size = |
1770 | pxa2xx_spi_max_dma_transfer_size; | |
e0c9905e | 1771 | } |
e0c9905e SS |
1772 | } |
1773 | ||
1774 | /* Enable SOC clock */ | |
62bbc864 TJ |
1775 | status = clk_prepare_enable(ssp->clk); |
1776 | if (status) | |
1777 | goto out_error_dma_irq_alloc; | |
3343b7a6 | 1778 | |
51eea52d | 1779 | controller->max_speed_hz = clk_get_rate(ssp->clk); |
23cdddb2 JN |
1780 | /* |
1781 | * Set minimum speed for all other platforms than Intel Quark which is | |
1782 | * able do under 1 Hz transfers. | |
1783 | */ | |
1784 | if (!pxa25x_ssp_comp(drv_data)) | |
1785 | controller->min_speed_hz = | |
1786 | DIV_ROUND_UP(controller->max_speed_hz, 4096); | |
1787 | else if (!is_quark_x1000_ssp(drv_data)) | |
1788 | controller->min_speed_hz = | |
1789 | DIV_ROUND_UP(controller->max_speed_hz, 512); | |
e0c9905e | 1790 | |
0c8ccd8b AS |
1791 | pxa_ssp_disable(ssp); |
1792 | ||
e0c9905e | 1793 | /* Load default SSP configuration */ |
e5262d05 WC |
1794 | switch (drv_data->ssp_type) { |
1795 | case QUARK_X1000_SSP: | |
7c7289a4 AS |
1796 | tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) | |
1797 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); | |
c039dd27 | 1798 | pxa2xx_spi_write(drv_data, SSCR1, tmp); |
e5262d05 | 1799 | |
8083d6b8 | 1800 | /* Using the Motorola SPI protocol and use 8 bit frame */ |
7c7289a4 AS |
1801 | tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8); |
1802 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
e5262d05 | 1803 | break; |
7c7289a4 AS |
1804 | case CE4100_SSP: |
1805 | tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) | | |
1806 | CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT); | |
1807 | pxa2xx_spi_write(drv_data, SSCR1, tmp); | |
1808 | tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); | |
1809 | pxa2xx_spi_write(drv_data, SSCR0, tmp); | |
a2dd8af0 | 1810 | break; |
e5262d05 | 1811 | default: |
ec93cb6f | 1812 | |
51eea52d | 1813 | if (spi_controller_is_slave(controller)) { |
ec93cb6f LR |
1814 | tmp = SSCR1_SCFR | |
1815 | SSCR1_SCLKDIR | | |
1816 | SSCR1_SFRMDIR | | |
1817 | SSCR1_RxTresh(2) | | |
1818 | SSCR1_TxTresh(1) | | |
1819 | SSCR1_SPH; | |
1820 | } else { | |
1821 | tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | | |
1822 | SSCR1_TxTresh(TX_THRESH_DFLT); | |
1823 | } | |
c039dd27 | 1824 | pxa2xx_spi_write(drv_data, SSCR1, tmp); |
ec93cb6f | 1825 | tmp = SSCR0_Motorola | SSCR0_DataSize(8); |
51eea52d | 1826 | if (!spi_controller_is_slave(controller)) |
ec93cb6f | 1827 | tmp |= SSCR0_SCR(2); |
c039dd27 | 1828 | pxa2xx_spi_write(drv_data, SSCR0, tmp); |
e5262d05 WC |
1829 | break; |
1830 | } | |
1831 | ||
2a8626a9 | 1832 | if (!pxa25x_ssp_comp(drv_data)) |
c039dd27 | 1833 | pxa2xx_spi_write(drv_data, SSTO, 0); |
e5262d05 WC |
1834 | |
1835 | if (!is_quark_x1000_ssp(drv_data)) | |
c039dd27 | 1836 | pxa2xx_spi_write(drv_data, SSPSP, 0); |
e0c9905e | 1837 | |
8b136baa JN |
1838 | if (is_lpss_ssp(drv_data)) { |
1839 | lpss_ssp_setup(drv_data); | |
1840 | config = lpss_get_config(drv_data); | |
1841 | if (config->reg_capabilities >= 0) { | |
1842 | tmp = __lpss_ssp_read_priv(drv_data, | |
1843 | config->reg_capabilities); | |
1844 | tmp &= LPSS_CAPS_CS_EN_MASK; | |
1845 | tmp >>= LPSS_CAPS_CS_EN_SHIFT; | |
1846 | platform_info->num_chipselect = ffz(tmp); | |
30f3a6ab MW |
1847 | } else if (config->cs_num) { |
1848 | platform_info->num_chipselect = config->cs_num; | |
8b136baa JN |
1849 | } |
1850 | } | |
51eea52d | 1851 | controller->num_chipselect = platform_info->num_chipselect; |
778c12e6 | 1852 | controller->use_gpio_descriptors = true; |
6ac5a435 | 1853 | |
77d33897 LR |
1854 | if (platform_info->is_slave) { |
1855 | drv_data->gpiod_ready = devm_gpiod_get_optional(dev, | |
1856 | "ready", GPIOD_OUT_LOW); | |
1857 | if (IS_ERR(drv_data->gpiod_ready)) { | |
1858 | status = PTR_ERR(drv_data->gpiod_ready); | |
1859 | goto out_error_clock_enabled; | |
1860 | } | |
1861 | } | |
1862 | ||
836d1a22 AO |
1863 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1864 | pm_runtime_use_autosuspend(&pdev->dev); | |
1865 | pm_runtime_set_active(&pdev->dev); | |
1866 | pm_runtime_enable(&pdev->dev); | |
1867 | ||
e0c9905e SS |
1868 | /* Register with the SPI framework */ |
1869 | platform_set_drvdata(pdev, drv_data); | |
32e5b572 | 1870 | status = spi_register_controller(controller); |
eb743ec6 | 1871 | if (status) { |
8083d6b8 | 1872 | dev_err(&pdev->dev, "problem registering SPI controller\n"); |
12742045 | 1873 | goto out_error_pm_runtime_enabled; |
e0c9905e SS |
1874 | } |
1875 | ||
1876 | return status; | |
1877 | ||
12742045 | 1878 | out_error_pm_runtime_enabled: |
e2b714af | 1879 | pm_runtime_disable(&pdev->dev); |
12742045 LR |
1880 | |
1881 | out_error_clock_enabled: | |
3343b7a6 | 1882 | clk_disable_unprepare(ssp->clk); |
62bbc864 TJ |
1883 | |
1884 | out_error_dma_irq_alloc: | |
cd7bed00 | 1885 | pxa2xx_spi_dma_release(drv_data); |
2f1a74e5 | 1886 | free_irq(ssp->irq, drv_data); |
e0c9905e | 1887 | |
51eea52d | 1888 | out_error_controller_alloc: |
baffe169 | 1889 | pxa_ssp_free(ssp); |
e0c9905e SS |
1890 | return status; |
1891 | } | |
1892 | ||
1893 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1894 | { | |
1895 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
3d24b2a4 | 1896 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e | 1897 | |
7d94a505 MW |
1898 | pm_runtime_get_sync(&pdev->dev); |
1899 | ||
32e5b572 LW |
1900 | spi_unregister_controller(drv_data->controller); |
1901 | ||
e0c9905e | 1902 | /* Disable the SSP at the peripheral and SOC level */ |
0c8ccd8b | 1903 | pxa_ssp_disable(ssp); |
3343b7a6 | 1904 | clk_disable_unprepare(ssp->clk); |
e0c9905e SS |
1905 | |
1906 | /* Release DMA */ | |
51eea52d | 1907 | if (drv_data->controller_info->enable_dma) |
cd7bed00 | 1908 | pxa2xx_spi_dma_release(drv_data); |
e0c9905e | 1909 | |
7d94a505 MW |
1910 | pm_runtime_put_noidle(&pdev->dev); |
1911 | pm_runtime_disable(&pdev->dev); | |
1912 | ||
e0c9905e | 1913 | /* Release IRQ */ |
2f1a74e5 | 1914 | free_irq(ssp->irq, drv_data); |
1915 | ||
1916 | /* Release SSP */ | |
baffe169 | 1917 | pxa_ssp_free(ssp); |
e0c9905e | 1918 | |
e0c9905e SS |
1919 | return 0; |
1920 | } | |
1921 | ||
382cebb0 | 1922 | #ifdef CONFIG_PM_SLEEP |
86d2593a | 1923 | static int pxa2xx_spi_suspend(struct device *dev) |
e0c9905e | 1924 | { |
86d2593a | 1925 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1926 | struct ssp_device *ssp = drv_data->ssp; |
bffc967e | 1927 | int status; |
e0c9905e | 1928 | |
51eea52d | 1929 | status = spi_controller_suspend(drv_data->controller); |
eb743ec6 | 1930 | if (status) |
e0c9905e | 1931 | return status; |
0c8ccd8b AS |
1932 | |
1933 | pxa_ssp_disable(ssp); | |
2b9375b9 DB |
1934 | |
1935 | if (!pm_runtime_suspended(dev)) | |
1936 | clk_disable_unprepare(ssp->clk); | |
e0c9905e SS |
1937 | |
1938 | return 0; | |
1939 | } | |
1940 | ||
86d2593a | 1941 | static int pxa2xx_spi_resume(struct device *dev) |
e0c9905e | 1942 | { |
86d2593a | 1943 | struct driver_data *drv_data = dev_get_drvdata(dev); |
2f1a74e5 | 1944 | struct ssp_device *ssp = drv_data->ssp; |
bffc967e | 1945 | int status; |
e0c9905e SS |
1946 | |
1947 | /* Enable the SSP clock */ | |
62bbc864 TJ |
1948 | if (!pm_runtime_suspended(dev)) { |
1949 | status = clk_prepare_enable(ssp->clk); | |
1950 | if (status) | |
1951 | return status; | |
1952 | } | |
e0c9905e SS |
1953 | |
1954 | /* Start the queue running */ | |
51eea52d | 1955 | return spi_controller_resume(drv_data->controller); |
e0c9905e | 1956 | } |
7d94a505 MW |
1957 | #endif |
1958 | ||
ec833050 | 1959 | #ifdef CONFIG_PM |
7d94a505 MW |
1960 | static int pxa2xx_spi_runtime_suspend(struct device *dev) |
1961 | { | |
1962 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
1963 | ||
1964 | clk_disable_unprepare(drv_data->ssp->clk); | |
1965 | return 0; | |
1966 | } | |
1967 | ||
1968 | static int pxa2xx_spi_runtime_resume(struct device *dev) | |
1969 | { | |
1970 | struct driver_data *drv_data = dev_get_drvdata(dev); | |
62bbc864 | 1971 | int status; |
7d94a505 | 1972 | |
62bbc864 TJ |
1973 | status = clk_prepare_enable(drv_data->ssp->clk); |
1974 | return status; | |
7d94a505 MW |
1975 | } |
1976 | #endif | |
86d2593a | 1977 | |
47145210 | 1978 | static const struct dev_pm_ops pxa2xx_spi_pm_ops = { |
7d94a505 MW |
1979 | SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) |
1980 | SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, | |
1981 | pxa2xx_spi_runtime_resume, NULL) | |
86d2593a | 1982 | }; |
e0c9905e SS |
1983 | |
1984 | static struct platform_driver driver = { | |
1985 | .driver = { | |
86d2593a | 1986 | .name = "pxa2xx-spi", |
86d2593a | 1987 | .pm = &pxa2xx_spi_pm_ops, |
a3496855 | 1988 | .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), |
87ae1d2d | 1989 | .of_match_table = of_match_ptr(pxa2xx_spi_of_match), |
e0c9905e | 1990 | }, |
fbd29a14 | 1991 | .probe = pxa2xx_spi_probe, |
d1e44d9c | 1992 | .remove = pxa2xx_spi_remove, |
e0c9905e SS |
1993 | }; |
1994 | ||
1995 | static int __init pxa2xx_spi_init(void) | |
1996 | { | |
fbd29a14 | 1997 | return platform_driver_register(&driver); |
e0c9905e | 1998 | } |
5b61a749 | 1999 | subsys_initcall(pxa2xx_spi_init); |
e0c9905e SS |
2000 | |
2001 | static void __exit pxa2xx_spi_exit(void) | |
2002 | { | |
2003 | platform_driver_unregister(&driver); | |
2004 | } | |
2005 | module_exit(pxa2xx_spi_exit); | |
51ebf6ac FS |
2006 | |
2007 | MODULE_SOFTDEP("pre: dw_dmac"); |