[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-pxa2xx.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
 * Copyright (C) 2013, 2021 Intel Corporation
 */

#ifndef SPI_PXA2XX_H
#define SPI_PXA2XX_H

#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/types.h>
#include <linux/sizes.h>

#include <linux/pxa2xx_ssp.h>

struct gpio_desc;
struct pxa2xx_spi_controller;
struct spi_controller;
struct spi_device;
struct spi_transfer;

struct driver_data {
	/* SSP Info */
	struct ssp_device *ssp;

	/* SPI framework hookup */
	enum pxa_ssp_type ssp_type;
	struct spi_controller *controller;

	/* PXA hookup */
	struct pxa2xx_spi_controller *controller_info;

	/* SSP masks*/
	u32 dma_cr1;
	u32 int_cr1;
	u32 clear_sr;
	u32 mask_sr;

	/* DMA engine support */
	atomic_t dma_running;

	/* Current transfer state info */
	void *tx;
	void *tx_end;
	void *rx;
	void *rx_end;
	u8 n_bytes;
	int (*write)(struct driver_data *drv_data);
	int (*read)(struct driver_data *drv_data);
	irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
	void (*cs_control)(u32 command);

	void __iomem *lpss_base;

	/* Optional slave FIFO ready signal */
	struct gpio_desc *gpiod_ready;
};

struct chip_data {
	u32 cr1;
	u32 dds_rate;
	u32 timeout;
	u8 n_bytes;
	u8 enable_dma;
	u32 dma_burst_size;
	u32 dma_threshold;
	u32 threshold;
	u16 lpss_rx_threshold;
	u16 lpss_tx_threshold;

	int (*write)(struct driver_data *drv_data);
	int (*read)(struct driver_data *drv_data);

	void (*cs_control)(u32 command);
};

static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
{
	return pxa_ssp_read_reg(drv_data->ssp, reg);
}

static inline void pxa2xx_spi_write(const struct driver_data *drv_data, u32 reg, u32 val)
{
	pxa_ssp_write_reg(drv_data->ssp, reg, val);
}

#define DMA_ALIGNMENT		8

static inline int pxa25x_ssp_comp(const struct driver_data *drv_data)
{
	switch (drv_data->ssp_type) {
	case PXA25x_SSP:
	case CE4100_SSP:
	case QUARK_X1000_SSP:
		return 1;
	default:
		return 0;
	}
}

static inline void clear_SSCR1_bits(const struct driver_data *drv_data, u32 bits)
{
	pxa2xx_spi_write(drv_data, SSCR1, pxa2xx_spi_read(drv_data, SSCR1) & ~bits);
}

static inline u32 read_SSSR_bits(const struct driver_data *drv_data, u32 bits)
{
	return pxa2xx_spi_read(drv_data, SSSR) & bits;
}

static inline void write_SSSR_CS(const struct driver_data *drv_data, u32 val)
{
	if (drv_data->ssp_type == CE4100_SSP ||
	    drv_data->ssp_type == QUARK_X1000_SSP)
		val |= read_SSSR_bits(drv_data, SSSR_ALT_FRM_MASK);

	pxa2xx_spi_write(drv_data, SSSR, val);
}

extern int pxa2xx_spi_flush(struct driver_data *drv_data);

#define MAX_DMA_LEN		SZ_64K
#define DEFAULT_DMA_CR1		(SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)

extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
				  struct spi_transfer *xfer);
extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
						  struct spi_device *spi,
						  u8 bits_per_word,
						  u32 *burst_code,
						  u32 *threshold);

#endif /* SPI_PXA2XX_H */
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
cd7bed00 MW	2	/*
cd7bed00 MW	3	* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
8083d6b8	4	* Copyright (C) 2013, 2021 Intel Corporation
cd7bed00 MW	5	*/
	6
	7	#ifndef SPI_PXA2XX_H
	8	#define SPI_PXA2XX_H
	9
cd7bed00	10	#include <linux/interrupt.h>
0e476871 AS	11	#include <linux/io.h>
0e476871 AS	12	#include <linux/types.h>
5928808e	13	#include <linux/sizes.h>
0e476871 AS	14
	15	#include <linux/pxa2xx_ssp.h>
	16
	17	struct gpio_desc;
	18	struct pxa2xx_spi_controller;
	19	struct spi_controller;
	20	struct spi_device;
	21	struct spi_transfer;
cd7bed00 MW	22
cd7bed00 MW	23	struct driver_data {
cd7bed00 MW	24	/* SSP Info */
	25	struct ssp_device *ssp;
	26
	27	/* SPI framework hookup */
	28	enum pxa_ssp_type ssp_type;
51eea52d	29	struct spi_controller *controller;
cd7bed00 MW	30
cd7bed00 MW	31	/* PXA hookup */
51eea52d	32	struct pxa2xx_spi_controller *controller_info;
cd7bed00	33
cd7bed00 MW	34	/* SSP masks*/
	35	u32 dma_cr1;
	36	u32 int_cr1;
	37	u32 clear_sr;
	38	u32 mask_sr;
	39
5928808e	40	/* DMA engine support */
5928808e MW	41	atomic_t dma_running;
5928808e MW	42
d5898e19	43	/* Current transfer state info */
cd7bed00 MW	44	void *tx;
	45	void *tx_end;
	46	void *rx;
	47	void *rx_end;
cd7bed00 MW	48	u8 n_bytes;
	49	int (write)(struct driver_data drv_data);
	50	int (read)(struct driver_data drv_data);
	51	irqreturn_t (transfer_handler)(struct driver_data drv_data);
	52	void (*cs_control)(u32 command);
a0d2642e MW	53
a0d2642e MW	54	void __iomem *lpss_base;
99f499cd	55
77d33897 LR	56	/* Optional slave FIFO ready signal */
77d33897 LR	57	struct gpio_desc *gpiod_ready;
cd7bed00 MW	58	};
	59
	60	struct chip_data {
cd7bed00	61	u32 cr1;
e5262d05	62	u32 dds_rate;
cd7bed00 MW	63	u32 timeout;
cd7bed00 MW	64	u8 n_bytes;
de6926f3	65	u8 enable_dma;
cd7bed00	66	u32 dma_burst_size;
cd7bed00	67	u32 dma_threshold;
de6926f3	68	u32 threshold;
a0d2642e MW	69	u16 lpss_rx_threshold;
a0d2642e MW	70	u16 lpss_tx_threshold;
de6926f3	71
cd7bed00 MW	72	int (write)(struct driver_data drv_data);
cd7bed00 MW	73	int (read)(struct driver_data drv_data);
de6926f3	74
cd7bed00 MW	75	void (*cs_control)(u32 command);
	76	};
	77
9e43c9a8	78	static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
c039dd27	79	{
9e43c9a8	80	return pxa_ssp_read_reg(drv_data->ssp, reg);
c039dd27 JN	81	}
c039dd27 JN	82
9e43c9a8	83	static inline void pxa2xx_spi_write(const struct driver_data *drv_data, u32 reg, u32 val)
c039dd27	84	{
9e43c9a8	85	pxa_ssp_write_reg(drv_data->ssp, reg, val);
c039dd27	86	}
cd7bed00	87
cd7bed00 MW	88	#define DMA_ALIGNMENT 8
cd7bed00 MW	89
eca32c39	90	static inline int pxa25x_ssp_comp(const struct driver_data *drv_data)
cd7bed00	91	{
e5262d05 WC	92	switch (drv_data->ssp_type) {
	93	case PXA25x_SSP:
	94	case CE4100_SSP:
	95	case QUARK_X1000_SSP:
cd7bed00	96	return 1;
e5262d05 WC	97	default:
	98	return 0;
	99	}
cd7bed00 MW	100	}
cd7bed00 MW	101
42c80cd4 AS	102	static inline void clear_SSCR1_bits(const struct driver_data *drv_data, u32 bits)
	103	{
	104	pxa2xx_spi_write(drv_data, SSCR1, pxa2xx_spi_read(drv_data, SSCR1) & ~bits);
	105	}
	106
6d380132 AS	107	static inline u32 read_SSSR_bits(const struct driver_data *drv_data, u32 bits)
	108	{
	109	return pxa2xx_spi_read(drv_data, SSSR) & bits;
	110	}
	111
eca32c39	112	static inline void write_SSSR_CS(const struct driver_data *drv_data, u32 val)
cd7bed00	113	{
e5262d05 WC	114	if (drv_data->ssp_type == CE4100_SSP \|\|
e5262d05 WC	115	drv_data->ssp_type == QUARK_X1000_SSP)
6d380132	116	val \|= read_SSSR_bits(drv_data, SSSR_ALT_FRM_MASK);
cd7bed00	117
c039dd27	118	pxa2xx_spi_write(drv_data, SSSR, val);
cd7bed00 MW	119	}
	120
	121	extern int pxa2xx_spi_flush(struct driver_data *drv_data);
cd7bed00	122
5928808e MW	123	#define MAX_DMA_LEN SZ_64K
5928808e MW	124	#define DEFAULT_DMA_CR1 (SSCR1_TSRE \| SSCR1_RSRE \| SSCR1_TRAIL)
5928808e	125
cd7bed00	126	extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
d5898e19 JN	127	extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
d5898e19 JN	128	struct spi_transfer *xfer);
cd7bed00	129	extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
d5898e19	130	extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
cd7bed00 MW	131	extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
cd7bed00 MW	132	extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
cd7bed00 MW	133	extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
	134	struct spi_device *spi,
	135	u8 bits_per_word,
	136	u32 *burst_code,
	137	u32 *threshold);
cd7bed00 MW	138
cd7bed00 MW	139	#endif /* SPI_PXA2XX_H */