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1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
3 | * Copyright (C) 2013, Intel Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #ifndef SPI_PXA2XX_H | |
11 | #define SPI_PXA2XX_H | |
12 | ||
5928808e MW |
13 | #include <linux/atomic.h> |
14 | #include <linux/dmaengine.h> | |
cd7bed00 MW |
15 | #include <linux/errno.h> |
16 | #include <linux/io.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/pxa2xx_ssp.h> | |
5928808e MW |
20 | #include <linux/scatterlist.h> |
21 | #include <linux/sizes.h> | |
cd7bed00 MW |
22 | #include <linux/spi/spi.h> |
23 | #include <linux/spi/pxa2xx_spi.h> | |
24 | ||
25 | struct driver_data { | |
26 | /* Driver model hookup */ | |
27 | struct platform_device *pdev; | |
28 | ||
29 | /* SSP Info */ | |
30 | struct ssp_device *ssp; | |
31 | ||
32 | /* SPI framework hookup */ | |
33 | enum pxa_ssp_type ssp_type; | |
34 | struct spi_master *master; | |
35 | ||
36 | /* PXA hookup */ | |
37 | struct pxa2xx_spi_master *master_info; | |
38 | ||
cd7bed00 MW |
39 | /* SSP register addresses */ |
40 | void __iomem *ioaddr; | |
41 | u32 ssdr_physical; | |
42 | ||
43 | /* SSP masks*/ | |
44 | u32 dma_cr1; | |
45 | u32 int_cr1; | |
46 | u32 clear_sr; | |
47 | u32 mask_sr; | |
48 | ||
cd7bed00 MW |
49 | /* Message Transfer pump */ |
50 | struct tasklet_struct pump_transfers; | |
51 | ||
5928808e | 52 | /* DMA engine support */ |
5928808e MW |
53 | atomic_t dma_running; |
54 | ||
cd7bed00 | 55 | /* Current message transfer state info */ |
cd7bed00 MW |
56 | struct spi_transfer *cur_transfer; |
57 | struct chip_data *cur_chip; | |
58 | size_t len; | |
59 | void *tx; | |
60 | void *tx_end; | |
61 | void *rx; | |
62 | void *rx_end; | |
cd7bed00 MW |
63 | u8 n_bytes; |
64 | int (*write)(struct driver_data *drv_data); | |
65 | int (*read)(struct driver_data *drv_data); | |
66 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); | |
67 | void (*cs_control)(u32 command); | |
a0d2642e MW |
68 | |
69 | void __iomem *lpss_base; | |
cd7bed00 MW |
70 | }; |
71 | ||
72 | struct chip_data { | |
cd7bed00 | 73 | u32 cr1; |
e5262d05 | 74 | u32 dds_rate; |
cd7bed00 MW |
75 | u32 timeout; |
76 | u8 n_bytes; | |
77 | u32 dma_burst_size; | |
78 | u32 threshold; | |
79 | u32 dma_threshold; | |
a0d2642e MW |
80 | u16 lpss_rx_threshold; |
81 | u16 lpss_tx_threshold; | |
cd7bed00 | 82 | u8 enable_dma; |
cd7bed00 MW |
83 | union { |
84 | int gpio_cs; | |
85 | unsigned int frm; | |
86 | }; | |
87 | int gpio_cs_inverted; | |
88 | int (*write)(struct driver_data *drv_data); | |
89 | int (*read)(struct driver_data *drv_data); | |
90 | void (*cs_control)(u32 command); | |
91 | }; | |
92 | ||
c039dd27 JN |
93 | static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, |
94 | unsigned reg) | |
95 | { | |
96 | return __raw_readl(drv_data->ioaddr + reg); | |
97 | } | |
98 | ||
99 | static inline void pxa2xx_spi_write(const struct driver_data *drv_data, | |
100 | unsigned reg, u32 val) | |
101 | { | |
102 | __raw_writel(val, drv_data->ioaddr + reg); | |
103 | } | |
cd7bed00 MW |
104 | |
105 | #define START_STATE ((void *)0) | |
106 | #define RUNNING_STATE ((void *)1) | |
107 | #define DONE_STATE ((void *)2) | |
108 | #define ERROR_STATE ((void *)-1) | |
109 | ||
cd7bed00 MW |
110 | #define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT) |
111 | #define DMA_ALIGNMENT 8 | |
112 | ||
113 | static inline int pxa25x_ssp_comp(struct driver_data *drv_data) | |
114 | { | |
e5262d05 WC |
115 | switch (drv_data->ssp_type) { |
116 | case PXA25x_SSP: | |
117 | case CE4100_SSP: | |
118 | case QUARK_X1000_SSP: | |
cd7bed00 | 119 | return 1; |
e5262d05 WC |
120 | default: |
121 | return 0; | |
122 | } | |
cd7bed00 MW |
123 | } |
124 | ||
125 | static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val) | |
126 | { | |
e5262d05 WC |
127 | if (drv_data->ssp_type == CE4100_SSP || |
128 | drv_data->ssp_type == QUARK_X1000_SSP) | |
c039dd27 | 129 | val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK; |
cd7bed00 | 130 | |
c039dd27 | 131 | pxa2xx_spi_write(drv_data, SSSR, val); |
cd7bed00 MW |
132 | } |
133 | ||
134 | extern int pxa2xx_spi_flush(struct driver_data *drv_data); | |
135 | extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data); | |
136 | ||
5928808e MW |
137 | #define MAX_DMA_LEN SZ_64K |
138 | #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL) | |
5928808e | 139 | |
cd7bed00 MW |
140 | extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data); |
141 | extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst); | |
142 | extern void pxa2xx_spi_dma_start(struct driver_data *drv_data); | |
143 | extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data); | |
144 | extern void pxa2xx_spi_dma_release(struct driver_data *drv_data); | |
cd7bed00 MW |
145 | extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip, |
146 | struct spi_device *spi, | |
147 | u8 bits_per_word, | |
148 | u32 *burst_code, | |
149 | u32 *threshold); | |
cd7bed00 MW |
150 | |
151 | #endif /* SPI_PXA2XX_H */ |