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64e36824 | 1 | /* |
2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
5dcc44ed | 3 | * Author: Addy Ke <addy.ke@rock-chips.com> |
64e36824 | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | */ | |
15 | ||
64e36824 | 16 | #include <linux/clk.h> |
ec5c5d8a SL |
17 | #include <linux/dmaengine.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
23e291c2 | 20 | #include <linux/pinctrl/consumer.h> |
64e36824 | 21 | #include <linux/platform_device.h> |
64e36824 | 22 | #include <linux/spi/spi.h> |
64e36824 | 23 | #include <linux/pm_runtime.h> |
ec5c5d8a | 24 | #include <linux/scatterlist.h> |
64e36824 | 25 | |
26 | #define DRIVER_NAME "rockchip-spi" | |
27 | ||
aa099382 JC |
28 | #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ |
29 | writel_relaxed(readl_relaxed(reg) & ~(bits), reg) | |
30 | #define ROCKCHIP_SPI_SET_BITS(reg, bits) \ | |
31 | writel_relaxed(readl_relaxed(reg) | (bits), reg) | |
32 | ||
64e36824 | 33 | /* SPI register offsets */ |
34 | #define ROCKCHIP_SPI_CTRLR0 0x0000 | |
35 | #define ROCKCHIP_SPI_CTRLR1 0x0004 | |
36 | #define ROCKCHIP_SPI_SSIENR 0x0008 | |
37 | #define ROCKCHIP_SPI_SER 0x000c | |
38 | #define ROCKCHIP_SPI_BAUDR 0x0010 | |
39 | #define ROCKCHIP_SPI_TXFTLR 0x0014 | |
40 | #define ROCKCHIP_SPI_RXFTLR 0x0018 | |
41 | #define ROCKCHIP_SPI_TXFLR 0x001c | |
42 | #define ROCKCHIP_SPI_RXFLR 0x0020 | |
43 | #define ROCKCHIP_SPI_SR 0x0024 | |
44 | #define ROCKCHIP_SPI_IPR 0x0028 | |
45 | #define ROCKCHIP_SPI_IMR 0x002c | |
46 | #define ROCKCHIP_SPI_ISR 0x0030 | |
47 | #define ROCKCHIP_SPI_RISR 0x0034 | |
48 | #define ROCKCHIP_SPI_ICR 0x0038 | |
49 | #define ROCKCHIP_SPI_DMACR 0x003c | |
50 | #define ROCKCHIP_SPI_DMATDLR 0x0040 | |
51 | #define ROCKCHIP_SPI_DMARDLR 0x0044 | |
52 | #define ROCKCHIP_SPI_TXDR 0x0400 | |
53 | #define ROCKCHIP_SPI_RXDR 0x0800 | |
54 | ||
55 | /* Bit fields in CTRLR0 */ | |
56 | #define CR0_DFS_OFFSET 0 | |
57 | ||
58 | #define CR0_CFS_OFFSET 2 | |
59 | ||
60 | #define CR0_SCPH_OFFSET 6 | |
61 | ||
62 | #define CR0_SCPOL_OFFSET 7 | |
63 | ||
64 | #define CR0_CSM_OFFSET 8 | |
65 | #define CR0_CSM_KEEP 0x0 | |
66 | /* ss_n be high for half sclk_out cycles */ | |
67 | #define CR0_CSM_HALF 0X1 | |
68 | /* ss_n be high for one sclk_out cycle */ | |
69 | #define CR0_CSM_ONE 0x2 | |
70 | ||
71 | /* ss_n to sclk_out delay */ | |
72 | #define CR0_SSD_OFFSET 10 | |
73 | /* | |
74 | * The period between ss_n active and | |
75 | * sclk_out active is half sclk_out cycles | |
76 | */ | |
77 | #define CR0_SSD_HALF 0x0 | |
78 | /* | |
79 | * The period between ss_n active and | |
80 | * sclk_out active is one sclk_out cycle | |
81 | */ | |
82 | #define CR0_SSD_ONE 0x1 | |
83 | ||
84 | #define CR0_EM_OFFSET 11 | |
85 | #define CR0_EM_LITTLE 0x0 | |
86 | #define CR0_EM_BIG 0x1 | |
87 | ||
88 | #define CR0_FBM_OFFSET 12 | |
89 | #define CR0_FBM_MSB 0x0 | |
90 | #define CR0_FBM_LSB 0x1 | |
91 | ||
92 | #define CR0_BHT_OFFSET 13 | |
93 | #define CR0_BHT_16BIT 0x0 | |
94 | #define CR0_BHT_8BIT 0x1 | |
95 | ||
96 | #define CR0_RSD_OFFSET 14 | |
97 | ||
98 | #define CR0_FRF_OFFSET 16 | |
99 | #define CR0_FRF_SPI 0x0 | |
100 | #define CR0_FRF_SSP 0x1 | |
101 | #define CR0_FRF_MICROWIRE 0x2 | |
102 | ||
103 | #define CR0_XFM_OFFSET 18 | |
104 | #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) | |
105 | #define CR0_XFM_TR 0x0 | |
106 | #define CR0_XFM_TO 0x1 | |
107 | #define CR0_XFM_RO 0x2 | |
108 | ||
109 | #define CR0_OPM_OFFSET 20 | |
110 | #define CR0_OPM_MASTER 0x0 | |
111 | #define CR0_OPM_SLAVE 0x1 | |
112 | ||
113 | #define CR0_MTM_OFFSET 0x21 | |
114 | ||
115 | /* Bit fields in SER, 2bit */ | |
116 | #define SER_MASK 0x3 | |
117 | ||
118 | /* Bit fields in SR, 5bit */ | |
119 | #define SR_MASK 0x1f | |
120 | #define SR_BUSY (1 << 0) | |
121 | #define SR_TF_FULL (1 << 1) | |
122 | #define SR_TF_EMPTY (1 << 2) | |
123 | #define SR_RF_EMPTY (1 << 3) | |
124 | #define SR_RF_FULL (1 << 4) | |
125 | ||
126 | /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ | |
127 | #define INT_MASK 0x1f | |
128 | #define INT_TF_EMPTY (1 << 0) | |
129 | #define INT_TF_OVERFLOW (1 << 1) | |
130 | #define INT_RF_UNDERFLOW (1 << 2) | |
131 | #define INT_RF_OVERFLOW (1 << 3) | |
132 | #define INT_RF_FULL (1 << 4) | |
133 | ||
134 | /* Bit fields in ICR, 4bit */ | |
135 | #define ICR_MASK 0x0f | |
136 | #define ICR_ALL (1 << 0) | |
137 | #define ICR_RF_UNDERFLOW (1 << 1) | |
138 | #define ICR_RF_OVERFLOW (1 << 2) | |
139 | #define ICR_TF_OVERFLOW (1 << 3) | |
140 | ||
141 | /* Bit fields in DMACR */ | |
142 | #define RF_DMA_EN (1 << 0) | |
143 | #define TF_DMA_EN (1 << 1) | |
144 | ||
145 | #define RXBUSY (1 << 0) | |
146 | #define TXBUSY (1 << 1) | |
147 | ||
f9cfd522 AK |
148 | /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ |
149 | #define MAX_SCLK_OUT 50000000 | |
150 | ||
5185a81c BN |
151 | /* |
152 | * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, | |
153 | * the controller seems to hang when given 0x10000, so stick with this for now. | |
154 | */ | |
155 | #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff | |
156 | ||
aa099382 JC |
157 | #define ROCKCHIP_SPI_MAX_CS_NUM 2 |
158 | ||
64e36824 | 159 | enum rockchip_ssi_type { |
160 | SSI_MOTO_SPI = 0, | |
161 | SSI_TI_SSP, | |
162 | SSI_NS_MICROWIRE, | |
163 | }; | |
164 | ||
165 | struct rockchip_spi_dma_data { | |
166 | struct dma_chan *ch; | |
167 | enum dma_transfer_direction direction; | |
168 | dma_addr_t addr; | |
169 | }; | |
170 | ||
171 | struct rockchip_spi { | |
172 | struct device *dev; | |
173 | struct spi_master *master; | |
174 | ||
175 | struct clk *spiclk; | |
176 | struct clk *apb_pclk; | |
177 | ||
178 | void __iomem *regs; | |
179 | /*depth of the FIFO buffer */ | |
180 | u32 fifo_len; | |
181 | /* max bus freq supported */ | |
182 | u32 max_freq; | |
183 | /* supported slave numbers */ | |
184 | enum rockchip_ssi_type type; | |
185 | ||
186 | u16 mode; | |
187 | u8 tmode; | |
188 | u8 bpw; | |
189 | u8 n_bytes; | |
108b5c8b | 190 | u32 rsd_nsecs; |
64e36824 | 191 | unsigned len; |
192 | u32 speed; | |
193 | ||
194 | const void *tx; | |
195 | const void *tx_end; | |
196 | void *rx; | |
197 | void *rx_end; | |
198 | ||
199 | u32 state; | |
5dcc44ed | 200 | /* protect state */ |
64e36824 | 201 | spinlock_t lock; |
202 | ||
aa099382 JC |
203 | bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM]; |
204 | ||
64e36824 | 205 | u32 use_dma; |
206 | struct sg_table tx_sg; | |
207 | struct sg_table rx_sg; | |
208 | struct rockchip_spi_dma_data dma_rx; | |
209 | struct rockchip_spi_dma_data dma_tx; | |
80abf888 | 210 | struct dma_slave_caps dma_caps; |
64e36824 | 211 | }; |
212 | ||
213 | static inline void spi_enable_chip(struct rockchip_spi *rs, int enable) | |
214 | { | |
215 | writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR); | |
216 | } | |
217 | ||
218 | static inline void spi_set_clk(struct rockchip_spi *rs, u16 div) | |
219 | { | |
220 | writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR); | |
221 | } | |
222 | ||
223 | static inline void flush_fifo(struct rockchip_spi *rs) | |
224 | { | |
225 | while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR)) | |
226 | readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); | |
227 | } | |
228 | ||
2df08e78 AK |
229 | static inline void wait_for_idle(struct rockchip_spi *rs) |
230 | { | |
231 | unsigned long timeout = jiffies + msecs_to_jiffies(5); | |
232 | ||
233 | do { | |
234 | if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) | |
235 | return; | |
64bc0110 | 236 | } while (!time_after(jiffies, timeout)); |
2df08e78 AK |
237 | |
238 | dev_warn(rs->dev, "spi controller is in busy state!\n"); | |
239 | } | |
240 | ||
64e36824 | 241 | static u32 get_fifo_len(struct rockchip_spi *rs) |
242 | { | |
243 | u32 fifo; | |
244 | ||
245 | for (fifo = 2; fifo < 32; fifo++) { | |
246 | writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
247 | if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR)) | |
248 | break; | |
249 | } | |
250 | ||
251 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
252 | ||
253 | return (fifo == 31) ? 0 : fifo; | |
254 | } | |
255 | ||
256 | static inline u32 tx_max(struct rockchip_spi *rs) | |
257 | { | |
258 | u32 tx_left, tx_room; | |
259 | ||
260 | tx_left = (rs->tx_end - rs->tx) / rs->n_bytes; | |
261 | tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); | |
262 | ||
263 | return min(tx_left, tx_room); | |
264 | } | |
265 | ||
266 | static inline u32 rx_max(struct rockchip_spi *rs) | |
267 | { | |
268 | u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes; | |
269 | u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); | |
270 | ||
271 | return min(rx_left, rx_room); | |
272 | } | |
273 | ||
274 | static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) | |
275 | { | |
b920cc31 HH |
276 | struct spi_master *master = spi->master; |
277 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
aa099382 | 278 | bool cs_asserted = !enable; |
b920cc31 | 279 | |
aa099382 JC |
280 | /* Return immediately for no-op */ |
281 | if (cs_asserted == rs->cs_asserted[spi->chip_select]) | |
282 | return; | |
64e36824 | 283 | |
aa099382 JC |
284 | if (cs_asserted) { |
285 | /* Keep things powered as long as CS is asserted */ | |
286 | pm_runtime_get_sync(rs->dev); | |
64e36824 | 287 | |
aa099382 JC |
288 | ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, |
289 | BIT(spi->chip_select)); | |
290 | } else { | |
291 | ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, | |
292 | BIT(spi->chip_select)); | |
64e36824 | 293 | |
aa099382 JC |
294 | /* Drop reference from when we first asserted CS */ |
295 | pm_runtime_put(rs->dev); | |
296 | } | |
b920cc31 | 297 | |
aa099382 | 298 | rs->cs_asserted[spi->chip_select] = cs_asserted; |
64e36824 | 299 | } |
300 | ||
301 | static int rockchip_spi_prepare_message(struct spi_master *master, | |
5dcc44ed | 302 | struct spi_message *msg) |
64e36824 | 303 | { |
304 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
305 | struct spi_device *spi = msg->spi; | |
306 | ||
64e36824 | 307 | rs->mode = spi->mode; |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
2291793c AS |
312 | static void rockchip_spi_handle_err(struct spi_master *master, |
313 | struct spi_message *msg) | |
64e36824 | 314 | { |
315 | unsigned long flags; | |
316 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
317 | ||
318 | spin_lock_irqsave(&rs->lock, flags); | |
319 | ||
5dcc44ed AK |
320 | /* |
321 | * For DMA mode, we need terminate DMA channel and flush | |
322 | * fifo for the next transfer if DMA thansfer timeout. | |
2291793c AS |
323 | * handle_err() was called by core if transfer failed. |
324 | * Maybe it is reasonable for error handling here. | |
5dcc44ed | 325 | */ |
64e36824 | 326 | if (rs->use_dma) { |
327 | if (rs->state & RXBUSY) { | |
557b7ea3 | 328 | dmaengine_terminate_async(rs->dma_rx.ch); |
64e36824 | 329 | flush_fifo(rs); |
330 | } | |
331 | ||
332 | if (rs->state & TXBUSY) | |
557b7ea3 | 333 | dmaengine_terminate_async(rs->dma_tx.ch); |
64e36824 | 334 | } |
335 | ||
336 | spin_unlock_irqrestore(&rs->lock, flags); | |
2291793c AS |
337 | } |
338 | ||
339 | static int rockchip_spi_unprepare_message(struct spi_master *master, | |
340 | struct spi_message *msg) | |
341 | { | |
342 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
64e36824 | 343 | |
c28be31b AK |
344 | spi_enable_chip(rs, 0); |
345 | ||
64e36824 | 346 | return 0; |
347 | } | |
348 | ||
349 | static void rockchip_spi_pio_writer(struct rockchip_spi *rs) | |
350 | { | |
351 | u32 max = tx_max(rs); | |
352 | u32 txw = 0; | |
353 | ||
354 | while (max--) { | |
355 | if (rs->n_bytes == 1) | |
356 | txw = *(u8 *)(rs->tx); | |
357 | else | |
358 | txw = *(u16 *)(rs->tx); | |
359 | ||
360 | writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); | |
361 | rs->tx += rs->n_bytes; | |
362 | } | |
363 | } | |
364 | ||
365 | static void rockchip_spi_pio_reader(struct rockchip_spi *rs) | |
366 | { | |
367 | u32 max = rx_max(rs); | |
368 | u32 rxw; | |
369 | ||
370 | while (max--) { | |
371 | rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); | |
372 | if (rs->n_bytes == 1) | |
373 | *(u8 *)(rs->rx) = (u8)rxw; | |
374 | else | |
375 | *(u16 *)(rs->rx) = (u16)rxw; | |
376 | rs->rx += rs->n_bytes; | |
5dcc44ed | 377 | } |
64e36824 | 378 | } |
379 | ||
380 | static int rockchip_spi_pio_transfer(struct rockchip_spi *rs) | |
381 | { | |
382 | int remain = 0; | |
383 | ||
384 | do { | |
385 | if (rs->tx) { | |
386 | remain = rs->tx_end - rs->tx; | |
387 | rockchip_spi_pio_writer(rs); | |
388 | } | |
389 | ||
390 | if (rs->rx) { | |
391 | remain = rs->rx_end - rs->rx; | |
392 | rockchip_spi_pio_reader(rs); | |
393 | } | |
394 | ||
395 | cpu_relax(); | |
396 | } while (remain); | |
397 | ||
2df08e78 AK |
398 | /* If tx, wait until the FIFO data completely. */ |
399 | if (rs->tx) | |
400 | wait_for_idle(rs); | |
401 | ||
c28be31b AK |
402 | spi_enable_chip(rs, 0); |
403 | ||
64e36824 | 404 | return 0; |
405 | } | |
406 | ||
407 | static void rockchip_spi_dma_rxcb(void *data) | |
408 | { | |
409 | unsigned long flags; | |
410 | struct rockchip_spi *rs = data; | |
411 | ||
412 | spin_lock_irqsave(&rs->lock, flags); | |
413 | ||
414 | rs->state &= ~RXBUSY; | |
c28be31b AK |
415 | if (!(rs->state & TXBUSY)) { |
416 | spi_enable_chip(rs, 0); | |
64e36824 | 417 | spi_finalize_current_transfer(rs->master); |
c28be31b | 418 | } |
64e36824 | 419 | |
420 | spin_unlock_irqrestore(&rs->lock, flags); | |
421 | } | |
422 | ||
423 | static void rockchip_spi_dma_txcb(void *data) | |
424 | { | |
425 | unsigned long flags; | |
426 | struct rockchip_spi *rs = data; | |
427 | ||
2df08e78 AK |
428 | /* Wait until the FIFO data completely. */ |
429 | wait_for_idle(rs); | |
430 | ||
64e36824 | 431 | spin_lock_irqsave(&rs->lock, flags); |
432 | ||
433 | rs->state &= ~TXBUSY; | |
2c2bc748 AK |
434 | if (!(rs->state & RXBUSY)) { |
435 | spi_enable_chip(rs, 0); | |
64e36824 | 436 | spi_finalize_current_transfer(rs->master); |
2c2bc748 | 437 | } |
64e36824 | 438 | |
439 | spin_unlock_irqrestore(&rs->lock, flags); | |
440 | } | |
441 | ||
ea984911 | 442 | static int rockchip_spi_prepare_dma(struct rockchip_spi *rs) |
64e36824 | 443 | { |
444 | unsigned long flags; | |
445 | struct dma_slave_config rxconf, txconf; | |
446 | struct dma_async_tx_descriptor *rxdesc, *txdesc; | |
447 | ||
448 | spin_lock_irqsave(&rs->lock, flags); | |
449 | rs->state &= ~RXBUSY; | |
450 | rs->state &= ~TXBUSY; | |
451 | spin_unlock_irqrestore(&rs->lock, flags); | |
452 | ||
97cf5669 | 453 | rxdesc = NULL; |
64e36824 | 454 | if (rs->rx) { |
455 | rxconf.direction = rs->dma_rx.direction; | |
456 | rxconf.src_addr = rs->dma_rx.addr; | |
457 | rxconf.src_addr_width = rs->n_bytes; | |
80abf888 AK |
458 | if (rs->dma_caps.max_burst > 4) |
459 | rxconf.src_maxburst = 4; | |
460 | else | |
461 | rxconf.src_maxburst = 1; | |
64e36824 | 462 | dmaengine_slave_config(rs->dma_rx.ch, &rxconf); |
463 | ||
5dcc44ed AK |
464 | rxdesc = dmaengine_prep_slave_sg( |
465 | rs->dma_rx.ch, | |
64e36824 | 466 | rs->rx_sg.sgl, rs->rx_sg.nents, |
467 | rs->dma_rx.direction, DMA_PREP_INTERRUPT); | |
ea984911 SL |
468 | if (!rxdesc) |
469 | return -EINVAL; | |
64e36824 | 470 | |
471 | rxdesc->callback = rockchip_spi_dma_rxcb; | |
472 | rxdesc->callback_param = rs; | |
473 | } | |
474 | ||
97cf5669 | 475 | txdesc = NULL; |
64e36824 | 476 | if (rs->tx) { |
477 | txconf.direction = rs->dma_tx.direction; | |
478 | txconf.dst_addr = rs->dma_tx.addr; | |
479 | txconf.dst_addr_width = rs->n_bytes; | |
80abf888 AK |
480 | if (rs->dma_caps.max_burst > 4) |
481 | txconf.dst_maxburst = 4; | |
482 | else | |
483 | txconf.dst_maxburst = 1; | |
64e36824 | 484 | dmaengine_slave_config(rs->dma_tx.ch, &txconf); |
485 | ||
5dcc44ed AK |
486 | txdesc = dmaengine_prep_slave_sg( |
487 | rs->dma_tx.ch, | |
64e36824 | 488 | rs->tx_sg.sgl, rs->tx_sg.nents, |
489 | rs->dma_tx.direction, DMA_PREP_INTERRUPT); | |
ea984911 SL |
490 | if (!txdesc) { |
491 | if (rxdesc) | |
492 | dmaengine_terminate_sync(rs->dma_rx.ch); | |
493 | return -EINVAL; | |
494 | } | |
64e36824 | 495 | |
496 | txdesc->callback = rockchip_spi_dma_txcb; | |
497 | txdesc->callback_param = rs; | |
498 | } | |
499 | ||
500 | /* rx must be started before tx due to spi instinct */ | |
97cf5669 | 501 | if (rxdesc) { |
64e36824 | 502 | spin_lock_irqsave(&rs->lock, flags); |
503 | rs->state |= RXBUSY; | |
504 | spin_unlock_irqrestore(&rs->lock, flags); | |
505 | dmaengine_submit(rxdesc); | |
506 | dma_async_issue_pending(rs->dma_rx.ch); | |
507 | } | |
508 | ||
97cf5669 | 509 | if (txdesc) { |
64e36824 | 510 | spin_lock_irqsave(&rs->lock, flags); |
511 | rs->state |= TXBUSY; | |
512 | spin_unlock_irqrestore(&rs->lock, flags); | |
513 | dmaengine_submit(txdesc); | |
514 | dma_async_issue_pending(rs->dma_tx.ch); | |
515 | } | |
ea984911 SL |
516 | |
517 | return 0; | |
64e36824 | 518 | } |
519 | ||
520 | static void rockchip_spi_config(struct rockchip_spi *rs) | |
521 | { | |
522 | u32 div = 0; | |
523 | u32 dmacr = 0; | |
76b17e6e | 524 | int rsd = 0; |
64e36824 | 525 | |
526 | u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) | |
0277e01a AK |
527 | | (CR0_SSD_ONE << CR0_SSD_OFFSET) |
528 | | (CR0_EM_BIG << CR0_EM_OFFSET); | |
64e36824 | 529 | |
530 | cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); | |
531 | cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); | |
532 | cr0 |= (rs->tmode << CR0_XFM_OFFSET); | |
533 | cr0 |= (rs->type << CR0_FRF_OFFSET); | |
534 | ||
535 | if (rs->use_dma) { | |
536 | if (rs->tx) | |
537 | dmacr |= TF_DMA_EN; | |
538 | if (rs->rx) | |
539 | dmacr |= RF_DMA_EN; | |
540 | } | |
541 | ||
f9cfd522 AK |
542 | if (WARN_ON(rs->speed > MAX_SCLK_OUT)) |
543 | rs->speed = MAX_SCLK_OUT; | |
544 | ||
bb51537a | 545 | /* the minimum divisor is 2 */ |
f9cfd522 AK |
546 | if (rs->max_freq < 2 * rs->speed) { |
547 | clk_set_rate(rs->spiclk, 2 * rs->speed); | |
548 | rs->max_freq = clk_get_rate(rs->spiclk); | |
549 | } | |
550 | ||
64e36824 | 551 | /* div doesn't support odd number */ |
754ec43c | 552 | div = DIV_ROUND_UP(rs->max_freq, rs->speed); |
64e36824 | 553 | div = (div + 1) & 0xfffe; |
554 | ||
76b17e6e JW |
555 | /* Rx sample delay is expressed in parent clock cycles (max 3) */ |
556 | rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8), | |
557 | 1000000000 >> 8); | |
558 | if (!rsd && rs->rsd_nsecs) { | |
559 | pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n", | |
560 | rs->max_freq, rs->rsd_nsecs); | |
561 | } else if (rsd > 3) { | |
562 | rsd = 3; | |
563 | pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n", | |
564 | rs->max_freq, rs->rsd_nsecs, | |
565 | rsd * 1000000000U / rs->max_freq); | |
566 | } | |
567 | cr0 |= rsd << CR0_RSD_OFFSET; | |
568 | ||
64e36824 | 569 | writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); |
570 | ||
571 | writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); | |
572 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
573 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); | |
574 | ||
575 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR); | |
576 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR); | |
577 | writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); | |
578 | ||
579 | spi_set_clk(rs, div); | |
580 | ||
5dcc44ed | 581 | dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div); |
64e36824 | 582 | } |
583 | ||
5185a81c BN |
584 | static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) |
585 | { | |
586 | return ROCKCHIP_SPI_MAX_TRANLEN; | |
587 | } | |
588 | ||
5dcc44ed AK |
589 | static int rockchip_spi_transfer_one( |
590 | struct spi_master *master, | |
64e36824 | 591 | struct spi_device *spi, |
592 | struct spi_transfer *xfer) | |
593 | { | |
4dc0dd83 | 594 | int ret = 0; |
64e36824 | 595 | struct rockchip_spi *rs = spi_master_get_devdata(master); |
596 | ||
62946172 DA |
597 | WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && |
598 | (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); | |
64e36824 | 599 | |
600 | if (!xfer->tx_buf && !xfer->rx_buf) { | |
601 | dev_err(rs->dev, "No buffer for transfer\n"); | |
602 | return -EINVAL; | |
603 | } | |
604 | ||
5185a81c BN |
605 | if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) { |
606 | dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len); | |
607 | return -EINVAL; | |
608 | } | |
609 | ||
64e36824 | 610 | rs->speed = xfer->speed_hz; |
611 | rs->bpw = xfer->bits_per_word; | |
612 | rs->n_bytes = rs->bpw >> 3; | |
613 | ||
614 | rs->tx = xfer->tx_buf; | |
615 | rs->tx_end = rs->tx + xfer->len; | |
616 | rs->rx = xfer->rx_buf; | |
617 | rs->rx_end = rs->rx + xfer->len; | |
618 | rs->len = xfer->len; | |
619 | ||
620 | rs->tx_sg = xfer->tx_sg; | |
621 | rs->rx_sg = xfer->rx_sg; | |
622 | ||
64e36824 | 623 | if (rs->tx && rs->rx) |
624 | rs->tmode = CR0_XFM_TR; | |
625 | else if (rs->tx) | |
626 | rs->tmode = CR0_XFM_TO; | |
627 | else if (rs->rx) | |
628 | rs->tmode = CR0_XFM_RO; | |
629 | ||
a24e70c0 | 630 | /* we need prepare dma before spi was enabled */ |
c28be31b | 631 | if (master->can_dma && master->can_dma(master, spi, xfer)) |
64e36824 | 632 | rs->use_dma = 1; |
c28be31b | 633 | else |
64e36824 | 634 | rs->use_dma = 0; |
635 | ||
636 | rockchip_spi_config(rs); | |
637 | ||
c28be31b AK |
638 | if (rs->use_dma) { |
639 | if (rs->tmode == CR0_XFM_RO) { | |
640 | /* rx: dma must be prepared first */ | |
ea984911 | 641 | ret = rockchip_spi_prepare_dma(rs); |
c28be31b AK |
642 | spi_enable_chip(rs, 1); |
643 | } else { | |
644 | /* tx or tr: spi must be enabled first */ | |
645 | spi_enable_chip(rs, 1); | |
ea984911 | 646 | ret = rockchip_spi_prepare_dma(rs); |
c28be31b | 647 | } |
4dc0dd83 TV |
648 | /* successful DMA prepare means the transfer is in progress */ |
649 | ret = ret ? ret : 1; | |
c28be31b AK |
650 | } else { |
651 | spi_enable_chip(rs, 1); | |
64e36824 | 652 | ret = rockchip_spi_pio_transfer(rs); |
c28be31b | 653 | } |
64e36824 | 654 | |
655 | return ret; | |
656 | } | |
657 | ||
658 | static bool rockchip_spi_can_dma(struct spi_master *master, | |
5dcc44ed AK |
659 | struct spi_device *spi, |
660 | struct spi_transfer *xfer) | |
64e36824 | 661 | { |
662 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
663 | ||
664 | return (xfer->len > rs->fifo_len); | |
665 | } | |
666 | ||
667 | static int rockchip_spi_probe(struct platform_device *pdev) | |
668 | { | |
669 | int ret = 0; | |
670 | struct rockchip_spi *rs; | |
671 | struct spi_master *master; | |
672 | struct resource *mem; | |
76b17e6e | 673 | u32 rsd_nsecs; |
64e36824 | 674 | |
675 | master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi)); | |
5dcc44ed | 676 | if (!master) |
64e36824 | 677 | return -ENOMEM; |
5dcc44ed | 678 | |
64e36824 | 679 | platform_set_drvdata(pdev, master); |
680 | ||
681 | rs = spi_master_get_devdata(master); | |
64e36824 | 682 | |
683 | /* Get basic io resource and map it */ | |
684 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
685 | rs->regs = devm_ioremap_resource(&pdev->dev, mem); | |
686 | if (IS_ERR(rs->regs)) { | |
64e36824 | 687 | ret = PTR_ERR(rs->regs); |
c351587e | 688 | goto err_put_master; |
64e36824 | 689 | } |
690 | ||
691 | rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | |
692 | if (IS_ERR(rs->apb_pclk)) { | |
693 | dev_err(&pdev->dev, "Failed to get apb_pclk\n"); | |
694 | ret = PTR_ERR(rs->apb_pclk); | |
c351587e | 695 | goto err_put_master; |
64e36824 | 696 | } |
697 | ||
698 | rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); | |
699 | if (IS_ERR(rs->spiclk)) { | |
700 | dev_err(&pdev->dev, "Failed to get spi_pclk\n"); | |
701 | ret = PTR_ERR(rs->spiclk); | |
c351587e | 702 | goto err_put_master; |
64e36824 | 703 | } |
704 | ||
705 | ret = clk_prepare_enable(rs->apb_pclk); | |
706 | if (ret) { | |
707 | dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); | |
c351587e | 708 | goto err_put_master; |
64e36824 | 709 | } |
710 | ||
711 | ret = clk_prepare_enable(rs->spiclk); | |
712 | if (ret) { | |
713 | dev_err(&pdev->dev, "Failed to enable spi_clk\n"); | |
c351587e | 714 | goto err_disable_apbclk; |
64e36824 | 715 | } |
716 | ||
717 | spi_enable_chip(rs, 0); | |
718 | ||
719 | rs->type = SSI_MOTO_SPI; | |
720 | rs->master = master; | |
721 | rs->dev = &pdev->dev; | |
722 | rs->max_freq = clk_get_rate(rs->spiclk); | |
723 | ||
76b17e6e JW |
724 | if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", |
725 | &rsd_nsecs)) | |
726 | rs->rsd_nsecs = rsd_nsecs; | |
727 | ||
64e36824 | 728 | rs->fifo_len = get_fifo_len(rs); |
729 | if (!rs->fifo_len) { | |
730 | dev_err(&pdev->dev, "Failed to get fifo length\n"); | |
db7e8d90 | 731 | ret = -EINVAL; |
c351587e | 732 | goto err_disable_spiclk; |
64e36824 | 733 | } |
734 | ||
735 | spin_lock_init(&rs->lock); | |
736 | ||
737 | pm_runtime_set_active(&pdev->dev); | |
738 | pm_runtime_enable(&pdev->dev); | |
739 | ||
740 | master->auto_runtime_pm = true; | |
741 | master->bus_num = pdev->id; | |
ee780997 | 742 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
aa099382 | 743 | master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM; |
64e36824 | 744 | master->dev.of_node = pdev->dev.of_node; |
745 | master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); | |
746 | ||
747 | master->set_cs = rockchip_spi_set_cs; | |
748 | master->prepare_message = rockchip_spi_prepare_message; | |
749 | master->unprepare_message = rockchip_spi_unprepare_message; | |
750 | master->transfer_one = rockchip_spi_transfer_one; | |
5185a81c | 751 | master->max_transfer_size = rockchip_spi_max_transfer_size; |
2291793c | 752 | master->handle_err = rockchip_spi_handle_err; |
c863795c | 753 | master->flags = SPI_MASTER_GPIO_SS; |
64e36824 | 754 | |
e4c0e06f SL |
755 | rs->dma_tx.ch = dma_request_chan(rs->dev, "tx"); |
756 | if (IS_ERR(rs->dma_tx.ch)) { | |
61cadcf4 SL |
757 | /* Check tx to see if we need defer probing driver */ |
758 | if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) { | |
759 | ret = -EPROBE_DEFER; | |
c351587e | 760 | goto err_disable_pm_runtime; |
61cadcf4 | 761 | } |
64e36824 | 762 | dev_warn(rs->dev, "Failed to request TX DMA channel\n"); |
e4c0e06f | 763 | rs->dma_tx.ch = NULL; |
61cadcf4 | 764 | } |
64e36824 | 765 | |
e4c0e06f SL |
766 | rs->dma_rx.ch = dma_request_chan(rs->dev, "rx"); |
767 | if (IS_ERR(rs->dma_rx.ch)) { | |
768 | if (PTR_ERR(rs->dma_rx.ch) == -EPROBE_DEFER) { | |
e4c0e06f | 769 | ret = -EPROBE_DEFER; |
5de7ed0c | 770 | goto err_free_dma_tx; |
64e36824 | 771 | } |
772 | dev_warn(rs->dev, "Failed to request RX DMA channel\n"); | |
e4c0e06f | 773 | rs->dma_rx.ch = NULL; |
64e36824 | 774 | } |
775 | ||
776 | if (rs->dma_tx.ch && rs->dma_rx.ch) { | |
80abf888 | 777 | dma_get_slave_caps(rs->dma_rx.ch, &(rs->dma_caps)); |
64e36824 | 778 | rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR); |
779 | rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR); | |
780 | rs->dma_tx.direction = DMA_MEM_TO_DEV; | |
0ac7a490 | 781 | rs->dma_rx.direction = DMA_DEV_TO_MEM; |
64e36824 | 782 | |
783 | master->can_dma = rockchip_spi_can_dma; | |
784 | master->dma_tx = rs->dma_tx.ch; | |
785 | master->dma_rx = rs->dma_rx.ch; | |
786 | } | |
787 | ||
788 | ret = devm_spi_register_master(&pdev->dev, master); | |
789 | if (ret) { | |
790 | dev_err(&pdev->dev, "Failed to register master\n"); | |
c351587e | 791 | goto err_free_dma_rx; |
64e36824 | 792 | } |
793 | ||
64e36824 | 794 | return 0; |
795 | ||
c351587e | 796 | err_free_dma_rx: |
64e36824 | 797 | if (rs->dma_rx.ch) |
798 | dma_release_channel(rs->dma_rx.ch); | |
5de7ed0c DC |
799 | err_free_dma_tx: |
800 | if (rs->dma_tx.ch) | |
801 | dma_release_channel(rs->dma_tx.ch); | |
c351587e JC |
802 | err_disable_pm_runtime: |
803 | pm_runtime_disable(&pdev->dev); | |
804 | err_disable_spiclk: | |
64e36824 | 805 | clk_disable_unprepare(rs->spiclk); |
c351587e | 806 | err_disable_apbclk: |
64e36824 | 807 | clk_disable_unprepare(rs->apb_pclk); |
c351587e | 808 | err_put_master: |
64e36824 | 809 | spi_master_put(master); |
810 | ||
811 | return ret; | |
812 | } | |
813 | ||
814 | static int rockchip_spi_remove(struct platform_device *pdev) | |
815 | { | |
816 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); | |
817 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
818 | ||
819 | pm_runtime_disable(&pdev->dev); | |
820 | ||
821 | clk_disable_unprepare(rs->spiclk); | |
822 | clk_disable_unprepare(rs->apb_pclk); | |
823 | ||
824 | if (rs->dma_tx.ch) | |
825 | dma_release_channel(rs->dma_tx.ch); | |
826 | if (rs->dma_rx.ch) | |
827 | dma_release_channel(rs->dma_rx.ch); | |
828 | ||
844c9f47 SL |
829 | spi_master_put(master); |
830 | ||
64e36824 | 831 | return 0; |
832 | } | |
833 | ||
834 | #ifdef CONFIG_PM_SLEEP | |
835 | static int rockchip_spi_suspend(struct device *dev) | |
836 | { | |
837 | int ret = 0; | |
838 | struct spi_master *master = dev_get_drvdata(dev); | |
839 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
840 | ||
841 | ret = spi_master_suspend(rs->master); | |
842 | if (ret) | |
843 | return ret; | |
844 | ||
845 | if (!pm_runtime_suspended(dev)) { | |
846 | clk_disable_unprepare(rs->spiclk); | |
847 | clk_disable_unprepare(rs->apb_pclk); | |
848 | } | |
849 | ||
23e291c2 BN |
850 | pinctrl_pm_select_sleep_state(dev); |
851 | ||
64e36824 | 852 | return ret; |
853 | } | |
854 | ||
855 | static int rockchip_spi_resume(struct device *dev) | |
856 | { | |
857 | int ret = 0; | |
858 | struct spi_master *master = dev_get_drvdata(dev); | |
859 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
860 | ||
23e291c2 BN |
861 | pinctrl_pm_select_default_state(dev); |
862 | ||
64e36824 | 863 | if (!pm_runtime_suspended(dev)) { |
864 | ret = clk_prepare_enable(rs->apb_pclk); | |
865 | if (ret < 0) | |
866 | return ret; | |
867 | ||
868 | ret = clk_prepare_enable(rs->spiclk); | |
869 | if (ret < 0) { | |
870 | clk_disable_unprepare(rs->apb_pclk); | |
871 | return ret; | |
872 | } | |
873 | } | |
874 | ||
875 | ret = spi_master_resume(rs->master); | |
876 | if (ret < 0) { | |
877 | clk_disable_unprepare(rs->spiclk); | |
878 | clk_disable_unprepare(rs->apb_pclk); | |
879 | } | |
880 | ||
881 | return ret; | |
882 | } | |
883 | #endif /* CONFIG_PM_SLEEP */ | |
884 | ||
ec833050 | 885 | #ifdef CONFIG_PM |
64e36824 | 886 | static int rockchip_spi_runtime_suspend(struct device *dev) |
887 | { | |
888 | struct spi_master *master = dev_get_drvdata(dev); | |
889 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
890 | ||
891 | clk_disable_unprepare(rs->spiclk); | |
892 | clk_disable_unprepare(rs->apb_pclk); | |
893 | ||
894 | return 0; | |
895 | } | |
896 | ||
897 | static int rockchip_spi_runtime_resume(struct device *dev) | |
898 | { | |
899 | int ret; | |
900 | struct spi_master *master = dev_get_drvdata(dev); | |
901 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
902 | ||
903 | ret = clk_prepare_enable(rs->apb_pclk); | |
904 | if (ret) | |
905 | return ret; | |
906 | ||
907 | ret = clk_prepare_enable(rs->spiclk); | |
908 | if (ret) | |
909 | clk_disable_unprepare(rs->apb_pclk); | |
910 | ||
911 | return ret; | |
912 | } | |
ec833050 | 913 | #endif /* CONFIG_PM */ |
64e36824 | 914 | |
915 | static const struct dev_pm_ops rockchip_spi_pm = { | |
916 | SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) | |
917 | SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, | |
918 | rockchip_spi_runtime_resume, NULL) | |
919 | }; | |
920 | ||
921 | static const struct of_device_id rockchip_spi_dt_match[] = { | |
aa29ea3d | 922 | { .compatible = "rockchip,rk3036-spi", }, |
64e36824 | 923 | { .compatible = "rockchip,rk3066-spi", }, |
b839b785 | 924 | { .compatible = "rockchip,rk3188-spi", }, |
aa29ea3d | 925 | { .compatible = "rockchip,rk3228-spi", }, |
b839b785 | 926 | { .compatible = "rockchip,rk3288-spi", }, |
aa29ea3d | 927 | { .compatible = "rockchip,rk3368-spi", }, |
9b7a5622 | 928 | { .compatible = "rockchip,rk3399-spi", }, |
64e36824 | 929 | { }, |
930 | }; | |
931 | MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); | |
932 | ||
933 | static struct platform_driver rockchip_spi_driver = { | |
934 | .driver = { | |
935 | .name = DRIVER_NAME, | |
64e36824 | 936 | .pm = &rockchip_spi_pm, |
937 | .of_match_table = of_match_ptr(rockchip_spi_dt_match), | |
938 | }, | |
939 | .probe = rockchip_spi_probe, | |
940 | .remove = rockchip_spi_remove, | |
941 | }; | |
942 | ||
943 | module_platform_driver(rockchip_spi_driver); | |
944 | ||
5dcc44ed | 945 | MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); |
64e36824 | 946 | MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); |
947 | MODULE_LICENSE("GPL v2"); |