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2025cf9e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
64e36824 | 2 | /* |
3 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
5dcc44ed | 4 | * Author: Addy Ke <addy.ke@rock-chips.com> |
64e36824 | 5 | */ |
6 | ||
64e36824 | 7 | #include <linux/clk.h> |
ec5c5d8a | 8 | #include <linux/dmaengine.h> |
8af0c18a | 9 | #include <linux/interrupt.h> |
ec5c5d8a SL |
10 | #include <linux/module.h> |
11 | #include <linux/of.h> | |
23e291c2 | 12 | #include <linux/pinctrl/consumer.h> |
64e36824 | 13 | #include <linux/platform_device.h> |
64e36824 | 14 | #include <linux/spi/spi.h> |
64e36824 | 15 | #include <linux/pm_runtime.h> |
ec5c5d8a | 16 | #include <linux/scatterlist.h> |
64e36824 | 17 | |
18 | #define DRIVER_NAME "rockchip-spi" | |
19 | ||
aa099382 JC |
20 | #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ |
21 | writel_relaxed(readl_relaxed(reg) & ~(bits), reg) | |
22 | #define ROCKCHIP_SPI_SET_BITS(reg, bits) \ | |
23 | writel_relaxed(readl_relaxed(reg) | (bits), reg) | |
24 | ||
64e36824 | 25 | /* SPI register offsets */ |
26 | #define ROCKCHIP_SPI_CTRLR0 0x0000 | |
27 | #define ROCKCHIP_SPI_CTRLR1 0x0004 | |
28 | #define ROCKCHIP_SPI_SSIENR 0x0008 | |
29 | #define ROCKCHIP_SPI_SER 0x000c | |
30 | #define ROCKCHIP_SPI_BAUDR 0x0010 | |
31 | #define ROCKCHIP_SPI_TXFTLR 0x0014 | |
32 | #define ROCKCHIP_SPI_RXFTLR 0x0018 | |
33 | #define ROCKCHIP_SPI_TXFLR 0x001c | |
34 | #define ROCKCHIP_SPI_RXFLR 0x0020 | |
35 | #define ROCKCHIP_SPI_SR 0x0024 | |
36 | #define ROCKCHIP_SPI_IPR 0x0028 | |
37 | #define ROCKCHIP_SPI_IMR 0x002c | |
38 | #define ROCKCHIP_SPI_ISR 0x0030 | |
39 | #define ROCKCHIP_SPI_RISR 0x0034 | |
40 | #define ROCKCHIP_SPI_ICR 0x0038 | |
41 | #define ROCKCHIP_SPI_DMACR 0x003c | |
13a96935 JL |
42 | #define ROCKCHIP_SPI_DMATDLR 0x0040 |
43 | #define ROCKCHIP_SPI_DMARDLR 0x0044 | |
44 | #define ROCKCHIP_SPI_VERSION 0x0048 | |
64e36824 | 45 | #define ROCKCHIP_SPI_TXDR 0x0400 |
46 | #define ROCKCHIP_SPI_RXDR 0x0800 | |
47 | ||
48 | /* Bit fields in CTRLR0 */ | |
49 | #define CR0_DFS_OFFSET 0 | |
65498c6a ERB |
50 | #define CR0_DFS_4BIT 0x0 |
51 | #define CR0_DFS_8BIT 0x1 | |
52 | #define CR0_DFS_16BIT 0x2 | |
64e36824 | 53 | |
54 | #define CR0_CFS_OFFSET 2 | |
55 | ||
56 | #define CR0_SCPH_OFFSET 6 | |
57 | ||
58 | #define CR0_SCPOL_OFFSET 7 | |
59 | ||
60 | #define CR0_CSM_OFFSET 8 | |
61 | #define CR0_CSM_KEEP 0x0 | |
62 | /* ss_n be high for half sclk_out cycles */ | |
63 | #define CR0_CSM_HALF 0X1 | |
64 | /* ss_n be high for one sclk_out cycle */ | |
65 | #define CR0_CSM_ONE 0x2 | |
66 | ||
67 | /* ss_n to sclk_out delay */ | |
68 | #define CR0_SSD_OFFSET 10 | |
69 | /* | |
70 | * The period between ss_n active and | |
71 | * sclk_out active is half sclk_out cycles | |
72 | */ | |
73 | #define CR0_SSD_HALF 0x0 | |
74 | /* | |
75 | * The period between ss_n active and | |
76 | * sclk_out active is one sclk_out cycle | |
77 | */ | |
78 | #define CR0_SSD_ONE 0x1 | |
79 | ||
80 | #define CR0_EM_OFFSET 11 | |
81 | #define CR0_EM_LITTLE 0x0 | |
82 | #define CR0_EM_BIG 0x1 | |
83 | ||
84 | #define CR0_FBM_OFFSET 12 | |
85 | #define CR0_FBM_MSB 0x0 | |
86 | #define CR0_FBM_LSB 0x1 | |
87 | ||
88 | #define CR0_BHT_OFFSET 13 | |
89 | #define CR0_BHT_16BIT 0x0 | |
90 | #define CR0_BHT_8BIT 0x1 | |
91 | ||
92 | #define CR0_RSD_OFFSET 14 | |
74b7efa8 | 93 | #define CR0_RSD_MAX 0x3 |
64e36824 | 94 | |
95 | #define CR0_FRF_OFFSET 16 | |
96 | #define CR0_FRF_SPI 0x0 | |
97 | #define CR0_FRF_SSP 0x1 | |
98 | #define CR0_FRF_MICROWIRE 0x2 | |
99 | ||
100 | #define CR0_XFM_OFFSET 18 | |
101 | #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) | |
102 | #define CR0_XFM_TR 0x0 | |
103 | #define CR0_XFM_TO 0x1 | |
104 | #define CR0_XFM_RO 0x2 | |
105 | ||
106 | #define CR0_OPM_OFFSET 20 | |
107 | #define CR0_OPM_MASTER 0x0 | |
108 | #define CR0_OPM_SLAVE 0x1 | |
109 | ||
110 | #define CR0_MTM_OFFSET 0x21 | |
111 | ||
112 | /* Bit fields in SER, 2bit */ | |
113 | #define SER_MASK 0x3 | |
114 | ||
420b82f8 ERB |
115 | /* Bit fields in BAUDR */ |
116 | #define BAUDR_SCKDV_MIN 2 | |
117 | #define BAUDR_SCKDV_MAX 65534 | |
118 | ||
64e36824 | 119 | /* Bit fields in SR, 5bit */ |
120 | #define SR_MASK 0x1f | |
121 | #define SR_BUSY (1 << 0) | |
122 | #define SR_TF_FULL (1 << 1) | |
123 | #define SR_TF_EMPTY (1 << 2) | |
124 | #define SR_RF_EMPTY (1 << 3) | |
125 | #define SR_RF_FULL (1 << 4) | |
126 | ||
127 | /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ | |
128 | #define INT_MASK 0x1f | |
129 | #define INT_TF_EMPTY (1 << 0) | |
130 | #define INT_TF_OVERFLOW (1 << 1) | |
131 | #define INT_RF_UNDERFLOW (1 << 2) | |
132 | #define INT_RF_OVERFLOW (1 << 3) | |
133 | #define INT_RF_FULL (1 << 4) | |
134 | ||
135 | /* Bit fields in ICR, 4bit */ | |
136 | #define ICR_MASK 0x0f | |
137 | #define ICR_ALL (1 << 0) | |
138 | #define ICR_RF_UNDERFLOW (1 << 1) | |
139 | #define ICR_RF_OVERFLOW (1 << 2) | |
140 | #define ICR_TF_OVERFLOW (1 << 3) | |
141 | ||
142 | /* Bit fields in DMACR */ | |
143 | #define RF_DMA_EN (1 << 0) | |
144 | #define TF_DMA_EN (1 << 1) | |
145 | ||
fab3e487 ERB |
146 | /* Driver state flags */ |
147 | #define RXDMA (1 << 0) | |
148 | #define TXDMA (1 << 1) | |
64e36824 | 149 | |
f9cfd522 | 150 | /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ |
420b82f8 | 151 | #define MAX_SCLK_OUT 50000000U |
f9cfd522 | 152 | |
5185a81c BN |
153 | /* |
154 | * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, | |
155 | * the controller seems to hang when given 0x10000, so stick with this for now. | |
156 | */ | |
157 | #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff | |
158 | ||
aa099382 | 159 | #define ROCKCHIP_SPI_MAX_CS_NUM 2 |
13a96935 JL |
160 | #define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002 |
161 | #define ROCKCHIP_SPI_VER2_TYPE2 0x00110002 | |
aa099382 | 162 | |
64e36824 | 163 | struct rockchip_spi { |
164 | struct device *dev; | |
64e36824 | 165 | |
166 | struct clk *spiclk; | |
167 | struct clk *apb_pclk; | |
168 | ||
169 | void __iomem *regs; | |
eee06a9e ERB |
170 | dma_addr_t dma_addr_rx; |
171 | dma_addr_t dma_addr_tx; | |
fab3e487 | 172 | |
01b59ce5 ERB |
173 | const void *tx; |
174 | void *rx; | |
175 | unsigned int tx_left; | |
176 | unsigned int rx_left; | |
177 | ||
fab3e487 ERB |
178 | atomic_t state; |
179 | ||
64e36824 | 180 | /*depth of the FIFO buffer */ |
181 | u32 fifo_len; | |
420b82f8 ERB |
182 | /* frequency of spiclk */ |
183 | u32 freq; | |
64e36824 | 184 | |
64e36824 | 185 | u8 n_bytes; |
74b7efa8 | 186 | u8 rsd; |
64e36824 | 187 | |
aa099382 | 188 | bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM]; |
d065f41a CR |
189 | |
190 | bool slave_abort; | |
64e36824 | 191 | }; |
192 | ||
30688e4e | 193 | static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable) |
64e36824 | 194 | { |
30688e4e | 195 | writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); |
64e36824 | 196 | } |
197 | ||
2df08e78 AK |
198 | static inline void wait_for_idle(struct rockchip_spi *rs) |
199 | { | |
200 | unsigned long timeout = jiffies + msecs_to_jiffies(5); | |
201 | ||
202 | do { | |
203 | if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) | |
204 | return; | |
64bc0110 | 205 | } while (!time_after(jiffies, timeout)); |
2df08e78 AK |
206 | |
207 | dev_warn(rs->dev, "spi controller is in busy state!\n"); | |
208 | } | |
209 | ||
64e36824 | 210 | static u32 get_fifo_len(struct rockchip_spi *rs) |
211 | { | |
13a96935 | 212 | u32 ver; |
64e36824 | 213 | |
13a96935 | 214 | ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION); |
64e36824 | 215 | |
13a96935 JL |
216 | switch (ver) { |
217 | case ROCKCHIP_SPI_VER2_TYPE1: | |
218 | case ROCKCHIP_SPI_VER2_TYPE2: | |
219 | return 64; | |
220 | default: | |
221 | return 32; | |
222 | } | |
64e36824 | 223 | } |
224 | ||
64e36824 | 225 | static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) |
226 | { | |
d66571a2 CR |
227 | struct spi_controller *ctlr = spi->controller; |
228 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); | |
aa099382 | 229 | bool cs_asserted = !enable; |
b920cc31 | 230 | |
aa099382 JC |
231 | /* Return immediately for no-op */ |
232 | if (cs_asserted == rs->cs_asserted[spi->chip_select]) | |
233 | return; | |
64e36824 | 234 | |
aa099382 JC |
235 | if (cs_asserted) { |
236 | /* Keep things powered as long as CS is asserted */ | |
237 | pm_runtime_get_sync(rs->dev); | |
64e36824 | 238 | |
aa099382 JC |
239 | ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, |
240 | BIT(spi->chip_select)); | |
241 | } else { | |
242 | ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, | |
243 | BIT(spi->chip_select)); | |
64e36824 | 244 | |
aa099382 JC |
245 | /* Drop reference from when we first asserted CS */ |
246 | pm_runtime_put(rs->dev); | |
247 | } | |
b920cc31 | 248 | |
aa099382 | 249 | rs->cs_asserted[spi->chip_select] = cs_asserted; |
64e36824 | 250 | } |
251 | ||
d66571a2 | 252 | static void rockchip_spi_handle_err(struct spi_controller *ctlr, |
2291793c | 253 | struct spi_message *msg) |
64e36824 | 254 | { |
d66571a2 | 255 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); |
64e36824 | 256 | |
ce386100 ERB |
257 | /* stop running spi transfer |
258 | * this also flushes both rx and tx fifos | |
5dcc44ed | 259 | */ |
ce386100 ERB |
260 | spi_enable_chip(rs, false); |
261 | ||
01b59ce5 ERB |
262 | /* make sure all interrupts are masked */ |
263 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); | |
264 | ||
fab3e487 | 265 | if (atomic_read(&rs->state) & TXDMA) |
d66571a2 | 266 | dmaengine_terminate_async(ctlr->dma_tx); |
64e36824 | 267 | |
ce386100 | 268 | if (atomic_read(&rs->state) & RXDMA) |
d66571a2 | 269 | dmaengine_terminate_async(ctlr->dma_rx); |
64e36824 | 270 | } |
271 | ||
272 | static void rockchip_spi_pio_writer(struct rockchip_spi *rs) | |
273 | { | |
01b59ce5 ERB |
274 | u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); |
275 | u32 words = min(rs->tx_left, tx_free); | |
276 | ||
277 | rs->tx_left -= words; | |
278 | for (; words; words--) { | |
279 | u32 txw; | |
64e36824 | 280 | |
64e36824 | 281 | if (rs->n_bytes == 1) |
01b59ce5 | 282 | txw = *(u8 *)rs->tx; |
64e36824 | 283 | else |
01b59ce5 | 284 | txw = *(u16 *)rs->tx; |
64e36824 | 285 | |
286 | writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); | |
287 | rs->tx += rs->n_bytes; | |
288 | } | |
289 | } | |
290 | ||
291 | static void rockchip_spi_pio_reader(struct rockchip_spi *rs) | |
292 | { | |
01b59ce5 | 293 | u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); |
4294e4ac | 294 | u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0; |
01b59ce5 ERB |
295 | |
296 | /* the hardware doesn't allow us to change fifo threshold | |
297 | * level while spi is enabled, so instead make sure to leave | |
298 | * enough words in the rx fifo to get the last interrupt | |
299 | * exactly when all words have been received | |
300 | */ | |
301 | if (rx_left) { | |
302 | u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1; | |
303 | ||
304 | if (rx_left < ftl) { | |
305 | rx_left = ftl; | |
306 | words = rs->rx_left - rx_left; | |
307 | } | |
308 | } | |
309 | ||
310 | rs->rx_left = rx_left; | |
311 | for (; words; words--) { | |
312 | u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); | |
313 | ||
314 | if (!rs->rx) | |
315 | continue; | |
64e36824 | 316 | |
64e36824 | 317 | if (rs->n_bytes == 1) |
01b59ce5 | 318 | *(u8 *)rs->rx = (u8)rxw; |
64e36824 | 319 | else |
01b59ce5 | 320 | *(u16 *)rs->rx = (u16)rxw; |
64e36824 | 321 | rs->rx += rs->n_bytes; |
5dcc44ed | 322 | } |
64e36824 | 323 | } |
324 | ||
01b59ce5 | 325 | static irqreturn_t rockchip_spi_isr(int irq, void *dev_id) |
64e36824 | 326 | { |
d66571a2 CR |
327 | struct spi_controller *ctlr = dev_id; |
328 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); | |
64e36824 | 329 | |
01b59ce5 ERB |
330 | if (rs->tx_left) |
331 | rockchip_spi_pio_writer(rs); | |
a3c17402 | 332 | |
01b59ce5 ERB |
333 | rockchip_spi_pio_reader(rs); |
334 | if (!rs->rx_left) { | |
335 | spi_enable_chip(rs, false); | |
336 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); | |
d66571a2 | 337 | spi_finalize_current_transfer(ctlr); |
01b59ce5 | 338 | } |
64e36824 | 339 | |
01b59ce5 ERB |
340 | return IRQ_HANDLED; |
341 | } | |
64e36824 | 342 | |
01b59ce5 ERB |
343 | static int rockchip_spi_prepare_irq(struct rockchip_spi *rs, |
344 | struct spi_transfer *xfer) | |
345 | { | |
346 | rs->tx = xfer->tx_buf; | |
347 | rs->rx = xfer->rx_buf; | |
348 | rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0; | |
349 | rs->rx_left = xfer->len / rs->n_bytes; | |
64e36824 | 350 | |
01b59ce5 ERB |
351 | writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR); |
352 | spi_enable_chip(rs, true); | |
2df08e78 | 353 | |
01b59ce5 ERB |
354 | if (rs->tx_left) |
355 | rockchip_spi_pio_writer(rs); | |
c28be31b | 356 | |
01b59ce5 ERB |
357 | /* 1 means the transfer is in progress */ |
358 | return 1; | |
64e36824 | 359 | } |
360 | ||
361 | static void rockchip_spi_dma_rxcb(void *data) | |
362 | { | |
d66571a2 CR |
363 | struct spi_controller *ctlr = data; |
364 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); | |
fab3e487 | 365 | int state = atomic_fetch_andnot(RXDMA, &rs->state); |
64e36824 | 366 | |
d065f41a | 367 | if (state & TXDMA && !rs->slave_abort) |
fab3e487 | 368 | return; |
64e36824 | 369 | |
fab3e487 | 370 | spi_enable_chip(rs, false); |
d66571a2 | 371 | spi_finalize_current_transfer(ctlr); |
64e36824 | 372 | } |
373 | ||
374 | static void rockchip_spi_dma_txcb(void *data) | |
375 | { | |
d66571a2 CR |
376 | struct spi_controller *ctlr = data; |
377 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); | |
fab3e487 ERB |
378 | int state = atomic_fetch_andnot(TXDMA, &rs->state); |
379 | ||
d065f41a | 380 | if (state & RXDMA && !rs->slave_abort) |
fab3e487 | 381 | return; |
64e36824 | 382 | |
2df08e78 AK |
383 | /* Wait until the FIFO data completely. */ |
384 | wait_for_idle(rs); | |
385 | ||
fab3e487 | 386 | spi_enable_chip(rs, false); |
d66571a2 | 387 | spi_finalize_current_transfer(ctlr); |
64e36824 | 388 | } |
389 | ||
4d9ca632 JL |
390 | static u32 rockchip_spi_calc_burst_size(u32 data_len) |
391 | { | |
392 | u32 i; | |
393 | ||
394 | /* burst size: 1, 2, 4, 8 */ | |
395 | for (i = 1; i < 8; i <<= 1) { | |
396 | if (data_len & i) | |
397 | break; | |
398 | } | |
399 | ||
400 | return i; | |
401 | } | |
402 | ||
fc1ad8ee | 403 | static int rockchip_spi_prepare_dma(struct rockchip_spi *rs, |
d66571a2 | 404 | struct spi_controller *ctlr, struct spi_transfer *xfer) |
64e36824 | 405 | { |
64e36824 | 406 | struct dma_async_tx_descriptor *rxdesc, *txdesc; |
407 | ||
fab3e487 | 408 | atomic_set(&rs->state, 0); |
64e36824 | 409 | |
97cf5669 | 410 | rxdesc = NULL; |
fc1ad8ee | 411 | if (xfer->rx_buf) { |
31bcb57b ERB |
412 | struct dma_slave_config rxconf = { |
413 | .direction = DMA_DEV_TO_MEM, | |
eee06a9e | 414 | .src_addr = rs->dma_addr_rx, |
31bcb57b | 415 | .src_addr_width = rs->n_bytes, |
4d9ca632 JL |
416 | .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / |
417 | rs->n_bytes), | |
31bcb57b ERB |
418 | }; |
419 | ||
d66571a2 | 420 | dmaengine_slave_config(ctlr->dma_rx, &rxconf); |
64e36824 | 421 | |
5dcc44ed | 422 | rxdesc = dmaengine_prep_slave_sg( |
d66571a2 | 423 | ctlr->dma_rx, |
fc1ad8ee | 424 | xfer->rx_sg.sgl, xfer->rx_sg.nents, |
d9071b7e | 425 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); |
ea984911 SL |
426 | if (!rxdesc) |
427 | return -EINVAL; | |
64e36824 | 428 | |
429 | rxdesc->callback = rockchip_spi_dma_rxcb; | |
d66571a2 | 430 | rxdesc->callback_param = ctlr; |
64e36824 | 431 | } |
432 | ||
97cf5669 | 433 | txdesc = NULL; |
fc1ad8ee | 434 | if (xfer->tx_buf) { |
31bcb57b ERB |
435 | struct dma_slave_config txconf = { |
436 | .direction = DMA_MEM_TO_DEV, | |
eee06a9e | 437 | .dst_addr = rs->dma_addr_tx, |
31bcb57b | 438 | .dst_addr_width = rs->n_bytes, |
47300728 | 439 | .dst_maxburst = rs->fifo_len / 4, |
31bcb57b ERB |
440 | }; |
441 | ||
d66571a2 | 442 | dmaengine_slave_config(ctlr->dma_tx, &txconf); |
64e36824 | 443 | |
5dcc44ed | 444 | txdesc = dmaengine_prep_slave_sg( |
d66571a2 | 445 | ctlr->dma_tx, |
fc1ad8ee | 446 | xfer->tx_sg.sgl, xfer->tx_sg.nents, |
d9071b7e | 447 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); |
ea984911 SL |
448 | if (!txdesc) { |
449 | if (rxdesc) | |
d66571a2 | 450 | dmaengine_terminate_sync(ctlr->dma_rx); |
ea984911 SL |
451 | return -EINVAL; |
452 | } | |
64e36824 | 453 | |
454 | txdesc->callback = rockchip_spi_dma_txcb; | |
d66571a2 | 455 | txdesc->callback_param = ctlr; |
64e36824 | 456 | } |
457 | ||
458 | /* rx must be started before tx due to spi instinct */ | |
97cf5669 | 459 | if (rxdesc) { |
fab3e487 | 460 | atomic_or(RXDMA, &rs->state); |
64e36824 | 461 | dmaengine_submit(rxdesc); |
d66571a2 | 462 | dma_async_issue_pending(ctlr->dma_rx); |
64e36824 | 463 | } |
464 | ||
30688e4e | 465 | spi_enable_chip(rs, true); |
a3c17402 | 466 | |
97cf5669 | 467 | if (txdesc) { |
fab3e487 | 468 | atomic_or(TXDMA, &rs->state); |
64e36824 | 469 | dmaengine_submit(txdesc); |
d66571a2 | 470 | dma_async_issue_pending(ctlr->dma_tx); |
64e36824 | 471 | } |
ea984911 | 472 | |
a3c17402 ERB |
473 | /* 1 means the transfer is in progress */ |
474 | return 1; | |
64e36824 | 475 | } |
476 | ||
fc1ad8ee | 477 | static void rockchip_spi_config(struct rockchip_spi *rs, |
eff0275e | 478 | struct spi_device *spi, struct spi_transfer *xfer, |
d065f41a | 479 | bool use_dma, bool slave_mode) |
64e36824 | 480 | { |
2410d6a3 ERB |
481 | u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET |
482 | | CR0_BHT_8BIT << CR0_BHT_OFFSET | |
483 | | CR0_SSD_ONE << CR0_SSD_OFFSET | |
484 | | CR0_EM_BIG << CR0_EM_OFFSET; | |
65498c6a ERB |
485 | u32 cr1; |
486 | u32 dmacr = 0; | |
64e36824 | 487 | |
d065f41a CR |
488 | if (slave_mode) |
489 | cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET; | |
490 | rs->slave_abort = false; | |
491 | ||
74b7efa8 | 492 | cr0 |= rs->rsd << CR0_RSD_OFFSET; |
fc1ad8ee | 493 | cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; |
04290192 ERB |
494 | if (spi->mode & SPI_LSB_FIRST) |
495 | cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; | |
fc1ad8ee ERB |
496 | |
497 | if (xfer->rx_buf && xfer->tx_buf) | |
498 | cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; | |
499 | else if (xfer->rx_buf) | |
500 | cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET; | |
01b59ce5 | 501 | else if (use_dma) |
fc1ad8ee | 502 | cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET; |
64e36824 | 503 | |
65498c6a ERB |
504 | switch (xfer->bits_per_word) { |
505 | case 4: | |
506 | cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET; | |
507 | cr1 = xfer->len - 1; | |
508 | break; | |
509 | case 8: | |
510 | cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET; | |
511 | cr1 = xfer->len - 1; | |
512 | break; | |
513 | case 16: | |
514 | cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET; | |
515 | cr1 = xfer->len / 2 - 1; | |
516 | break; | |
517 | default: | |
518 | /* we only whitelist 4, 8 and 16 bit words in | |
d66571a2 | 519 | * ctlr->bits_per_word_mask, so this shouldn't |
65498c6a ERB |
520 | * happen |
521 | */ | |
522 | unreachable(); | |
523 | } | |
524 | ||
eff0275e | 525 | if (use_dma) { |
fc1ad8ee | 526 | if (xfer->tx_buf) |
64e36824 | 527 | dmacr |= TF_DMA_EN; |
fc1ad8ee | 528 | if (xfer->rx_buf) |
64e36824 | 529 | dmacr |= RF_DMA_EN; |
530 | } | |
531 | ||
64e36824 | 532 | writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); |
65498c6a | 533 | writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1); |
04b37d2d | 534 | |
01b59ce5 ERB |
535 | /* unfortunately setting the fifo threshold level to generate an |
536 | * interrupt exactly when the fifo is full doesn't seem to work, | |
537 | * so we need the strict inequality here | |
538 | */ | |
539 | if (xfer->len < rs->fifo_len) | |
540 | writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); | |
541 | else | |
542 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); | |
64e36824 | 543 | |
47300728 | 544 | writel_relaxed(rs->fifo_len / 2, rs->regs + ROCKCHIP_SPI_DMATDLR); |
4d9ca632 JL |
545 | writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1, |
546 | rs->regs + ROCKCHIP_SPI_DMARDLR); | |
64e36824 | 547 | writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); |
548 | ||
420b82f8 ERB |
549 | /* the hardware only supports an even clock divisor, so |
550 | * round divisor = spiclk / speed up to nearest even number | |
551 | * so that the resulting speed is <= the requested speed | |
552 | */ | |
553 | writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz), | |
554 | rs->regs + ROCKCHIP_SPI_BAUDR); | |
64e36824 | 555 | } |
556 | ||
5185a81c BN |
557 | static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) |
558 | { | |
559 | return ROCKCHIP_SPI_MAX_TRANLEN; | |
560 | } | |
561 | ||
d065f41a CR |
562 | static int rockchip_spi_slave_abort(struct spi_controller *ctlr) |
563 | { | |
564 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); | |
565 | ||
566 | rs->slave_abort = true; | |
567 | complete(&ctlr->xfer_completion); | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
5dcc44ed | 572 | static int rockchip_spi_transfer_one( |
d66571a2 | 573 | struct spi_controller *ctlr, |
64e36824 | 574 | struct spi_device *spi, |
575 | struct spi_transfer *xfer) | |
576 | { | |
d66571a2 | 577 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); |
eff0275e | 578 | bool use_dma; |
64e36824 | 579 | |
62946172 DA |
580 | WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && |
581 | (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); | |
64e36824 | 582 | |
583 | if (!xfer->tx_buf && !xfer->rx_buf) { | |
584 | dev_err(rs->dev, "No buffer for transfer\n"); | |
585 | return -EINVAL; | |
586 | } | |
587 | ||
5185a81c BN |
588 | if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) { |
589 | dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len); | |
590 | return -EINVAL; | |
591 | } | |
592 | ||
65498c6a | 593 | rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2; |
64e36824 | 594 | |
d66571a2 | 595 | use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false; |
64e36824 | 596 | |
d065f41a | 597 | rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave); |
64e36824 | 598 | |
eff0275e | 599 | if (use_dma) |
d66571a2 | 600 | return rockchip_spi_prepare_dma(rs, ctlr, xfer); |
64e36824 | 601 | |
01b59ce5 | 602 | return rockchip_spi_prepare_irq(rs, xfer); |
64e36824 | 603 | } |
604 | ||
d66571a2 | 605 | static bool rockchip_spi_can_dma(struct spi_controller *ctlr, |
5dcc44ed AK |
606 | struct spi_device *spi, |
607 | struct spi_transfer *xfer) | |
64e36824 | 608 | { |
d66571a2 | 609 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); |
01b59ce5 | 610 | unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2; |
64e36824 | 611 | |
01b59ce5 ERB |
612 | /* if the numbor of spi words to transfer is less than the fifo |
613 | * length we can just fill the fifo and wait for a single irq, | |
614 | * so don't bother setting up dma | |
615 | */ | |
616 | return xfer->len / bytes_per_word >= rs->fifo_len; | |
64e36824 | 617 | } |
618 | ||
619 | static int rockchip_spi_probe(struct platform_device *pdev) | |
620 | { | |
43de979d | 621 | int ret; |
64e36824 | 622 | struct rockchip_spi *rs; |
d66571a2 | 623 | struct spi_controller *ctlr; |
64e36824 | 624 | struct resource *mem; |
d065f41a | 625 | struct device_node *np = pdev->dev.of_node; |
76b17e6e | 626 | u32 rsd_nsecs; |
d065f41a CR |
627 | bool slave_mode; |
628 | ||
629 | slave_mode = of_property_read_bool(np, "spi-slave"); | |
630 | ||
631 | if (slave_mode) | |
632 | ctlr = spi_alloc_slave(&pdev->dev, | |
633 | sizeof(struct rockchip_spi)); | |
634 | else | |
635 | ctlr = spi_alloc_master(&pdev->dev, | |
636 | sizeof(struct rockchip_spi)); | |
64e36824 | 637 | |
d66571a2 | 638 | if (!ctlr) |
64e36824 | 639 | return -ENOMEM; |
5dcc44ed | 640 | |
d66571a2 | 641 | platform_set_drvdata(pdev, ctlr); |
64e36824 | 642 | |
d66571a2 | 643 | rs = spi_controller_get_devdata(ctlr); |
d065f41a | 644 | ctlr->slave = slave_mode; |
64e36824 | 645 | |
646 | /* Get basic io resource and map it */ | |
647 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
648 | rs->regs = devm_ioremap_resource(&pdev->dev, mem); | |
649 | if (IS_ERR(rs->regs)) { | |
64e36824 | 650 | ret = PTR_ERR(rs->regs); |
d66571a2 | 651 | goto err_put_ctlr; |
64e36824 | 652 | } |
653 | ||
654 | rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | |
655 | if (IS_ERR(rs->apb_pclk)) { | |
656 | dev_err(&pdev->dev, "Failed to get apb_pclk\n"); | |
657 | ret = PTR_ERR(rs->apb_pclk); | |
d66571a2 | 658 | goto err_put_ctlr; |
64e36824 | 659 | } |
660 | ||
661 | rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); | |
662 | if (IS_ERR(rs->spiclk)) { | |
663 | dev_err(&pdev->dev, "Failed to get spi_pclk\n"); | |
664 | ret = PTR_ERR(rs->spiclk); | |
d66571a2 | 665 | goto err_put_ctlr; |
64e36824 | 666 | } |
667 | ||
668 | ret = clk_prepare_enable(rs->apb_pclk); | |
43de979d | 669 | if (ret < 0) { |
64e36824 | 670 | dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); |
d66571a2 | 671 | goto err_put_ctlr; |
64e36824 | 672 | } |
673 | ||
674 | ret = clk_prepare_enable(rs->spiclk); | |
43de979d | 675 | if (ret < 0) { |
64e36824 | 676 | dev_err(&pdev->dev, "Failed to enable spi_clk\n"); |
c351587e | 677 | goto err_disable_apbclk; |
64e36824 | 678 | } |
679 | ||
30688e4e | 680 | spi_enable_chip(rs, false); |
64e36824 | 681 | |
01b59ce5 ERB |
682 | ret = platform_get_irq(pdev, 0); |
683 | if (ret < 0) | |
684 | goto err_disable_spiclk; | |
685 | ||
686 | ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL, | |
d66571a2 | 687 | IRQF_ONESHOT, dev_name(&pdev->dev), ctlr); |
01b59ce5 ERB |
688 | if (ret) |
689 | goto err_disable_spiclk; | |
690 | ||
64e36824 | 691 | rs->dev = &pdev->dev; |
420b82f8 | 692 | rs->freq = clk_get_rate(rs->spiclk); |
64e36824 | 693 | |
76b17e6e | 694 | if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", |
74b7efa8 ERB |
695 | &rsd_nsecs)) { |
696 | /* rx sample delay is expressed in parent clock cycles (max 3) */ | |
697 | u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8), | |
698 | 1000000000 >> 8); | |
699 | if (!rsd) { | |
700 | dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n", | |
701 | rs->freq, rsd_nsecs); | |
702 | } else if (rsd > CR0_RSD_MAX) { | |
703 | rsd = CR0_RSD_MAX; | |
704 | dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n", | |
705 | rs->freq, rsd_nsecs, | |
706 | CR0_RSD_MAX * 1000000000U / rs->freq); | |
707 | } | |
708 | rs->rsd = rsd; | |
709 | } | |
76b17e6e | 710 | |
64e36824 | 711 | rs->fifo_len = get_fifo_len(rs); |
712 | if (!rs->fifo_len) { | |
713 | dev_err(&pdev->dev, "Failed to get fifo length\n"); | |
db7e8d90 | 714 | ret = -EINVAL; |
c351587e | 715 | goto err_disable_spiclk; |
64e36824 | 716 | } |
717 | ||
64e36824 | 718 | pm_runtime_set_active(&pdev->dev); |
719 | pm_runtime_enable(&pdev->dev); | |
720 | ||
d66571a2 CR |
721 | ctlr->auto_runtime_pm = true; |
722 | ctlr->bus_num = pdev->id; | |
723 | ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST; | |
d065f41a CR |
724 | if (slave_mode) { |
725 | ctlr->mode_bits |= SPI_NO_CS; | |
726 | ctlr->slave_abort = rockchip_spi_slave_abort; | |
727 | } else { | |
728 | ctlr->flags = SPI_MASTER_GPIO_SS; | |
eb1262e3 CR |
729 | ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM; |
730 | /* | |
731 | * rk spi0 has two native cs, spi1..5 one cs only | |
732 | * if num-cs is missing in the dts, default to 1 | |
733 | */ | |
734 | if (of_property_read_u16(np, "num-cs", &ctlr->num_chipselect)) | |
735 | ctlr->num_chipselect = 1; | |
736 | ctlr->use_gpio_descriptors = true; | |
d065f41a | 737 | } |
d66571a2 CR |
738 | ctlr->dev.of_node = pdev->dev.of_node; |
739 | ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4); | |
740 | ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX; | |
741 | ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT); | |
742 | ||
743 | ctlr->set_cs = rockchip_spi_set_cs; | |
744 | ctlr->transfer_one = rockchip_spi_transfer_one; | |
745 | ctlr->max_transfer_size = rockchip_spi_max_transfer_size; | |
746 | ctlr->handle_err = rockchip_spi_handle_err; | |
d66571a2 CR |
747 | |
748 | ctlr->dma_tx = dma_request_chan(rs->dev, "tx"); | |
749 | if (IS_ERR(ctlr->dma_tx)) { | |
61cadcf4 | 750 | /* Check tx to see if we need defer probing driver */ |
d66571a2 | 751 | if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) { |
61cadcf4 | 752 | ret = -EPROBE_DEFER; |
c351587e | 753 | goto err_disable_pm_runtime; |
61cadcf4 | 754 | } |
64e36824 | 755 | dev_warn(rs->dev, "Failed to request TX DMA channel\n"); |
d66571a2 | 756 | ctlr->dma_tx = NULL; |
61cadcf4 | 757 | } |
64e36824 | 758 | |
d66571a2 CR |
759 | ctlr->dma_rx = dma_request_chan(rs->dev, "rx"); |
760 | if (IS_ERR(ctlr->dma_rx)) { | |
761 | if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) { | |
e4c0e06f | 762 | ret = -EPROBE_DEFER; |
5de7ed0c | 763 | goto err_free_dma_tx; |
64e36824 | 764 | } |
765 | dev_warn(rs->dev, "Failed to request RX DMA channel\n"); | |
d66571a2 | 766 | ctlr->dma_rx = NULL; |
64e36824 | 767 | } |
768 | ||
d66571a2 | 769 | if (ctlr->dma_tx && ctlr->dma_rx) { |
eee06a9e ERB |
770 | rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR; |
771 | rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR; | |
d66571a2 | 772 | ctlr->can_dma = rockchip_spi_can_dma; |
64e36824 | 773 | } |
774 | ||
d66571a2 | 775 | ret = devm_spi_register_controller(&pdev->dev, ctlr); |
43de979d | 776 | if (ret < 0) { |
d66571a2 | 777 | dev_err(&pdev->dev, "Failed to register controller\n"); |
c351587e | 778 | goto err_free_dma_rx; |
64e36824 | 779 | } |
780 | ||
64e36824 | 781 | return 0; |
782 | ||
c351587e | 783 | err_free_dma_rx: |
d66571a2 CR |
784 | if (ctlr->dma_rx) |
785 | dma_release_channel(ctlr->dma_rx); | |
5de7ed0c | 786 | err_free_dma_tx: |
d66571a2 CR |
787 | if (ctlr->dma_tx) |
788 | dma_release_channel(ctlr->dma_tx); | |
c351587e JC |
789 | err_disable_pm_runtime: |
790 | pm_runtime_disable(&pdev->dev); | |
791 | err_disable_spiclk: | |
64e36824 | 792 | clk_disable_unprepare(rs->spiclk); |
c351587e | 793 | err_disable_apbclk: |
64e36824 | 794 | clk_disable_unprepare(rs->apb_pclk); |
d66571a2 CR |
795 | err_put_ctlr: |
796 | spi_controller_put(ctlr); | |
64e36824 | 797 | |
798 | return ret; | |
799 | } | |
800 | ||
801 | static int rockchip_spi_remove(struct platform_device *pdev) | |
802 | { | |
d66571a2 CR |
803 | struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev)); |
804 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); | |
64e36824 | 805 | |
6a06e895 | 806 | pm_runtime_get_sync(&pdev->dev); |
64e36824 | 807 | |
808 | clk_disable_unprepare(rs->spiclk); | |
809 | clk_disable_unprepare(rs->apb_pclk); | |
810 | ||
6a06e895 JC |
811 | pm_runtime_put_noidle(&pdev->dev); |
812 | pm_runtime_disable(&pdev->dev); | |
813 | pm_runtime_set_suspended(&pdev->dev); | |
814 | ||
d66571a2 CR |
815 | if (ctlr->dma_tx) |
816 | dma_release_channel(ctlr->dma_tx); | |
817 | if (ctlr->dma_rx) | |
818 | dma_release_channel(ctlr->dma_rx); | |
64e36824 | 819 | |
d66571a2 | 820 | spi_controller_put(ctlr); |
844c9f47 | 821 | |
64e36824 | 822 | return 0; |
823 | } | |
824 | ||
825 | #ifdef CONFIG_PM_SLEEP | |
826 | static int rockchip_spi_suspend(struct device *dev) | |
827 | { | |
43de979d | 828 | int ret; |
d66571a2 | 829 | struct spi_controller *ctlr = dev_get_drvdata(dev); |
64e36824 | 830 | |
d66571a2 | 831 | ret = spi_controller_suspend(ctlr); |
43de979d | 832 | if (ret < 0) |
64e36824 | 833 | return ret; |
834 | ||
d38c4ae1 JC |
835 | ret = pm_runtime_force_suspend(dev); |
836 | if (ret < 0) | |
837 | return ret; | |
64e36824 | 838 | |
23e291c2 BN |
839 | pinctrl_pm_select_sleep_state(dev); |
840 | ||
43de979d | 841 | return 0; |
64e36824 | 842 | } |
843 | ||
844 | static int rockchip_spi_resume(struct device *dev) | |
845 | { | |
43de979d | 846 | int ret; |
d66571a2 CR |
847 | struct spi_controller *ctlr = dev_get_drvdata(dev); |
848 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); | |
64e36824 | 849 | |
23e291c2 BN |
850 | pinctrl_pm_select_default_state(dev); |
851 | ||
d38c4ae1 JC |
852 | ret = pm_runtime_force_resume(dev); |
853 | if (ret < 0) | |
854 | return ret; | |
64e36824 | 855 | |
d66571a2 | 856 | ret = spi_controller_resume(ctlr); |
64e36824 | 857 | if (ret < 0) { |
858 | clk_disable_unprepare(rs->spiclk); | |
859 | clk_disable_unprepare(rs->apb_pclk); | |
860 | } | |
861 | ||
43de979d | 862 | return 0; |
64e36824 | 863 | } |
864 | #endif /* CONFIG_PM_SLEEP */ | |
865 | ||
ec833050 | 866 | #ifdef CONFIG_PM |
64e36824 | 867 | static int rockchip_spi_runtime_suspend(struct device *dev) |
868 | { | |
d66571a2 CR |
869 | struct spi_controller *ctlr = dev_get_drvdata(dev); |
870 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); | |
64e36824 | 871 | |
872 | clk_disable_unprepare(rs->spiclk); | |
873 | clk_disable_unprepare(rs->apb_pclk); | |
874 | ||
875 | return 0; | |
876 | } | |
877 | ||
878 | static int rockchip_spi_runtime_resume(struct device *dev) | |
879 | { | |
880 | int ret; | |
d66571a2 CR |
881 | struct spi_controller *ctlr = dev_get_drvdata(dev); |
882 | struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); | |
64e36824 | 883 | |
884 | ret = clk_prepare_enable(rs->apb_pclk); | |
43de979d | 885 | if (ret < 0) |
64e36824 | 886 | return ret; |
887 | ||
888 | ret = clk_prepare_enable(rs->spiclk); | |
43de979d | 889 | if (ret < 0) |
64e36824 | 890 | clk_disable_unprepare(rs->apb_pclk); |
891 | ||
43de979d | 892 | return 0; |
64e36824 | 893 | } |
ec833050 | 894 | #endif /* CONFIG_PM */ |
64e36824 | 895 | |
896 | static const struct dev_pm_ops rockchip_spi_pm = { | |
897 | SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) | |
898 | SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, | |
899 | rockchip_spi_runtime_resume, NULL) | |
900 | }; | |
901 | ||
902 | static const struct of_device_id rockchip_spi_dt_match[] = { | |
c6486ead | 903 | { .compatible = "rockchip,px30-spi", }, |
aa29ea3d | 904 | { .compatible = "rockchip,rk3036-spi", }, |
64e36824 | 905 | { .compatible = "rockchip,rk3066-spi", }, |
b839b785 | 906 | { .compatible = "rockchip,rk3188-spi", }, |
aa29ea3d | 907 | { .compatible = "rockchip,rk3228-spi", }, |
b839b785 | 908 | { .compatible = "rockchip,rk3288-spi", }, |
c6486ead JJ |
909 | { .compatible = "rockchip,rk3308-spi", }, |
910 | { .compatible = "rockchip,rk3328-spi", }, | |
aa29ea3d | 911 | { .compatible = "rockchip,rk3368-spi", }, |
9b7a5622 | 912 | { .compatible = "rockchip,rk3399-spi", }, |
c6486ead | 913 | { .compatible = "rockchip,rv1108-spi", }, |
64e36824 | 914 | { }, |
915 | }; | |
916 | MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); | |
917 | ||
918 | static struct platform_driver rockchip_spi_driver = { | |
919 | .driver = { | |
920 | .name = DRIVER_NAME, | |
64e36824 | 921 | .pm = &rockchip_spi_pm, |
922 | .of_match_table = of_match_ptr(rockchip_spi_dt_match), | |
923 | }, | |
924 | .probe = rockchip_spi_probe, | |
925 | .remove = rockchip_spi_remove, | |
926 | }; | |
927 | ||
928 | module_platform_driver(rockchip_spi_driver); | |
929 | ||
5dcc44ed | 930 | MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); |
64e36824 | 931 | MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); |
932 | MODULE_LICENSE("GPL v2"); |