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64e36824 | 1 | /* |
2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
5dcc44ed | 3 | * Author: Addy Ke <addy.ke@rock-chips.com> |
64e36824 | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/spi/spi.h> | |
25 | #include <linux/scatterlist.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/pm_runtime.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/scatterlist.h> | |
30 | #include <linux/dmaengine.h> | |
31 | ||
32 | #define DRIVER_NAME "rockchip-spi" | |
33 | ||
34 | /* SPI register offsets */ | |
35 | #define ROCKCHIP_SPI_CTRLR0 0x0000 | |
36 | #define ROCKCHIP_SPI_CTRLR1 0x0004 | |
37 | #define ROCKCHIP_SPI_SSIENR 0x0008 | |
38 | #define ROCKCHIP_SPI_SER 0x000c | |
39 | #define ROCKCHIP_SPI_BAUDR 0x0010 | |
40 | #define ROCKCHIP_SPI_TXFTLR 0x0014 | |
41 | #define ROCKCHIP_SPI_RXFTLR 0x0018 | |
42 | #define ROCKCHIP_SPI_TXFLR 0x001c | |
43 | #define ROCKCHIP_SPI_RXFLR 0x0020 | |
44 | #define ROCKCHIP_SPI_SR 0x0024 | |
45 | #define ROCKCHIP_SPI_IPR 0x0028 | |
46 | #define ROCKCHIP_SPI_IMR 0x002c | |
47 | #define ROCKCHIP_SPI_ISR 0x0030 | |
48 | #define ROCKCHIP_SPI_RISR 0x0034 | |
49 | #define ROCKCHIP_SPI_ICR 0x0038 | |
50 | #define ROCKCHIP_SPI_DMACR 0x003c | |
51 | #define ROCKCHIP_SPI_DMATDLR 0x0040 | |
52 | #define ROCKCHIP_SPI_DMARDLR 0x0044 | |
53 | #define ROCKCHIP_SPI_TXDR 0x0400 | |
54 | #define ROCKCHIP_SPI_RXDR 0x0800 | |
55 | ||
56 | /* Bit fields in CTRLR0 */ | |
57 | #define CR0_DFS_OFFSET 0 | |
58 | ||
59 | #define CR0_CFS_OFFSET 2 | |
60 | ||
61 | #define CR0_SCPH_OFFSET 6 | |
62 | ||
63 | #define CR0_SCPOL_OFFSET 7 | |
64 | ||
65 | #define CR0_CSM_OFFSET 8 | |
66 | #define CR0_CSM_KEEP 0x0 | |
67 | /* ss_n be high for half sclk_out cycles */ | |
68 | #define CR0_CSM_HALF 0X1 | |
69 | /* ss_n be high for one sclk_out cycle */ | |
70 | #define CR0_CSM_ONE 0x2 | |
71 | ||
72 | /* ss_n to sclk_out delay */ | |
73 | #define CR0_SSD_OFFSET 10 | |
74 | /* | |
75 | * The period between ss_n active and | |
76 | * sclk_out active is half sclk_out cycles | |
77 | */ | |
78 | #define CR0_SSD_HALF 0x0 | |
79 | /* | |
80 | * The period between ss_n active and | |
81 | * sclk_out active is one sclk_out cycle | |
82 | */ | |
83 | #define CR0_SSD_ONE 0x1 | |
84 | ||
85 | #define CR0_EM_OFFSET 11 | |
86 | #define CR0_EM_LITTLE 0x0 | |
87 | #define CR0_EM_BIG 0x1 | |
88 | ||
89 | #define CR0_FBM_OFFSET 12 | |
90 | #define CR0_FBM_MSB 0x0 | |
91 | #define CR0_FBM_LSB 0x1 | |
92 | ||
93 | #define CR0_BHT_OFFSET 13 | |
94 | #define CR0_BHT_16BIT 0x0 | |
95 | #define CR0_BHT_8BIT 0x1 | |
96 | ||
97 | #define CR0_RSD_OFFSET 14 | |
98 | ||
99 | #define CR0_FRF_OFFSET 16 | |
100 | #define CR0_FRF_SPI 0x0 | |
101 | #define CR0_FRF_SSP 0x1 | |
102 | #define CR0_FRF_MICROWIRE 0x2 | |
103 | ||
104 | #define CR0_XFM_OFFSET 18 | |
105 | #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) | |
106 | #define CR0_XFM_TR 0x0 | |
107 | #define CR0_XFM_TO 0x1 | |
108 | #define CR0_XFM_RO 0x2 | |
109 | ||
110 | #define CR0_OPM_OFFSET 20 | |
111 | #define CR0_OPM_MASTER 0x0 | |
112 | #define CR0_OPM_SLAVE 0x1 | |
113 | ||
114 | #define CR0_MTM_OFFSET 0x21 | |
115 | ||
116 | /* Bit fields in SER, 2bit */ | |
117 | #define SER_MASK 0x3 | |
118 | ||
119 | /* Bit fields in SR, 5bit */ | |
120 | #define SR_MASK 0x1f | |
121 | #define SR_BUSY (1 << 0) | |
122 | #define SR_TF_FULL (1 << 1) | |
123 | #define SR_TF_EMPTY (1 << 2) | |
124 | #define SR_RF_EMPTY (1 << 3) | |
125 | #define SR_RF_FULL (1 << 4) | |
126 | ||
127 | /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ | |
128 | #define INT_MASK 0x1f | |
129 | #define INT_TF_EMPTY (1 << 0) | |
130 | #define INT_TF_OVERFLOW (1 << 1) | |
131 | #define INT_RF_UNDERFLOW (1 << 2) | |
132 | #define INT_RF_OVERFLOW (1 << 3) | |
133 | #define INT_RF_FULL (1 << 4) | |
134 | ||
135 | /* Bit fields in ICR, 4bit */ | |
136 | #define ICR_MASK 0x0f | |
137 | #define ICR_ALL (1 << 0) | |
138 | #define ICR_RF_UNDERFLOW (1 << 1) | |
139 | #define ICR_RF_OVERFLOW (1 << 2) | |
140 | #define ICR_TF_OVERFLOW (1 << 3) | |
141 | ||
142 | /* Bit fields in DMACR */ | |
143 | #define RF_DMA_EN (1 << 0) | |
144 | #define TF_DMA_EN (1 << 1) | |
145 | ||
146 | #define RXBUSY (1 << 0) | |
147 | #define TXBUSY (1 << 1) | |
148 | ||
149 | enum rockchip_ssi_type { | |
150 | SSI_MOTO_SPI = 0, | |
151 | SSI_TI_SSP, | |
152 | SSI_NS_MICROWIRE, | |
153 | }; | |
154 | ||
155 | struct rockchip_spi_dma_data { | |
156 | struct dma_chan *ch; | |
157 | enum dma_transfer_direction direction; | |
158 | dma_addr_t addr; | |
159 | }; | |
160 | ||
161 | struct rockchip_spi { | |
162 | struct device *dev; | |
163 | struct spi_master *master; | |
164 | ||
165 | struct clk *spiclk; | |
166 | struct clk *apb_pclk; | |
167 | ||
168 | void __iomem *regs; | |
169 | /*depth of the FIFO buffer */ | |
170 | u32 fifo_len; | |
171 | /* max bus freq supported */ | |
172 | u32 max_freq; | |
173 | /* supported slave numbers */ | |
174 | enum rockchip_ssi_type type; | |
175 | ||
176 | u16 mode; | |
177 | u8 tmode; | |
178 | u8 bpw; | |
179 | u8 n_bytes; | |
180 | unsigned len; | |
181 | u32 speed; | |
182 | ||
183 | const void *tx; | |
184 | const void *tx_end; | |
185 | void *rx; | |
186 | void *rx_end; | |
187 | ||
188 | u32 state; | |
5dcc44ed | 189 | /* protect state */ |
64e36824 | 190 | spinlock_t lock; |
191 | ||
192 | struct completion xfer_completion; | |
193 | ||
194 | u32 use_dma; | |
195 | struct sg_table tx_sg; | |
196 | struct sg_table rx_sg; | |
197 | struct rockchip_spi_dma_data dma_rx; | |
198 | struct rockchip_spi_dma_data dma_tx; | |
199 | }; | |
200 | ||
201 | static inline void spi_enable_chip(struct rockchip_spi *rs, int enable) | |
202 | { | |
203 | writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR); | |
204 | } | |
205 | ||
206 | static inline void spi_set_clk(struct rockchip_spi *rs, u16 div) | |
207 | { | |
208 | writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR); | |
209 | } | |
210 | ||
211 | static inline void flush_fifo(struct rockchip_spi *rs) | |
212 | { | |
213 | while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR)) | |
214 | readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); | |
215 | } | |
216 | ||
2df08e78 AK |
217 | static inline void wait_for_idle(struct rockchip_spi *rs) |
218 | { | |
219 | unsigned long timeout = jiffies + msecs_to_jiffies(5); | |
220 | ||
221 | do { | |
222 | if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) | |
223 | return; | |
224 | } while (time_before(jiffies, timeout)); | |
225 | ||
226 | dev_warn(rs->dev, "spi controller is in busy state!\n"); | |
227 | } | |
228 | ||
64e36824 | 229 | static u32 get_fifo_len(struct rockchip_spi *rs) |
230 | { | |
231 | u32 fifo; | |
232 | ||
233 | for (fifo = 2; fifo < 32; fifo++) { | |
234 | writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
235 | if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR)) | |
236 | break; | |
237 | } | |
238 | ||
239 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
240 | ||
241 | return (fifo == 31) ? 0 : fifo; | |
242 | } | |
243 | ||
244 | static inline u32 tx_max(struct rockchip_spi *rs) | |
245 | { | |
246 | u32 tx_left, tx_room; | |
247 | ||
248 | tx_left = (rs->tx_end - rs->tx) / rs->n_bytes; | |
249 | tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); | |
250 | ||
251 | return min(tx_left, tx_room); | |
252 | } | |
253 | ||
254 | static inline u32 rx_max(struct rockchip_spi *rs) | |
255 | { | |
256 | u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes; | |
257 | u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); | |
258 | ||
259 | return min(rx_left, rx_room); | |
260 | } | |
261 | ||
262 | static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) | |
263 | { | |
264 | u32 ser; | |
265 | struct rockchip_spi *rs = spi_master_get_devdata(spi->master); | |
266 | ||
267 | ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK; | |
268 | ||
269 | /* | |
270 | * drivers/spi/spi.c: | |
271 | * static void spi_set_cs(struct spi_device *spi, bool enable) | |
272 | * { | |
273 | * if (spi->mode & SPI_CS_HIGH) | |
274 | * enable = !enable; | |
275 | * | |
276 | * if (spi->cs_gpio >= 0) | |
277 | * gpio_set_value(spi->cs_gpio, !enable); | |
278 | * else if (spi->master->set_cs) | |
279 | * spi->master->set_cs(spi, !enable); | |
280 | * } | |
281 | * | |
282 | * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs) | |
283 | */ | |
284 | if (!enable) | |
285 | ser |= 1 << spi->chip_select; | |
286 | else | |
287 | ser &= ~(1 << spi->chip_select); | |
288 | ||
289 | writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER); | |
290 | } | |
291 | ||
292 | static int rockchip_spi_prepare_message(struct spi_master *master, | |
5dcc44ed | 293 | struct spi_message *msg) |
64e36824 | 294 | { |
295 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
296 | struct spi_device *spi = msg->spi; | |
297 | ||
298 | if (spi->mode & SPI_CS_HIGH) { | |
299 | dev_err(rs->dev, "spi_cs_hign: not support\n"); | |
300 | return -EINVAL; | |
301 | } | |
302 | ||
303 | rs->mode = spi->mode; | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
308 | static int rockchip_spi_unprepare_message(struct spi_master *master, | |
5dcc44ed | 309 | struct spi_message *msg) |
64e36824 | 310 | { |
311 | unsigned long flags; | |
312 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
313 | ||
314 | spin_lock_irqsave(&rs->lock, flags); | |
315 | ||
5dcc44ed AK |
316 | /* |
317 | * For DMA mode, we need terminate DMA channel and flush | |
318 | * fifo for the next transfer if DMA thansfer timeout. | |
319 | * unprepare_message() was called by core if transfer complete | |
320 | * or timeout. Maybe it is reasonable for error handling here. | |
321 | */ | |
64e36824 | 322 | if (rs->use_dma) { |
323 | if (rs->state & RXBUSY) { | |
324 | dmaengine_terminate_all(rs->dma_rx.ch); | |
325 | flush_fifo(rs); | |
326 | } | |
327 | ||
328 | if (rs->state & TXBUSY) | |
329 | dmaengine_terminate_all(rs->dma_tx.ch); | |
330 | } | |
331 | ||
332 | spin_unlock_irqrestore(&rs->lock, flags); | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | static void rockchip_spi_pio_writer(struct rockchip_spi *rs) | |
338 | { | |
339 | u32 max = tx_max(rs); | |
340 | u32 txw = 0; | |
341 | ||
342 | while (max--) { | |
343 | if (rs->n_bytes == 1) | |
344 | txw = *(u8 *)(rs->tx); | |
345 | else | |
346 | txw = *(u16 *)(rs->tx); | |
347 | ||
348 | writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); | |
349 | rs->tx += rs->n_bytes; | |
350 | } | |
351 | } | |
352 | ||
353 | static void rockchip_spi_pio_reader(struct rockchip_spi *rs) | |
354 | { | |
355 | u32 max = rx_max(rs); | |
356 | u32 rxw; | |
357 | ||
358 | while (max--) { | |
359 | rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); | |
360 | if (rs->n_bytes == 1) | |
361 | *(u8 *)(rs->rx) = (u8)rxw; | |
362 | else | |
363 | *(u16 *)(rs->rx) = (u16)rxw; | |
364 | rs->rx += rs->n_bytes; | |
5dcc44ed | 365 | } |
64e36824 | 366 | } |
367 | ||
368 | static int rockchip_spi_pio_transfer(struct rockchip_spi *rs) | |
369 | { | |
370 | int remain = 0; | |
371 | ||
372 | do { | |
373 | if (rs->tx) { | |
374 | remain = rs->tx_end - rs->tx; | |
375 | rockchip_spi_pio_writer(rs); | |
376 | } | |
377 | ||
378 | if (rs->rx) { | |
379 | remain = rs->rx_end - rs->rx; | |
380 | rockchip_spi_pio_reader(rs); | |
381 | } | |
382 | ||
383 | cpu_relax(); | |
384 | } while (remain); | |
385 | ||
2df08e78 AK |
386 | /* If tx, wait until the FIFO data completely. */ |
387 | if (rs->tx) | |
388 | wait_for_idle(rs); | |
389 | ||
64e36824 | 390 | return 0; |
391 | } | |
392 | ||
393 | static void rockchip_spi_dma_rxcb(void *data) | |
394 | { | |
395 | unsigned long flags; | |
396 | struct rockchip_spi *rs = data; | |
397 | ||
398 | spin_lock_irqsave(&rs->lock, flags); | |
399 | ||
400 | rs->state &= ~RXBUSY; | |
401 | if (!(rs->state & TXBUSY)) | |
402 | spi_finalize_current_transfer(rs->master); | |
403 | ||
404 | spin_unlock_irqrestore(&rs->lock, flags); | |
405 | } | |
406 | ||
407 | static void rockchip_spi_dma_txcb(void *data) | |
408 | { | |
409 | unsigned long flags; | |
410 | struct rockchip_spi *rs = data; | |
411 | ||
2df08e78 AK |
412 | /* Wait until the FIFO data completely. */ |
413 | wait_for_idle(rs); | |
414 | ||
64e36824 | 415 | spin_lock_irqsave(&rs->lock, flags); |
416 | ||
417 | rs->state &= ~TXBUSY; | |
418 | if (!(rs->state & RXBUSY)) | |
419 | spi_finalize_current_transfer(rs->master); | |
420 | ||
421 | spin_unlock_irqrestore(&rs->lock, flags); | |
422 | } | |
423 | ||
424 | static int rockchip_spi_dma_transfer(struct rockchip_spi *rs) | |
425 | { | |
426 | unsigned long flags; | |
427 | struct dma_slave_config rxconf, txconf; | |
428 | struct dma_async_tx_descriptor *rxdesc, *txdesc; | |
429 | ||
430 | spin_lock_irqsave(&rs->lock, flags); | |
431 | rs->state &= ~RXBUSY; | |
432 | rs->state &= ~TXBUSY; | |
433 | spin_unlock_irqrestore(&rs->lock, flags); | |
434 | ||
435 | if (rs->rx) { | |
436 | rxconf.direction = rs->dma_rx.direction; | |
437 | rxconf.src_addr = rs->dma_rx.addr; | |
438 | rxconf.src_addr_width = rs->n_bytes; | |
439 | rxconf.src_maxburst = rs->n_bytes; | |
440 | dmaengine_slave_config(rs->dma_rx.ch, &rxconf); | |
441 | ||
5dcc44ed AK |
442 | rxdesc = dmaengine_prep_slave_sg( |
443 | rs->dma_rx.ch, | |
64e36824 | 444 | rs->rx_sg.sgl, rs->rx_sg.nents, |
445 | rs->dma_rx.direction, DMA_PREP_INTERRUPT); | |
446 | ||
447 | rxdesc->callback = rockchip_spi_dma_rxcb; | |
448 | rxdesc->callback_param = rs; | |
449 | } | |
450 | ||
451 | if (rs->tx) { | |
452 | txconf.direction = rs->dma_tx.direction; | |
453 | txconf.dst_addr = rs->dma_tx.addr; | |
454 | txconf.dst_addr_width = rs->n_bytes; | |
455 | txconf.dst_maxburst = rs->n_bytes; | |
456 | dmaengine_slave_config(rs->dma_tx.ch, &txconf); | |
457 | ||
5dcc44ed AK |
458 | txdesc = dmaengine_prep_slave_sg( |
459 | rs->dma_tx.ch, | |
64e36824 | 460 | rs->tx_sg.sgl, rs->tx_sg.nents, |
461 | rs->dma_tx.direction, DMA_PREP_INTERRUPT); | |
462 | ||
463 | txdesc->callback = rockchip_spi_dma_txcb; | |
464 | txdesc->callback_param = rs; | |
465 | } | |
466 | ||
467 | /* rx must be started before tx due to spi instinct */ | |
468 | if (rs->rx) { | |
469 | spin_lock_irqsave(&rs->lock, flags); | |
470 | rs->state |= RXBUSY; | |
471 | spin_unlock_irqrestore(&rs->lock, flags); | |
472 | dmaengine_submit(rxdesc); | |
473 | dma_async_issue_pending(rs->dma_rx.ch); | |
474 | } | |
475 | ||
476 | if (rs->tx) { | |
477 | spin_lock_irqsave(&rs->lock, flags); | |
478 | rs->state |= TXBUSY; | |
479 | spin_unlock_irqrestore(&rs->lock, flags); | |
480 | dmaengine_submit(txdesc); | |
481 | dma_async_issue_pending(rs->dma_tx.ch); | |
482 | } | |
483 | ||
484 | return 1; | |
485 | } | |
486 | ||
487 | static void rockchip_spi_config(struct rockchip_spi *rs) | |
488 | { | |
489 | u32 div = 0; | |
490 | u32 dmacr = 0; | |
491 | ||
492 | u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) | |
493 | | (CR0_SSD_ONE << CR0_SSD_OFFSET); | |
494 | ||
495 | cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); | |
496 | cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); | |
497 | cr0 |= (rs->tmode << CR0_XFM_OFFSET); | |
498 | cr0 |= (rs->type << CR0_FRF_OFFSET); | |
499 | ||
500 | if (rs->use_dma) { | |
501 | if (rs->tx) | |
502 | dmacr |= TF_DMA_EN; | |
503 | if (rs->rx) | |
504 | dmacr |= RF_DMA_EN; | |
505 | } | |
506 | ||
507 | /* div doesn't support odd number */ | |
508 | div = rs->max_freq / rs->speed; | |
509 | div = (div + 1) & 0xfffe; | |
510 | ||
511 | spi_enable_chip(rs, 0); | |
512 | ||
513 | writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); | |
514 | ||
515 | writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); | |
516 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR); | |
517 | writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); | |
518 | ||
519 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR); | |
520 | writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR); | |
521 | writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); | |
522 | ||
523 | spi_set_clk(rs, div); | |
524 | ||
5dcc44ed | 525 | dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div); |
64e36824 | 526 | |
527 | spi_enable_chip(rs, 1); | |
528 | } | |
529 | ||
5dcc44ed AK |
530 | static int rockchip_spi_transfer_one( |
531 | struct spi_master *master, | |
64e36824 | 532 | struct spi_device *spi, |
533 | struct spi_transfer *xfer) | |
534 | { | |
535 | int ret = 0; | |
536 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
537 | ||
538 | WARN_ON((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); | |
539 | ||
540 | if (!xfer->tx_buf && !xfer->rx_buf) { | |
541 | dev_err(rs->dev, "No buffer for transfer\n"); | |
542 | return -EINVAL; | |
543 | } | |
544 | ||
545 | rs->speed = xfer->speed_hz; | |
546 | rs->bpw = xfer->bits_per_word; | |
547 | rs->n_bytes = rs->bpw >> 3; | |
548 | ||
549 | rs->tx = xfer->tx_buf; | |
550 | rs->tx_end = rs->tx + xfer->len; | |
551 | rs->rx = xfer->rx_buf; | |
552 | rs->rx_end = rs->rx + xfer->len; | |
553 | rs->len = xfer->len; | |
554 | ||
555 | rs->tx_sg = xfer->tx_sg; | |
556 | rs->rx_sg = xfer->rx_sg; | |
557 | ||
64e36824 | 558 | if (rs->tx && rs->rx) |
559 | rs->tmode = CR0_XFM_TR; | |
560 | else if (rs->tx) | |
561 | rs->tmode = CR0_XFM_TO; | |
562 | else if (rs->rx) | |
563 | rs->tmode = CR0_XFM_RO; | |
564 | ||
565 | if (master->can_dma && master->can_dma(master, spi, xfer)) | |
566 | rs->use_dma = 1; | |
567 | else | |
568 | rs->use_dma = 0; | |
569 | ||
570 | rockchip_spi_config(rs); | |
571 | ||
572 | if (rs->use_dma) | |
573 | ret = rockchip_spi_dma_transfer(rs); | |
574 | else | |
575 | ret = rockchip_spi_pio_transfer(rs); | |
576 | ||
577 | return ret; | |
578 | } | |
579 | ||
580 | static bool rockchip_spi_can_dma(struct spi_master *master, | |
5dcc44ed AK |
581 | struct spi_device *spi, |
582 | struct spi_transfer *xfer) | |
64e36824 | 583 | { |
584 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
585 | ||
586 | return (xfer->len > rs->fifo_len); | |
587 | } | |
588 | ||
589 | static int rockchip_spi_probe(struct platform_device *pdev) | |
590 | { | |
591 | int ret = 0; | |
592 | struct rockchip_spi *rs; | |
593 | struct spi_master *master; | |
594 | struct resource *mem; | |
595 | ||
596 | master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi)); | |
5dcc44ed | 597 | if (!master) |
64e36824 | 598 | return -ENOMEM; |
5dcc44ed | 599 | |
64e36824 | 600 | platform_set_drvdata(pdev, master); |
601 | ||
602 | rs = spi_master_get_devdata(master); | |
603 | memset(rs, 0, sizeof(struct rockchip_spi)); | |
604 | ||
605 | /* Get basic io resource and map it */ | |
606 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
607 | rs->regs = devm_ioremap_resource(&pdev->dev, mem); | |
608 | if (IS_ERR(rs->regs)) { | |
609 | dev_err(&pdev->dev, "Failed to map SPI region\n"); | |
610 | ret = PTR_ERR(rs->regs); | |
611 | goto err_ioremap_resource; | |
612 | } | |
613 | ||
614 | rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | |
615 | if (IS_ERR(rs->apb_pclk)) { | |
616 | dev_err(&pdev->dev, "Failed to get apb_pclk\n"); | |
617 | ret = PTR_ERR(rs->apb_pclk); | |
618 | goto err_ioremap_resource; | |
619 | } | |
620 | ||
621 | rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); | |
622 | if (IS_ERR(rs->spiclk)) { | |
623 | dev_err(&pdev->dev, "Failed to get spi_pclk\n"); | |
624 | ret = PTR_ERR(rs->spiclk); | |
625 | goto err_ioremap_resource; | |
626 | } | |
627 | ||
628 | ret = clk_prepare_enable(rs->apb_pclk); | |
629 | if (ret) { | |
630 | dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); | |
631 | goto err_ioremap_resource; | |
632 | } | |
633 | ||
634 | ret = clk_prepare_enable(rs->spiclk); | |
635 | if (ret) { | |
636 | dev_err(&pdev->dev, "Failed to enable spi_clk\n"); | |
637 | goto err_spiclk_enable; | |
638 | } | |
639 | ||
640 | spi_enable_chip(rs, 0); | |
641 | ||
642 | rs->type = SSI_MOTO_SPI; | |
643 | rs->master = master; | |
644 | rs->dev = &pdev->dev; | |
645 | rs->max_freq = clk_get_rate(rs->spiclk); | |
646 | ||
647 | rs->fifo_len = get_fifo_len(rs); | |
648 | if (!rs->fifo_len) { | |
649 | dev_err(&pdev->dev, "Failed to get fifo length\n"); | |
650 | goto err_get_fifo_len; | |
651 | } | |
652 | ||
653 | spin_lock_init(&rs->lock); | |
654 | ||
655 | pm_runtime_set_active(&pdev->dev); | |
656 | pm_runtime_enable(&pdev->dev); | |
657 | ||
658 | master->auto_runtime_pm = true; | |
659 | master->bus_num = pdev->id; | |
660 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; | |
661 | master->num_chipselect = 2; | |
662 | master->dev.of_node = pdev->dev.of_node; | |
663 | master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); | |
664 | ||
665 | master->set_cs = rockchip_spi_set_cs; | |
666 | master->prepare_message = rockchip_spi_prepare_message; | |
667 | master->unprepare_message = rockchip_spi_unprepare_message; | |
668 | master->transfer_one = rockchip_spi_transfer_one; | |
669 | ||
670 | rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx"); | |
671 | if (!rs->dma_tx.ch) | |
672 | dev_warn(rs->dev, "Failed to request TX DMA channel\n"); | |
673 | ||
674 | rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx"); | |
675 | if (!rs->dma_rx.ch) { | |
676 | if (rs->dma_tx.ch) { | |
677 | dma_release_channel(rs->dma_tx.ch); | |
678 | rs->dma_tx.ch = NULL; | |
679 | } | |
680 | dev_warn(rs->dev, "Failed to request RX DMA channel\n"); | |
681 | } | |
682 | ||
683 | if (rs->dma_tx.ch && rs->dma_rx.ch) { | |
684 | rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR); | |
685 | rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR); | |
686 | rs->dma_tx.direction = DMA_MEM_TO_DEV; | |
687 | rs->dma_tx.direction = DMA_DEV_TO_MEM; | |
688 | ||
689 | master->can_dma = rockchip_spi_can_dma; | |
690 | master->dma_tx = rs->dma_tx.ch; | |
691 | master->dma_rx = rs->dma_rx.ch; | |
692 | } | |
693 | ||
694 | ret = devm_spi_register_master(&pdev->dev, master); | |
695 | if (ret) { | |
696 | dev_err(&pdev->dev, "Failed to register master\n"); | |
697 | goto err_register_master; | |
698 | } | |
699 | ||
64e36824 | 700 | return 0; |
701 | ||
702 | err_register_master: | |
703 | if (rs->dma_tx.ch) | |
704 | dma_release_channel(rs->dma_tx.ch); | |
705 | if (rs->dma_rx.ch) | |
706 | dma_release_channel(rs->dma_rx.ch); | |
707 | err_get_fifo_len: | |
708 | clk_disable_unprepare(rs->spiclk); | |
709 | err_spiclk_enable: | |
710 | clk_disable_unprepare(rs->apb_pclk); | |
711 | err_ioremap_resource: | |
712 | spi_master_put(master); | |
713 | ||
714 | return ret; | |
715 | } | |
716 | ||
717 | static int rockchip_spi_remove(struct platform_device *pdev) | |
718 | { | |
719 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); | |
720 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
721 | ||
722 | pm_runtime_disable(&pdev->dev); | |
723 | ||
724 | clk_disable_unprepare(rs->spiclk); | |
725 | clk_disable_unprepare(rs->apb_pclk); | |
726 | ||
727 | if (rs->dma_tx.ch) | |
728 | dma_release_channel(rs->dma_tx.ch); | |
729 | if (rs->dma_rx.ch) | |
730 | dma_release_channel(rs->dma_rx.ch); | |
731 | ||
732 | spi_master_put(master); | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
737 | #ifdef CONFIG_PM_SLEEP | |
738 | static int rockchip_spi_suspend(struct device *dev) | |
739 | { | |
740 | int ret = 0; | |
741 | struct spi_master *master = dev_get_drvdata(dev); | |
742 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
743 | ||
744 | ret = spi_master_suspend(rs->master); | |
745 | if (ret) | |
746 | return ret; | |
747 | ||
748 | if (!pm_runtime_suspended(dev)) { | |
749 | clk_disable_unprepare(rs->spiclk); | |
750 | clk_disable_unprepare(rs->apb_pclk); | |
751 | } | |
752 | ||
753 | return ret; | |
754 | } | |
755 | ||
756 | static int rockchip_spi_resume(struct device *dev) | |
757 | { | |
758 | int ret = 0; | |
759 | struct spi_master *master = dev_get_drvdata(dev); | |
760 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
761 | ||
762 | if (!pm_runtime_suspended(dev)) { | |
763 | ret = clk_prepare_enable(rs->apb_pclk); | |
764 | if (ret < 0) | |
765 | return ret; | |
766 | ||
767 | ret = clk_prepare_enable(rs->spiclk); | |
768 | if (ret < 0) { | |
769 | clk_disable_unprepare(rs->apb_pclk); | |
770 | return ret; | |
771 | } | |
772 | } | |
773 | ||
774 | ret = spi_master_resume(rs->master); | |
775 | if (ret < 0) { | |
776 | clk_disable_unprepare(rs->spiclk); | |
777 | clk_disable_unprepare(rs->apb_pclk); | |
778 | } | |
779 | ||
780 | return ret; | |
781 | } | |
782 | #endif /* CONFIG_PM_SLEEP */ | |
783 | ||
784 | #ifdef CONFIG_PM_RUNTIME | |
785 | static int rockchip_spi_runtime_suspend(struct device *dev) | |
786 | { | |
787 | struct spi_master *master = dev_get_drvdata(dev); | |
788 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
789 | ||
790 | clk_disable_unprepare(rs->spiclk); | |
791 | clk_disable_unprepare(rs->apb_pclk); | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static int rockchip_spi_runtime_resume(struct device *dev) | |
797 | { | |
798 | int ret; | |
799 | struct spi_master *master = dev_get_drvdata(dev); | |
800 | struct rockchip_spi *rs = spi_master_get_devdata(master); | |
801 | ||
802 | ret = clk_prepare_enable(rs->apb_pclk); | |
803 | if (ret) | |
804 | return ret; | |
805 | ||
806 | ret = clk_prepare_enable(rs->spiclk); | |
807 | if (ret) | |
808 | clk_disable_unprepare(rs->apb_pclk); | |
809 | ||
810 | return ret; | |
811 | } | |
812 | #endif /* CONFIG_PM_RUNTIME */ | |
813 | ||
814 | static const struct dev_pm_ops rockchip_spi_pm = { | |
815 | SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) | |
816 | SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, | |
817 | rockchip_spi_runtime_resume, NULL) | |
818 | }; | |
819 | ||
820 | static const struct of_device_id rockchip_spi_dt_match[] = { | |
821 | { .compatible = "rockchip,rk3066-spi", }, | |
822 | { }, | |
823 | }; | |
824 | MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); | |
825 | ||
826 | static struct platform_driver rockchip_spi_driver = { | |
827 | .driver = { | |
828 | .name = DRIVER_NAME, | |
829 | .owner = THIS_MODULE, | |
830 | .pm = &rockchip_spi_pm, | |
831 | .of_match_table = of_match_ptr(rockchip_spi_dt_match), | |
832 | }, | |
833 | .probe = rockchip_spi_probe, | |
834 | .remove = rockchip_spi_remove, | |
835 | }; | |
836 | ||
837 | module_platform_driver(rockchip_spi_driver); | |
838 | ||
5dcc44ed | 839 | MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); |
64e36824 | 840 | MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); |
841 | MODULE_LICENSE("GPL v2"); |