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spi/rockchip: cleanup some coding issues and uncessary output
[mirror_ubuntu-kernels.git] / drivers / spi / spi-rockchip.c
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64e36824 1/*
2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
5dcc44ed 3 * Author: Addy Ke <addy.ke@rock-chips.com>
64e36824 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <linux/spi/spi.h>
25#include <linux/scatterlist.h>
26#include <linux/of.h>
27#include <linux/pm_runtime.h>
28#include <linux/io.h>
29#include <linux/scatterlist.h>
30#include <linux/dmaengine.h>
31
32#define DRIVER_NAME "rockchip-spi"
33
34/* SPI register offsets */
35#define ROCKCHIP_SPI_CTRLR0 0x0000
36#define ROCKCHIP_SPI_CTRLR1 0x0004
37#define ROCKCHIP_SPI_SSIENR 0x0008
38#define ROCKCHIP_SPI_SER 0x000c
39#define ROCKCHIP_SPI_BAUDR 0x0010
40#define ROCKCHIP_SPI_TXFTLR 0x0014
41#define ROCKCHIP_SPI_RXFTLR 0x0018
42#define ROCKCHIP_SPI_TXFLR 0x001c
43#define ROCKCHIP_SPI_RXFLR 0x0020
44#define ROCKCHIP_SPI_SR 0x0024
45#define ROCKCHIP_SPI_IPR 0x0028
46#define ROCKCHIP_SPI_IMR 0x002c
47#define ROCKCHIP_SPI_ISR 0x0030
48#define ROCKCHIP_SPI_RISR 0x0034
49#define ROCKCHIP_SPI_ICR 0x0038
50#define ROCKCHIP_SPI_DMACR 0x003c
51#define ROCKCHIP_SPI_DMATDLR 0x0040
52#define ROCKCHIP_SPI_DMARDLR 0x0044
53#define ROCKCHIP_SPI_TXDR 0x0400
54#define ROCKCHIP_SPI_RXDR 0x0800
55
56/* Bit fields in CTRLR0 */
57#define CR0_DFS_OFFSET 0
58
59#define CR0_CFS_OFFSET 2
60
61#define CR0_SCPH_OFFSET 6
62
63#define CR0_SCPOL_OFFSET 7
64
65#define CR0_CSM_OFFSET 8
66#define CR0_CSM_KEEP 0x0
67/* ss_n be high for half sclk_out cycles */
68#define CR0_CSM_HALF 0X1
69/* ss_n be high for one sclk_out cycle */
70#define CR0_CSM_ONE 0x2
71
72/* ss_n to sclk_out delay */
73#define CR0_SSD_OFFSET 10
74/*
75 * The period between ss_n active and
76 * sclk_out active is half sclk_out cycles
77 */
78#define CR0_SSD_HALF 0x0
79/*
80 * The period between ss_n active and
81 * sclk_out active is one sclk_out cycle
82 */
83#define CR0_SSD_ONE 0x1
84
85#define CR0_EM_OFFSET 11
86#define CR0_EM_LITTLE 0x0
87#define CR0_EM_BIG 0x1
88
89#define CR0_FBM_OFFSET 12
90#define CR0_FBM_MSB 0x0
91#define CR0_FBM_LSB 0x1
92
93#define CR0_BHT_OFFSET 13
94#define CR0_BHT_16BIT 0x0
95#define CR0_BHT_8BIT 0x1
96
97#define CR0_RSD_OFFSET 14
98
99#define CR0_FRF_OFFSET 16
100#define CR0_FRF_SPI 0x0
101#define CR0_FRF_SSP 0x1
102#define CR0_FRF_MICROWIRE 0x2
103
104#define CR0_XFM_OFFSET 18
105#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
106#define CR0_XFM_TR 0x0
107#define CR0_XFM_TO 0x1
108#define CR0_XFM_RO 0x2
109
110#define CR0_OPM_OFFSET 20
111#define CR0_OPM_MASTER 0x0
112#define CR0_OPM_SLAVE 0x1
113
114#define CR0_MTM_OFFSET 0x21
115
116/* Bit fields in SER, 2bit */
117#define SER_MASK 0x3
118
119/* Bit fields in SR, 5bit */
120#define SR_MASK 0x1f
121#define SR_BUSY (1 << 0)
122#define SR_TF_FULL (1 << 1)
123#define SR_TF_EMPTY (1 << 2)
124#define SR_RF_EMPTY (1 << 3)
125#define SR_RF_FULL (1 << 4)
126
127/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
128#define INT_MASK 0x1f
129#define INT_TF_EMPTY (1 << 0)
130#define INT_TF_OVERFLOW (1 << 1)
131#define INT_RF_UNDERFLOW (1 << 2)
132#define INT_RF_OVERFLOW (1 << 3)
133#define INT_RF_FULL (1 << 4)
134
135/* Bit fields in ICR, 4bit */
136#define ICR_MASK 0x0f
137#define ICR_ALL (1 << 0)
138#define ICR_RF_UNDERFLOW (1 << 1)
139#define ICR_RF_OVERFLOW (1 << 2)
140#define ICR_TF_OVERFLOW (1 << 3)
141
142/* Bit fields in DMACR */
143#define RF_DMA_EN (1 << 0)
144#define TF_DMA_EN (1 << 1)
145
146#define RXBUSY (1 << 0)
147#define TXBUSY (1 << 1)
148
149enum rockchip_ssi_type {
150 SSI_MOTO_SPI = 0,
151 SSI_TI_SSP,
152 SSI_NS_MICROWIRE,
153};
154
155struct rockchip_spi_dma_data {
156 struct dma_chan *ch;
157 enum dma_transfer_direction direction;
158 dma_addr_t addr;
159};
160
161struct rockchip_spi {
162 struct device *dev;
163 struct spi_master *master;
164
165 struct clk *spiclk;
166 struct clk *apb_pclk;
167
168 void __iomem *regs;
169 /*depth of the FIFO buffer */
170 u32 fifo_len;
171 /* max bus freq supported */
172 u32 max_freq;
173 /* supported slave numbers */
174 enum rockchip_ssi_type type;
175
176 u16 mode;
177 u8 tmode;
178 u8 bpw;
179 u8 n_bytes;
180 unsigned len;
181 u32 speed;
182
183 const void *tx;
184 const void *tx_end;
185 void *rx;
186 void *rx_end;
187
188 u32 state;
5dcc44ed 189 /* protect state */
64e36824 190 spinlock_t lock;
191
192 struct completion xfer_completion;
193
194 u32 use_dma;
195 struct sg_table tx_sg;
196 struct sg_table rx_sg;
197 struct rockchip_spi_dma_data dma_rx;
198 struct rockchip_spi_dma_data dma_tx;
199};
200
201static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
202{
203 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
204}
205
206static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
207{
208 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
209}
210
211static inline void flush_fifo(struct rockchip_spi *rs)
212{
213 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
214 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
215}
216
217static u32 get_fifo_len(struct rockchip_spi *rs)
218{
219 u32 fifo;
220
221 for (fifo = 2; fifo < 32; fifo++) {
222 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
223 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
224 break;
225 }
226
227 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
228
229 return (fifo == 31) ? 0 : fifo;
230}
231
232static inline u32 tx_max(struct rockchip_spi *rs)
233{
234 u32 tx_left, tx_room;
235
236 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
237 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
238
239 return min(tx_left, tx_room);
240}
241
242static inline u32 rx_max(struct rockchip_spi *rs)
243{
244 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
245 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
246
247 return min(rx_left, rx_room);
248}
249
250static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
251{
252 u32 ser;
253 struct rockchip_spi *rs = spi_master_get_devdata(spi->master);
254
255 ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
256
257 /*
258 * drivers/spi/spi.c:
259 * static void spi_set_cs(struct spi_device *spi, bool enable)
260 * {
261 * if (spi->mode & SPI_CS_HIGH)
262 * enable = !enable;
263 *
264 * if (spi->cs_gpio >= 0)
265 * gpio_set_value(spi->cs_gpio, !enable);
266 * else if (spi->master->set_cs)
267 * spi->master->set_cs(spi, !enable);
268 * }
269 *
270 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
271 */
272 if (!enable)
273 ser |= 1 << spi->chip_select;
274 else
275 ser &= ~(1 << spi->chip_select);
276
277 writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
278}
279
280static int rockchip_spi_prepare_message(struct spi_master *master,
5dcc44ed 281 struct spi_message *msg)
64e36824 282{
283 struct rockchip_spi *rs = spi_master_get_devdata(master);
284 struct spi_device *spi = msg->spi;
285
286 if (spi->mode & SPI_CS_HIGH) {
287 dev_err(rs->dev, "spi_cs_hign: not support\n");
288 return -EINVAL;
289 }
290
291 rs->mode = spi->mode;
292
293 return 0;
294}
295
296static int rockchip_spi_unprepare_message(struct spi_master *master,
5dcc44ed 297 struct spi_message *msg)
64e36824 298{
299 unsigned long flags;
300 struct rockchip_spi *rs = spi_master_get_devdata(master);
301
302 spin_lock_irqsave(&rs->lock, flags);
303
5dcc44ed
AK		 304 /*
305 * For DMA mode, we need terminate DMA channel and flush
306 * fifo for the next transfer if DMA thansfer timeout.
307 * unprepare_message() was called by core if transfer complete
308 * or timeout. Maybe it is reasonable for error handling here.
309 */
64e36824 310 if (rs->use_dma) {
311 if (rs->state & RXBUSY) {
312 dmaengine_terminate_all(rs->dma_rx.ch);
313 flush_fifo(rs);
314 }
315
316 if (rs->state & TXBUSY)
317 dmaengine_terminate_all(rs->dma_tx.ch);
318 }
319
320 spin_unlock_irqrestore(&rs->lock, flags);
321
322 return 0;
323}
324
325static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
326{
327 u32 max = tx_max(rs);
328 u32 txw = 0;
329
330 while (max--) {
331 if (rs->n_bytes == 1)
332 txw = *(u8 *)(rs->tx);
333 else
334 txw = *(u16 *)(rs->tx);
335
336 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
337 rs->tx += rs->n_bytes;
338 }
339}
340
341static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
342{
343 u32 max = rx_max(rs);
344 u32 rxw;
345
346 while (max--) {
347 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
348 if (rs->n_bytes == 1)
349 *(u8 *)(rs->rx) = (u8)rxw;
350 else
351 *(u16 *)(rs->rx) = (u16)rxw;
352 rs->rx += rs->n_bytes;
5dcc44ed 353 }
64e36824 354}
355
356static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
357{
358 int remain = 0;
359
360 do {
361 if (rs->tx) {
362 remain = rs->tx_end - rs->tx;
363 rockchip_spi_pio_writer(rs);
364 }
365
366 if (rs->rx) {
367 remain = rs->rx_end - rs->rx;
368 rockchip_spi_pio_reader(rs);
369 }
370
371 cpu_relax();
372 } while (remain);
373
374 return 0;
375}
376
377static void rockchip_spi_dma_rxcb(void *data)
378{
379 unsigned long flags;
380 struct rockchip_spi *rs = data;
381
382 spin_lock_irqsave(&rs->lock, flags);
383
384 rs->state &= ~RXBUSY;
385 if (!(rs->state & TXBUSY))
386 spi_finalize_current_transfer(rs->master);
387
388 spin_unlock_irqrestore(&rs->lock, flags);
389}
390
391static void rockchip_spi_dma_txcb(void *data)
392{
393 unsigned long flags;
394 struct rockchip_spi *rs = data;
395
396 spin_lock_irqsave(&rs->lock, flags);
397
398 rs->state &= ~TXBUSY;
399 if (!(rs->state & RXBUSY))
400 spi_finalize_current_transfer(rs->master);
401
402 spin_unlock_irqrestore(&rs->lock, flags);
403}
404
405static int rockchip_spi_dma_transfer(struct rockchip_spi *rs)
406{
407 unsigned long flags;
408 struct dma_slave_config rxconf, txconf;
409 struct dma_async_tx_descriptor *rxdesc, *txdesc;
410
411 spin_lock_irqsave(&rs->lock, flags);
412 rs->state &= ~RXBUSY;
413 rs->state &= ~TXBUSY;
414 spin_unlock_irqrestore(&rs->lock, flags);
415
416 if (rs->rx) {
417 rxconf.direction = rs->dma_rx.direction;
418 rxconf.src_addr = rs->dma_rx.addr;
419 rxconf.src_addr_width = rs->n_bytes;
420 rxconf.src_maxburst = rs->n_bytes;
421 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
422
5dcc44ed
AK		 423 rxdesc = dmaengine_prep_slave_sg(
424 rs->dma_rx.ch,
64e36824 425 rs->rx_sg.sgl, rs->rx_sg.nents,
426 rs->dma_rx.direction, DMA_PREP_INTERRUPT);
427
428 rxdesc->callback = rockchip_spi_dma_rxcb;
429 rxdesc->callback_param = rs;
430 }
431
432 if (rs->tx) {
433 txconf.direction = rs->dma_tx.direction;
434 txconf.dst_addr = rs->dma_tx.addr;
435 txconf.dst_addr_width = rs->n_bytes;
436 txconf.dst_maxburst = rs->n_bytes;
437 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
438
5dcc44ed
AK		 439 txdesc = dmaengine_prep_slave_sg(
440 rs->dma_tx.ch,
64e36824 441 rs->tx_sg.sgl, rs->tx_sg.nents,
442 rs->dma_tx.direction, DMA_PREP_INTERRUPT);
443
444 txdesc->callback = rockchip_spi_dma_txcb;
445 txdesc->callback_param = rs;
446 }
447
448 /* rx must be started before tx due to spi instinct */
449 if (rs->rx) {
450 spin_lock_irqsave(&rs->lock, flags);
451 rs->state |= RXBUSY;
452 spin_unlock_irqrestore(&rs->lock, flags);
453 dmaengine_submit(rxdesc);
454 dma_async_issue_pending(rs->dma_rx.ch);
455 }
456
457 if (rs->tx) {
458 spin_lock_irqsave(&rs->lock, flags);
459 rs->state |= TXBUSY;
460 spin_unlock_irqrestore(&rs->lock, flags);
461 dmaengine_submit(txdesc);
462 dma_async_issue_pending(rs->dma_tx.ch);
463 }
464
465 return 1;
466}
467
468static void rockchip_spi_config(struct rockchip_spi *rs)
469{
470 u32 div = 0;
471 u32 dmacr = 0;
472
473 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
474 | (CR0_SSD_ONE << CR0_SSD_OFFSET);
475
476 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
477 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
478 cr0 |= (rs->tmode << CR0_XFM_OFFSET);
479 cr0 |= (rs->type << CR0_FRF_OFFSET);
480
481 if (rs->use_dma) {
482 if (rs->tx)
483 dmacr |= TF_DMA_EN;
484 if (rs->rx)
485 dmacr |= RF_DMA_EN;
486 }
487
488 /* div doesn't support odd number */
489 div = rs->max_freq / rs->speed;
490 div = (div + 1) & 0xfffe;
491
492 spi_enable_chip(rs, 0);
493
494 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
495
496 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
497 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
498 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
499
500 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
501 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
502 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
503
504 spi_set_clk(rs, div);
505
5dcc44ed 506 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
64e36824 507
508 spi_enable_chip(rs, 1);
509}
510
5dcc44ed
AK		 511static int rockchip_spi_transfer_one(
512 struct spi_master *master,
64e36824 513 struct spi_device *spi,
514 struct spi_transfer *xfer)
515{
516 int ret = 0;
517 struct rockchip_spi *rs = spi_master_get_devdata(master);
518
519 WARN_ON((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
520
521 if (!xfer->tx_buf && !xfer->rx_buf) {
522 dev_err(rs->dev, "No buffer for transfer\n");
523 return -EINVAL;
524 }
525
526 rs->speed = xfer->speed_hz;
527 rs->bpw = xfer->bits_per_word;
528 rs->n_bytes = rs->bpw >> 3;
529
530 rs->tx = xfer->tx_buf;
531 rs->tx_end = rs->tx + xfer->len;
532 rs->rx = xfer->rx_buf;
533 rs->rx_end = rs->rx + xfer->len;
534 rs->len = xfer->len;
535
536 rs->tx_sg = xfer->tx_sg;
537 rs->rx_sg = xfer->rx_sg;
538
539 /* Delay until the FIFO data completely */
540 if (xfer->tx_buf)
541 xfer->delay_usecs
542 = rs->fifo_len * rs->bpw * 1000000 / rs->speed;
543
544 if (rs->tx && rs->rx)
545 rs->tmode = CR0_XFM_TR;
546 else if (rs->tx)
547 rs->tmode = CR0_XFM_TO;
548 else if (rs->rx)
549 rs->tmode = CR0_XFM_RO;
550
551 if (master->can_dma && master->can_dma(master, spi, xfer))
552 rs->use_dma = 1;
553 else
554 rs->use_dma = 0;
555
556 rockchip_spi_config(rs);
557
558 if (rs->use_dma)
559 ret = rockchip_spi_dma_transfer(rs);
560 else
561 ret = rockchip_spi_pio_transfer(rs);
562
563 return ret;
564}
565
566static bool rockchip_spi_can_dma(struct spi_master *master,
5dcc44ed
AK		 567 struct spi_device *spi,
568 struct spi_transfer *xfer)
64e36824 569{
570 struct rockchip_spi *rs = spi_master_get_devdata(master);
571
572 return (xfer->len > rs->fifo_len);
573}
574
575static int rockchip_spi_probe(struct platform_device *pdev)
576{
577 int ret = 0;
578 struct rockchip_spi *rs;
579 struct spi_master *master;
580 struct resource *mem;
581
582 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
5dcc44ed 583 if (!master)
64e36824 584 return -ENOMEM;
5dcc44ed 585
64e36824 586 platform_set_drvdata(pdev, master);
587
588 rs = spi_master_get_devdata(master);
589 memset(rs, 0, sizeof(struct rockchip_spi));
590
591 /* Get basic io resource and map it */
592 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
593 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
594 if (IS_ERR(rs->regs)) {
595 dev_err(&pdev->dev, "Failed to map SPI region\n");
596 ret = PTR_ERR(rs->regs);
597 goto err_ioremap_resource;
598 }
599
600 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
601 if (IS_ERR(rs->apb_pclk)) {
602 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
603 ret = PTR_ERR(rs->apb_pclk);
604 goto err_ioremap_resource;
605 }
606
607 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
608 if (IS_ERR(rs->spiclk)) {
609 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
610 ret = PTR_ERR(rs->spiclk);
611 goto err_ioremap_resource;
612 }
613
614 ret = clk_prepare_enable(rs->apb_pclk);
615 if (ret) {
616 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
617 goto err_ioremap_resource;
618 }
619
620 ret = clk_prepare_enable(rs->spiclk);
621 if (ret) {
622 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
623 goto err_spiclk_enable;
624 }
625
626 spi_enable_chip(rs, 0);
627
628 rs->type = SSI_MOTO_SPI;
629 rs->master = master;
630 rs->dev = &pdev->dev;
631 rs->max_freq = clk_get_rate(rs->spiclk);
632
633 rs->fifo_len = get_fifo_len(rs);
634 if (!rs->fifo_len) {
635 dev_err(&pdev->dev, "Failed to get fifo length\n");
636 goto err_get_fifo_len;
637 }
638
639 spin_lock_init(&rs->lock);
640
641 pm_runtime_set_active(&pdev->dev);
642 pm_runtime_enable(&pdev->dev);
643
644 master->auto_runtime_pm = true;
645 master->bus_num = pdev->id;
646 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
647 master->num_chipselect = 2;
648 master->dev.of_node = pdev->dev.of_node;
649 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
650
651 master->set_cs = rockchip_spi_set_cs;
652 master->prepare_message = rockchip_spi_prepare_message;
653 master->unprepare_message = rockchip_spi_unprepare_message;
654 master->transfer_one = rockchip_spi_transfer_one;
655
656 rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
657 if (!rs->dma_tx.ch)
658 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
659
660 rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx");
661 if (!rs->dma_rx.ch) {
662 if (rs->dma_tx.ch) {
663 dma_release_channel(rs->dma_tx.ch);
664 rs->dma_tx.ch = NULL;
665 }
666 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
667 }
668
669 if (rs->dma_tx.ch && rs->dma_rx.ch) {
670 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
671 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
672 rs->dma_tx.direction = DMA_MEM_TO_DEV;
673 rs->dma_tx.direction = DMA_DEV_TO_MEM;
674
675 master->can_dma = rockchip_spi_can_dma;
676 master->dma_tx = rs->dma_tx.ch;
677 master->dma_rx = rs->dma_rx.ch;
678 }
679
680 ret = devm_spi_register_master(&pdev->dev, master);
681 if (ret) {
682 dev_err(&pdev->dev, "Failed to register master\n");
683 goto err_register_master;
684 }
685
64e36824 686 return 0;
687
688err_register_master:
689 if (rs->dma_tx.ch)
690 dma_release_channel(rs->dma_tx.ch);
691 if (rs->dma_rx.ch)
692 dma_release_channel(rs->dma_rx.ch);
693err_get_fifo_len:
694 clk_disable_unprepare(rs->spiclk);
695err_spiclk_enable:
696 clk_disable_unprepare(rs->apb_pclk);
697err_ioremap_resource:
698 spi_master_put(master);
699
700 return ret;
701}
702
703static int rockchip_spi_remove(struct platform_device *pdev)
704{
705 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
706 struct rockchip_spi *rs = spi_master_get_devdata(master);
707
708 pm_runtime_disable(&pdev->dev);
709
710 clk_disable_unprepare(rs->spiclk);
711 clk_disable_unprepare(rs->apb_pclk);
712
713 if (rs->dma_tx.ch)
714 dma_release_channel(rs->dma_tx.ch);
715 if (rs->dma_rx.ch)
716 dma_release_channel(rs->dma_rx.ch);
717
718 spi_master_put(master);
719
720 return 0;
721}
722
723#ifdef CONFIG_PM_SLEEP
724static int rockchip_spi_suspend(struct device *dev)
725{
726 int ret = 0;
727 struct spi_master *master = dev_get_drvdata(dev);
728 struct rockchip_spi *rs = spi_master_get_devdata(master);
729
730 ret = spi_master_suspend(rs->master);
731 if (ret)
732 return ret;
733
734 if (!pm_runtime_suspended(dev)) {
735 clk_disable_unprepare(rs->spiclk);
736 clk_disable_unprepare(rs->apb_pclk);
737 }
738
739 return ret;
740}
741
742static int rockchip_spi_resume(struct device *dev)
743{
744 int ret = 0;
745 struct spi_master *master = dev_get_drvdata(dev);
746 struct rockchip_spi *rs = spi_master_get_devdata(master);
747
748 if (!pm_runtime_suspended(dev)) {
749 ret = clk_prepare_enable(rs->apb_pclk);
750 if (ret < 0)
751 return ret;
752
753 ret = clk_prepare_enable(rs->spiclk);
754 if (ret < 0) {
755 clk_disable_unprepare(rs->apb_pclk);
756 return ret;
757 }
758 }
759
760 ret = spi_master_resume(rs->master);
761 if (ret < 0) {
762 clk_disable_unprepare(rs->spiclk);
763 clk_disable_unprepare(rs->apb_pclk);
764 }
765
766 return ret;
767}
768#endif /* CONFIG_PM_SLEEP */
769
770#ifdef CONFIG_PM_RUNTIME
771static int rockchip_spi_runtime_suspend(struct device *dev)
772{
773 struct spi_master *master = dev_get_drvdata(dev);
774 struct rockchip_spi *rs = spi_master_get_devdata(master);
775
776 clk_disable_unprepare(rs->spiclk);
777 clk_disable_unprepare(rs->apb_pclk);
778
779 return 0;
780}
781
782static int rockchip_spi_runtime_resume(struct device *dev)
783{
784 int ret;
785 struct spi_master *master = dev_get_drvdata(dev);
786 struct rockchip_spi *rs = spi_master_get_devdata(master);
787
788 ret = clk_prepare_enable(rs->apb_pclk);
789 if (ret)
790 return ret;
791
792 ret = clk_prepare_enable(rs->spiclk);
793 if (ret)
794 clk_disable_unprepare(rs->apb_pclk);
795
796 return ret;
797}
798#endif /* CONFIG_PM_RUNTIME */
799
800static const struct dev_pm_ops rockchip_spi_pm = {
801 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
802 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
803 rockchip_spi_runtime_resume, NULL)
804};
805
806static const struct of_device_id rockchip_spi_dt_match[] = {
807 { .compatible = "rockchip,rk3066-spi", },
808 { },
809};
810MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
811
812static struct platform_driver rockchip_spi_driver = {
813 .driver = {
814 .name = DRIVER_NAME,
815 .owner = THIS_MODULE,
816 .pm = &rockchip_spi_pm,
817 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
818 },
819 .probe = rockchip_spi_probe,
820 .remove = rockchip_spi_remove,
821};
822
823module_platform_driver(rockchip_spi_driver);
824
5dcc44ed 825MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
64e36824 826MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
827MODULE_LICENSE("GPL v2");
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