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spi: rockchip: add bindings for rk3399 spi
[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-rockchip.c
CommitLineData
64e36824 1/*
2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
5dcc44ed 3 * Author: Addy Ke <addy.ke@rock-chips.com>
64e36824 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <linux/spi/spi.h>
25#include <linux/scatterlist.h>
26#include <linux/of.h>
27#include <linux/pm_runtime.h>
28#include <linux/io.h>
64e36824 29#include <linux/dmaengine.h>
30
31#define DRIVER_NAME "rockchip-spi"
32
33/* SPI register offsets */
34#define ROCKCHIP_SPI_CTRLR0 0x0000
35#define ROCKCHIP_SPI_CTRLR1 0x0004
36#define ROCKCHIP_SPI_SSIENR 0x0008
37#define ROCKCHIP_SPI_SER 0x000c
38#define ROCKCHIP_SPI_BAUDR 0x0010
39#define ROCKCHIP_SPI_TXFTLR 0x0014
40#define ROCKCHIP_SPI_RXFTLR 0x0018
41#define ROCKCHIP_SPI_TXFLR 0x001c
42#define ROCKCHIP_SPI_RXFLR 0x0020
43#define ROCKCHIP_SPI_SR 0x0024
44#define ROCKCHIP_SPI_IPR 0x0028
45#define ROCKCHIP_SPI_IMR 0x002c
46#define ROCKCHIP_SPI_ISR 0x0030
47#define ROCKCHIP_SPI_RISR 0x0034
48#define ROCKCHIP_SPI_ICR 0x0038
49#define ROCKCHIP_SPI_DMACR 0x003c
50#define ROCKCHIP_SPI_DMATDLR 0x0040
51#define ROCKCHIP_SPI_DMARDLR 0x0044
52#define ROCKCHIP_SPI_TXDR 0x0400
53#define ROCKCHIP_SPI_RXDR 0x0800
54
55/* Bit fields in CTRLR0 */
56#define CR0_DFS_OFFSET 0
57
58#define CR0_CFS_OFFSET 2
59
60#define CR0_SCPH_OFFSET 6
61
62#define CR0_SCPOL_OFFSET 7
63
64#define CR0_CSM_OFFSET 8
65#define CR0_CSM_KEEP 0x0
66/* ss_n be high for half sclk_out cycles */
67#define CR0_CSM_HALF 0X1
68/* ss_n be high for one sclk_out cycle */
69#define CR0_CSM_ONE 0x2
70
71/* ss_n to sclk_out delay */
72#define CR0_SSD_OFFSET 10
73/*
74 * The period between ss_n active and
75 * sclk_out active is half sclk_out cycles
76 */
77#define CR0_SSD_HALF 0x0
78/*
79 * The period between ss_n active and
80 * sclk_out active is one sclk_out cycle
81 */
82#define CR0_SSD_ONE 0x1
83
84#define CR0_EM_OFFSET 11
85#define CR0_EM_LITTLE 0x0
86#define CR0_EM_BIG 0x1
87
88#define CR0_FBM_OFFSET 12
89#define CR0_FBM_MSB 0x0
90#define CR0_FBM_LSB 0x1
91
92#define CR0_BHT_OFFSET 13
93#define CR0_BHT_16BIT 0x0
94#define CR0_BHT_8BIT 0x1
95
96#define CR0_RSD_OFFSET 14
97
98#define CR0_FRF_OFFSET 16
99#define CR0_FRF_SPI 0x0
100#define CR0_FRF_SSP 0x1
101#define CR0_FRF_MICROWIRE 0x2
102
103#define CR0_XFM_OFFSET 18
104#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
105#define CR0_XFM_TR 0x0
106#define CR0_XFM_TO 0x1
107#define CR0_XFM_RO 0x2
108
109#define CR0_OPM_OFFSET 20
110#define CR0_OPM_MASTER 0x0
111#define CR0_OPM_SLAVE 0x1
112
113#define CR0_MTM_OFFSET 0x21
114
115/* Bit fields in SER, 2bit */
116#define SER_MASK 0x3
117
118/* Bit fields in SR, 5bit */
119#define SR_MASK 0x1f
120#define SR_BUSY (1 << 0)
121#define SR_TF_FULL (1 << 1)
122#define SR_TF_EMPTY (1 << 2)
123#define SR_RF_EMPTY (1 << 3)
124#define SR_RF_FULL (1 << 4)
125
126/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
127#define INT_MASK 0x1f
128#define INT_TF_EMPTY (1 << 0)
129#define INT_TF_OVERFLOW (1 << 1)
130#define INT_RF_UNDERFLOW (1 << 2)
131#define INT_RF_OVERFLOW (1 << 3)
132#define INT_RF_FULL (1 << 4)
133
134/* Bit fields in ICR, 4bit */
135#define ICR_MASK 0x0f
136#define ICR_ALL (1 << 0)
137#define ICR_RF_UNDERFLOW (1 << 1)
138#define ICR_RF_OVERFLOW (1 << 2)
139#define ICR_TF_OVERFLOW (1 << 3)
140
141/* Bit fields in DMACR */
142#define RF_DMA_EN (1 << 0)
143#define TF_DMA_EN (1 << 1)
144
145#define RXBUSY (1 << 0)
146#define TXBUSY (1 << 1)
147
f9cfd522
AK		 148/* sclk_out: spi master internal logic in rk3x can support 50Mhz */
149#define MAX_SCLK_OUT 50000000
150
64e36824 151enum rockchip_ssi_type {
152 SSI_MOTO_SPI = 0,
153 SSI_TI_SSP,
154 SSI_NS_MICROWIRE,
155};
156
157struct rockchip_spi_dma_data {
158 struct dma_chan *ch;
159 enum dma_transfer_direction direction;
160 dma_addr_t addr;
161};
162
163struct rockchip_spi {
164 struct device *dev;
165 struct spi_master *master;
166
167 struct clk *spiclk;
168 struct clk *apb_pclk;
169
170 void __iomem *regs;
171 /*depth of the FIFO buffer */
172 u32 fifo_len;
173 /* max bus freq supported */
174 u32 max_freq;
175 /* supported slave numbers */
176 enum rockchip_ssi_type type;
177
178 u16 mode;
179 u8 tmode;
180 u8 bpw;
181 u8 n_bytes;
76b17e6e 182 u8 rsd_nsecs;
64e36824 183 unsigned len;
184 u32 speed;
185
186 const void *tx;
187 const void *tx_end;
188 void *rx;
189 void *rx_end;
190
191 u32 state;
5dcc44ed 192 /* protect state */
64e36824 193 spinlock_t lock;
194
64e36824 195 u32 use_dma;
196 struct sg_table tx_sg;
197 struct sg_table rx_sg;
198 struct rockchip_spi_dma_data dma_rx;
199 struct rockchip_spi_dma_data dma_tx;
200};
201
202static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
203{
204 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
205}
206
207static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
208{
209 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
210}
211
212static inline void flush_fifo(struct rockchip_spi *rs)
213{
214 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
215 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
216}
217
2df08e78
AK		 218static inline void wait_for_idle(struct rockchip_spi *rs)
219{
220 unsigned long timeout = jiffies + msecs_to_jiffies(5);
221
222 do {
223 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
224 return;
64bc0110 225 } while (!time_after(jiffies, timeout));
2df08e78
AK		 226
227 dev_warn(rs->dev, "spi controller is in busy state!\n");
228}
229
64e36824 230static u32 get_fifo_len(struct rockchip_spi *rs)
231{
232 u32 fifo;
233
234 for (fifo = 2; fifo < 32; fifo++) {
235 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
236 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
237 break;
238 }
239
240 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
241
242 return (fifo == 31) ? 0 : fifo;
243}
244
245static inline u32 tx_max(struct rockchip_spi *rs)
246{
247 u32 tx_left, tx_room;
248
249 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
250 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
251
252 return min(tx_left, tx_room);
253}
254
255static inline u32 rx_max(struct rockchip_spi *rs)
256{
257 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
258 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
259
260 return min(rx_left, rx_room);
261}
262
263static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
264{
265 u32 ser;
266 struct rockchip_spi *rs = spi_master_get_devdata(spi->master);
267
268 ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
269
270 /*
271 * drivers/spi/spi.c:
272 * static void spi_set_cs(struct spi_device *spi, bool enable)
273 * {
274 * if (spi->mode & SPI_CS_HIGH)
275 * enable = !enable;
276 *
277 * if (spi->cs_gpio >= 0)
278 * gpio_set_value(spi->cs_gpio, !enable);
279 * else if (spi->master->set_cs)
280 * spi->master->set_cs(spi, !enable);
281 * }
282 *
283 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
284 */
285 if (!enable)
286 ser |= 1 << spi->chip_select;
287 else
288 ser &= ~(1 << spi->chip_select);
289
290 writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
291}
292
293static int rockchip_spi_prepare_message(struct spi_master *master,
5dcc44ed 294 struct spi_message *msg)
64e36824 295{
296 struct rockchip_spi *rs = spi_master_get_devdata(master);
297 struct spi_device *spi = msg->spi;
298
64e36824 299 rs->mode = spi->mode;
300
301 return 0;
302}
303
2291793c
AS		 304static void rockchip_spi_handle_err(struct spi_master *master,
305 struct spi_message *msg)
64e36824 306{
307 unsigned long flags;
308 struct rockchip_spi *rs = spi_master_get_devdata(master);
309
310 spin_lock_irqsave(&rs->lock, flags);
311
5dcc44ed
AK		 312 /*
313 * For DMA mode, we need terminate DMA channel and flush
314 * fifo for the next transfer if DMA thansfer timeout.
2291793c
AS		 315 * handle_err() was called by core if transfer failed.
316 * Maybe it is reasonable for error handling here.
5dcc44ed 317 */
64e36824 318 if (rs->use_dma) {
319 if (rs->state & RXBUSY) {
320 dmaengine_terminate_all(rs->dma_rx.ch);
321 flush_fifo(rs);
322 }
323
324 if (rs->state & TXBUSY)
325 dmaengine_terminate_all(rs->dma_tx.ch);
326 }
327
328 spin_unlock_irqrestore(&rs->lock, flags);
2291793c
AS		 329}
330
331static int rockchip_spi_unprepare_message(struct spi_master *master,
332 struct spi_message *msg)
333{
334 struct rockchip_spi *rs = spi_master_get_devdata(master);
64e36824 335
c28be31b
AK		 336 spi_enable_chip(rs, 0);
337
64e36824 338 return 0;
339}
340
341static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
342{
343 u32 max = tx_max(rs);
344 u32 txw = 0;
345
346 while (max--) {
347 if (rs->n_bytes == 1)
348 txw = *(u8 *)(rs->tx);
349 else
350 txw = *(u16 *)(rs->tx);
351
352 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
353 rs->tx += rs->n_bytes;
354 }
355}
356
357static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
358{
359 u32 max = rx_max(rs);
360 u32 rxw;
361
362 while (max--) {
363 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
364 if (rs->n_bytes == 1)
365 *(u8 *)(rs->rx) = (u8)rxw;
366 else
367 *(u16 *)(rs->rx) = (u16)rxw;
368 rs->rx += rs->n_bytes;
5dcc44ed 369 }
64e36824 370}
371
372static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
373{
374 int remain = 0;
375
376 do {
377 if (rs->tx) {
378 remain = rs->tx_end - rs->tx;
379 rockchip_spi_pio_writer(rs);
380 }
381
382 if (rs->rx) {
383 remain = rs->rx_end - rs->rx;
384 rockchip_spi_pio_reader(rs);
385 }
386
387 cpu_relax();
388 } while (remain);
389
2df08e78
AK		 390 /* If tx, wait until the FIFO data completely. */
391 if (rs->tx)
392 wait_for_idle(rs);
393
c28be31b
AK		 394 spi_enable_chip(rs, 0);
395
64e36824 396 return 0;
397}
398
399static void rockchip_spi_dma_rxcb(void *data)
400{
401 unsigned long flags;
402 struct rockchip_spi *rs = data;
403
404 spin_lock_irqsave(&rs->lock, flags);
405
406 rs->state &= ~RXBUSY;
c28be31b
AK		 407 if (!(rs->state & TXBUSY)) {
408 spi_enable_chip(rs, 0);
64e36824 409 spi_finalize_current_transfer(rs->master);
c28be31b 410 }
64e36824 411
412 spin_unlock_irqrestore(&rs->lock, flags);
413}
414
415static void rockchip_spi_dma_txcb(void *data)
416{
417 unsigned long flags;
418 struct rockchip_spi *rs = data;
419
2df08e78
AK		 420 /* Wait until the FIFO data completely. */
421 wait_for_idle(rs);
422
64e36824 423 spin_lock_irqsave(&rs->lock, flags);
424
425 rs->state &= ~TXBUSY;
2c2bc748
AK		 426 if (!(rs->state & RXBUSY)) {
427 spi_enable_chip(rs, 0);
64e36824 428 spi_finalize_current_transfer(rs->master);
2c2bc748 429 }
64e36824 430
431 spin_unlock_irqrestore(&rs->lock, flags);
432}
433
a24e70c0 434static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
64e36824 435{
436 unsigned long flags;
437 struct dma_slave_config rxconf, txconf;
438 struct dma_async_tx_descriptor *rxdesc, *txdesc;
439
440 spin_lock_irqsave(&rs->lock, flags);
441 rs->state &= ~RXBUSY;
442 rs->state &= ~TXBUSY;
443 spin_unlock_irqrestore(&rs->lock, flags);
444
97cf5669 445 rxdesc = NULL;
64e36824 446 if (rs->rx) {
447 rxconf.direction = rs->dma_rx.direction;
448 rxconf.src_addr = rs->dma_rx.addr;
449 rxconf.src_addr_width = rs->n_bytes;
450 rxconf.src_maxburst = rs->n_bytes;
451 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
452
5dcc44ed
AK		 453 rxdesc = dmaengine_prep_slave_sg(
454 rs->dma_rx.ch,
64e36824 455 rs->rx_sg.sgl, rs->rx_sg.nents,
456 rs->dma_rx.direction, DMA_PREP_INTERRUPT);
457
458 rxdesc->callback = rockchip_spi_dma_rxcb;
459 rxdesc->callback_param = rs;
460 }
461
97cf5669 462 txdesc = NULL;
64e36824 463 if (rs->tx) {
464 txconf.direction = rs->dma_tx.direction;
465 txconf.dst_addr = rs->dma_tx.addr;
466 txconf.dst_addr_width = rs->n_bytes;
467 txconf.dst_maxburst = rs->n_bytes;
468 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
469
5dcc44ed
AK		 470 txdesc = dmaengine_prep_slave_sg(
471 rs->dma_tx.ch,
64e36824 472 rs->tx_sg.sgl, rs->tx_sg.nents,
473 rs->dma_tx.direction, DMA_PREP_INTERRUPT);
474
475 txdesc->callback = rockchip_spi_dma_txcb;
476 txdesc->callback_param = rs;
477 }
478
479 /* rx must be started before tx due to spi instinct */
97cf5669 480 if (rxdesc) {
64e36824 481 spin_lock_irqsave(&rs->lock, flags);
482 rs->state |= RXBUSY;
483 spin_unlock_irqrestore(&rs->lock, flags);
484 dmaengine_submit(rxdesc);
485 dma_async_issue_pending(rs->dma_rx.ch);
486 }
487
97cf5669 488 if (txdesc) {
64e36824 489 spin_lock_irqsave(&rs->lock, flags);
490 rs->state |= TXBUSY;
491 spin_unlock_irqrestore(&rs->lock, flags);
492 dmaengine_submit(txdesc);
493 dma_async_issue_pending(rs->dma_tx.ch);
494 }
64e36824 495}
496
497static void rockchip_spi_config(struct rockchip_spi *rs)
498{
499 u32 div = 0;
500 u32 dmacr = 0;
76b17e6e 501 int rsd = 0;
64e36824 502
503 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
504 | (CR0_SSD_ONE << CR0_SSD_OFFSET);
505
506 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
507 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
508 cr0 |= (rs->tmode << CR0_XFM_OFFSET);
509 cr0 |= (rs->type << CR0_FRF_OFFSET);
510
511 if (rs->use_dma) {
512 if (rs->tx)
513 dmacr |= TF_DMA_EN;
514 if (rs->rx)
515 dmacr |= RF_DMA_EN;
516 }
517
f9cfd522
AK		 518 if (WARN_ON(rs->speed > MAX_SCLK_OUT))
519 rs->speed = MAX_SCLK_OUT;
520
521 /* the minimum divsor is 2 */
522 if (rs->max_freq < 2 * rs->speed) {
523 clk_set_rate(rs->spiclk, 2 * rs->speed);
524 rs->max_freq = clk_get_rate(rs->spiclk);
525 }
526
64e36824 527 /* div doesn't support odd number */
754ec43c 528 div = DIV_ROUND_UP(rs->max_freq, rs->speed);
64e36824 529 div = (div + 1) & 0xfffe;
530
76b17e6e
JW		 531 /* Rx sample delay is expressed in parent clock cycles (max 3) */
532 rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
533 1000000000 >> 8);
534 if (!rsd && rs->rsd_nsecs) {
535 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
536 rs->max_freq, rs->rsd_nsecs);
537 } else if (rsd > 3) {
538 rsd = 3;
539 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
540 rs->max_freq, rs->rsd_nsecs,
541 rsd * 1000000000U / rs->max_freq);
542 }
543 cr0 |= rsd << CR0_RSD_OFFSET;
544
64e36824 545 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
546
547 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
548 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
549 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
550
551 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
552 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
553 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
554
555 spi_set_clk(rs, div);
556
5dcc44ed 557 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
64e36824 558}
559
5dcc44ed
AK		 560static int rockchip_spi_transfer_one(
561 struct spi_master *master,
64e36824 562 struct spi_device *spi,
563 struct spi_transfer *xfer)
564{
c28be31b 565 int ret = 1;
64e36824 566 struct rockchip_spi *rs = spi_master_get_devdata(master);
567
62946172
DA		 568 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
569 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
64e36824 570
571 if (!xfer->tx_buf && !xfer->rx_buf) {
572 dev_err(rs->dev, "No buffer for transfer\n");
573 return -EINVAL;
574 }
575
576 rs->speed = xfer->speed_hz;
577 rs->bpw = xfer->bits_per_word;
578 rs->n_bytes = rs->bpw >> 3;
579
580 rs->tx = xfer->tx_buf;
581 rs->tx_end = rs->tx + xfer->len;
582 rs->rx = xfer->rx_buf;
583 rs->rx_end = rs->rx + xfer->len;
584 rs->len = xfer->len;
585
586 rs->tx_sg = xfer->tx_sg;
587 rs->rx_sg = xfer->rx_sg;
588
64e36824 589 if (rs->tx && rs->rx)
590 rs->tmode = CR0_XFM_TR;
591 else if (rs->tx)
592 rs->tmode = CR0_XFM_TO;
593 else if (rs->rx)
594 rs->tmode = CR0_XFM_RO;
595
a24e70c0 596 /* we need prepare dma before spi was enabled */
c28be31b 597 if (master->can_dma && master->can_dma(master, spi, xfer))
64e36824 598 rs->use_dma = 1;
c28be31b 599 else
64e36824 600 rs->use_dma = 0;
601
602 rockchip_spi_config(rs);
603
c28be31b
AK		 604 if (rs->use_dma) {
605 if (rs->tmode == CR0_XFM_RO) {
606 /* rx: dma must be prepared first */
607 rockchip_spi_prepare_dma(rs);
608 spi_enable_chip(rs, 1);
609 } else {
610 /* tx or tr: spi must be enabled first */
611 spi_enable_chip(rs, 1);
612 rockchip_spi_prepare_dma(rs);
613 }
614 } else {
615 spi_enable_chip(rs, 1);
64e36824 616 ret = rockchip_spi_pio_transfer(rs);
c28be31b 617 }
64e36824 618
619 return ret;
620}
621
622static bool rockchip_spi_can_dma(struct spi_master *master,
5dcc44ed
AK		 623 struct spi_device *spi,
624 struct spi_transfer *xfer)
64e36824 625{
626 struct rockchip_spi *rs = spi_master_get_devdata(master);
627
628 return (xfer->len > rs->fifo_len);
629}
630
631static int rockchip_spi_probe(struct platform_device *pdev)
632{
633 int ret = 0;
634 struct rockchip_spi *rs;
635 struct spi_master *master;
636 struct resource *mem;
76b17e6e 637 u32 rsd_nsecs;
64e36824 638
639 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
5dcc44ed 640 if (!master)
64e36824 641 return -ENOMEM;
5dcc44ed 642
64e36824 643 platform_set_drvdata(pdev, master);
644
645 rs = spi_master_get_devdata(master);
64e36824 646
647 /* Get basic io resource and map it */
648 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
649 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
650 if (IS_ERR(rs->regs)) {
64e36824 651 ret = PTR_ERR(rs->regs);
652 goto err_ioremap_resource;
653 }
654
655 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
656 if (IS_ERR(rs->apb_pclk)) {
657 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
658 ret = PTR_ERR(rs->apb_pclk);
659 goto err_ioremap_resource;
660 }
661
662 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
663 if (IS_ERR(rs->spiclk)) {
664 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
665 ret = PTR_ERR(rs->spiclk);
666 goto err_ioremap_resource;
667 }
668
669 ret = clk_prepare_enable(rs->apb_pclk);
670 if (ret) {
671 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
672 goto err_ioremap_resource;
673 }
674
675 ret = clk_prepare_enable(rs->spiclk);
676 if (ret) {
677 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
678 goto err_spiclk_enable;
679 }
680
681 spi_enable_chip(rs, 0);
682
683 rs->type = SSI_MOTO_SPI;
684 rs->master = master;
685 rs->dev = &pdev->dev;
686 rs->max_freq = clk_get_rate(rs->spiclk);
687
76b17e6e
JW		 688 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
689 &rsd_nsecs))
690 rs->rsd_nsecs = rsd_nsecs;
691
64e36824 692 rs->fifo_len = get_fifo_len(rs);
693 if (!rs->fifo_len) {
694 dev_err(&pdev->dev, "Failed to get fifo length\n");
db7e8d90 695 ret = -EINVAL;
64e36824 696 goto err_get_fifo_len;
697 }
698
699 spin_lock_init(&rs->lock);
700
701 pm_runtime_set_active(&pdev->dev);
702 pm_runtime_enable(&pdev->dev);
703
704 master->auto_runtime_pm = true;
705 master->bus_num = pdev->id;
ee780997 706 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
64e36824 707 master->num_chipselect = 2;
708 master->dev.of_node = pdev->dev.of_node;
709 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
710
711 master->set_cs = rockchip_spi_set_cs;
712 master->prepare_message = rockchip_spi_prepare_message;
713 master->unprepare_message = rockchip_spi_unprepare_message;
714 master->transfer_one = rockchip_spi_transfer_one;
2291793c 715 master->handle_err = rockchip_spi_handle_err;
64e36824 716
717 rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
718 if (!rs->dma_tx.ch)
719 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
720
721 rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx");
722 if (!rs->dma_rx.ch) {
723 if (rs->dma_tx.ch) {
724 dma_release_channel(rs->dma_tx.ch);
725 rs->dma_tx.ch = NULL;
726 }
727 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
728 }
729
730 if (rs->dma_tx.ch && rs->dma_rx.ch) {
731 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
732 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
733 rs->dma_tx.direction = DMA_MEM_TO_DEV;
0ac7a490 734 rs->dma_rx.direction = DMA_DEV_TO_MEM;
64e36824 735
736 master->can_dma = rockchip_spi_can_dma;
737 master->dma_tx = rs->dma_tx.ch;
738 master->dma_rx = rs->dma_rx.ch;
739 }
740
741 ret = devm_spi_register_master(&pdev->dev, master);
742 if (ret) {
743 dev_err(&pdev->dev, "Failed to register master\n");
744 goto err_register_master;
745 }
746
64e36824 747 return 0;
748
749err_register_master:
750 if (rs->dma_tx.ch)
751 dma_release_channel(rs->dma_tx.ch);
752 if (rs->dma_rx.ch)
753 dma_release_channel(rs->dma_rx.ch);
754err_get_fifo_len:
755 clk_disable_unprepare(rs->spiclk);
756err_spiclk_enable:
757 clk_disable_unprepare(rs->apb_pclk);
758err_ioremap_resource:
759 spi_master_put(master);
760
761 return ret;
762}
763
764static int rockchip_spi_remove(struct platform_device *pdev)
765{
766 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
767 struct rockchip_spi *rs = spi_master_get_devdata(master);
768
769 pm_runtime_disable(&pdev->dev);
770
771 clk_disable_unprepare(rs->spiclk);
772 clk_disable_unprepare(rs->apb_pclk);
773
774 if (rs->dma_tx.ch)
775 dma_release_channel(rs->dma_tx.ch);
776 if (rs->dma_rx.ch)
777 dma_release_channel(rs->dma_rx.ch);
778
64e36824 779 return 0;
780}
781
782#ifdef CONFIG_PM_SLEEP
783static int rockchip_spi_suspend(struct device *dev)
784{
785 int ret = 0;
786 struct spi_master *master = dev_get_drvdata(dev);
787 struct rockchip_spi *rs = spi_master_get_devdata(master);
788
789 ret = spi_master_suspend(rs->master);
790 if (ret)
791 return ret;
792
793 if (!pm_runtime_suspended(dev)) {
794 clk_disable_unprepare(rs->spiclk);
795 clk_disable_unprepare(rs->apb_pclk);
796 }
797
798 return ret;
799}
800
801static int rockchip_spi_resume(struct device *dev)
802{
803 int ret = 0;
804 struct spi_master *master = dev_get_drvdata(dev);
805 struct rockchip_spi *rs = spi_master_get_devdata(master);
806
807 if (!pm_runtime_suspended(dev)) {
808 ret = clk_prepare_enable(rs->apb_pclk);
809 if (ret < 0)
810 return ret;
811
812 ret = clk_prepare_enable(rs->spiclk);
813 if (ret < 0) {
814 clk_disable_unprepare(rs->apb_pclk);
815 return ret;
816 }
817 }
818
819 ret = spi_master_resume(rs->master);
820 if (ret < 0) {
821 clk_disable_unprepare(rs->spiclk);
822 clk_disable_unprepare(rs->apb_pclk);
823 }
824
825 return ret;
826}
827#endif /* CONFIG_PM_SLEEP */
828
ec833050 829#ifdef CONFIG_PM
64e36824 830static int rockchip_spi_runtime_suspend(struct device *dev)
831{
832 struct spi_master *master = dev_get_drvdata(dev);
833 struct rockchip_spi *rs = spi_master_get_devdata(master);
834
835 clk_disable_unprepare(rs->spiclk);
836 clk_disable_unprepare(rs->apb_pclk);
837
838 return 0;
839}
840
841static int rockchip_spi_runtime_resume(struct device *dev)
842{
843 int ret;
844 struct spi_master *master = dev_get_drvdata(dev);
845 struct rockchip_spi *rs = spi_master_get_devdata(master);
846
847 ret = clk_prepare_enable(rs->apb_pclk);
848 if (ret)
849 return ret;
850
851 ret = clk_prepare_enable(rs->spiclk);
852 if (ret)
853 clk_disable_unprepare(rs->apb_pclk);
854
855 return ret;
856}
ec833050 857#endif /* CONFIG_PM */
64e36824 858
859static const struct dev_pm_ops rockchip_spi_pm = {
860 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
861 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
862 rockchip_spi_runtime_resume, NULL)
863};
864
865static const struct of_device_id rockchip_spi_dt_match[] = {
866 { .compatible = "rockchip,rk3066-spi", },
b839b785
AK		 867 { .compatible = "rockchip,rk3188-spi", },
868 { .compatible = "rockchip,rk3288-spi", },
9b7a5622 869 { .compatible = "rockchip,rk3399-spi", },
64e36824 870 { },
871};
872MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
873
874static struct platform_driver rockchip_spi_driver = {
875 .driver = {
876 .name = DRIVER_NAME,
64e36824 877 .pm = &rockchip_spi_pm,
878 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
879 },
880 .probe = rockchip_spi_probe,
881 .remove = rockchip_spi_remove,
882};
883
884module_platform_driver(rockchip_spi_driver);
885
5dcc44ed 886MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
64e36824 887MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
888MODULE_LICENSE("GPL v2");
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