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0b2182dd SY |
1 | /* |
2 | * SH RSPI driver | |
3 | * | |
4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
5 | * | |
6 | * Based on spi-sh.c: | |
7 | * Copyright (C) 2011 Renesas Solutions Corp. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/errno.h> | |
0b2182dd SY |
28 | #include <linux/interrupt.h> |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/clk.h> | |
a3633fe7 SY |
32 | #include <linux/dmaengine.h> |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/sh_dma.h> | |
0b2182dd | 35 | #include <linux/spi/spi.h> |
a3633fe7 | 36 | #include <linux/spi/rspi.h> |
0b2182dd | 37 | |
6ab4865b GU |
38 | #define RSPI_SPCR 0x00 /* Control Register */ |
39 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ | |
40 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ | |
41 | #define RSPI_SPSR 0x03 /* Status Register */ | |
42 | #define RSPI_SPDR 0x04 /* Data Register */ | |
43 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ | |
44 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ | |
45 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ | |
46 | #define RSPI_SPDCR 0x0b /* Data Control Register */ | |
47 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ | |
48 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ | |
49 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ | |
50 | #define RSPI_SPCR2 0x0f /* Control Register 2 */ | |
51 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ | |
52 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ | |
53 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ | |
54 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ | |
55 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ | |
56 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ | |
57 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ | |
58 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ | |
59 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ | |
60 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ | |
0b2182dd | 61 | |
5ce0ba88 | 62 | /*qspi only */ |
fbe5072b GU |
63 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
64 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ | |
65 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ | |
66 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ | |
67 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ | |
68 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ | |
5ce0ba88 | 69 | |
6ab4865b GU |
70 | /* SPCR - Control Register */ |
71 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ | |
72 | #define SPCR_SPE 0x40 /* Function Enable */ | |
73 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ | |
74 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ | |
75 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ | |
76 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ | |
77 | /* RSPI on SH only */ | |
78 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ | |
79 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ | |
fbe5072b GU |
80 | /* QSPI on R-Car M2 only */ |
81 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ | |
82 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ | |
6ab4865b GU |
83 | |
84 | /* SSLP - Slave Select Polarity Register */ | |
85 | #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ | |
86 | #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ | |
87 | ||
88 | /* SPPCR - Pin Control Register */ | |
89 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ | |
90 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ | |
0b2182dd | 91 | #define SPPCR_SPOM 0x04 |
6ab4865b GU |
92 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
93 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ | |
94 | ||
fbe5072b GU |
95 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
96 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ | |
97 | ||
6ab4865b GU |
98 | /* SPSR - Status Register */ |
99 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ | |
100 | #define SPSR_TEND 0x40 /* Transmit End */ | |
101 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ | |
102 | #define SPSR_PERF 0x08 /* Parity Error Flag */ | |
103 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ | |
104 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ | |
105 | #define SPSR_OVRF 0x01 /* Overrun Error Flag */ | |
106 | ||
107 | /* SPSCR - Sequence Control Register */ | |
108 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ | |
109 | ||
110 | /* SPSSR - Sequence Status Register */ | |
111 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ | |
112 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ | |
113 | ||
114 | /* SPDCR - Data Control Register */ | |
115 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ | |
116 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ | |
117 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ | |
118 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) | |
119 | #define SPDCR_SPLWORD SPDCR_SPLW1 | |
120 | #define SPDCR_SPLBYTE SPDCR_SPLW0 | |
121 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ | |
122 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select */ | |
0b2182dd SY |
123 | #define SPDCR_SLSEL1 0x08 |
124 | #define SPDCR_SLSEL0 0x04 | |
6ab4865b | 125 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select */ |
0b2182dd SY |
126 | #define SPDCR_SPFC1 0x02 |
127 | #define SPDCR_SPFC0 0x01 | |
6ab4865b | 128 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) */ |
0b2182dd | 129 | |
6ab4865b GU |
130 | /* SPCKD - Clock Delay Register */ |
131 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ | |
0b2182dd | 132 | |
6ab4865b GU |
133 | /* SSLND - Slave Select Negation Delay Register */ |
134 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ | |
0b2182dd | 135 | |
6ab4865b GU |
136 | /* SPND - Next-Access Delay Register */ |
137 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ | |
0b2182dd | 138 | |
6ab4865b GU |
139 | /* SPCR2 - Control Register 2 */ |
140 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ | |
141 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ | |
142 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ | |
143 | #define SPCR2_SPPE 0x01 /* Parity Enable */ | |
0b2182dd | 144 | |
6ab4865b GU |
145 | /* SPCMDn - Command Registers */ |
146 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ | |
147 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ | |
148 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ | |
149 | #define SPCMD_LSBF 0x1000 /* LSB First */ | |
150 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ | |
0b2182dd | 151 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
5ce0ba88 HCM |
152 | #define SPCMD_SPB_8BIT 0x0000 /* qspi only */ |
153 | #define SPCMD_SPB_16BIT 0x0100 | |
0b2182dd SY |
154 | #define SPCMD_SPB_20BIT 0x0000 |
155 | #define SPCMD_SPB_24BIT 0x0100 | |
156 | #define SPCMD_SPB_32BIT 0x0200 | |
6ab4865b | 157 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
fbe5072b GU |
158 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
159 | #define SPCMD_SPIMOD1 0x0040 | |
160 | #define SPCMD_SPIMOD0 0x0020 | |
161 | #define SPCMD_SPIMOD_SINGLE 0 | |
162 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 | |
163 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 | |
164 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ | |
6ab4865b GU |
165 | #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ |
166 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ | |
167 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ | |
168 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ | |
169 | ||
170 | /* SPBFCR - Buffer Control Register */ | |
171 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset (qspi only) */ | |
172 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset (qspi only) */ | |
173 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ | |
174 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ | |
5ce0ba88 | 175 | |
2aae80b2 GU |
176 | #define DUMMY_DATA 0x00 |
177 | ||
0b2182dd SY |
178 | struct rspi_data { |
179 | void __iomem *addr; | |
180 | u32 max_speed_hz; | |
181 | struct spi_master *master; | |
0b2182dd | 182 | wait_queue_head_t wait; |
0b2182dd | 183 | struct clk *clk; |
97b95c11 | 184 | u8 spsr; |
348e5153 | 185 | u16 spcmd; |
5ce0ba88 | 186 | const struct spi_ops *ops; |
a3633fe7 SY |
187 | |
188 | /* for dmaengine */ | |
a3633fe7 SY |
189 | struct dma_chan *chan_tx; |
190 | struct dma_chan *chan_rx; | |
191 | int irq; | |
192 | ||
193 | unsigned dma_width_16bit:1; | |
194 | unsigned dma_callbacked:1; | |
74da7686 | 195 | unsigned byte_access:1; |
0b2182dd SY |
196 | }; |
197 | ||
baf588f4 | 198 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
0b2182dd SY |
199 | { |
200 | iowrite8(data, rspi->addr + offset); | |
201 | } | |
202 | ||
baf588f4 | 203 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
0b2182dd SY |
204 | { |
205 | iowrite16(data, rspi->addr + offset); | |
206 | } | |
207 | ||
baf588f4 | 208 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
5ce0ba88 HCM |
209 | { |
210 | iowrite32(data, rspi->addr + offset); | |
211 | } | |
212 | ||
baf588f4 | 213 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
214 | { |
215 | return ioread8(rspi->addr + offset); | |
216 | } | |
217 | ||
baf588f4 | 218 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
219 | { |
220 | return ioread16(rspi->addr + offset); | |
221 | } | |
222 | ||
74da7686 GU |
223 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
224 | { | |
225 | if (rspi->byte_access) | |
226 | rspi_write8(rspi, data, RSPI_SPDR); | |
227 | else /* 16 bit */ | |
228 | rspi_write16(rspi, data, RSPI_SPDR); | |
229 | } | |
230 | ||
231 | static u16 rspi_read_data(const struct rspi_data *rspi) | |
232 | { | |
233 | if (rspi->byte_access) | |
234 | return rspi_read8(rspi, RSPI_SPDR); | |
235 | else /* 16 bit */ | |
236 | return rspi_read16(rspi, RSPI_SPDR); | |
237 | } | |
238 | ||
5ce0ba88 HCM |
239 | /* optional functions */ |
240 | struct spi_ops { | |
74da7686 | 241 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
eb557f75 GU |
242 | int (*transfer_one)(struct spi_master *master, struct spi_device *spi, |
243 | struct spi_transfer *xfer); | |
5ce0ba88 HCM |
244 | }; |
245 | ||
246 | /* | |
247 | * functions for RSPI | |
248 | */ | |
74da7686 | 249 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
0b2182dd | 250 | { |
5ce0ba88 HCM |
251 | int spbr; |
252 | ||
253 | /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ | |
254 | rspi_write8(rspi, 0x00, RSPI_SPPCR); | |
0b2182dd | 255 | |
5ce0ba88 HCM |
256 | /* Sets transfer bit rate */ |
257 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1; | |
258 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
259 | ||
74da7686 GU |
260 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
261 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
262 | rspi->byte_access = 0; | |
0b2182dd | 263 | |
5ce0ba88 HCM |
264 | /* Sets RSPCK, SSL, next-access delay value */ |
265 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
266 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
267 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
268 | ||
269 | /* Sets parity, interrupt mask */ | |
270 | rspi_write8(rspi, 0x00, RSPI_SPCR2); | |
271 | ||
272 | /* Sets SPCMD */ | |
348e5153 | 273 | rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd, |
5ce0ba88 HCM |
274 | RSPI_SPCMD0); |
275 | ||
276 | /* Sets RSPI mode */ | |
277 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
278 | ||
279 | return 0; | |
0b2182dd SY |
280 | } |
281 | ||
5ce0ba88 HCM |
282 | /* |
283 | * functions for QSPI | |
284 | */ | |
74da7686 | 285 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
5ce0ba88 HCM |
286 | { |
287 | u16 spcmd; | |
288 | int spbr; | |
289 | ||
290 | /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */ | |
291 | rspi_write8(rspi, 0x00, RSPI_SPPCR); | |
292 | ||
293 | /* Sets transfer bit rate */ | |
294 | spbr = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz); | |
295 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); | |
296 | ||
74da7686 GU |
297 | /* Disable dummy transmission, set byte access */ |
298 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
299 | rspi->byte_access = 1; | |
5ce0ba88 HCM |
300 | |
301 | /* Sets RSPCK, SSL, next-access delay value */ | |
302 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
303 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
304 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
305 | ||
306 | /* Data Length Setting */ | |
307 | if (access_size == 8) | |
308 | spcmd = SPCMD_SPB_8BIT; | |
309 | else if (access_size == 16) | |
310 | spcmd = SPCMD_SPB_16BIT; | |
8e1c8096 | 311 | else |
5ce0ba88 HCM |
312 | spcmd = SPCMD_SPB_32BIT; |
313 | ||
348e5153 | 314 | spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN; |
5ce0ba88 HCM |
315 | |
316 | /* Resets transfer data length */ | |
317 | rspi_write32(rspi, 0, QSPI_SPBMUL0); | |
318 | ||
319 | /* Resets transmit and receive buffer */ | |
320 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); | |
321 | /* Sets buffer to allow normal operation */ | |
322 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
323 | ||
324 | /* Sets SPCMD */ | |
325 | rspi_write16(rspi, spcmd, RSPI_SPCMD0); | |
326 | ||
327 | /* Enables SPI function in a master mode */ | |
328 | rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) | |
334 | ||
baf588f4 | 335 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
0b2182dd SY |
336 | { |
337 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); | |
338 | } | |
339 | ||
baf588f4 | 340 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
0b2182dd SY |
341 | { |
342 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); | |
343 | } | |
344 | ||
345 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, | |
346 | u8 enable_bit) | |
347 | { | |
348 | int ret; | |
349 | ||
350 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); | |
351 | rspi_enable_irq(rspi, enable_bit); | |
352 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); | |
353 | if (ret == 0 && !(rspi->spsr & wait_mask)) | |
354 | return -ETIMEDOUT; | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
35301c99 GU |
359 | static int rspi_data_out(struct rspi_data *rspi, u8 data) |
360 | { | |
361 | if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) { | |
362 | dev_err(&rspi->master->dev, "transmit timeout\n"); | |
363 | return -ETIMEDOUT; | |
364 | } | |
365 | rspi_write_data(rspi, data); | |
366 | return 0; | |
367 | } | |
368 | ||
369 | static int rspi_data_in(struct rspi_data *rspi) | |
370 | { | |
371 | u8 data; | |
372 | ||
373 | if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) { | |
374 | dev_err(&rspi->master->dev, "receive timeout\n"); | |
375 | return -ETIMEDOUT; | |
376 | } | |
377 | data = rspi_read_data(rspi); | |
378 | return data; | |
379 | } | |
380 | ||
381 | static int rspi_data_out_in(struct rspi_data *rspi, u8 data) | |
382 | { | |
383 | int ret; | |
384 | ||
385 | ret = rspi_data_out(rspi, data); | |
386 | if (ret < 0) | |
387 | return ret; | |
388 | ||
389 | return rspi_data_in(rspi); | |
390 | } | |
391 | ||
a3633fe7 SY |
392 | static void rspi_dma_complete(void *arg) |
393 | { | |
394 | struct rspi_data *rspi = arg; | |
395 | ||
396 | rspi->dma_callbacked = 1; | |
397 | wake_up_interruptible(&rspi->wait); | |
398 | } | |
399 | ||
c132f094 GU |
400 | static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf, |
401 | unsigned len, struct dma_chan *chan, | |
a3633fe7 SY |
402 | enum dma_transfer_direction dir) |
403 | { | |
404 | sg_init_table(sg, 1); | |
405 | sg_set_buf(sg, buf, len); | |
406 | sg_dma_len(sg) = len; | |
407 | return dma_map_sg(chan->device->dev, sg, 1, dir); | |
408 | } | |
409 | ||
410 | static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan, | |
411 | enum dma_transfer_direction dir) | |
412 | { | |
413 | dma_unmap_sg(chan->device->dev, sg, 1, dir); | |
414 | } | |
415 | ||
416 | static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len) | |
417 | { | |
418 | u16 *dst = buf; | |
419 | const u8 *src = data; | |
420 | ||
421 | while (len) { | |
422 | *dst++ = (u16)(*src++); | |
423 | len--; | |
424 | } | |
425 | } | |
426 | ||
427 | static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len) | |
428 | { | |
429 | u8 *dst = buf; | |
430 | const u16 *src = data; | |
431 | ||
432 | while (len) { | |
433 | *dst++ = (u8)*src++; | |
434 | len--; | |
435 | } | |
436 | } | |
437 | ||
438 | static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t) | |
439 | { | |
440 | struct scatterlist sg; | |
c132f094 | 441 | const void *buf = NULL; |
a3633fe7 SY |
442 | struct dma_async_tx_descriptor *desc; |
443 | unsigned len; | |
444 | int ret = 0; | |
445 | ||
446 | if (rspi->dma_width_16bit) { | |
c132f094 | 447 | void *tmp; |
a3633fe7 SY |
448 | /* |
449 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
450 | * buffer. And, the driver converts original data into the | |
451 | * DMAC data as the following format: | |
452 | * original data: 1st byte, 2nd byte ... | |
453 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
454 | */ | |
455 | len = t->len * 2; | |
c132f094 GU |
456 | tmp = kmalloc(len, GFP_KERNEL); |
457 | if (!tmp) | |
a3633fe7 | 458 | return -ENOMEM; |
c132f094 GU |
459 | rspi_memory_to_8bit(tmp, t->tx_buf, t->len); |
460 | buf = tmp; | |
a3633fe7 SY |
461 | } else { |
462 | len = t->len; | |
c132f094 | 463 | buf = t->tx_buf; |
a3633fe7 SY |
464 | } |
465 | ||
466 | if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) { | |
467 | ret = -EFAULT; | |
468 | goto end_nomap; | |
469 | } | |
470 | desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE, | |
471 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
472 | if (!desc) { | |
473 | ret = -EIO; | |
474 | goto end; | |
475 | } | |
476 | ||
477 | /* | |
478 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
479 | * called. So, this driver disables the IRQ while DMA transfer. | |
480 | */ | |
481 | disable_irq(rspi->irq); | |
482 | ||
483 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR); | |
484 | rspi_enable_irq(rspi, SPCR_SPTIE); | |
485 | rspi->dma_callbacked = 0; | |
486 | ||
487 | desc->callback = rspi_dma_complete; | |
488 | desc->callback_param = rspi; | |
489 | dmaengine_submit(desc); | |
490 | dma_async_issue_pending(rspi->chan_tx); | |
491 | ||
492 | ret = wait_event_interruptible_timeout(rspi->wait, | |
493 | rspi->dma_callbacked, HZ); | |
494 | if (ret > 0 && rspi->dma_callbacked) | |
495 | ret = 0; | |
496 | else if (!ret) | |
497 | ret = -ETIMEDOUT; | |
498 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
499 | ||
500 | enable_irq(rspi->irq); | |
501 | ||
502 | end: | |
503 | rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE); | |
504 | end_nomap: | |
505 | if (rspi->dma_width_16bit) | |
506 | kfree(buf); | |
507 | ||
508 | return ret; | |
509 | } | |
510 | ||
baf588f4 | 511 | static void rspi_receive_init(const struct rspi_data *rspi) |
0b2182dd | 512 | { |
97b95c11 | 513 | u8 spsr; |
0b2182dd SY |
514 | |
515 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
516 | if (spsr & SPSR_SPRF) | |
74da7686 | 517 | rspi_read_data(rspi); /* dummy read */ |
0b2182dd SY |
518 | if (spsr & SPSR_OVRF) |
519 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, | |
df900e67 | 520 | RSPI_SPSR); |
a3633fe7 SY |
521 | } |
522 | ||
baf588f4 | 523 | static void qspi_receive_init(const struct rspi_data *rspi) |
cb52c673 | 524 | { |
97b95c11 | 525 | u8 spsr; |
cb52c673 HCM |
526 | |
527 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
528 | if (spsr & SPSR_SPRF) | |
74da7686 | 529 | rspi_read_data(rspi); /* dummy read */ |
cb52c673 | 530 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
340a15e6 | 531 | rspi_write8(rspi, 0, QSPI_SPBFCR); |
cb52c673 HCM |
532 | } |
533 | ||
a3633fe7 SY |
534 | static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t) |
535 | { | |
536 | struct scatterlist sg, sg_dummy; | |
537 | void *dummy = NULL, *rx_buf = NULL; | |
538 | struct dma_async_tx_descriptor *desc, *desc_dummy; | |
539 | unsigned len; | |
540 | int ret = 0; | |
541 | ||
542 | if (rspi->dma_width_16bit) { | |
543 | /* | |
544 | * If DMAC bus width is 16-bit, the driver allocates a dummy | |
545 | * buffer. And, finally the driver converts the DMAC data into | |
546 | * actual data as the following format: | |
547 | * DMAC data: 1st byte, dummy, 2nd byte, dummy ... | |
548 | * actual data: 1st byte, 2nd byte ... | |
549 | */ | |
550 | len = t->len * 2; | |
551 | rx_buf = kmalloc(len, GFP_KERNEL); | |
552 | if (!rx_buf) | |
553 | return -ENOMEM; | |
554 | } else { | |
555 | len = t->len; | |
556 | rx_buf = t->rx_buf; | |
557 | } | |
558 | ||
559 | /* prepare dummy transfer to generate SPI clocks */ | |
560 | dummy = kzalloc(len, GFP_KERNEL); | |
561 | if (!dummy) { | |
562 | ret = -ENOMEM; | |
563 | goto end_nomap; | |
564 | } | |
565 | if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx, | |
566 | DMA_TO_DEVICE)) { | |
567 | ret = -EFAULT; | |
568 | goto end_nomap; | |
569 | } | |
570 | desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1, | |
571 | DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
572 | if (!desc_dummy) { | |
573 | ret = -EIO; | |
574 | goto end_dummy_mapped; | |
575 | } | |
576 | ||
577 | /* prepare receive transfer */ | |
578 | if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx, | |
579 | DMA_FROM_DEVICE)) { | |
580 | ret = -EFAULT; | |
581 | goto end_dummy_mapped; | |
582 | ||
583 | } | |
584 | desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE, | |
585 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
586 | if (!desc) { | |
587 | ret = -EIO; | |
588 | goto end; | |
589 | } | |
590 | ||
591 | rspi_receive_init(rspi); | |
592 | ||
593 | /* | |
594 | * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be | |
595 | * called. So, this driver disables the IRQ while DMA transfer. | |
596 | */ | |
597 | disable_irq(rspi->irq); | |
598 | ||
599 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR); | |
600 | rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
601 | rspi->dma_callbacked = 0; | |
602 | ||
603 | desc->callback = rspi_dma_complete; | |
604 | desc->callback_param = rspi; | |
605 | dmaengine_submit(desc); | |
606 | dma_async_issue_pending(rspi->chan_rx); | |
607 | ||
608 | desc_dummy->callback = NULL; /* No callback */ | |
609 | dmaengine_submit(desc_dummy); | |
610 | dma_async_issue_pending(rspi->chan_tx); | |
611 | ||
612 | ret = wait_event_interruptible_timeout(rspi->wait, | |
613 | rspi->dma_callbacked, HZ); | |
614 | if (ret > 0 && rspi->dma_callbacked) | |
615 | ret = 0; | |
616 | else if (!ret) | |
617 | ret = -ETIMEDOUT; | |
618 | rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE); | |
619 | ||
620 | enable_irq(rspi->irq); | |
621 | ||
622 | end: | |
623 | rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE); | |
624 | end_dummy_mapped: | |
625 | rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE); | |
626 | end_nomap: | |
627 | if (rspi->dma_width_16bit) { | |
628 | if (!ret) | |
629 | rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len); | |
630 | kfree(rx_buf); | |
631 | } | |
632 | kfree(dummy); | |
633 | ||
634 | return ret; | |
635 | } | |
636 | ||
baf588f4 | 637 | static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t) |
a3633fe7 SY |
638 | { |
639 | if (t->tx_buf && rspi->chan_tx) | |
640 | return 1; | |
641 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
642 | if (t->rx_buf && rspi->chan_tx && rspi->chan_rx) | |
643 | return 1; | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
8449fd76 GU |
648 | static int rspi_transfer_out_in(struct rspi_data *rspi, |
649 | struct spi_transfer *xfer) | |
650 | { | |
651 | int remain = xfer->len, ret; | |
652 | const u8 *tx_buf = xfer->tx_buf; | |
653 | u8 *rx_buf = xfer->rx_buf; | |
654 | u8 spcr, data; | |
655 | ||
656 | rspi_receive_init(rspi); | |
657 | ||
658 | spcr = rspi_read8(rspi, RSPI_SPCR); | |
659 | if (rx_buf) | |
660 | spcr &= ~SPCR_TXMD; | |
661 | else | |
662 | spcr |= SPCR_TXMD; | |
663 | rspi_write8(rspi, spcr, RSPI_SPCR); | |
664 | ||
665 | while (remain > 0) { | |
666 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
667 | ret = rspi_data_out(rspi, data); | |
668 | if (ret < 0) | |
669 | return ret; | |
670 | if (rx_buf) { | |
671 | ret = rspi_data_in(rspi); | |
672 | if (ret < 0) | |
673 | return ret; | |
674 | *rx_buf++ = ret; | |
675 | } | |
676 | remain--; | |
677 | } | |
678 | ||
679 | /* Wait for the last transmission */ | |
680 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
79d23495 GU |
685 | static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
686 | struct spi_transfer *xfer) | |
0b2182dd | 687 | { |
79d23495 | 688 | struct rspi_data *rspi = spi_master_get_devdata(master); |
8449fd76 GU |
689 | int ret; |
690 | ||
691 | if (!rspi_is_dma(rspi, xfer)) | |
692 | return rspi_transfer_out_in(rspi, xfer); | |
0b2182dd | 693 | |
79d23495 | 694 | if (xfer->tx_buf) { |
8449fd76 | 695 | ret = rspi_send_dma(rspi, xfer); |
79d23495 GU |
696 | if (ret < 0) |
697 | return ret; | |
0b2182dd | 698 | } |
8449fd76 GU |
699 | if (xfer->rx_buf) |
700 | return rspi_receive_dma(rspi, xfer); | |
701 | ||
702 | return 0; | |
eb557f75 GU |
703 | } |
704 | ||
340a15e6 GU |
705 | static int qspi_transfer_out_in(struct rspi_data *rspi, |
706 | struct spi_transfer *xfer) | |
eb557f75 | 707 | { |
340a15e6 GU |
708 | int remain = xfer->len, ret; |
709 | const u8 *tx_buf = xfer->tx_buf; | |
710 | u8 *rx_buf = xfer->rx_buf; | |
711 | u8 data; | |
eb557f75 | 712 | |
340a15e6 GU |
713 | qspi_receive_init(rspi); |
714 | ||
715 | while (remain > 0) { | |
716 | data = tx_buf ? *tx_buf++ : DUMMY_DATA; | |
717 | ret = rspi_data_out_in(rspi, data); | |
eb557f75 GU |
718 | if (ret < 0) |
719 | return ret; | |
340a15e6 GU |
720 | if (rx_buf) |
721 | *rx_buf++ = ret; | |
722 | remain--; | |
79d23495 | 723 | } |
340a15e6 GU |
724 | |
725 | /* Wait for the last transmission */ | |
726 | rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
727 | ||
728 | return 0; | |
729 | } | |
730 | ||
731 | static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, | |
732 | struct spi_transfer *xfer) | |
733 | { | |
734 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
735 | ||
736 | return qspi_transfer_out_in(rspi, xfer); | |
0b2182dd SY |
737 | } |
738 | ||
739 | static int rspi_setup(struct spi_device *spi) | |
740 | { | |
741 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); | |
742 | ||
0b2182dd SY |
743 | rspi->max_speed_hz = spi->max_speed_hz; |
744 | ||
348e5153 GU |
745 | rspi->spcmd = SPCMD_SSLKP; |
746 | if (spi->mode & SPI_CPOL) | |
747 | rspi->spcmd |= SPCMD_CPOL; | |
748 | if (spi->mode & SPI_CPHA) | |
749 | rspi->spcmd |= SPCMD_CPHA; | |
750 | ||
5ce0ba88 | 751 | set_config_register(rspi, 8); |
0b2182dd SY |
752 | |
753 | return 0; | |
754 | } | |
755 | ||
79d23495 | 756 | static void rspi_cleanup(struct spi_device *spi) |
0b2182dd | 757 | { |
79d23495 | 758 | } |
0b2182dd | 759 | |
79d23495 GU |
760 | static int rspi_prepare_message(struct spi_master *master, |
761 | struct spi_message *message) | |
762 | { | |
763 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
0b2182dd | 764 | |
79d23495 | 765 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
0b2182dd SY |
766 | return 0; |
767 | } | |
768 | ||
79d23495 GU |
769 | static int rspi_unprepare_message(struct spi_master *master, |
770 | struct spi_message *message) | |
0b2182dd | 771 | { |
79d23495 GU |
772 | struct rspi_data *rspi = spi_master_get_devdata(master); |
773 | ||
774 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); | |
775 | return 0; | |
0b2182dd SY |
776 | } |
777 | ||
778 | static irqreturn_t rspi_irq(int irq, void *_sr) | |
779 | { | |
c132f094 | 780 | struct rspi_data *rspi = _sr; |
97b95c11 | 781 | u8 spsr; |
0b2182dd | 782 | irqreturn_t ret = IRQ_NONE; |
97b95c11 | 783 | u8 disable_irq = 0; |
0b2182dd SY |
784 | |
785 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
786 | if (spsr & SPSR_SPRF) | |
787 | disable_irq |= SPCR_SPRIE; | |
788 | if (spsr & SPSR_SPTEF) | |
789 | disable_irq |= SPCR_SPTIE; | |
790 | ||
791 | if (disable_irq) { | |
792 | ret = IRQ_HANDLED; | |
793 | rspi_disable_irq(rspi, disable_irq); | |
794 | wake_up(&rspi->wait); | |
795 | } | |
796 | ||
797 | return ret; | |
798 | } | |
799 | ||
fd4a319b | 800 | static int rspi_request_dma(struct rspi_data *rspi, |
0243c536 | 801 | struct platform_device *pdev) |
a3633fe7 | 802 | { |
baf588f4 | 803 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
e2b05099 | 804 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3633fe7 | 805 | dma_cap_mask_t mask; |
0243c536 SY |
806 | struct dma_slave_config cfg; |
807 | int ret; | |
a3633fe7 | 808 | |
e2b05099 | 809 | if (!res || !rspi_pd) |
0243c536 | 810 | return 0; /* The driver assumes no error. */ |
a3633fe7 SY |
811 | |
812 | rspi->dma_width_16bit = rspi_pd->dma_width_16bit; | |
813 | ||
814 | /* If the module receives data by DMAC, it also needs TX DMAC */ | |
815 | if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) { | |
816 | dma_cap_zero(mask); | |
817 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
818 | rspi->chan_rx = dma_request_channel(mask, shdma_chan_filter, |
819 | (void *)rspi_pd->dma_rx_id); | |
820 | if (rspi->chan_rx) { | |
821 | cfg.slave_id = rspi_pd->dma_rx_id; | |
822 | cfg.direction = DMA_DEV_TO_MEM; | |
e2b05099 GL |
823 | cfg.dst_addr = 0; |
824 | cfg.src_addr = res->start + RSPI_SPDR; | |
0243c536 SY |
825 | ret = dmaengine_slave_config(rspi->chan_rx, &cfg); |
826 | if (!ret) | |
827 | dev_info(&pdev->dev, "Use DMA when rx.\n"); | |
828 | else | |
829 | return ret; | |
830 | } | |
a3633fe7 SY |
831 | } |
832 | if (rspi_pd->dma_tx_id) { | |
833 | dma_cap_zero(mask); | |
834 | dma_cap_set(DMA_SLAVE, mask); | |
0243c536 SY |
835 | rspi->chan_tx = dma_request_channel(mask, shdma_chan_filter, |
836 | (void *)rspi_pd->dma_tx_id); | |
837 | if (rspi->chan_tx) { | |
838 | cfg.slave_id = rspi_pd->dma_tx_id; | |
839 | cfg.direction = DMA_MEM_TO_DEV; | |
e2b05099 GL |
840 | cfg.dst_addr = res->start + RSPI_SPDR; |
841 | cfg.src_addr = 0; | |
0243c536 SY |
842 | ret = dmaengine_slave_config(rspi->chan_tx, &cfg); |
843 | if (!ret) | |
844 | dev_info(&pdev->dev, "Use DMA when tx\n"); | |
845 | else | |
846 | return ret; | |
847 | } | |
a3633fe7 | 848 | } |
0243c536 SY |
849 | |
850 | return 0; | |
a3633fe7 SY |
851 | } |
852 | ||
fd4a319b | 853 | static void rspi_release_dma(struct rspi_data *rspi) |
a3633fe7 SY |
854 | { |
855 | if (rspi->chan_tx) | |
856 | dma_release_channel(rspi->chan_tx); | |
857 | if (rspi->chan_rx) | |
858 | dma_release_channel(rspi->chan_rx); | |
859 | } | |
860 | ||
fd4a319b | 861 | static int rspi_remove(struct platform_device *pdev) |
0b2182dd | 862 | { |
5ffbe2d9 | 863 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
0b2182dd | 864 | |
a3633fe7 | 865 | rspi_release_dma(rspi); |
fcb4ed74 | 866 | clk_disable(rspi->clk); |
0b2182dd SY |
867 | |
868 | return 0; | |
869 | } | |
870 | ||
fd4a319b | 871 | static int rspi_probe(struct platform_device *pdev) |
0b2182dd SY |
872 | { |
873 | struct resource *res; | |
874 | struct spi_master *master; | |
875 | struct rspi_data *rspi; | |
876 | int ret, irq; | |
877 | char clk_name[16]; | |
baf588f4 | 878 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev); |
5ce0ba88 HCM |
879 | const struct spi_ops *ops; |
880 | const struct platform_device_id *id_entry = pdev->id_entry; | |
881 | ||
882 | ops = (struct spi_ops *)id_entry->driver_data; | |
883 | /* ops parameter check */ | |
884 | if (!ops->set_config_register) { | |
885 | dev_err(&pdev->dev, "there is no set_config_register\n"); | |
886 | return -ENODEV; | |
887 | } | |
0b2182dd SY |
888 | |
889 | irq = platform_get_irq(pdev, 0); | |
890 | if (irq < 0) { | |
891 | dev_err(&pdev->dev, "platform_get_irq error\n"); | |
892 | return -ENODEV; | |
893 | } | |
894 | ||
895 | master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); | |
896 | if (master == NULL) { | |
897 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | |
898 | return -ENOMEM; | |
899 | } | |
900 | ||
901 | rspi = spi_master_get_devdata(master); | |
24b5a82c | 902 | platform_set_drvdata(pdev, rspi); |
5ce0ba88 | 903 | rspi->ops = ops; |
0b2182dd | 904 | rspi->master = master; |
5d79e9ac LP |
905 | |
906 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
907 | rspi->addr = devm_ioremap_resource(&pdev->dev, res); | |
908 | if (IS_ERR(rspi->addr)) { | |
909 | ret = PTR_ERR(rspi->addr); | |
0b2182dd SY |
910 | goto error1; |
911 | } | |
912 | ||
5ce0ba88 | 913 | snprintf(clk_name, sizeof(clk_name), "%s%d", id_entry->name, pdev->id); |
5d79e9ac | 914 | rspi->clk = devm_clk_get(&pdev->dev, clk_name); |
0b2182dd SY |
915 | if (IS_ERR(rspi->clk)) { |
916 | dev_err(&pdev->dev, "cannot get clock\n"); | |
917 | ret = PTR_ERR(rspi->clk); | |
5d79e9ac | 918 | goto error1; |
0b2182dd SY |
919 | } |
920 | clk_enable(rspi->clk); | |
921 | ||
0b2182dd SY |
922 | init_waitqueue_head(&rspi->wait); |
923 | ||
efd85acb GU |
924 | if (rspi_pd && rspi_pd->num_chipselect) |
925 | master->num_chipselect = rspi_pd->num_chipselect; | |
926 | else | |
5ce0ba88 HCM |
927 | master->num_chipselect = 2; /* default */ |
928 | ||
0b2182dd SY |
929 | master->bus_num = pdev->id; |
930 | master->setup = rspi_setup; | |
eb557f75 | 931 | master->transfer_one = ops->transfer_one; |
0b2182dd | 932 | master->cleanup = rspi_cleanup; |
79d23495 GU |
933 | master->prepare_message = rspi_prepare_message; |
934 | master->unprepare_message = rspi_unprepare_message; | |
348e5153 | 935 | master->mode_bits = SPI_CPHA | SPI_CPOL; |
0b2182dd | 936 | |
5d79e9ac LP |
937 | ret = devm_request_irq(&pdev->dev, irq, rspi_irq, 0, |
938 | dev_name(&pdev->dev), rspi); | |
0b2182dd SY |
939 | if (ret < 0) { |
940 | dev_err(&pdev->dev, "request_irq error\n"); | |
fcb4ed74 | 941 | goto error2; |
0b2182dd SY |
942 | } |
943 | ||
a3633fe7 | 944 | rspi->irq = irq; |
0243c536 SY |
945 | ret = rspi_request_dma(rspi, pdev); |
946 | if (ret < 0) { | |
947 | dev_err(&pdev->dev, "rspi_request_dma failed.\n"); | |
fcb4ed74 | 948 | goto error3; |
0243c536 | 949 | } |
a3633fe7 | 950 | |
9e03d05e | 951 | ret = devm_spi_register_master(&pdev->dev, master); |
0b2182dd SY |
952 | if (ret < 0) { |
953 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
fcb4ed74 | 954 | goto error3; |
0b2182dd SY |
955 | } |
956 | ||
957 | dev_info(&pdev->dev, "probed\n"); | |
958 | ||
959 | return 0; | |
960 | ||
fcb4ed74 | 961 | error3: |
5d79e9ac | 962 | rspi_release_dma(rspi); |
fcb4ed74 GU |
963 | error2: |
964 | clk_disable(rspi->clk); | |
0b2182dd SY |
965 | error1: |
966 | spi_master_put(master); | |
967 | ||
968 | return ret; | |
969 | } | |
970 | ||
5ce0ba88 HCM |
971 | static struct spi_ops rspi_ops = { |
972 | .set_config_register = rspi_set_config_register, | |
eb557f75 | 973 | .transfer_one = rspi_transfer_one, |
5ce0ba88 HCM |
974 | }; |
975 | ||
976 | static struct spi_ops qspi_ops = { | |
977 | .set_config_register = qspi_set_config_register, | |
eb557f75 | 978 | .transfer_one = qspi_transfer_one, |
5ce0ba88 HCM |
979 | }; |
980 | ||
981 | static struct platform_device_id spi_driver_ids[] = { | |
982 | { "rspi", (kernel_ulong_t)&rspi_ops }, | |
983 | { "qspi", (kernel_ulong_t)&qspi_ops }, | |
984 | {}, | |
985 | }; | |
986 | ||
987 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); | |
988 | ||
0b2182dd SY |
989 | static struct platform_driver rspi_driver = { |
990 | .probe = rspi_probe, | |
fd4a319b | 991 | .remove = rspi_remove, |
5ce0ba88 | 992 | .id_table = spi_driver_ids, |
0b2182dd | 993 | .driver = { |
5ce0ba88 | 994 | .name = "renesas_spi", |
0b2182dd SY |
995 | .owner = THIS_MODULE, |
996 | }, | |
997 | }; | |
998 | module_platform_driver(rspi_driver); | |
999 | ||
1000 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); | |
1001 | MODULE_LICENSE("GPL v2"); | |
1002 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
1003 | MODULE_ALIAS("platform:rspi"); |